ANALOG DEVICES AD8367

500 MHz, Linear-in-dB VGA with AGC Detector AD8367 FEATURES FUNCTIONAL BLOCK DIAGRAM VPSI VPSO ENBL Broad-range analog variable gain: −2.5 dB to +42.5 dB 12 11 2 3 dB cutoff frequency of 500 MHz AD8367 ICOM 1 14 ICOM Gain up and gain down modes INPT 3 9-STAGE ATTENUATOR BY 5dB BIAS 9 DECL Linear-in-dB, scaled 20 mV/dB 13 HPFL Resistive ground referenced input g m 10 VOUT CELLS Nominal Z = 200 Ω IN On-chip, square-law detector SQUARE GAUSSIAN INTERPOLATOR LAW Single-supply operation: 2.7 V to 5.5 V DETECTOR ICOM 7 8 OCOM APPLICATIONS 4 5 6 MODE GAIN DETO Cellular base stations Figure 1. Broadband access Power amplifier control loops Complete, linear IF AGC amplifiers High speed data I/O GENERAL DESCRIPTION The AD8367 is a high performance 45 dB variable gain The analog gain-control input is scaled at 20 mV/dB and runs amplifier with linear-in-dB gain control for use from low from 50 mV to 950 mV. This corresponds to a gain of −2.5 dB frequencies up to several hundred megahertz. The range, to +42.5 dB, respectively, when the gain up mode is selected and flatness, and accuracy of the gain response are achieved using +42.5 dB to −2.5 dB, respectively, when gain down mode is Analog Devices’ X-AMP® architecture, the most recent in a selected. The gain down, or inverse, mode must be selected series of powerful proprietary concepts for variable gain when operating in AGC in which an integrated square-law applications, which far surpasses what can be achieved using detector with an internal setpoint is used to level the output to competing techniques. 354 mV rms, regardless of the crest factor of the output signal. A single external capacitor sets up the loop averaging time. The input is applied to a 9-stage, 200 Ω resistive ladder network. Each stage has 5 dB of loss, giving a total attenuation of 45 dB. The AD8367 can be powered on or off by a voltage applied to At maximum gain, the first tap is selected; at progressively the ENBL pin. When this voltage is at a logic LO, the total lower gains, the tap moves smoothly and continuously toward power dissipation drops to the milliwatt range. For a logic HI, higher attenuation values. The attenuator is followed by a the chip powers up rapidly to its normal quiescent current of 42.5 dB fixed gain feedback amplifier—essentially an 26 mA at 25°C. The AD8367 is available in a 14-lead TSSOP operational amplifier with a gain bandwidth product of package for the industrial temperature range of −40°C to +85°C. 100 GHz—and is very linear, even at high frequencies. The output third order intercept is +20 dBV at 100 MHz (+27 dBm, re 200 Ω), measured at an output level of 1 V p-p with VS = 5 V. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 02710-001 AD8367 TABLE OF CONTENTS Features .............................................................................................. 1 Noise and Distortion.................................................................. 12 Applications....................................................................................... 1 Output Centering ....................................................................... 12 Functional Block Diagram .............................................................. 1 RMS Detection ........................................................................... 13 General Description ......................................................................... 1 Applications..................................................................................... 14 Revision History ............................................................................... 2 Input and Output Matching...................................................... 14 Specifications..................................................................................... 3 VGA Operation .......................................................................... 15 Absolute Maximum Ratings............................................................ 5 Modulated Gain Mode .............................................................. 15 ESD Caution.................................................................................. 5 AGC Operation .......................................................................... 15 Pin Configuration and Function Descriptions............................. 6 Modifying the AGC Setpoint.................................................... 16 Typical Performance Characteristics ............................................. 7 Evaluation Board........................................................................ 19 Theory of Operation ...................................................................... 11 Characterization Setup and Methods ...................................... 20 Input Attenuator and Gain Control ......................................... 11 Outline Dimensions ....................................................................... 21 Input and Output Interfaces...................................................... 11 Ordering Guide .......................................................................... 21 Power and Voltage Metrics........................................................ 12 REVISION HISTORY 7/05—Rev. 0 to Rev. A Changes to Format .............................................................Universal Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 3............................................................................ 6 Changes to Figure 8.......................................................................... 7 Changes to Figure 9, Figure 12, and Figure 14 ............................. 8 Changes to Input and Output Interfaces Section ....................... 11 Changes to Output Centering Section and Figure 31................ 12 Changes to RMS Detection Section ............................................. 13 Changes to Figure 32, Table 4, and Table 5 ................................. 14 Changes to Figure 33, Figure 34, and AGC Operation Section................................................................. 15 Changes to the Modifying the AGC Set Point Section.............. 16 Changes to Figure 38...................................................................... 17 Changes to Figure 42...................................................................... 19 Changes to Table 7.......................................................................... 20 Moved Table 7 to Page ................................................................... 20 Moved Characterization Setup and Methods Section to Page . 20 Moved Figure 45 to Page ............................................................... 20 Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 21 10/01—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8367 SPECIFICATIONS VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, f = 10 MHz, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit OVERALL FUNCTION Frequency Range LF 500 MHz GAIN Range 45 dB INPUT STAGE Pins INPT and ICOM Maximum Input To avoid input overload 700 mV p-p Input Resistance From INPT to ICOM 175 200 225 Ω GAIN CONTROL INTERFACE Pin GAIN Scaling Factor V = 5 V, 50 mV ≤ V ≤ 950 mV +20 mV/dB MODE GAIN VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV −20 mV/dB Gain Law Conformance 100 mV ≤ VGAIN ≤ 900 mV ±0.2 dB Maximum Gain V = 0.95 V +42.5 dB GAIN Minimum Gain V = 0.05 V −2.5 dB GAIN V Step Response From 0 dB to 30 dB 300 ns GAIN From 30 dB to 0 dB 300 ns Small Signal Bandwidth VGAIN = 0.5 V 5 MHz OUTPUT STAGE Pin VOUT Maximum Output Voltage Swing RL = 1 kΩ 4.3 V p-p RL = 200 Ω 3.5 V p-p Output Source Resistance Series resistance of output buffer 50 Ω 1 Output Centering Voltage V/2 V S SQUARE LAW DETECTOR Pin DETO Output Set Point 354 mV rms AGC Small Signal Response Time C = 100 pF, 6 dB gain step 1 μs AGC POWER INTERFACE Pins VPSI, VPSO, ICOM, and OCOM Supply Voltage 2.7 5.5 V Total Supply Current ENBL high, maximum gain, R = 200 Ω 26 30 mA L (includes load current) Disable Current vs. Temperature ENBL low 1.3 1.6 mA −40°C ≤ TA ≤ +85°C 1.8 mA MODE CONTROL INTERFACE Pin MODE Mode LO Threshold Device in negative slope mode of operation 1.2 V Mode HI Threshold Device in positive slope mode of operation 1.4 V ENABLE INTERFACE Pin ENBL Enable Threshold 2.5 V Enable Response Time Time delay following LO to HI transition until 1.5 μs device meets full specifications. Enable Input Bias Current ENBL at 5 V 27 μA ENBL at 0 V 32 nA f = 70 MHz Gain Maximum gain +42.5 dB Minimum gain −3.7 dB Gain Scaling Factor 19.9 mV/dB Gain Intercept −5.6 dB Noise Figure Maximum gain 6.2 dB Output IP3 f1 = 70 MHz, f2 = 71 MHz, VGAIN = 0.5 V 36.5 dBm 29.5 dBV rms Output 1 dB Compression Point VGAIN = 0.5 V 8.5 dBm 1.5 dBV rms Rev. A | Page 3 of 24 AD8367 Parameter Conditions Min Typ Max Unit f = 140 MHz Gain Maximum gain +43.5 dB Minimum gain −3.6 dB Gain Scaling Factor 19.7 mV/dB Gain Intercept −5.3 dB Noise Figure Maximum gain 7.4 dB Output IP3 f1 = 140 MHz, f2 = 141 MHz, VGAIN = 0.5 V 32.7 dBm 25.7 dBV rms Output 1 dB Compression Point V = 0.5 V 8.4 dBm GAIN 1.4 dBV rms f = 190 MHz Gain Maximum gain +43.5 dB Minimum gain −3.8 dB Gain Scaling Factor 19.6 mV/dB Gain Intercept −5.3 dB Noise Figure Maximum gain 7.5 dB Output IP3 f1 = 190 MHz, f2 = 191 MHz, VGAIN = 0.5 V 30.9 dBm 23.9 dBV rms Output 1 dB Compression Point V = 0.5 V 8.4 dBm GAIN 1.4 dBV rms f = 240 MHz Gain Maximum gain +43 dB Minimum gain −4.1 dB Gain Scaling Factor 19.7 mV/dB Gain Intercept −5.2 dB Noise Figure Maximum gain 7.6 dB Output IP3 f1 = 240 MHz, f2 = 241 MHz, V = 0.5 V 29.2 dBm GAIN 22.2 dBV rms Output 1 dB Compression Point VGAIN = 0.5 V 8.1 dBm 1.1 dBV rms 1 The output dc centering voltage is normally set at VS/2 and can be adjusted by applying a voltage to DECL. Rev. A | Page 4 of 24 AD8367 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage VPSO, VPSI 5.5 V rating only; functional operation of the device at these or any ENBL Voltage V + 200 mV S other conditions above those indicated in the operational MODE Select Voltage VS + 200 mV section of this specification is not implied. Exposure to absolute VGAIN Control Voltage 1.2 V maximum rating conditions for extended periods may affect Input Voltage ±600 mV device reliability. Internal Power Dissipation 250 mW θ 150°C/W JA Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Range 300°C (Soldering 60 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 24 AD8367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ICOM 1 14 ICOM ENBL 2 13 HPFL INPT 3 12 VPSI AD8367 MODE 4 11 VPSO TOP VIEW (Not to Scale) GAIN 5 10 VOUT DETO 6 9 DECL ICOM 7 8 OCOM Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 7, 14 ICOM Signal Common. Connect to low impedance ground. 2 ENBL A HI Activates the Device. 3 INPT Signal Input. 200 Ω to ground. 4 MODE Gain Direction Control. HI for positive slope; LO for negative slope. 5 GAIN Gain Control Voltage Input. 6 DETO Detector Output. Provides output current for RSSI function and AGC control. 8 OCOM Power Common. Connect to low impedance ground. 9 DECL Output Centering Loop Decoupling Pin. 10 VOUT Signal Output. To be externally ac-coupled to load. 11 VPSO Positive Supply Voltage. 2.7 V to 5.5 V. VPSI and VPSO are tied together internally with back-to-back PN junctions. They should be tied together externally and properly bypassed. 12 VPSI Positive Supply Voltage. 2.7 V to 5.5 V. 13 HPFL High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop. Rev. A | Page 6 of 24 02710-002 AD8367 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, unless otherwise noted. 50 10 +85°C 1V 0.9V 40 9 0.8V +25°C 0.7V 30 8 0.6V –40°C 0.5V 20 7 0.4V 0.3V 10 6 0.2V 0.1V 0 5 –10 4 10 100 1000 70 90 110 130 150 170 190 210 230 250 FREQUENCY (MHz) FREQUENCY (MHz) ` Figure 3. Gain vs. Frequency for Values of V GAIN Figure 6. NF (re 200 Ω) vs. Frequency at Maximum Gain 45 60 40 50 35 30 40 MODE = 5V MODE = 0V 25 10MHz 10MHz 70MHz 70MHz 20 30 140MHz 140MHz 240MHz 240MHz 15 20 10 5 10 0 –5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V (V) V (V) GAIN GAIN Figure 4. Gain vs. VGAIN (Mode LO and Mode HI) Figure 7. NF (re 200 Ω) vs. V at 70 MHz GAIN 40 45 2.0 70MHz 10MHz 40 1.6 35 35 1.2 30 30 0.8 140MHz –40°C 25 25 0.4 240MHz +25°C 20 0 20 +85°C 15 –0.4 15 10 –0.8 10 5 –1.2 5 0 –1.6 –5 –2.0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V (V) V (V) GAIN GAIN Figure 5. Gain Conformance at 70 MHz for T = −40°C, +25°C, and +85°C Figure 8. OIP3 vs. VGAIN Rev. A | Page 7 of 24 GAIN (dB) GAIN (dB) GAIN (dB) 02710-004 02710-003 LINEARITY ERROR (dB) 02710-005 OIP3 (dBm) NOISE FIGURE (dB) NOISE FIGURE (dB) 02710-006 02710-007 02710-008 AD8367 40 33 0 –10 35 28 –20 30 23 –30 25 18 –40 240MHz –50 140MHz 20 13 10MHz –60 70MHz 15 8 –70 10 3 –80 10 100 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FREQUENCY (MHz) V (V) GAIN Figure 9. OIP3 vs. Frequency for V = 500 mV GAIN Figure 12. IMD3 vs. Gain (VOUT = 1 V p-p Composite) 4 11 4 11 10MHz 70MHz 2 9 2 9 140MHz 0 7 0 7 200MHz –2 5 –2 5 –4 3 –4 3 –6 1 –6 1 –8 –1 –8 –1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) GAIN V (V) S Figure 10. Output P1dB vs. VGAIN Figure 13. Output Compression Point vs. Supply Voltage at 70 MHz, VGAIN = 500 mV 5 12 40 33 4 11 35 28 3 10 30 23 2 9 25 18 1 8 0 7 20 13 –1 6 15 8 –2 5 10 3 –3 4 5 –2 –4 3 –5 2 0 –7 10 100 1000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (MHz) V (V) S Figure 11. Output P1dB vs. Frequency at VGAIN = 500 mV Figure 14. Output Third-Order Intercept vs. Supply Voltage at 70 MHz, VGAIN = 500 mV Rev. A | Page 8 of 24 OUTPUT 1dB COMPRESSION (dBV rms) OUTPUT 1dB COMPRESSION (dBV rms) OIP3 (dBm re 200Ω) OUTPUT 1dB COMPRESSION (dBm re 200Ω) OUTPUT 1dB COMPRESSION (dBm re 200Ω) OIP3 (dBV rms) 02710-011 02710-010 02710-009 OUTPUT IP3 (dBm re 200Ω) OUTPUT 1dB COMPRESSION (dBV rms) OUTPUT IMD3 (dBc) 02710-012 OUTPUT 1dB COMPRESSION (dBm re 200Ω) OUTPUT IP3 (dBV rms) 02710-014 02710-013 AD8367 90 250 0 60 120 200 –25 150 30 150 –47 500mV 300mV 700mV 180 0 100 –73 50 –95 210 330 0 –120 240 300 0 100 200 300 400 500 FREQUENCY (MHz) 270 Figure 15. Input Resistance and Series Reactance vs. Frequency Figure 18. Output Reflection Coefficient vs. Frequency from at V = 500 mV 10 MHz to 500 MHz for Multiple Values of V GAIN GAIN 90 0.5 120 60 V GAIN 0.4 0.3 150 30 V OUT 0.2 180 0 0.1 0 300mV 210 330 –0.1 500mV 700mV –0.2 240 300 –0.3 TIME (200ns/DIV) 270 Figure 16. Input Reflection Coefficient vs. Figure 19. AGA Time Domain Response (3 dB Steps) Frequency from 10 MHz to 500 MHz for Multiple Values of V GAIN 70 20 25 65 15 20 10nF 60 10 15 1nF 55 5 10pF 10 100pF 50 0 5 45 –5 NO CAP 40 –10 0 0 100 200 300 400 500 0.1 1 10 100 1k 10k 100k FREQUENCY (MHz) FREQUENCY (kHz) Figure 17. Output Resistance and Series Reactance vs. Figure 20. Gain vs. Frequency for Multiple Values of Frequency at VGAIN = 500 mV HPFL Capacitor at V = 500 mV GAIN Rev. A | Page 9 of 24 RESISTANCE (Ω) RESISTANCE (Ω) 02710-016 SERIES REACTANCE (Ω) SERIES REACTANCE (Ω) 02710-017 02710-015 GAIN (dB) V (V) 02710-018 02710-020 02710-019 AD8367 1.0 2.0 0.8 0.9 1.5 10MHz V AGC 0.8 70MHz 1.0 140MHz 140MHz 0.7 70MHz 240MHz 0.7 0.5 C = 100pF AGC 0.6 0 0.5 –0.5 0.6 240MHz V OUT 0.4 10MHz –1.0 0.3 –1.5 0.5 0.2 –2.0 0.1 –2.5 0 –3.0 0.4 –5 –5 –5 –5 –60 –50 –40 –30 –20 –10 0 –2 –1 01 2 INPUT LEVEL (dBV rms) TIME (Seconds) Figure 21. AGC RSSI (Voltage on DETO Pin) vs. Input Power at 10 MHz, Figure 24. AGC Time Domain Response (3 dB Step) 70 MHz, 140 MHz, and 240 MHz 1.0 2.0 +25°C 0.9 1.5 –40°C +85°C 0.8 1.0 +85°C +25°C 0.7 0.5 0.6 0 0.5 –0.5 –40°C 0.4 –1.0 0.3 –1.5 0.2 –2.0 0.1 –2.5 0 –3.0 19.0097 19.7297 19.9097 20.0897 20.2697 –60 –50 –40 –30 –20 –10 0 GAIN SCALING (mV/dB) INPUT LEVEL (dBV rms) Figure 22. AGC RSSI (Voltage on DETO Pin) vs. Figure 25. Gain Scaling Distribution at 70 MHz Input Power over Temperature at 70 MHz 1.0 2.5 0.9 2.0 0.8 1.5 0.7 WCDMA 1.0 16QAM 256QAM 64QAM 0.6 0.5 SINE 0.5 0 0.4 –0.5 IS95FWD 0.3 –1.0 0.2 –1.5 0.1 –2.0 0 –2.5 –60 –50 –40 –30 –20 –10 0 –6.4 –6.2 –6.0 –5.8 –5.6 –5.4 –5.2 –5.0 –4.8 INPUT LEVEL (dBV rms) INTERCEPT (dB) Figure 23. AGC RSSI (Voltage on DETO Pin) vs. Input Power Figure 26. Gain Intercept Distribution at 70 MHz for Various Modulation Schemes Rev. A | Page 10 of 24 RSSI (V) RSSI (V) RSSI (V) 02710-023 LINEARITY ERROR (dB) 02710-022 LINEARITY ERROR (dB) 02710-021 LINEARITY ERROR (dB) V (V) 02710-025 02710-026 02710-024 AD8367 THEORY OF OPERATION deviation from Equation 1, that is, the gain conformance error, The AD8367 is a variable gain, single-ended, IF amplifier based is also illustrated in Figure 28. The ripples in the error are a on Analog Devices’ patented X-AMP architecture. It offers result of the interpolation action between accurate gain control with a 45 dB span and a 3 dB bandwidth tap points. The AD8367 provides better than ±0.5 dB of of 500 MHz. It can be configured as a traditional VGA with conformance error over >40 dB gain range at 200 MHz 50 dB/V gain scaling or as an AGC amplifier by using the built and ±1 dB at 400 MHz. in rms detector. Figure 27 is a simplified block diagram of the amplifier. The main signal path consists of a voltage controlled 44 2.0 50dB/V 0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed 40 1.6 GAIN LO MODE SLOPE 36 gain amplifier. The AD8367 is designed to operate optimally in 1.2 32 a 200 Ω impedance system. 0.8 28 0.4 INTEGRATOR 24 OUTPUT 0 BUFFER GAIN GAIN INTERPOLATOR 20 –0.4 VOUT 16 g g g g –0.8 m m m m 12 V –42.5dB –1.2 OUT 0dB –5dB –10dB –45dB 8 –1.6 INPT 4 HI MODE –2.0 200Ω 0 –2.4 ATTENUATOR LADDER –4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V (V) Figure 27. Simplified Architecture GAIN Figure 28. The gain function can be either an increasing or decreasing INPUT ATTENUATOR AND GAIN CONTROL function of V , depending on the MODE pin. GAIN The variable attenuator consists of a 200 Ω single-ended The gain is a decreasing function of VGAIN when the MODE pin resistive ladder that comprises of nine 5 dB sections and an is low. Figure 28 also illustrates this mode, which is described by interpolator that selects the attenuation factor. Each tap point down the ladder network further attenuates the input signal Gain (dB) = 45 − 50 × V (2) GAIN by a fixed decibel factor. Gain control is achieved by sensing This gain mode is required in AGC applications using the built- different tap points with variable transconductance stages. in, square-law level detector. Based on the gain control voltage, an interpolator selects which stage(s) are active. For example, if only the first stage is active, INPUT AND OUTPUT INTERFACES the 0 dB tap point is sensed; if the last stage is active, the 45 dB The AD8367 was designed to operate best in a 200 Ω imped- tap point is sensed. Attenuation levels that fall between tap ance system. Its gain range, conformance law, noise, and points are achieved by having neighboring gm stages active distortion assume that 200 Ω source and load impedances simultaneously, creating a weighted average of the discrete are used. Interfacing the AD8367 to other common impedances tap point attenuations. In this way, a smooth, monotonic (from 50 Ω used at radio frequencies to 1 kΩ presented by data attenuation function is synthesized, that is, linear-in-dB converters) can be accomplished using resistive or reactive with a very precise scaling. passive networks, whose design depends on specific system The gain of the AD8367 can be an increasing or decreasing requirements, such as bandwidth, return loss, noise figure, function of the control voltage, VGAIN, depending on whether and absolute gain range. the MODE pin is pulled up to the positive supply or down to The input impedance of the AD8367 is nominally 200 Ω, ground. When the MODE pin is high, the gain increases with determined by the resistive ladder network. This presents a VGAIN, as shown in Figure 28. The ideal linear-in-dB scaled 200 Ω dc resistance to ground, and, in cases where an elevated transfer function is given by signal potential is used, ac coupling is necessary. The input Gain (dB) = 50 × V − 5 (1) GAIN signal level must not exceed 700 mV p-p to avoid overloading the input stage. The output impedance is determined by an where V is expressed in volts. GAIN internal 50 Ω damping resistor, as shown in Figure 29. Despite the fact that the output impedance is 50 Ω, the AD8367 should Equation 1 contains the gain scaling factor of 50 dB/V (20 still be presented with a load of 200 Ω. This implies that the mV/dB) and the gain intercept of −5 dB, which represents the load is mismatched, but doing so preserves the distortion extrapolated gain for VGAIN = 0 V. The gain ranges from −2.5 dB performance of the amplifier. to +42.5 dB for VGAIN ranging from 50 mV to 950 mV. The Rev. A | Page 11 of 24 02710-027 GAIN (dB) LINEARITY ERROR (dB) 02710-028 AD8367 60 60 50 50 NF V B1 40 40 50Ω FROM V OUT INTEGRATOR 30 30 V B2 20 20 IIP3 10 10 0 0 Figure 29. A 50 Ω resistor is added to the output to prevent package resonance. –10 –10 POWER AND VOLTAGE METRICS –20 –20 Although power is the traditional metric used in the analysis –30 –30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 of cascaded systems, most active circuit blocks fundamentally V (V) GAIN respond to voltage. The relationship between power and voltage Figure 30. Noise Figure and Input Third-Order Intercept vs. is defined by the impedance level. When input and output Gain (RSOURCE = 200 Ω) impedance levels are the same, power gain and voltage gain are identical. However, when impedance levels change between OUTPUT CENTERING input and output, they differ. Thus, one must be very careful to To maximize the ac swing at the output of the AD8367, the use the appropriate gain for system chain analyses. Quantities output level is centered midway between ground and the supply. such as OIP3 are quoted in dBV rms as well as dBm referenced This is achieved when the DECL pin is bypassed to ground via a to 200 Ω. The dBV rms unit is defined as decibels relative to shunt capacitor. The loop acts to suppress deviations from the 1 V rms. In a 200 Ω environment, the conversion from dBV rms reference at outputs below its corner frequency while not affect- to dBm requires the addition of 7 dB to the dBV rms value. For ing signals above it, as shown in Figure 31. The maximum example, a 2 dBV rms level corresponds to 9 dBm. corner frequency with no external capacitor is 500 kHz. The corner frequency can be lowered arbitrarily by adding an NOISE AND DISTORTION external capacitor, C : HP Since the AD8367 consists of a passive variable attenuator followed by a fixed gain amplifier, the noise and distortion 10 f (kHz)= (3) HP characteristics as a function of the gain voltage are easily C (nF)+ 0.02 HP predicted. The input-referred noise increases in proportion to A 100 Ω in series with the C capacitor is recommended to the attenuation level. Figure 30 shows noise figure, NF, as a HP function of VGAIN for the MODE pin pulled high. The minimum de-Q the resonant tank that is formed by the bond-wire NF of 7.5 dB occurs at maximum gain and increases 1 dB for inductance and CHP. Failure to insert this capacitor can every 1 dB reduction in gain. In receiver applications, the potentially cause oscillations at higher frequencies at high minimum NF should occur at the maximum gain where the gain settings. received signal presumably is weak. At higher levels, a lower MAIN AMPLIFIER gain is needed, and the increased NF becomes less important. FROM VOUT INPUT The input-referred distortion varies in a similar manner to the g noise. Figure 30 illustrates how the third-order intercept point m V MID at the input, IIP3, behaves as a function of V . The highest GAIN HPFL A = 1 V C IIP3 of 20 dBV rms (27 dBm re 200 Ω) occurs at minimum HP DECL R HP gain. The IIP3 then decreases 1 dB for every 1 dB increase in gain. At lower levels, a degraded IIP3 is acceptable. Overall, the Figure 31. The dc output level is centered to midsupply by a control loop dynamic range, represented by the difference between IIP3 and whose corner frequency is determined by C . HP NF, remains reasonably constant as a function of gain. The output distortion and compression are essentially independent of the gain. At low gains, when the input level is high, input overload can occur, causing premature distortion. Rev. A | Page 12 of 24 02710-029 IIP3 (dBV) 02710-031 NF (dB) 02710-030 AD8367 RMS DETECTION The resulting voltage is used as an AGC bias. For this application, the MODE pin is pulled low and the DETO pin is The AD8367 contains a square-law detector that senses tied to the GAIN pin. The output signal level is then regulated the output signal and compares it to a calibrated setpoint of to 354 mV rms. The AGC bias represents a calibrated rms 354 mV rms, which corresponds to a 1 V p-p sine wave. This measure of the received signal strength (RSSI). Since in AGC setpoint is internally set and cannot be modified to change the mode the output signal is forced to the 354 mV rms setpoint AGC setpoint and the resulting VOUT level without using (−9.02 dBV rms), Equation 2 can be recast to express the additional external components. This is described in the strength of the received signal, V , in terms of the AGC IN-RMS Modifying the AGC Setpoint section. bias V . DETO Any difference between the output and setpoint generates V (dBV rms) = 54.02 + 50 × V (4) IN − RMS DETO a current that is integrated by an external capacitor, CAGC, connected from the DETO pin to ground, to provide an AGC where −54.02 dBV rms = −45 dB − 9.02 dBV rms. control voltage. There is also an internal 5 pF capacitor on the For small changes in input signal level, VDETO responds with a DETO pin. characteristic single-pole time constant, τAGC, which is proportional to CAGC. τAGC (μs) = 10 × CAGC (nf) (5) where the internal 5 pF capacitor is lumped with the external capacitor to give C . AGC Rev. A | Page 13 of 24 AD8367 APPLICATIONS The AD8367 can be configured either as a VGA whose gain Minimum-loss, L-pad networks are used on the evaluation is controlled externally through the GAIN pin or as an AGC board (see Figure 45) to allow easy interfacing to standard amplifier, using a supply voltage of 2.7 V to 5.5 V. The supply 50 Ω test equipment. Each pad introduces an 11.5 dB power to the VPSO and VPSI pins should be decoupled using a low loss (5.5 dB voltage loss). inductance, 0.1 μF surface-mount, ceramic capacitor as close 1 as possible to the device. Additional supply decoupling can be provided by a small series resistor. A 10 nF capacitor from Pin DECL to Pin OCOM is recommended to decouple the 3 0.3333 output reference voltage. INPUT AND OUTPUT MATCHING The AD8367 is designed to operate in a 200 Ω impedance system. The output amplifier is a low output impedance voltage R SOURCE buffer with a 50 Ω damping resistor to desensitize it from load 0.3333 1 3 reactance and parasitics. The quoted performance includes the Z IN voltage division between the 50 Ω resistor and the 200 Ω load. SERIES L SHUNT C The AD8367 can be reactively matched to an impedance other than 200 Ω by using traditional step-up and step down matching networks or high quality transformers. Table 4 lists –0.3333 –3 the 50 Ω S-parameters for the AD8367 at a V = 750 mV. GAIN Figure 32 illustrates an example where the AD8367 is matched to 50 Ω at 140 MHz. As shown in the Smith Chart, the input –1 matching network shifts the input impedance from ZIN to 50 Ω f = 140MHz, Z = 197 – j34.2, R = 50Ω C IN SOURCE with an insertion loss of <2 dB over a 5 MHz bandwidth. For XS IN the output network, the 50 Ω load is made to present 200 Ω to 100nH the AD8367 output. Table 5 provides the component values AD8367 XP IN C XS required for 50 Ω matching at several frequencies of interest. AC OUT R SOURCE 8.2pF 0.1μF 13pF 50Ω Z Z OUT IN When added loss and noise can be tolerated, a resistive pad can V S Z be used to provide broadband, near-matched impedances at the IN Z LOAD device terminals and the terminations. R LOAD XP 50Ω OUT 120nH Figure 32. Reactive Matching Example for f = 140 MHz Table 4. S-Parameters for 200 Ω System for V = 5 V and V = 0.75 V S GAIN Frequency (MHz) S11 S21 S12 S22 10 0.04 ∠ −43.8° 41.1 ∠ 178.8° 0.0003 ∠ 76.1° 0.56 ∠ −179.3° 70 0.09 ∠ −81.5° 43.6 ∠ 163.4° 0.0002 ∠ 63.7° 0.55 ∠ +176.1° 140 0.17 ∠ −103.4° 48.0 ∠ 141.4° 0.0009 ∠ 130.8° 0.56 ∠ +170.2° 190 0.21 ∠ −111.7° 47.5 ∠ 124.0° 0.0017 ∠ 96.8° 0.54 ∠ +166.5° 240 0.26 ∠ −103.8° 48.3 ∠ 107.6° 0.0018 ∠ 113.5° 0.48 ∠ +164.6° Table 5. Reactive Matching Components for a 50 Ω System where RSOURCE = 50 Ω, RLOAD = 50 Ω Frequency (MHz) XSIN XPIN (pF) XSOUT (pF) XPOUT 10 1.5 μH 120 180 1.8 μH 70 220 nH 15 27 270 nH 140 100 nH 8.2 13 120 nH 190 82 nH 2.7 10 100 nH 240 68 nH 1.5 7 82 nH Rev. A | Page 14 of 24 02710-032 AD8367 VGA OPERATION AGC OPERATION The AD8367 is a general-purpose VGA suitable for use in a The AD8367 can be used as an AGC amplifier, as shown in wide variety of applications where voltage control of gain is Figure 34. For this application, the accurate internal, square-law needed. While having a 500 MHz bandwidth, its use is not detector is employed. The output of this detector is a current limited to high frequency signal processing. Its accurate, that varies in polarity, depending on whether the rms value of temperature- and supply-stable linear-in-dB scaling is the output is greater or less than its internally-determined valuable wherever it is important to have a more dependable setpoint of 354 mV rms. This is 1 V p-p for sine-wave signals, response to the control voltage than is usually offered by VGAs but the peak amplitude for other signals, such as Gaussian of this sort. For example, there is no preclusion to its use in noise, or those carrying complex modulation, is invariably speech-bandwidth systems. somewhat greater. However, for all waveforms having a crest factor of <5, and when using a supply voltage of 4.5 V to 5.5 V, Figure 33 shows the basic connections. The CHP capacitor at the rms value is correctly measured and delivered at V . OUT Pin HPFL can be used to alter the high-pass corner frequency of When using lower supplies, the rms value of V is unaffected OUT the signal path and is associated with the offset control loop that (the setpoint is determined by a band gap reference), but the eliminates the inherent variation in the internal dc balance of the peak crest factor capacity is reduced. signal path as the gain is varied (offset ripple). This frequency should be chosen to be about a decade below the lowest frequency The gain pin is connected to the base of a transistor internally component of the signal. If made much lower than necessary, the and thus requires only 1 μA of current drive. The output of the offset loop is not able to track the variations that occur when there detector is delivered to Pin DETO. The detector can source up are rapid changes in VGAIN. The control of offset is important even to 60 μA and can sink up to 11 μA. For a sine-wave output when the output is ac-coupled because of the potential reduction of signal, and under conditions where the AGC loop is settled, the the upper and lower voltage range at this pin. detector output also takes the form of a sine-wave, but at twice the frequency and having a mean value of 0. If the input to the However, in many applications these components are amplifier increases, the mean of this current also increases and unnecessary because an internal network provides a default charges the external loop filter capacitor, CAGC, toward more high-pass corner of about 500 kHz. For CHP = 1 nF, the positive voltages. Conversely, a reduction in VOUT below the modified corner is at ~10 kHz; it scales downward with setpoint of 354 mV rms causes this voltage to fall toward increasing capacitance. Figure 20 shows representative ground. The capacitor voltage is the AGC bias; this can be response curves for the indicated component values. used as a received signal strength indicator (RSSI) output V and is scaled exactly as V , that is, 20 mV/dB. GAIN P C1 R6 R5 1μF 4.7Ω 4.7Ω V AD8367 P C1 C C2 C3 R6 R5 HP R 1 ICOM ICOM 14 HP 1μF 10nF 0.1μF 0.1μF 4.7Ω 4.7Ω 100Ω AD8367 2 ENBL HPFL 13 C C2 C3 HP R 1 ICOM ICOM 14 HP 10nF 0.1μF 0.1μF 100Ω V 3 INPT VPSI 12 IN 2 ENBL HPFL 13 4 MODE VPSO 11 V 3 INPT VPSI 12 IN V 5 GAIN VOUT 10 VOUT GAIN 4 MODE VPSO 11 C4 6 DETO DECL 9 C5 0.1μF V 5 GAIN VOUT 10 VOUT AGC 10nF 7 ICOM OCOM 8 C4 6 DETO DECL 9 C5 0.1μF C AGC 10nF 0.1μF 7 ICOM OCOM 8 Figure 33. Basic Connections for Voltage Controlled Gain Mode Figure 34. Basic Connections for AGC Operation MODULATED GAIN MODE The AD8367 can be used as a means of modulating the signal A valuable feature of using a square law detector is that the level. Keep in mind, however, that the gain is a nonlinear RSSI voltage is a true reflection of signal power and can be (exponential) function of VGAIN; thus, it is not suitable for converted to an absolute power measurement for any given normal amplitude-modulation functions. The small signal source impedance. The AD8367 can thus be employed as a bandwidth of the gain interface is ~5 MHz, and the slew rate true-power meter, or decibel-reading ac voltmeter, as distinct is of the order of ±500 dB/μs. During gain slewing from close from its basic amplifier function. to minimum to maximum gain (or vice versa), the internal The AGC mode of operation requires that the correct gain interpolation processes in an X-AMP-based VGA rapidly direction is chosen. Specifically, the gain must fall as V AGC scan the full range of gain values. The gain and offset ripple increases to restore the needed balance against the setpoint. associated with this process can cause transient disturbances Therefore, the MODE pin must be pulled low. This accurate in the output. Therefore, it is inadvisable to use high amplitude leveling function is shown in Figure 35, where the rms output is pulse drives with rise and fall times below 200 ns. Rev. A | Page 15 of 24 02710-033 02710-034 AD8367 held to within 0.1 dB of the setpoint for >35 dB range of Most AGC loops incorporating a true error-integrating input levels. technique have a common weakness. When driven from an increasingly larger signal, the AGC bias increases to reduce the The dynamics of this loop are controlled by C acting in AGC gain. However, eventually the gain falls to its minimum value, conjunction with an on-chip equivalent resistance, RAGC, of for which further increase in this bias has no effect on the gain. 10 kΩ which form an effective time-constant TAGC = RAGC CAGC. That is, the voltage on the loop capacitor is forced progressively The loop thus operates as a single-pole system with a loop higher because the detector output is a current, and the AGC bandwidth of 1/(2π TAGC). Because the gain control function is bias is its integral. Consequently, there is always a precipitous linear in decibels, this bandwidth is independent of the absolute increase in this bias voltage when the input to the AD8367 signal level. Figure 36 illustrates the loop dynamics for a 30 dB exceeds that value that overdrives the detector, and because the change in input signal level with C = 100 pF. AGC minimum gain is −2.5 dB, that happens for all inputs 2.5 dB –1.2 greater than the setpoint of ~350 mV rms. If possible, the user –1.3 should ensure that this limitation is preserved, preferably with a –1.4 guard-band of 5 dB to 10 dB below overload –1.5 In some cases, if driven into AGC overload, the AD8367 –1.6 requires unusually long times to recover; that is, the voltage –1.7 at DETO remains at an abnormally high value and the gain is at its lowest value. To avoid this situation, it is recommended that –1.8 a clamp be placed on the DETO pin, as shown in Figure 37. –1.9 –2.0 AD8367 1 14 –2.1 2 13 +V –2.2 S 3 12 –50 –40 –30 –20 –10 0 10 4 MODE 11 PIN (dBm re 200Ω) V AGC RB 5 GAIN 10 Figure 35. Leveling Accuracy of the AGC Function Q1 0.5V 6 DETO 9 2N2907 C AGC 0.1μF 1.0 7 ICOM 8 RA V AGC 0.8 Figure 37. External Clamp to Prevent AGC Overload. The resistive divider network, RA and RB, should be designed 0.6 such that the base of Q1 is driven to 0.5 V. 0.4 MODIFYING THE AGC SETPOINT 0.2 If an AGC setpoint other than the internal one is desired, an V OUT 0 external detector must be used. Figure 38 shows a method that uses an external true-rms detector and error integrator to –0.2 operate the AD8367 as a closed-loop AGC system with a user- –0.4 settable operating level. –0.6 The AD8361 (U2) produces a dc output level that is 0 5 10 15 20 25 30 35 40 proportional to the rms value of its input, taken as a sample TIME (μs) of the AD8367 (U1) output. This dc voltage is compared to Figure 36. AGC Response to a 32 dB Step in Input Level (f = 50 MHz) an externally-supplied setpoint voltage, and the difference is It is important to understand that RAGC does not act as if in integrated by the AD820 (U3) to form the gain control voltage shunt with C . Rather, the error-correction process is that of a AGC that is applied to the GAIN input of the AD8367 through the true integrator, to guarantee an output that is exactly equal in divider composed of R4 and R5. This divider is included in rms amplitude to the specified setpoint. For large changes in order to minimize overload recovery time of the loop by having input level, the integrating action of this loop is most apparent. the integrator saturate at a point that only slightly overdrives the The slew rate of VAGC is determined by the peak output current gain control input of the AD8367. The scale factor at V is AGC from the detector and the capacitor. Thus, for a representative influenced by the values of R4 and R5; for the values shown, the value of CAGC = 3 nF, this rate is about 20 V rms or 10 dB/μs, factor is 86 mV/dB. while the small-signal bandwidth is 1 kHz. Rev. A | Page 16 of 24 V (V); V (arb) POUT (dBm re 200Ω) ACG OUT 02710-035 02710-036 02710-037 AD8367 2.2Ω 5V 10nF C2 V INTO A OUT 0.27μF 200Ω LOAD AD8367 C HP R 1 ICOM ICOM 14 HP 10nF 10nF 100Ω U2 2 ENBL HPFL 13 J1 U1 10nF 0.1μF AD8361 3 INPT VPSI 12 1 VPOS SREF 8 INPUT R6 R1 2 IREF VRMS 7 4 MODE VPSO 11 57.6Ω 200kΩ 5 GAIN VOUT 10 3 RFIN FLTR 6 6 DETO DECL 9 4 PWDN COMM 5 C5 C1 10nF 3.3nF 7 ICOM OCOM 8 R3 V g 20pF 82kΩ R2 V AGC 4 150kΩ 2 R4 Vrms 33kΩ U3 6 AD820 12kΩ 3 R5 V SET 10kΩ 0.1μF 7 5V Figure 38. Example of Using an External Detector to Form an AGC Loop The component values shown in Figure 38 were chosen for a Note that in this circuit the AD8367’s MODE pin must be 64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz. pulled high to obtain correct feedback polarity because the The response time of the loop as shown is roughly 5 ms for integrator inverts the polarity of the feedback signal. an abrupt input level change of 40 dB. Figure 41 shows the The relationship between the setpoint voltage and the rms dynamic performance of the loop with a step-modulated output voltage of the AD8367 is CW signal applied to the input for a VSET of about 1 V. (R1+ 225) For a linear-in-dB response, detectors such as the AD8318 or V = V × (6) OUT−RMS SET the AD8362 can be used in place of the AD8361. 225× 7.5 4.0 where 225 is the input resistance of the AD8361 and 7.5 is its 3.5 conversion gain. For R1 = 200 Ω, this reduces to V = V OUT –RMS SET × 0.25. 3.0 10MHz Capacitor C2 sets the averaging time for the rms detector. This 2.5 should be made long enough to provide sufficient smoothing of 380MHz 2.0 the detector’s output in the presence of the modulation on the RF signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p 1.5 at the AD8361’s output is a reasonable value. A considerably 1.0 longer time constant needlessly lowers the AGC bandwidth, while a short time constant can degrade the accuracy of the 0.5 true-rms measurement process. Components C1, R2, and R3 0 set the control loop’s bandwidth and stability. The maximum –20 –15 –10 –5 0 5 10 POUT (dBm INTO 200Ω) stable loop bandwidth is limited by the rms detector’s averaging Figure 39. AGC Setpoint Voltage vs. Output Power time constant as previously discussed. (QPSK: 4.096 MS/s; α = 0.22; 1 User) For an input signal consisting of a 4.096 MS/s QPSK modulated carrier, the relationship between V and the output power for SET Figure 39. The exponential shape reflects this setup is shown in the linear-in-magnitude response of the AD8361. The adjacent channel power ratio (ACPR) as a function of output power is illustrated in Figure 40. The minima occur where the distortion and integrated noise powers cross over. Rev. A | Page 17 of 24 V (V) SET 02710-038 02710-039 AD8367 –20 1.0 V g –25 0.5 –30 0 –35 140MHz V OUT –40 –0.5 380MHz –45 –1.0 –50 10MHz –1.5 70MHz –55 –60 –2.0 –20 –15 –10 –5 0 5 10 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 POUT (dBm INTO 200Ω) TIME (Seconds) Figure 40. ACPR vs. Output Power for QPSK Waveform Figure 41. AGC Dynamic Response: 8367 AGC with an External Detector (QPSK: 4.096 MS/s; α = 0.22; 1 User) Table 6. Suggested Component Values for External AGC Detector Circuit Modulation Type Rate Sys/s C1 (μF) C2 (μF) R2 (kΩ) R3 (kΩ) QPSK 1.23 M 0.0022 0.033 150 62 QPSK 4 M 0.0022 0.015 150 39 π/4 DQPSK 24.3 K 0.033 0.68 150 51 64 QAM 100 K 0.015 1.5 150 51 64 QAM 500 K 0.0068 0.33 150 62 64 QAM 4 M 0.0022 0.068 150 100 Rev. A | Page 18 of 24 ACPR (dBc) 02710-041 Vg (V); V (arb) OUT 02710-040 AD8367 EVALUATION BOARD Figure 42 shows the schematic of the AD8367 evaluation board. The board is powered by a single supply of 2.7 V to 5.5 V. R7 SW2 TP1 10kΩ V P C1 R6 R5 1μF 4.7Ω 4.7Ω LK1 AD8367 TP3 C C2 C3 HP MODE R 1 ICOM ICOM 14 HP 10nF 0.1μF 0.1μF 100Ω R2 2 ENBL HPFL 13 J1 174Ω 3 INPT VPSI 12 INPUT R1 57.6Ω TP4 4 MODE VPSO 11 J2 GAIN 5 GAIN VOUT 10 OUTPUT R1 R4 C4 57.6Ω 6 DETO DECL 9 SW1 174Ω C5 0.1μF C AGC 10nF 7 8 ICOM OCOM 0.1μF Figure 42. Evaluation Board Schematic Figure 43. Layout of Component Side Figure 44. Silkscreen of Component Side Rev. A | Page 19 of 24 02710-043 02710-042 02710-044 AD8367 Table 7 details the various configuration options of the evaluation board. Table 7. Evaluation Board Configuration Options Component Function Default Condition TP1, TP2 Supply and Ground Vector Pins. Not Applicable TP3, TP4 Mode and Gain Vector Pins. Not Applicable SW1 VGA/AGC Select: Used to select VGA (Position A) or AGC (Position B) mode of SW1 = A operation. SW2 must be set for Position A for AGC mode of operation. SW2 MODE Select. Used to select positive or negative VGA slope. Set to Position B for an SW2 = B increasing gain with VGAIN, Position A for decreasing gain law. LK1 Device Enable. When LK1 is installed, the ENBL pin is connected to the positive supply LK1 = Installed and the AD8367 is in operating mode. R1, R2 Input Interface. R1 and R2 are used to provide an L-pad impedance-transforming R1 = 57.6 Ω (Size 0603) network. The broadband matching network transforms a 50 Ω source to match a R2 = 174 Ω (Size 0603) 200 Ω load with 11.5 dB of insertion loss. R3, R4, C4 Output Interface. R3 and R4 are used to transform a 50 Ω load termination to look like R3 = 57.6 Ω (Size 0603) a 200 Ω load with 11.5 dB of insertion loss. The ac coupling capacitor, C4, can be R4 = 174 Ω (Size 0603) increased to obtain a lower high-pass corner frequency. C4 = 0.1 μF (Size 0603) C1, C2, C3, R5, R6 Power Supply Decoupling. The nominal supply decoupling consists of a 1 μF capacitor C1 = 1 μF (Size 0603) to ground, a 4.7 Ω series resistor, and a 0.1 μF capacitor to ground. The same R5 = R6 = 4.7 Ω (Size 0805) decoupling network should be used on both the VPSI and VPSO supply lines. C2 = C3 = 0.1 μF (Size 0603) C5 Internal Supply Decoupling. Capacitor C5 provides midsupply decoupling. C5 = 10 nF (Size 0603) C Filter Capacitor. HPFL capacitor, sets the high-pass corner frequency. C = 0.01 μF (Size 0805) HP HP R = 0 Ω (Size 0603) HP C AGC Filter Capacitor. Capacitor, CAGC, sets closed-loop AGC response time. C = 0.1 μF (Size 0805) AGC AGC R7 Mode Pull-Up Resistor. R7 = 10 kΩ (Size 0805) RHP High-Pass Filter Resistor. RHP = 100 Ω (Size) CHARACTERIZATION SETUP AND METHODS Minimum-loss, L-pad matching networks were used to AD8367 interface standard 50 Ω. A test equipment to the 200 Ω input 174Ω 174Ω impedance during the characterization process. Using a 57.6 Ω 57.6Ω 57.6Ω shunt resistor followed by a 174 Ω series resistor provides a broadband match between the 50 Ω test equipment and the Figure 45. Characterization Test Setup 200 Ω device impedance, as illustrated in Figure 45. The insertion loss of this network is 11.5 dB. Rev. A | Page 20 of 24 02710-045 AD8367 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 1.05 BSC 1.00 0.20 0.80 1.20 0.09 0.75 MAX 8° 0.60 0.15 0.30 0° 0.45 0.05 SEATING 0.19 COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AB-1 Figure 46. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimension shown millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD8367ARU −40°C to +85°C 14-Lead TSSOP, Tube RU-14 AD8367ARU-REEL-7 −40°C to +85°C 14-Lead TSSOP, 7" Tape and Reel RU-14 1 AD8367ARUZ −40°C to +85°C 14-Lead TSSOP, Tube RU-14 1 AD8367ARUZ-RL7 −40°C to +85°C 14-Lead TSSOP, 7" Tape and Reel RU-14 AD8367-EVAL Evaluation Board 1 Z = Pb-free part. Rev. A | Page 21 of 24 AD8367 NOTES Rev. A | Page 22 of 24 AD8367 NOTES Rev. A | Page 23 of 24 AD8367 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02710–0–7/05(A) Rev. A | Page 24 of 24