ANALOG DEVICES AD8366

DC to 600 MHz, Dual-Digital Variable Gain Amplifiers AD8366 FEATURES FUNCTIONAL BLOCK DIAGRAM Matched pair of differential, digitally controlled VGAs Gain range: 4.5 dB to 20.25 dB 0.25 dB gain step size Operating frequency VPSIA BIT0/CS DC to 150 MHz (2 V p-p) 3 dB bandwidth: 600 MHz IPPA BIT1/SDAT Noise figure (NF) IPMA BIT2/SCLK 11.4 dB at 10 MHz at maximum gain ENBL BIT3 18 dB at 10 MHz at minimum gain DIGITAL GAIN CONTROL LOGIC ICOM OCOM OIP3: 45 dBm at 10 MHz HD2/HD3 IPMB BIT4 Better than −90 dBc for 2 V p-p output at 10 MHz at IPPB BIT 5 maximum gain VPSIB DENA Differential input and output Adjustable output common-mode Optional dc output offset correction Serial/parallel mode gain control Power-down feature Figure 1. Single 5 V supply operation APPLICATIONS Baseband I/Q receivers Diversity receivers Wideband ADC drivers GENERAL DESCRIPTION The AD8366 is a matched pair of fully differential, low noise and The output common-mode voltage defaults to VPOS/2 but can low distortion, digitally programmable variable gain amplifiers be programmed via the VCMA and VCMB pins over a range (VGAs). The gain of each amplifier can be programmed separately of voltages. The input common-mode voltage also defaults or simultaneously over a range of 4.5 dB to 20.25 dB in steps of to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset 0.25 dB. The amplifier offers flat frequency performance from dc compensation loop can be used to eliminate dc offsets from prior to 70 MHz, independent of gain code. stages in the signal chain. This loop can also be disabled if dc- coupled operation is desired. The AD8366 offers excellent spurious-free dynamic range, suitable for driving high resolution analog-to-digital converters (ADCs). The digital interface allows for parallel or serial mode gain The NF at maximum gain is 11.4 dB at 10 MHz and increases programming. The AD8366 operates from a 4.75 V to 5.25 V ~2 dB for every 4 dB decrease in gain. Over the entire gain range, supply and consumes typically 180 mA. When disabled, the the HD3/HD2 are better than −90 dBc for 2 V p-p at the output at part consumes roughly 3 mA. The AD8366 is fabricated using 10 MHz into 200 Ω. The two-tone intermodulation distortion of Analog Devices, Inc., advanced silicon-germanium bipolar −90 dBc into 200 Ω translates to an OIP3 of 45 dBm (38 dBVrms). process, and it is available in a 32-lead exposed paddle LFCSP The differential input impedance of 200 Ω provides a well-defined package. Performance is specified over the −40°C to +85°C termination. The differential output has a low impedance of ~25 Ω. temperature range. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. DECB DECA OFSB OFSA CCMB CCMA VCMB VCMA VPSOB VPSOA OPPB OPPA OPMB OPMA DENB SENB 07584-001 AD8366 TABLE OF CONTENTS Features .............................................................................................. 1  Output Differential Offset Correction .................................... 15  Applications....................................................................................... 1  Output Common-Mode Control ............................................. 15  Functional Block Diagram .............................................................. 1  Gain Control Interface............................................................... 16  General Description ......................................................................... 1  Applications Information .............................................................. 17  Revision History ............................................................................... 2  Basic Connections...................................................................... 17  Specifications..................................................................................... 3  Direct Conversion Receiver Design......................................... 18  Parallel and Serial Interface timing............................................ 5  Quadrature Errors and Image Rejection................................. 18  Absolute Maximum Ratings............................................................ 6  Low Frequency IMD3 Performance ........................................ 19  ESD Caution.................................................................................. 6  Baseband Interface ..................................................................... 21  Pin Configuration and Function Descriptions............................. 7  Characterization Setups................................................................. 22  Typical Performance Characteristics ............................................. 8  Evaluation Board ............................................................................ 25  Circuit Description......................................................................... 15  Outline Dimensions....................................................................... 28  Inputs ........................................................................................... 15  Ordering Guide .......................................................................... 28  Outputs ........................................................................................ 15  REVISION HISTORY 3/11—Rev. 0 to Rev. A Changes to Table 2, Internal Power Dissipation Value................ 6 10/10—Revision 0: Initial Version Rev. A | Page 2 of 28 AD8366 SPECIFICATIONS VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth 3 dB; all gain codes 600 MHz 1 dB; all gain codes 200 MHz Slew Rate Maximum gain 1100 V/μs Minimum gain 1500 V/μs INPUT STAGE IPPA, IPMA, IPPB, IPMB Linear Input Swing At minimum gain A = 4.5 dB, 1 dB gain compression 3.6 V p-p V Differential Input Impedance 217 Ω Minimum Input Common-Mode Voltage 1.5 V Maximum Input Common-Mode Voltage V /2 + 0.075 V POS Input pins left floating VPOS/2 V GAIN Minimum Voltage Gain 4.5 dB Maximum Voltage Gain 20.25 dB Gain Step Size All gain codes 0.25 dB Gain Step Accuracy All gain codes ±0.25 dB Gain Flatness Maximum gain, DC to 70 MHz 0.1 dB Gain Mismatch Channel A/Channel B at minimum/maximum gain code 0.1 dB Group Delay Flatness All gain codes, 20% fractional bandwidth, f < 100 MHz <0.5 ns C Mismatch Channel A and Channel B at same gain code 2 ps Gain Step Response Maximum gain to minimum gain 30 ns Minimum gain to maximum gain 60 ns Common-Mode Rejection Ratio −66.2 dB OUTPUT STAGE OPPA, OPMA, OPPB, OPMB, VCMA, VCMB Linear Output Swing 1 dB gain compression 6 V p-p Differential Output Impedance 28 Ω Output DC Offset Inputs shorted, offset loop disabled at −10/−30 mV minimum/maximum gain Inputs shorted, offset loop enabled (across all gain codes) 10 mV Minimum Output Common-Mode Voltage HD3, HD2 > −90 dBc, 2 V p-p output 1.6 V Maximum Output Common-Mode Voltage HD3, HD2 > −90 dBc, 2 V p-p output 3 V VCMA and VCMB left floating VPOS/2 V Common-Mode Setpoint Input Impedance 4 kΩ NOISE/DISTORTION 3 MHz Noise Figure Maximum gain 11.3 dB Minimum gain 18.2 dB Second Harmonic 2 V p-p output, maximum gain −82 dBc 2 V p-p output, minimum gain −82 dBc Third Harmonic 2 V p-p output, maximum gain −87 dBc 2 V p-p output, minimum gain −90 dBc 1 OIP3 2 V p-p composite, maximum gain 34 dBVrms 2 V p-p composite, minimum gain 35 dBVrms 1 OIP2 2 V p-p composite, maximum gain 76 dBVrms 2 V p-p composite, minimum gain 76 dBVrms 1 Output 1 dB Compression Point Maximum gain 6.7 dBVrms Minimum gain 6.9 dBVrms Rev. A | Page 3 of 28 AD8366 Parameter Test Conditions/Comments Min Typ Max Unit 10 MHz Noise Figure Maximum gain 11.4 dB Minimum gain 18 dB Second Harmonic 2 V p-p output, maximum gain −97 dBc 2 V p-p output, minimum gain −96 dBc Third Harmonic 2 V p-p output, maximum gain −97 dBc 2 V p-p output, minimum gain −90 dBc 1 OIP3 2 V p-p composite, maximum gain 38 dBVrms 2 V p-p composite, minimum gain 36 dBVrms 1 OIP2 2 V p-p composite, maximum gain 72 dBVrms 2 V p-p composite, minimum gain 76 dBVrms 1 Output 1 dB Compression Point Maximum gain 7 dBVrms Minimum gain 6.7 dBVrms 50 MHz Noise Figure Maximum gain 11.8 dB Minimum gain 18.2 dB Second Harmonic 2 V p-p output, maximum gain −82 dBc 2 V p-p output, minimum gain −84 dBc Third Harmonic 2 V p-p output, maximum gain −80 dBc 2 V p-p output, minimum gain −71 dBc 1 OIP3 2 V p-p composite, maximum gain 32 dBVrms 2 V p-p composite, minimum gain 26 dBVrms 1 OIP2 2 V p-p composite, maximum gain 71 dBVrms 2 V p-p composite, minimum gain 78 dBVrms 1 Output 1 dB Compression Point Maximum gain 6.7 dBVrms Minimum gain 6.7 dBVrms DIGITAL LOGIC SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5 Input High Voltage, VINH 2.2 V Input Low Voltage, V 1.2 V INL Input Capacitance, CIN 1 pF Input Resistance, RIN 50 kΩ SPI INTERFACE TIMING SENB = high f Serial clock frequency (maximum) 44.4 MHz SCLK t1 CS rising edge to first SCLK rising edge (minimum) 7.5 ns t2 SCLK high pulse width (minimum) 7.5 ns t SCLK low pulse width (minimum) 15 ns 3 t4 SCLK falling edge to CS low (minimum) 7.5 ns t SDAT setup time (minimum) 7.5 ns 5 t6 SDAT hold time (minimum) 15 ns PARALLEL PORT TIMING SENB = low t7 DENA/DENB high pulse width (minimum) 7.5 ns t DENA/DENB low pulse width (minimum) 15 ns 8 t9 BITx setup time (minimum) 7.5 ns t10 BITx hold time (minimum) 7.5 ns POWER AND ENABLE VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL Supply Voltage Range 4.75 5.25 V Total Supply Current ENBL = 5 V 180 mA Disable Current ENBL = 0 V 3.2 mA Disable Threshold 1.65 V Enable Response Time Delay following high-to-low transition until device 150 ns meets full specifications Disable Response Time Delay following low-to-high transition until device 3 μs produces full attenuation 1 To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value. Rev. A | Page 4 of 28 AD8366 PARALLEL AND SERIAL INTERFACE TIMING CS t t 3 4 t 2 t 1 SCLK t t 5 6 X B-LSB B-MSB A-LSB A-MSB X SDAT SENB ALWAYS HIGH Figure 2. SPI Port Timing Diagram BIT[5:0] GAIN A GAIN B GAIN A, GAIN B t DENA t 10 9 DENB t t 7 8 SENB ALWAYS LOW Figure 3. Parallel Port Timing Diagram Rev. A | Page 5 of 28 07584-003 07584-004 AD8366 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltages, VPSIx and VPSOx 5.5 V other conditions above those indicated in the operational ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2, 5.5 V section of this specification is not implied. Exposure to absolute BIT3, BIT4, BIT5 maximum rating conditions for extended periods may affect IPPA, IPMA, IPPB, IPMB 5.5 V device reliability. OPPA, OPMA, OPPB, OPMB 5.5 V OFSA, OFSB 5.5 V DECA, DECB, VCMA, VCMB, CCMA, CCMB 5.5 V ESD CAUTION Internal Power Dissipation 1.4 W θJA (With Pad Soldered to Board) 45.4°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Rev. A | Page 6 of 28 AD8366 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BIT0/CS VPSIA 1 24 PIN 1 BIT1/SDAT IPPA 2 23 INDICATOR IPMA 3 22 BIT2/SCLK 4 21 BIT3 ENBL AD8366 OCOM ICOM 5 20 TOP VIEW BIT4 IPMB 6 (Not to Scale) 19 BIT5 IPPB 7 18 VPSIB 8 17 DENA NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 4. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1, 8, 13, 28 VPSIA, VPSIB, VPSOB, Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V). VPSOA 2, 3, 6, 7 IPPA, IPMA, IPMB, Differential Inputs. IPPB 4 ENBL Chip Enable. Pull this pin high to enable. 5, 20 ICOM, OCOM Input and Output Ground Pins. Connect these pins via the lowest possible impedance to ground. 9, 32 DECB, DECA VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to ground. 10, 31 OFSB, OFSA Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to ground to enable the correction loop. Tie this pin to ground to disable. 11, 30 CCMB, CCMA Connect These Nodes to Ground. 12, 29 VCMB, VCMA Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins from a low impedance source to change the output common-mode voltage. 14, 15, 26, 27 OPPB, OPMB, OPMA, Differential Outputs. OPPA 16, 17 DENB, DENA Data Enable. Pull these pins high to address each or both channels for parallel gain programming. These pins are not used in serial mode. 18, 19, 21, 22, 23, 24 BIT5, BIT4, BIT3, Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS), BIT2/SCLK, BIT1/SDAT, BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5 BIT0/CS are not used in serial mode. 25 SENB Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low for parallel gain programming mode. EPAD The exposed pad must be connected to ground. Rev. A | Page 7 of 28 DECA DECB OFSA OFSB CCMA CCMB VCMA VCMB VPSOA VPSOB OPPA OPPB OPMA OPMB SENB DENB 07584-028 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 AD8366 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted. 22 0.5 FREQUENCY = 3MHz T = +85°C A FREQUENCY = 50MHz T = +25°C A 0.4 20 T = –40°C A 0.3 T = +85°C 18 A T = +25°C A 0.2 T = –40°C A 16 0.1 14 0 12 –0.1 10 –0.2 8 –0.3 6 –0.4 –0.5 4 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 GAIN CODE GAIN CODE Figure 8. Gain Error vs. Gain Code, Error Normalized to 10 MHz Figure 5. Gain vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz 21.0 25 20.8 GAIN CODE 63 20 20.6 GAIN CODE 48 15 20.4 GAIN CODE 32 20.2 10 GAIN CODE 16 20.0 GAIN CODE 00 5 19.8 19.6 0 19.4 5 19.2 19.0 –10 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 100k 1M 10M 100M 1G TEMPERATURE (°C) FREQUENCY (Hz) Figure 9. Gain vs. Temperature at Maximum Gain at 10 MHz Figure 6. Frequency Response vs. Gain Code 1.0 1.0 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 –0.6 –0.6 –0.7 –0.7 –0.8 –0.8 –0.9 –0.9 –1.0 –1.0 0 10 2030405060 0 102030405060 GAIN CODE GAIN CODE Figure 10. Channel A-to-Channel B Phase Mismatch vs. Gain Code, Figure 7. Channel A-to-Channel B Amplitude Mismatch vs. Gain Code, 2 V p-p Output 2 V p-p Output Rev. A | Page 8 of 28 GAIN CHANNEL A, GAIN CHANNEL B (dB) AMPLITUDE MISMATCH (dB) GAIN (dB) 07584-005 07584-008 07584-007 GAIN ERROR (dB) GAIN (dB) PHASE MISMATCH (Degrees) 07584-009 07584-017 07584-006 AD8366 20 20 20 20 T = +85°C GAIN CODE 0 T = +85°C A A T = +25°C GAIN CODE 63 T = +25°C A A 18 18 18 18 T = –40°C T = –40°C A A 16 16 16 16 14 14 14 14 12 12 12 12 10 10 10 10 8 8 8 8 6 6 6 6 4 4 4 4 2 2 2 2 0 0 0 0 0 102030405060708090 100110120130140150 0 5 10 15 20 25 30 35 40 45 50 55 60 GAIN CODE FREQUENCY (MHz) Figure 11. OP1dB vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz Figure 14. OP1dB vs. Frequency at Gain Code 0 and Gain Code 63 50 50 60 45 45 55 GAIN CODE 63 GAIN CODE 32 40 40 50 35 35 45 30 30 40 25 25 35 20 20 30 15 15 25 10 GAIN CODE 0 10 20 T = +85°C T = +85°C A A 5 5 15 T = +25°C FREQUENCY = 10MHz T = +25°C CHANNEL A A A T = –40°C FREQUENCY = 50MHz T = –40°C CHANNEL B A A 0 0 10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) GAIN CODE Figure 15. OIP3 vs. Frequency, Gain Code 0, Gain Code 32, and Gain Code 63, Figure 12. OIP3 vs. Gain Code at 10 MHz and 50 MHz Frequency, 2 V p-p 2 V p-p Composite Output Composite Output 0 CHANNEL A T = +85°C A T = +85°C CHANNEL B FREQUENCY = 10MHz T = +25°C A –10 A –10 T = +25°C FREQUENCY = 50MHz T = –40°C A A T = –40°C A –20 GAIN CODE 0 –30 –30 –40 –50 –50 –60 –70 –70 –80 GAIN CODE 32 –90 GAIN CODE 63 –90 –100 –110 –110 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) GAIN CODE Figure 16. Two-Tone Output IMD3 vs. Frequency at Gain Code 0, Figure 13. Two-Tone Output IMD3 vs. Gain Code at 10 MHz and 50 MHz Gain Code 32, and Gain Code 63, 2 V p-p Composite Output Frequency, 2 V p-p Composite Output Rev. A | Page 9 of 28 OIP3 (dBm) OP1dB (dBm) IMD3 (dBc) OP1dB (dBVrms) 07584-042 OIP3 (dBVrms) 07584-030 07584-039 OP1dB (dBm) IMD3 (dBc) OIP3 (dBm) 07584-040 07584-041 OP1dB (dBVrms) 07584-029 AD8366 100 100 100 90 90 90 80 80 80 GAIN CODE 63 70 70 70 60 60 60 50 50 50 40 40 40 30 30 GAIN CODE 0 30 20 20 20 T = +85°C T = +85°C A A 10 10 10 T = +25°C FREQUENCY = 10MHz CHANNEL A T = +25°C A A T = –40°C FREQUENCY = 50MHz CHANNEL B T = –40°C A A 0 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 GAIN CODE FREQUENCY (MHz) Figure 17. OIP2 vs. Gain Code at 10 MHz and 50 MHz Frequency, Figure 20. OIP2 vs. Frequency at Gain Code 0 and Gain Code 63, 2 V p-p 2 V p-p Composite Output Composite Output 0 0 T = +85°C CHANNEL A A FREQUENCY = 10MHz T = +85°C A T = +25°C CHANNEL B –10 A FREQUENCY = 50MHz T = +25°C –10 A T = –40°C A T = –40°C A –20 –20 –30 –30 GAIN CODE 0 –40 –40 –50 –50 –60 –60 –70 –70 GAIN CODE 63 –80 –80 –90 –90 –100 –100 0 5 10 15 20 25 30 35 40 45 50 55 60 0 102030405060708090 100110120130140150 GAIN CODE FREQUENCY (MHz) Figure 18. Two-Tone Output IMD2 vs. Gain Code at 10 MHz and 50 MHz Figure 21. Two-Tone Output IMD2 vs. Frequency, Frequency, 2 V p-p Composite Output Gain Code 0 and Gain Code 63, 2 V p-p Composite Output 0 0 0 CHANNEL A T = +85°C GAIN CODE 0 HD2 A CHANNEL B –10 GAIN CODE 32 HD3 –10 T = +25°C A –10 GAIN CODE 63 T = –40°C A –20 –20 –20 –30 –30 –30 –40 –40 –40 –50 –50 –60 –50 –60 –70 –60 –70 –80 –70 –80 –90 –80 –90 –100 –90 –100 –110 –110 –100 –120 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1 10 100 1000 VCMA, VCMB (V) FREQUENCY (MHz) Figure 22. HD3/HD2 vs. V at 10 MHz, Gain Code 0, 2 V p-p Output Figure 19. Harmonic Distortion vs. Frequency at Gain Code 0, Gain Code 32, OCM and Gain Code 63, 2 V p-p Output Rev. A | Page 10 of 28 OIP2 (dBm) HD2, HD3 (dBc) IMD2 (dBc) 07584-045 07584-032 OIP2 (dBVrms) 07584-044 HD2, GAIN CODE 0 (dBc) IMD2 (dBc) OIP2 (dBm) HD3, GAIN CODE 0 (dBc) 07584-052 07584-043 07584-023 AD8366 0 60 T = +85°C GAIN CODE 0 A T = +25°C GAIN CODE 63 –10 A T = –40°C A 50 –20 –30 40 –40 –50 30 –60 –70 20 –80 –90 10 T = +85°C A –100 T = +25°C GAIN CODE 0 A T = –40°C GAIN CODE 63 A –110 0 –3 –2 –1 012345 –3 –2 –1 0 1 2 3 4 5 P PER TONE (dBm) P PER TONE (dBm) OUT OUT Figure 26. IMD3 vs. Output Power (POUT) at Minimum-to-Maximum Gain Figure 23. OIP3 vs. Output Power (POUT) at Minimum and Maximum Gain Codes, 10 MHz Frequency Codes, 10 MHz Frequency 0 100 GAIN CODE 0 T = +85°C A GAIN CODE 63 T = +25°C A –10 90 T = –40°C A –20 80 –30 70 –40 60 –50 50 –60 40 –70 30 –80 20 T = +85°C A –90 10 T = +25°C GAIN CODE 0 A T = –40°C GAIN CODE 63 A –100 0 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 –8 –7 –6 –5 –4 –3 –2 –1 012345 P PER TONE (dBm) P PER TONE (dBm) OUT OUT Figure 27. IMD2 vs. Output Power (P ) at Minimum and Maximum Gain Figure 24. OIP2 vs. Output Power (P ) at Minimum and Maximum Gain OUT OUT Codes, 10 MHz Frequency Codes, 10 MHz Frequency –60 –60 T = +85°C GAIN CODE 0 T = +85°C A A GAIN CODE 0 T = +25°C GAIN CODE 63 T = +25°C –65 A A GAIN CODE 63 –65 T = –40°C T = –40°C A A –70 –70 –75 –75 –80 –80 –85 –90 –85 –95 –90 –100 –95 –105 –100 –110 –105 –115 –120 –110 –5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 01 2345678 P (dBm) P (dBm) OUT OUT Figure 28. HD3 vs. Output Power (P ) for Gain Code 0 and Gain Code 63, OUT Figure 25. HD2 vs. Output Power (POUT) at Gain Code 0 and Gain Code 63, 10 MHz Frequency 10 MHz Frequency Rev. A | Page 11 of 28 HD2 (dBc) OIP2 (dBm) OIP3 (dBm) 07584-053 07584-060 07584-055 HD3 (dBc) IMD2 (dBc) IMD3 (dBc) 07584-054 07584-062 07584-061 AD8366 300 60 CHANNEL A T = +85°C A CHANNEL B T = +25°C 280 A 55 T = –40°C A GAIN CODE 63 260 50 GAIN CODE 47 GAIN CODE 48 GAIN CODE 31 240 45 GAIN CODE 32 GAIN CODE 15 40 220 GAIN CODE 16 GAIN CODE 0 200 35 180 30 25 160 20 140 120 15 10 100 0.1 1 10 100 1000 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (kHz) GAIN CODE Figure 29. Supply Current vs. Gain Code at 10 MHz Figure 32. Noise Spectral Density vs. Frequency 30 30 CHANNEL A CHANNEL B, FREQUENCY = 0.5MHz CHANNEL B CHANNEL A, FREQUENCY = 0.5MHz 28 28 CHANNEL B, FREQUENCY = 3MHz GAIN CODE 0 CHANNEL A, FREQUENCY = 3MHz GAIN CODE 15 26 26 CHANNEL B, FREQUENCY = 10MHz GAIN CODE 16 CHANNEL A, FREQUENCY = 10MHz GAIN CODE 31 CHANNEL B, FREQUENCY = 50MHz 24 GAIN CODE 32 24 CHANNEL A, FREQUENCY = 50MHz GAIN CODE 47 GAIN CODE 48 22 22 GAIN CODE 63 20 20 18 18 16 16 14 14 12 12 10 10 0.1 1 10 100 1000 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (kHz) GAIN CODE Figure 33. Noise Figure vs. Frequency Figure 30. Noise Figure vs. Gain Code at 0.5 MHz, 3 MHz, 10 MHz, and 50 MHz 40 7.5 280 3.0 CHANNEL A: R , GAIN CODE 0 OUT CHANNEL A: R , GAIN CODE 0 IN CHANNEL A: R , GAIN CODE 63 OUT CHANNEL A: R , GAIN CODE 63 IN 37 7.2 270 2.7 CHANNEL B: R , GAIN CODE 32 OUT CHANNEL B: R , GAIN CODE 32 IN CHANNEL A: L , GAIN CODE 0 OUT CHANNEL A: C , GAIN CODE 0 IN CHANNEL A: L , GAIN CODE 63 34 6.9 260 2.4 OUT CHANNEL A: C , GAIN CODE 63 IN CHANNEL B: L , GAIN CODE 32 OUT CHANNEL B: C , GAIN CODE 32 IN CHANNEL A: R , GAIN CODE 32 OUT CHANNEL A: R , GAIN CODE 32 31 6.6 250 IN 2.1 CHANNEL A: R , GAIN CODE 0 OUT CHANNEL A: R , GAIN CODE 0 IN CHANNEL B: R , GAIN CODE 63 IN 28 6.3 240 1.8 25 6.0 230 1.5 22 5.7 220 1.2 210 0.9 19 5.4 200 16 5.1 0.6 CHANNEL B: R , GAIN CODE 63 OUT CHANNEL A: C , GAIN CODE 32 CHANNEL A: L , GAIN CODE 32 IN OUT 13 4.8 190 0.3 CHANNEL B: C , GAIN CODE 0 CHANNEL B: L , GAIN CODE 0 IN OUT CHANNEL B: C , GAIN CODE 63 CHANNEL B: L , GAIN CODE 63 IN OUT 10 4.5 180 0 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) FREQUENCY (MHz) Figure 34. Differential Series Output Resistance and Inductance vs. Figure 31. Differential Parallel Input Resistance and Capacitance vs. Frequency Frequency Rev. A | Page 12 of 28 INPUT RESISTANCE (Ω) SUPPLY CURRENT (mA) NOISE FIGURE (dB) 07584-011 07584-038 INPUT CAPACITANCE (pF) 07584-013 OUTPUT RESISTANCE (Ω) NOISE SPECTRAL DENSITY (nV/√Hz) NOISE FIGURE (dB) 07584-012 07584-010 OUTPUT INDUCTNACE (nH) 07584-014 AD8366 0 140 PSRR GAIN CODE 0 130 PSRR GAIN CODE 63 –10 120 –20 110 100 –30 90 80 –40 70 –50 60 50 –60 40 –70 30 20 T = +85°C –80 A T = +25°C FREQUENCY = 10MHz 10 A T = –40°C FREQUENCY = 50MHz A –90 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 5 10 15 20 25 30 35 40 45 50 55 60 FREQUENCY (MHz) GAIN CODE Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 38. SFDR vs. Gain Code at 10 MHz and 50 MHz, 1 Hz Analysis Bandwidth 2.0 90 GAIN CODE 32 GAIN CODE 0 1.8 GAIN CODE 63 80 GAIN CODE 63 1.6 70 1.4 60 GAIN CODE 32 1.2 50 1.0 40 0.8 30 0.6 GAIN CODE 0 20 0.4 10 0.2 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 1M 10M 100M 1G FREQUENCY (MHz) FREQUENCY (Hz) Figure 36. Group Delay vs. Frequency at Gain Code 0, Gain Code 32, and Figure 39. Common-Mode Rejection Ratio (CMRR) vs. Frequency Gain Code 63 0 0 P = +10dBm MEASURED CHANNEL AT GAIN CODE 63 IN P = +5dBm MEASURED CHANNEL AT GAIN CODE 32 IN P = 0dBm MEASURED CHANNEL AT GAIN CODE 0 –20 IN –20 P = –5dBm IN P = –10dBm IN –40 –40 –60 –60 –80 –100 –80 –120 –100 –140 DRIVEN CHANNEL AT GAIN CODE 0 –120 –160 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 37. Channel-to-Channel Isolation vs. Frequency, Figure 40. Forward Leakage vs. Frequency, Part Disabled Channel A Driven, Channel B Measured Rev. A | Page 13 of 28 ISOLATION (dB) GROUP DELAY (ns) PSRR (dB) 07584-034 07584-021 07584-036 FORWARD LEAKAGE (dBm) CMRR (dB) SFDR (dB) 07584-037 07584-016 07584-031 AD8366 1.2 1.4 0pF 1.0 1.2 0pF 1.0 0.8 0.8 0.6 10pF 10pF 0.6 0.4 0.4 0.2 0.2 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 –1.2 –1.2 –5 –4 –3 –2 –1 0 12345 –5 –4 –3 –2 –1 01 2345 TIME (ns) TIME (ns) Figure 41. Large Signal Pulse Response, Gain Code 0, Input Signal 1.2 V p-p, Figure 44. Large Signal Pulse Response, Gain Code 63, Input Signal 240 mV p-p, 0 pF and 10 pF Capacitive Loading Conditions 0 pF and 10 pF Capacitive Loading Conditions 1 2 3 CH1 1VΩΩ CH2 100mV M1µs 5GS/s A CH1 1.60V M 200ns 250MS/s 4.0ns/pt A CH4 2.48V 100k pts CH3 50mVΩΩ CH4 1V T 4.02µs Figure 42. ENBL Time Domain Response Figure 45. Gain Step Time Domain Response, Minimum-to-Maximum Gain (Time Scale 200 ns/division), CH4 = Digital Control Inputs 0 –20 –40 –60 –80 –100 –120 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 43. Reverse Isolation (S12) vs. Frequency Rev. A | Page 14 of 28 S12 MAG (dB) OUTPUT VOLTAGE (V) 07584-065 07584-067 07584-033 OUTPUT VOLTAGE (V) 07584-064 07584-068 AD8366 CIRCUIT DESCRIPTION The AD8366 is a dual, differential, digitally controlled VGA OUTPUT DIFFERENTIAL OFFSET CORRECTION with 600 MHz of 3 dB bandwidth and a gain range of 4.5 dB to To prevent significant levels of offset from appearing at the 20.25 dB adjustable in 0.25 dB steps. Using a proprietary variable outputs of the AD8366, each digitally controlled VGA has a gain architecture, the AD8366 is able to achieve excellent linearity differential offset correction loop, as shown in Figure 47. This (45 dBm) and noise performance (11.7 nV/√Hz) at 10 MHz at loop senses any differential offset at the output and corrects for minimum gain. Intended for use in direct conversion systems, the it by injecting an opposing current at the input differential ground. part also includes dc offset correction that can be disabled easily The loop is able to correct for input dc offsets of up to ±20 mV. by grounding either OFSA or OFSB. In addition, the part offers Because the loop automatically nulls out any dc or low frequency an adjustable output common-mode range of 1.6 V to 3 V. offset, the effect of the loop is to introduce a high-pass corner into The main signal path is shown in Figure 46. It consists of an the transfer function of the digitally controlled VGA. The input transconductance, a variable-gain cell, and an output location of this high-pass corner depends on both the gain transimpedance amplifier. setting and the value of the capacitor connected to the OFSx pin VARIABLE (OFSA for DVGA A and OFSB for DVGA B) and is given by CURRENT-GAIN OUTPUT STAGE BUFFER GC 100Ω 12.5Ω 4300() 1.037 + 4000 INP OUTP f () kHz = 3dB,HP 2π() C +10 A Z I OFS INM OUTM 100Ω 12.5Ω VIRTUAL VIRTUAL where: GROUND GROUND GC is the gain code (a value from 0 to 63). Figure 46. Main Signal Path COFS is the value of the capacitance connected to OFSA or OFSB, The input transconductance provides a broadband 200 Ω in picofarads (pF). differential termination and converts the input voltage to a The offset correction loop can be disabled by grounding either current. This current is fed into the variable current-gain cell. OFSA or OFSB. The output of this cell goes into the transimpedance stage, which VARIABLE-GAIN OUTPUT generates the output voltage. The transimpedance is fixed at 500 Ω, STAGE BUFFER with a roughly 25 Ω differential output impedance. OUTP A Z I OUTM INPUTS The inputs to the digitally-controlled VGAs in the AD8366 are differential and can be either ac- or dc-coupled. The AD8366 INP g g synthesizes a 200 Ω (differential) input impedance, with a return m2 m1 INM loss (re: 200 Ω) of better than 10 dB to 200 MHz. The nominal common-mode input voltage to the part is V /2, but the AD8366 POS C OFFSET OFS COMPENSATION can be dc-coupled to parts with lower common modes if these LOOP parts can sink current. The amount of current sinking required Figure 47. Differential Offset Correction Loop depends on the input common-mode level and is given by OUTPUT COMMON-MODE CONTROL ISINK (per leg) = (VPOS/2 − VICM)/100 To interface to ADCs that require different input common-mode The input common-mode range is 1.5 V to VPOS/2. voltages, the AD8366 has an adjustable output common-mode OUTPUTS level. The output common-mode level is normally set to VPOS/2; The outputs of the digitally-controlled VGAs are differential and however, it can be changed between 1.6 V and 3 V by driving can be either ac- or dc-coupled. The AD8366 synthesizes a 25 Ω the VCMA pin or the VCMB pin. The input equivalent circuit differential output impedance, with a return loss (re: 25 Ω) of for the VCMA pin is shown in Figure 48; the VCMB pin has the better than 10 dB to 120 MHz. The nominal common-mode same input equivalent circuit. output voltage is V /2; however, it can be lowered or raised by POS 4kΩ driving the VCMA or VCMB pins. V /2 POS 500Ω VCMA Figure 48. Input Equivalent Circuit for VCMA Rev. A | Page 15 of 28 07584-071 07584-072 07584-073 AD8366 25.0 1.0 GAIN CONTROL INTERFACE 22.5 0.8 The AD8366 provides two methods of digital gain control: 20.0 0.6 serial or parallel. When the SENB pin is pulled low, the part 0.4 17.5 is in parallel gain control mode. In this mode, the two digitally controlled VGAs can be programmed simultaneously, or one at 0.2 15.0 a time, depending on the levels at DENA and DENB. If the SENB 0 12.5 pin is pulled high, the part is in serial gain control mode, with –0.2 10.0 Pin 24, Pin 23, and Pin 22 corresponding to the CS, SDAT, and –0.4 7.5 SCLK signals, respectively. –0.6 5.0 The voltage gain of the AD8366 is well approximated by –0.8 2.5 Gain (dB) = GainCode × 0.253 + 4.5 –1.0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 Note that at several major transitions (15 to 16, 31 to 32, and 47 to GAIN CODE 48), the gain changes significantly less (0 dB step) or significantly Figure 49. Gain and Gain Step Error vs. Gain Code at 10 MHz more (0.5 dB step) than the desired 0.25 dB step. This is inherent in the design of the part and is related to the partitioning of the variable gain block into a fine-gain and a coarse-gain section. Rev. A | Page 16 of 28 GAIN (dB) GAIN STEP ERROR (dB) 07584-063 AD8366 APPLICATIONS INFORMATION The output buffers of the AD8366 are low impedance around BASIC CONNECTIONS 25 Ω designed to drive ADC inputs. The output common-mode Figure 50 shows the basic connections for operating the AD8366. voltage defaults to VPOS/2; however, it can be adjusted by applying a A voltage from 4.75 V to 5.25 V should be applied to the supply desired external voltage to VCMA/VCMB. The common-mode pins. Each supply pin should be decoupled with at least one low voltage can be adjusted from 1.6 V to 3.0 V without significant inductance, surface-mount ceramic capacitor of 0.1 μF placed as harmonic distortion degradation. close as possible to the device. To enable the AD8366, the ENBL pin must be pulled high. Taking The differential input impedance is 200 Ω and sits at a nominal ENBL low disables the device, reducing current consumption to common-mode voltage of VPOS/2. The inputs can be dc-coupled approximately 3 mA at ambient temperature. or ac-coupled. If using direct dc coupling, the common-mode voltage, V , can range from 1.5 V to V /2. CM POS VPOS 0.01µF 8200pF CHANNEL A 0.01µF OUTPUT 0.01µF VPOS 0.1µF 0.1µF VPSIA BIT0/CS IPPA BIT1/SDAT CHANNEL A INPUT IPMA BIT2/SCLK VPOS ENBL BIT3 AD8366 ICOM OCOM 0.1µF 0.1µF IPMB BIT4 IPPB BIT5 CHANNEL B VPSIB DENA INPUT VPOS 0.1µF 0.1µF 0.01µF CHANNEL B OUTPUT 0.01µF 0.01µF 8200pF 0.01µF VPOS Figure 50. Basic Connections Rev. A | Page 17 of 28 PARALLEL/SERIAL CONTROL INTERFACE (PCI) 07584-046 DECB DECA OFSB OFSA CCMB CCMA VCMA VCMB VPSOB VPSOA OPPB OPPA OPMB OPMA DENB SENB AD8366 LC LOW- LC LOW- PASS PASS FILTER FILTER PAD 0 LO MATCHING FILTER RF TO NETWORK BALUN 90 ADC ADF4350 ADL5523 ADL5523 LC LOW- LC LOW- PASS PASS FILTER FILTER ADL5380 AD8366 Figure 51. Direct Conversion Receiver Block Diagram The image rejection ratio is the ratio of the intermediate frequency DIRECT CONVERSION RECEIVER DESIGN (IF) signal level produced by the desired input frequency to that A direct conversion receiver directly demodulates an RF modulated produced by the image frequency. The image rejection ratio is carrier to baseband frequencies, where the signals can be detected expressed in decibels (dB). Appropriate image rejection is critical and the conveyed information recovered. Eliminating the IF because the image power can be much higher than that of the stages and directly converting the signal to effectively zero IF desired signal, thereby plaguing the downconversion process. results in reduced component count. The image problems Amplitude and phase balance between the I/Q channels are associated with the traditional superheterodyne architectures critical for high levels of image rejection. Image rejection of can be ignored as well. However, there are different challenges greater than 47 dB was measured for the combined ADL5380 associated with direct conversion that include LO leakage, dc and the AD8366 for a 5 MHz baseband frequency, as seen in offsets, quadrature imperfections, and image rejection. LO Figure 53. This level of image rejection corresponds to a ±0.5° leakage causes self mixing that results in squaring of the LO phase mismatch and a ±0.05 dB of amplitude mismatch for the waveform which generates a dc offset that falls in band for the combined ADL5380 and AD8366. Looking back to Figure 7 and direct conversion receiver. Residual dc offsets create a similar Figure 10, the AD8366 exhibits only ±0.05 dB of amplitude mismatch interfering signal that falls in band. I/Q amplitude and phase o and ±0.05 of phase mismatch, thus implying that the AD8366 mismatch lead to degraded SNR performance and poor image does not introduce additional amplitude and phase imbalance. rejection in the direct conversion system. Figure 51 shows the 55 block diagram for a direct conversion receiver system. QUADRATURE ERRORS AND IMAGE REJECTION 50 An overall RF-to-baseband EVM performance was measured 45 with the ADL5380 IQ demodulator preceding the AD8366, as shown in Figure 56. In this setup, no LC low-pass filters were used 40 between the ADL5380 and AD8366. A 1900 MHz W-CDMA RF signal with a 3.84 MHz symbol rate was used. The local oscillator 35 (LO) is set at 1900 MHz to obtain a zero IF baseband signal. The gain of the AD8366 is set to maximum gain (~20.25 dB). 30 Figure 52 shows the SNR vs. the input power of the cascaded system for a 5 MHz analysis bandwidth. The broad input power 25 range over which the system exhibits strong SNR performance 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 reflects the superior dynamic range of the AD8366. RF FREQUENCY (MHz) 45 Figure 53. Image Rejection vs. RF Frequency 40 35 30 25 20 15 10 5 0 –75 –65 –55 –45 –35 –25 –15 –5 5 INPUT POWER (dBm) Figure 52. SNR vs. RF Input Power Level Rev. A | Page 18 of 28 SNR (dB) 07584-048 IMAGE REJECTION (dB) 07584-047 07584-049 AD8366 –20 LOW FREQUENCY IMD3 PERFORMANCE GC63 GC0 To measure the IMD3 data at low frequencies, wideband –30 transformer baluns from North Hills Signal Processing Corp. –40 were used, specifically the 0301BB and the 0520BB. Figure 55 shows the IMD3 performance vs. frequency for a 2 V p-p –50 composite output. The IMD3 performance was also measured for the combined ADL5380 and AD8366 system, as shown in –60 Figure 56, with an FFT spectrum analyzer. An FFT spectrum –70 analyzer works very similar to a typical ADC, the input signal is digitized at a high sampling rate that is then passed through an –80 antialiasing filter. The resulting signal is transformed to the frequency domain using fast Fourier transforms (FFT). –90 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 The single-ended RF signal from the source generator is converted FREQUENCY (MHz) to a differential signal using a balun that gets demodulated and Figure 54. System IMD3 vs. Frequency, 2 V p-p Composite at the Output of the AD8366 down converted to differential IF signals through the ADL5380. 50 0 This differential IF signal drives the AD8366, thus eliminating FREQUENCY = 1MHz FREQUENCY = 3MHz the need for low frequency baluns. Figure 54 shows the IMD3 –10 45 performance vs. frequency over the 500 kHz to 5 MHz range 40 –20 for minimum and maximum gain code setting on the AD8366. 35 –30 During the measurements, the output was set to 2 V p-p composite. –40 30 25 –50 20 –60 –70 15 10 –80 5 –90 0 –100 0 5 10 15 20 25 30 35 40 45 50 55 60 GAIN CODE Figure 55. OIP3 on Low Frequency, 2 V p-p Composite Rev. A | Page 19 of 28 OIP3 (dBm) IMD3 (dBc) 07584-018 IMD3 (dBc) 07584-035 AD8366 RFIN BALUN 100pF 100pF V VPOS POS 0.1µF 100pF 24 23 22 21 20 19 1 18 GND GND 2 GND GND 17 3 QHI 16 IHI ADL5380 4 QLO 15 ILO 5 GND 14 GND V 6 VCC 13 POS V VCC POS 0.1µF 100pF 100pF 0.1µF 7 8 9 10 11 12 100pF 100pF BALUN LO V V POS POS V POS 0.1µF 0.1µF 0.1µF 0.01µF 0.01µF C C OFS OFS 0.01µF 0.01µF OFSB OFSA CCMB CCMA VCMB VCMA AD8366 V POS VPSOB VPSOA V POS 0.1µF 0.01µF 0.01µF 0.1µF OPPB OPPA OPMB OPMA 200Ω 200Ω I CHANNEL Q CHANNEL PARALLEL/SERIAL CONTROL INTERFACE Figure 56. ADL5380 and AD8366 Interface Block Diagram Rev. A | Page 20 of 28 DENB DECB VPSIB DENA ENBL VCC IPPB BIT5 GND GND IPMB BIT4 LOIP RFIP OCOM ICOM ENBL BIT3 LOIN RFIN BIT2 IPMA GND GND BIT1 IPPA NC ADJ BIT0 VPSIA SENB DECA 07584-050 AD8366 The order and type of filter network depends on the desired high BASEBAND INTERFACE frequency rejection required, pass-band ripple, and group delay. In most direct-conversion receiver designs, it is desirable to select a Figure 57 shows the schematic for a typical fourth-order, Chebyshev, wanted carrier within a specified band. The desired channel can be demodulated by tuning the LO to the appropriate carrier frequency. low-pass filter. Table 4 shows the typical values of the filter If the desired RF band contains multiple carriers of interest, the components for a fourth-order, Chebyshev, low-pass filter with adjacent carriers would also be down converted to a lower IF a differential source impedance of 25 Ω and a differential load frequency. These adjacent carriers can be a problem if they are impedance of 200 Ω. L1 L3 large relative to the desired carrier because they can overdrive the baseband signal detection circuitry. As a result, it is often necessary to insert a filter to provide sufficient rejection of the Z C1 C2 Z SOURCE LOAD adjacent carriers. It is necessary to consider the overall source and load impedance L2 L4 presented by the AD8366 and the ADC input to design the Figure 57. Schematic of a Fourth-Order, Chebyshev, Low-Pass Filter filter network. The differential baseband output impedance of the AD8366 is 25 Ω and is designed to drive a high impedance ADC input. It may be desirable to terminate the ADC input down to the lower impedance by using a terminating resistor, such as 500 Ω. The terminating resistor helps to better define the input impedance at the ADC input at the cost of a slightly reduced gain. Table 4. Typical Values for Fourth-Order, Chebyshev, Low-Pass Filter 3 dB Corner (MHz) ZSOURCE (Ω) ZLOAD (Ω) L1 (μH) L2 (μH) L3 (μH) L4 (μH) C1 (pF) C2 (pF) 5 25 200 6.6 6.6 6.0 6.0 220 180 10 25 200 3.3 3.3 3 3 110 90 28 25 200 1.2 1.2 1 1 39 33 Rev. A | Page 21 of 28 07584-051 AD8366 CHARACTERIZATION SETUPS Figure 58 and Figure 59 are characterization setups used the output of the device under test (DUT), and 2 V p-p composite extensively to characterize the AD8366. Characterization was output for two-tone measurements. To measure harmonic done on single-ended and differential evaluation boards. The distortion, band-pass and band-reject filters were used on bulk of the characterization was done using an automated VEE the input and output of the DUT. program to control the equipment as shown in Figure 58. This Figure 59 shows the setup used to make differential measurements. setup was used to measure P1dB, OIP3, OIP2, IMD2, IMD3, All measurements on this setup were done in a 50 Ω system and harmonic distortion, gain, gain error, supply current, and noise post processed to reference the measurements to a 200 Ω system. density. All measurements were done with a 200 Ω load. All balun, Gain and phase mismatch were measured with 2 V p-p on the output matching network, and filter losses were de-embedded. output, and small signal frequency responses were measured Gain error was measured with constant input power. All other with −30 dBm on the input of the DUT. measurements were done on 2 V p-p (4 dBm, re: 200 Ω) on Rev. A | Page 22 of 28 AD8366 AGILENT E8251D AGILENT E8251A AGILENT E4440A SIGNAL GENERATOR SIGNAL GENERATOR SPECTRUM ANALYZER COMBINER RF SWITCH IEEE MATRIX KEITHLEY RF SWITCH IEEE MATRIX KEITHLEY BAND PASS BAND REJECT CH2 CH1 CH2 CH1 RF IN RF IN RF OUT RF OUT AD8366 EVALUATION BOARD AGILENT E3631A POWER AGILENT 34401A DMM SUPPLY AGILENT 34980A (IN DC I MODE FOR SUPPLY MULTIFUNCTION SWITCH CURRENT MEASUREMENT) (WITH 34950 AND 34921 MODULES) Figure 58. Characterization Setup, Single-Ended Measurements Rev. A | Page 23 of 28 IEEE IEEE IEEE IEEE IEEE IEEE 07584-069 AD8366 Rohde & Schwarz ZVA8 RF SWITCH MATRIX KEITHLEY CH2 CH2 IP IP AD8366 CH2 EVALUATION BOARD CH2 IM IM CH1 CH1 CH2 CH2 OP OM OP OM AGILENT E3631A POWER SUPPLY Figure 59. Characterization Setup, Differential Measurements Rev. A | Page 24 of 28 07584-070 AD8366 EVALUATION BOARD The schematic for the AD8366 evaluation board is shown in Figure 60. The board can be used for single-ended or differential baseband analysis. The default configuration of the board is for single-ended baseband analysis. C26 C27 R39 R38 T3 T4 R35 R34 R37 R36 R30 R29 R33 R31 C24 C25 R71 R70 R69 R74 R73 R72 R67 R65 R80 R68 C33 C29 C31 OPMA OPMB C28 OPPA OPPB VPSO_A VPSOA VPSOB VPSO_B AD8366 VCMA VCMB VCMA VCMB C10 C9 CCMA CCMB S12 S11 OFSA OFSB C12 C3 C2 C11 VPSI_A VPSI_B C22 C15 C16 R54 R50 R48 R63 R62 R58 R45 R44 R46 R47 C20 C5 R14 R15 T1 T2 C23 R13 R16 R17 R20 R18 R21 R12 R19 C30 C13 C14 C18 C21 S1 C1 Figure 60. Evaluation Board Schematic Rev. A | Page 25 of 28 VPSI_B VPSI_A VPSI_A R28 R79 R22 R24 VCMB ENBL R10 VCMA R3 R5 VPOS VPSI_A VPSO_A R4 R6 VPSI_B VPSO_B VPSI_A R40 S4 VPSI_A R61 S9 DECA SENB BIT0 VPSIA VPSI_A R41 BIT1 IPPA S2 VPSI_A BIT2 IPMA BIT2 R42 S6 BIT3 ENBL ENBL OCOM ICOM VPSI_A R43 BIT4 S8 IPMB VPSI_A R64 BIT5 IPPB S10 VPSIB DENA DECB DENB VPSI_A R53 S5 VPSI_A R57 S7 VPSI_A R26 S3 R32 U1 BIT2 07584-056 AD8366 Figure 61. AD8366 Evaluation Board Printed Circuit Board (PCB), Top Side Figure 62. AD8366 Evaluation Board PCB, Bottom Side Table 5. Evaluation Board Configuration Options Components Function Default Conditions C1, C13 to C16, R3 to R6 Power supply decoupling. Nominal supply decoupling consists of a C1 = 0.1 μF (size 0603), 0.1 μF capacitor to ground followed by 0.01 μF capacitors to ground C13 to C16 = 0.01 μF (size 0402), positioned as close to the device as possible. R3 to R6 = 0 Ω (size 0603) T1, T2, C5, C18, C20, C21, Input interface. The default configuration of the evaluation board is T1, T2 = ADT4-6T+ (Mini-Circuits), R12 to R21, R44 to R48, for single-ended operation. T1 and T2 are 4:1 impedance ratio baluns to C5, C20 = 0.1 μF (size 0402), R50, R54, R58, R62, R63 transform a 50 Ω single-ended input into a 200 Ω balanced differential C18, C21 = do not install, signal. R12 to R14 and R15, R16, and R19 are populated for appropriate R12 to R16, R19, R44 to R47 = 0 Ω balun interface. R44 to R48 and R50, R54, R58, R62, and R63 are (size 0402), provided for generic placement of matching components. C5, C18, R17, R18, R20, R21,R48, R50, R54, C20, and C21 are balun decoupling capacitors. R17, R18, R20, and R58, R62, and R63 = open (size 0402) R21 can be populated with 0 Ω, and the balun interfacing resistors can be removed to bypass T1 and T2 for differential interfacing. T3, T4, C24 to C27, R29 to Output interface. The default configuration of the evaluation board T3, T4 = ADT4-6T+ (Mini-Circuits), R31, R33 to R39, R65, R67 is for single-ended operation. T3 and T4 are 4:1 impedance ratio C24, C25 = 0.1 μF (size 0402), to R74, R80 baluns to transform a 50 Ω single-ended output into a 200 Ω balanced C26, C27 = do not install, differential load. R29 to R31, R33, R38, and R39 are populated for R29 to R31, R33, R38, R39, R65, R67, appropriate balun interface. R65, R67 to R74, and R80 are provided R68, R80 = 0 Ω (size 0402), for generic placement of matching components. C24, C25, C26, and R34 to R37, R69 to R74 = open (size 0402) C27 are balun decoupling capacitors. R34 to R37 can be populated with 0 Ω, and the balun interfacing resistors can be removed to bypass T3 and T4 for differential interfacing. Rev. A | Page 26 of 28 07584-059 07584-058 AD8366 Components Function Default Conditions S1, S5, S7, R53, R57, R79, Enable interface includes device enable and data enable. S1, S5, S7 = installed, C29, C30, C31 R53, R57 = 5.1 kΩ (size 0603), Device enable. The AD8366 is enabled by applying a logic high R79 = 10 kΩ (size 0402), voltage to the ENBL pin. The device is enabled when the S1 switch is C30 = 0.01 μF (size 0402), set in the down position (high), connecting the ENBL pin to VPSI_A. C29, C31 = 1500 pF (size 0402) Data enable. DENA and DENB are used to enable the data path for Channel A and Channel B, respectively. Channel A is enabled when the S5 switch is set in the down position (high), connecting the DENA pin to VPSI_A. Likewise, Channel B is enabled when the S7 switch is set in the down position (high), connecting the DENB pin to VPSI_A. Both channels are disabled by setting the switches to the up position, connecting the DENA and DENB pins to GND. S2, S3, S4, S6, S8, S9, S10 Serial/parallel interface control. SENB is used to set the data control S2, S3, S4, S6, S8, S9, S10 = installed, R26, R32, R40 to R43, R61, either in parallel or serial mode. The parallel interface is enabled when R26 = 698 kΩ (size 0603), R64, C23, C33, U1 S4 is in the up position (low). The serial interface is enabled when S4 R32, R40 to R43, R61, R64 = 5.1 kΩ is in the down position (high). (size 0603), C23, C33 = 1500 pF (size 0603), For SENB pulled low, BIT0 (S9) sets 0.25 dB gain, BIT1 (S2) sets 0.5 dB U1 = SN74LVC2G14 inverter chip gain, BIT2 (S3) sets 1 dB gain, BIT3 (S6) sets 2 dB gain, BIT4 (S8) sets 4 dB gain, and BIT5 (S10) sets 8 dB gain. For SENB pulled high, BIT0 becomes a chip select (CS), BIT1 becomes a serial data input (SDAT), and BIT2 becomes serial clock (SCLK). BIT3 to BIT5 are not used in serial mode. U1 is used to deglitch the SCLK signal. S11, S12, C9, C10 DC offset correction loop compensation. S11, S12 = installed, C9, C10 = 8200 pF (size 0402) The dc offset correction loop is enabled (high) with S11 and S12 for Channel A and Channel B, respectively, when the enabled pins, OFSA/ OFSB, are connected to ground through the C9 and C10 capacitors. When disabled (low), OFSA/OFSB are connected to ground directly. R10, R22, R24, R28, C22, Output common-mode setpoint. The output common mode on R10, R24 = 10 kΩ potentiometers, C28 Channel A and Channel B can be set externally when applied to R22, R28 = 0 Ω, VCMA and VCMB. The resistive change through the potentiometer C22, C28 = 0.1 μF (size 0402) sets a variable VCMA voltage. If left open, the output common mode defaults to V /2. POS C2, C3, C11, C12 Reference output decoupling capacitor to circuit common. C2, C3 = 0.1 μF (size 0402), C11, C12 = 0.01 μF (size 0402) Rev. A | Page 27 of 28 AD8366 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 0.50 PIN 1 TOP 2.85 INDICATOR BSC EXPOSED 4.75 VIEW 2.70 SQ PAD BSC SQ (BOTTOM VIEW) 2.55 0.50 17 0.40 8 16 9 0.30 0.20 MIN 3.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS 0.30 SEATING SECTION OF THIS DATA SHEET. COPLANARITY 0.20 REF PLANE 0.25 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8366ACPZ-R7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 AD8366-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07584-0-3/11(A) Rev. A | Page 28 of 28 032807-A