ANALOG DEVICES AD8352

2 GHz Ultralow Distortion Differential RF/IF Amplifier AD8352 FEATURES FUNCTIONAL BLOCK DIAGRAM −3 dB bandwidth of 2.2 GHz (A = 10 dB) V VCM ENB BIAS CELL Single resistor gain adjust: 3 dB ≤ A ≤ 25 dB V VCC Single resistor and capacitor distortion adjust RGP Input resistance: 3 kΩ, independent of gain (A ) V Differential or single-ended input to differential output RDP Low noise input stage: 2.7 nV/√Hz RTI @ A = 10 dB V + VOP VIP Low broadband distortion C D R R G D 10 MHz: −86 dBc HD2, −82 dBc HD3 VIN 70 MHz: −84 dBc HD2, −82 dBc HD3 – VON 190 MHz: −81 dBc HD2, −87 dBc HD3 RDN OIP3 of 41 dBm @ 150 MHz GND Slew rate: 8 V/ns RGN AD8352 Fast settling and overdrive recovery of <2 ns Figure 1. Single-supply operation: 3 V to 5.5 V Low power dissipation: 37 mA typical @ 5 V Power-down capability: 5 mA @ 5 V –60 44 Fabricated using the high speed XFCB3 SiGe process –65 42 –70 40 APPLICATIONS Differential ADC drivers –75 38 Single-ended-to-differential conversion –80 36 RF/IF gain blocks SAW filter interfacing –85 34 –90 32 –95 30 –100 28 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY (MHz) Figure 2. Third Harmonic Distortion (HD3) and IP3 vs. Frequency, Measured Differentially GENERAL DESCRIPTION The AD8352 is a high performance differential amplifier The device is optimized for wideband, low distortion performance optimized for RF and IF applications. It achieves better than at frequencies beyond 500 MHz. These attributes, together with 80 dB SFDR performance at frequencies up to 200 MHz, and its wide gain adjust capability, make this device the amplifier of 65 dB beyond 500 MHz, making it an ideal driver for high choice for general-purpose IF and broadband applications speed 12-bit to 16-bit analog-to-digital converters (ADCs). where low distortion, noise, and power are critical. It is ideally suited for driving not only ADCs but also mixers, pin diode Unlike other wideband differential amplifiers, the AD8352 has attenuators, SAW filters, and multi-element discrete devices. The buffers that isolate the gain setting resistor (R ) from the signal G device is available in a compact 3 mm × 3 mm, 16-lead LFCSP inputs. As a result, the AD8352 maintains a constant 3 kΩ input and operates over a temperature range of −40°C to +85°C. resistance for gains of 3 dB to 25 dB, easing matching and input drive requirements. The AD8352 has a nominal 100 Ω differential output resistance. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. HD3 (dBc) IP3 (dBm) 05728-002 05728-001 AD8352 TABLE OF CONTENTS Features .............................................................................................. 1  Gain and Distortion Adjustment (Differential Input) .......... 11  Applications ....................................................................................... 1  Single-Ended Input Operation ................................................. 12  Functional Block Diagram .............................................................. 1  Narrow-Band, Third-Order Intermodulation Cancellation . 13  General Description ......................................................................... 1  High Performance ADC Driving ............................................. 14  Revision History ............................................................................... 2  Layout and Transmission Line Effects ..................................... 15  Specif ica t ions ..................................................................................... 3  Evaluation Board ............................................................................ 16  Noise Distortion Specifications .................................................. 4  Evaluation Board Loading Schemes ........................................ 16  Absolute Maximum Ratings ............................................................ 6  Soldering Information ............................................................... 16  ESD Caution .................................................................................. 6  Evaluation Board Schematics ................................................... 17  Pin Configuration and Function Descriptions ............................. 7  Outline Dimensions ....................................................................... 19  Typical Performance Characteristics ............................................. 8  Ordering Guide .......................................................................... 19  Applications Information .............................................................. 11  REVISION HISTORY 7/08—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Figure 21 ...................................................................... 10 Changes to Table 9 .......................................................................... 16 Added Soldering Information Section ......................................... 16 Changes to Figure 38 ...................................................................... 17 Changes to Ordering Guide .......................................................... 19 9/06—Rev. 0 to Rev. A Changes to Absolute Maximum Ratings ....................................... 6 Inserted Figure 10, Figure 11, and Figure 13 ................................ 9 Inserted Figure 17, Figure 18, and Figure 21 .............................. 10 Changes to Figure 34 ...................................................................... 14 Changes to Table 9 .......................................................................... 16 Changes to Figure 38 ...................................................................... 18 Changes to Ordering Guide .......................................................... 19 1/06—Revision 0: Initial Version Rev. B | Page 2 of 20 AD8352 SPECIFICATIONS VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), f = 100 MHz, T = 25°C; parameters specified differentially (in/out), unless otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6). Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth AV = 6 dB, VOUT ≤ 1.0 V p-p 2500 MHz AV = 10 dB, VOUT ≤ 1.0 V p-p 2200 MHz AV = 14 dB, VOUT ≤ 1.0 V p-p 1800 MHz Bandwidth for 0.1 dB Flatness 3 dB ≤ A ≤ 20 dB, V ≤ 1.0 V p-p 190 MHz V OUT Bandwidth for 0.2 dB Flatness 3 dB ≤ A ≤ 20 dB, V ≤ 1.0 V p-p 300 MHz V OUT Gain Accuracy Using 1% resistor for R , 0 dB ≤ A ≤ 20 dB ±1 dB G V Gain Supply Sensitivity VS ± 5% 0.06 dB/V Gain Temperature Sensitivity −40°C to +85°C 4 mdB/°C Slew Rate RL = 1 kΩ, VOUT = 2 V step 9 V/ns R = 200 Ω, V = 2 V step 8 V/ns L OUT Settling Time 2 V step to 1% <2 ns Overdrive Recovery Time VIN = 4 V to 0 V step, VOUT ≤ ±10 mV <3 ns Reverse Isolation (S12) −80 dB INPUT/OUTPUT CHARACTERISTICS Common-Mode Nominal VCC/2 V Voltage Adjustment Range 1.2 to 3.8 V Maximum Output Voltage Swing 1 dB compressed 6 V p-p Output Common-Mode Offset Referenced to VCC/2 −100 +20 mV Output Common-Mode Drift −40°C to +85°C 0.25 mV/°C Output Differential Offset Voltage −20 +20 mV Common-Mode Rejection Ratio (CMRR) 57 dB Output Differential Offset Drift −40°C to +85°C 0.15 mV/°C Input Bias Current ±5 μA Input Resistance 3 kΩ Input Capacitance (Single Ended) 0.9 pF Output Resistance 100 Ω Output Capacitance 3 pF POWER INTERFACE Supply Voltage 3 5 5.5 V ENB Threshold 1.5 V ENB Input Bias Current ENB at 3 V 75 nA ENB at 0.6 V −125 μA Quiescent Current ENB at 3 V 35 37 39 mA ENB at 0.6 V 5.3 mA Rev. B | Page 3 of 20 AD8352 NOISE DISTORTION SPECIFICATIONS VS = 5 V, RL = 200 Ω differential, RG = 118 Ω (AV = 10 dB), VOUT = 2 V p-p composite, T = 25°C; parameters specified differentially, unless otherwise noted. CD and RD are selected for differential broadband operation (see Table 5 and Table 6). See the Applications Information section for single-ended-to-differential performance characteristics. Table 2. Parameter Conditions Min Typ Max Unit 10 MHz 1 Second/Third Harmonic Distortion RL = 1 kΩ, VOUT = 2 V p-p −88/−95 dBc R = 200 Ω, V = 2 V p-p −86/−82 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 9.5 MHz, f = 10.5 MHz 38 dBm L 1 2 Third-Order IMD −86 dBc RL = 1 kΩ, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite RL = 200 Ω, f1 = 9.5 MHz, f2 = 10.5 MHz, −81 dBc V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.7 dBm 70 MHz Second/Third Harmonic Distortion R = 1 kΩ, R = 178 Ω, V = 2 V p-p −83/−84 dBc L G OUT R = 200 Ω, R = 115 Ω, V = 2 V p-p −84/−82 dBc L G OUT Output Third-Order Intercept RL = 200 Ω, f1 = 69.5 MHz, f2 = 70.5 MHz 40 dBm Third-Order IMD RL = 1 kΩ, f1 = 69.5 MHz, f2 = 70.5 MHz, −91 dBc VOUT = 2 V p-p composite R = 200 Ω, f = 69.5 MHz, f = 70.5 MHz, −83 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.7 dBm 100 MHz Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −83/−83 dBc L OUT RL = 200 Ω, VOUT = 2 V p-p −84/−82 dBc Output Third-Order Intercept RL = 200 Ω, f1 = 99.5 MHz, f2 = 100.5 MHz 40 dBm Third-Order IMD R = 1 kΩ, f = 99.5 MHz, f = 100.5 MHz, −91 dBc L 1 2 V = 2 V p-p composite OUT R = 200 Ω, f = 99.5 MHz, f = 100.5 MHz, −84 dBc L 1 2 VOUT = 2 V p-p composite Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.6 dBm 140 MHz Second/Third Harmonic Distortion RL = 1 kΩ, VOUT = 2 V p-p −83/−82 dBc RL = 200 Ω, VOUT = 2 V p-p −82/−84 dBc Output Third-Order Intercept R = 200 Ω, f = 139.5 MHz, f = 140.5 MHz 41 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 139.5 MHz, f = 140.5 MHz, −89 dBc L 1 2 VOUT = 2 V p-p composite RL = 200 Ω, f1 = 139.5 MHz, f2 = 140.5 MHz, −85 dBc VOUT = 2 V p-p composite Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.5 dBm Rev. B | Page 4 of 20 AD8352 Parameter Conditions Min Typ Max Unit 190 MHz Second/Third Harmonic Distortion RL = 1 kΩ, VOUT = 2 V p-p −82/−85 dBc RL = 200 Ω, VOUT = 2 V p-p −81/−87 dBc Output Third-Order Intercept R = 200 Ω, f = 180.5 MHz, f = 190.5 MHz 39 dBm L 1 2 Third-Order IMD R = 1 kΩ, f = 180.5 MHz, f = 190.5 MHz, −83 dBc L 1 2 VOUT = 2 V p-p composite RL = 200 Ω, f1 = 180.5 MHz, f2 = 190.5 MHz, −81 dBc VOUT = 2 V p-p composite Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.4 dBm 240 MHz Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −82/−76 dBc L OUT R = 200 Ω, V = 2 V p-p −80/−73 dBc L OUT Output Third-Order Intercept R = 200 Ω, f = 239.5 MHz, f = 240.5 MHz 36 dBm L 1 2 Third-Order IMD RL = 1 kΩ, f1 = 239.5 MHz, f2 = 240.5 MHz, −85 dBc VOUT = 2 V p-p composite RL = 200 Ω, f1 = 239.5 MHz, f2 = 240.5 MHz, −77 dBc V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 15.3 dBm 380 MHz 2 Second/Third Harmonic Distortion R = 1 kΩ, V = 2 V p-p −72/−68 dBc L OUT RL = 200 Ω, VOUT = 2 V p-p −74/−69 dBc Output Third-Order Intercept RL = 200 Ω, f1 = 379.5 MHz, f2 = 380.5 MHz 33 dBm Third-Order IMD RL = 1 kΩ, f1 = 379.5 MHz, f2 = 380.5 MHz, −74 dBc V = 2 V p-p composite OUT R = 200 Ω, f = 379.5 MHz, f = 380.5 MHz, −70 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 14.6 dBm 500 MHz 2 Second/Third Harmonic Distortion RL = 200 Ω, VOUT = 2 V p-p −71/−64 dBc Output Third-Order Intercept RL = 200 Ω, f1 = 499.5 MHz, f2 = 500.5 MHz 28 dBm Third-Order IMD R = 200 Ω, f = 499.5 MHz, f = 500.5 MHz, −61 dBc L 1 2 V = 2 V p-p composite OUT Noise Spectral Density (RTI) 2.7 nV/√Hz 1 dB Compression Point (RTO) 13.9 dBm 1 When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer, such as Mini-Circuits® ADT1-1WT to obtain the low frequency balance required for differential HD2 cancellation. 2 C and R can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, C and R components are not required. D D D D Rev. B | Page 5 of 20 AD8352 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating ESD CAUTION Supply Voltage, VCC 5.5 V VIP, VIN VCC + 0.5 V Internal Power Dissipation 210 mW θJA 91.4°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 6 of 20 AD8352 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR RDP 1 12 GND RGP 2 11 VOP AD8352 RGN 3 10 VON TOP VIEW (Not to Scale) RDN 4 9GND Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RDP Positive Distortion Adjust. 2 RGP Positive Gain Adjust. 3 RGN Negative Gain Adjust. 4 RDN Negative Distortion Adjust. 5 VIN Balanced Differential Input. This pin is biased to VCM, typically ac-coupled. 6, 7, 9, 12 GND Ground. Connect this pin to low impedance GND. 8, 13 VCC Positive Supply. 10 VON Balanced Differential Output. This pin is biased to VCM, typically ac-coupled. 11 VOP Balanced Differential Output. This pin is biased to VCM, typically ac-coupled. 14 VCM Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output. Typically decoupled to ground with a 0.1 μF capacitor. With no reference applied, input and output common mode floats to midsupply (VCC/2). 15 ENB Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. 16 VIP Balanced Differential Input. This pin is biased to VCM, typically ac-coupled. Rev. B | Page 7 of 20 05728-003 VIN 5 16 VIP 15 ENB GND 6 GND 7 14 VCM VCC 8 13 VCC AD8352 TYPICAL PERFORMANCE CHARACTERISTICS 25 30 25 R =20Ω 20 G R =43Ω G 20 15 R = 100Ω G R = 100Ω G 15 10 R = 182Ω G 10 R = 520Ω G R = 383Ω G 5 5 R = 715Ω G 0 0 –5 –5 10 100 1k 10k 10 100 1k 10k FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Gain vs. Frequency for a 200 Ω Differential Load with Baluns, Figure 7. Gain vs. Frequency for a 1 kΩ Differential Load Without Baluns, AV = 18 dB, 12 dB, and 6 dB RD/CD Open, AV = 25 dB, 14 dB, 10 dB, 6 dB, and 3 dB 25 13.0 11.0 R = 1kΩ L R = 182Ω 12.5 G 10.5 –40°C T = 0.002dB/°C C 20 R =62Ω G 12.0 10.0 +85°C +25°C 11.5 9.5 15 R = 190Ω G 11.0 9.0 10 10.5 8.5 –40°C R =3kΩ G 10.0 8.0 5 +85°C 9.5 7.5 R = 200Ω +25°C L 9.0 7.0 R = 118Ω G 0 T = 0.004dB/°C C 8.5 6.5 6.0 –5 8.0 10 100 1k 10k 10 100 1k 10k FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Gain vs. Frequency for a 1 kΩ Differential Load with Baluns, Figure 8. Gain vs. Frequency over Temperature (−40°C, +25°C, +85°C) AV = 18 dB, 12 dB, and 6 dB Without Baluns, A = 10 dB, R = 200 Ω and 1 kΩ V L 25 80 R =19Ω G 70 20 R = 200Ω L 60 R =64Ω 15 G R =1kΩ 50 L R = 118Ω G 10 40 R = 232Ω G 5 30 R = 392Ω G 0 20 –5 10 10 100 1k 10k 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Gain vs. Frequency for a 200 Ω Differential Load Without Baluns, Figure 9. CMRR vs. Frequency, R = 200 Ω and 1 kΩ, L RD/CD Open, AV = 22 dB, 14 dB, 10 dB, 6 dB, and 3 dB Differential Source Resistance Rev. B | Page 8 of 20 GAIN (dB) GAIN (dB) GAIN (dB) 05728-038 05728-037 05728-036 GAIN (dB) CMRR (dB) GAIN (dB) 05728-039 05728-043 05728-040 GAIN (dB) AD8352 50 5.0 16.5 100MHz 45 4.5 16.0 70MHz 140MHz OIP3 40 4.0 A = 10dB V 15.5 A = 15dB 35 V 3.5 190MHz 15.0 240MHz 380MHz A = 6dB V 30 3.0 14.5 25 2.5 A = 10dB V 14.0 500MHz 20 2.0 A = 10dB V NOISE FIGURE 13.5 15 1.5 10 1.0 13.0 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 FREQUENCY (MHz) GAIN SETTING RESISTOR (Ω) Figure 10. Noise Figure, OIP3, and Spectral Noise Density vs. Figure 13. Output 1 dB Compression Point (P1dB) vs. Frequency, 2 V p-p Composite, R = 200 Ω L RG for Multiple Frequencies, RL = 200 Ω 45 –60 140MHz 100MHz 70MHz –65 HD3 40 –70 190MHz –75 240MHz 35 –80 HD2 380MHz –85 30 500MHz –90 –95 25 –100 –105 20 –110 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 450 500 GAIN SETTING RESISTOR (Ω) FREQUENCY (MHz) Figure 11. Output IP3 (OIP3) vs. R for Multiple Frequencies, R = 200 Ω Figure 14. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 kΩ, G L AV = 10 dB, 5 V Supply, RG = 180 Ω, RD = 6.8 kΩ, CD = 0.1 pF –50 –60 > 300MHz NO C OR R USED D D –60 –65 HD3 –70 –70 HD3 2V p-p HD2 –80 –75 2V p-p HD2 –90 –80 HD3 1V p-p –100 –85 –110 –90 0 50 100 150 200 250 300 350 400 220 260 300 340 380 420 460 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Harmonic Distortion vs. Frequency for 2 V p-p into R = 200 Ω, Figure 12. Third-Order Harmonic Distortion (HD3) vs. Frequency, L A = 10 dB, R = 115 Ω, R = 4.3 kΩ, C = 0.2 pF A = 10 dB, R = 200 Ω V G D D V L Rev. B | Page 9 of 20 NOISE FIGURE (dB), OIP3 (dBm) HARMONIC DISTORTION (dBc) OIP3 (dBm) 05728-050 05728-009 SPECTRAL NOISE DENSITY RTI (nV/ Hz) 05728-049 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) OUTPUT P1dB (dBm) 05728-051 05728-007 05728-005 AD8352 1.5 0.6 0 t (10/90) = 215ps RISE t (10/90) = 210ps FALL 1.0 0.5 –20 0.5 0.4 –40 0 0.3 –60 –0.5 0.2 –80 –1.0 0.1 –100 –120 –1.5 0 03 0.5 1.0 1.5 2.0 2.5.0 0 100 200 300 400 500 600 700 800 900 1000 TIME (nsec) FREQUENCY (MHz) Figure 16. Group Delay and Phase vs. Frequency, AV = 10 dB, RL = 200 Ω Figure 19. Large Signal Output Transient Response, RL = 200 Ω, AV = 10 dB. 3500 0 5 4 3000 –0.05 3 2500 –0.10 2 1 2000 –0.15 0 1500 –0.20 –1 –2 1000 –0.25 –3 500 –0.30 –4 0 –0.35 –5 0 100 200 300 400 500 600 700 800 900 1000 04 0.5 1.0 1.5 2.0 2.5 3.0 3.5.0 FREQUENCY (MHz) TIME (nsec) Figure 20. 1% Settling Time for a 2 V p-p Step Response, Figure 17. S11 Equivalent RC Parallel Network, RG = 115 Ω A = 10 dB, R = 200 Ω V L 6 160 0.7 25 140 0.6 5 120 0.5 20 4 100 0.4 3 80 0.3 15 60 0.2 2 40 0.1 10 1 20 0 0 –1.0 0 5 0 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) GAIN SETTING RESISTOR (Ω) Figure 21. Spectral Noise Density RTI and Noise Figure vs. R , R = 200 Ω G L Figure 18. S22 Equivalent RC Parallel Network, RG = 115 Ω Rev. B | Page 10 of 20 INPUT RESISTANCE (Ω) OUTPUT RESISTANCE (Ω) GROUP DELAY (ns) OUTPUT CAPACITANCE (pF) 05728-042 PHASE (Degrees) 05728-053 INPUT CAPACITANCE (pF) 05728-052 SPECTRAL NOISE DENSITY RTI (nV/ Hz) VOLTAGE (V) SETTLING (%) 05728-047 NOISE FIGURE (dB) 05728-046 05728-054 AD8352 APPLICATIONS INFORMATION GAIN AND DISTORTION ADJUSTMENT Table 6. Broadband Selection of RG, CD, and RD, 1 kΩ Load (DIFFERENTIAL INPUT) A (dB) R (Ω) C (pF) R (kΩ) V G D D Table 5 and Table 6 show the required value of RG for the gains 3 750 Open 6.8 specified at 200 Ω and 1 kΩ loads. Figure 22 and Figure 24 plot 6 360 Open 6.8 gain vs. RG up to 18 dB for both load conditions. For other output 9 210 Open 6.8 loads (R ), use Equation 1 to compute gain vs. R . L G 10 180 0.05 6.8 12 130 0.1 6.8 ⎛ ⎞ R + 500 G ⎜ ⎟ A = R (1) VDifferential L 15 82 0.3 6.8 ⎜ ⎟ (R + 5) (R+ 53)+ 430 G L ⎝ ⎠ 18 54 0.5 6.8 where 20 R is the single-ended load. L 18 RG is the gain setting resistor. 16 The third-order harmonic distortion can be reduced by using external components RD and CD. Table 5 and Table 6 show the 14 required values for RD and CD for the specified gains to achieve 12 (single tone) third-order distortion reduction at 180 MHz. 10 Figure 23 and Figure 25 show any gain (up to 18 dB) vs. C for D 8 200 Ω and 1 kΩ loads, respectively. When these values are selected, 6 they result in minimum single tone, third-order distortion at 4 180 MHz. This frequency point provides the best overall broad- band distortion for the specified frequencies below and above 2 this value. For applications above ~300 MHz, CD and RD are 0 0 50 100 150 200 250 300 350 400 not required. See the Specifications section and the third-order R (Ω) G harmonic plots for more details (see Figure 12, Figure 14, and Figure 22. Gain vs. R , R = 200 Ω G L Figure 15). 20 C can be further optimized for narrow-band tuning requirements D 18 below 180 MHz that result in relatively lower third-order (in- 16 band) intermodulation distortion terms. See the Narrow-Band, Third-Order Intermodulation Cancellation section for more 14 information. Though not shown, single tone, third-order 12 optimization can also be improved for narrow-band frequency 10 applications below 180 MHz with the proper selection of C , D 8 and 3 dB to 6 dB of relative third-order improvement can be 6 realized at frequencies below approximately 140 MHz. 4 Using the information listed in Table 5 and Table 6, an extrapolated 2 value for RD can be determined for loads between 200 Ω and 1 kΩ. For loads above 1 kΩ, use the 1 kΩ RD values listed in Table 6. 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 C (pF) Table 5. Broadband Selection of RG, CD, and RD, 200 Ω Load D Figure 23. Gain vs. CD, RL = 200 Ω AV (dB) RG (Ω) CD (pF) RD (kΩ) 3 390 Open 6.8 6 220 Open 4.3 9 140 0.1 4.3 10 115 0.2 4.3 12 86 0.3 4.3 15 56 0.6 4.3 18 35 1 4.3 Rev. B | Page 11 of 20 GAIN (dB) GAIN (dB) 05728-027 05728-026 AD8352 20 Figure 27 plots gain vs. R for 200 Ω and 1 kΩ loads. Table 7 G 18 and Table 8 show the values of C and R required (for 180 MHz D D broadband, third-order, single tone optimization) for 200 Ω and 16 1 kΩ loads, respectively. This single-ended configuration provides 14 −3 dB bandwidths similar to input differential drive. Figure 28 12 through Figure 31 show distortion levels at a gain of 12 dB for 10 both 200 Ω and 1 kΩ loads. Gains from 3 dB to 18 dB, using 8 optimized CD and RD values, obtain similar distortion levels. 6 0.1µF 0.1µF 4 VIP 2 RGP 65Ω 0 50Ω C R R AD8352 D D G 0 100 200 300 400 500 600 700 800 RGN 0.1µF R (Ω) G AC Figure 24. Gain vs. RG, RL = 1 kΩ 0.1µF R 25Ω N 200Ω 20 18 Figure 26. Single-Ended Schematic 16 40 14 12 35 10 30 8 25 6 GAIN, R =1kΩ L 20 4 2 15 GAIN, R =200Ω L 0 10 00 0.1 0.2 0.3 0.4.5 C (pF) D 5 Figure 25. Gain vs. C , R = 1 kΩ D L 0 1 10 100 1k 10k SINGLE-ENDED INPUT OPERATION R (Ω) G The AD8352 can be configured as a single-ended-to-differential Figure 27. Gain vs. RG amplifier, as shown in Figure 26. To balance the outputs when driving the VIP input, an external resistor (RN) of 200 Ω is added –60 between VIP and RGN. See Equation 2 to determine the single- ended input gain (A ) for a given R or R . V Single-Ended G L –70 2V p-p OUT ⎛ R+ 500 ⎞ R G L ⎜ ⎟ A = R+ (2) VSingle−Ended L ⎜ ⎟ R + 30 (R + 5) (R+ 53)+ 430 L L ⎝ G ⎠ –80 1V p-p OUT where R is the single-ended load. L –90 RG is the gain setting resistor. –100 –110 10 70 140 190 240 FREQUENCY (MHz) Figure 28. Single-Ended, Second-Order Harmonic Distortion (HD2) vs. Frequency, 200 Ω Load Rev. B | Page 12 of 20 GAIN (dB) GAIN (dB) 05728-029 05728-028 GAIN (dB) HD2 (dBc) 05728-024 05728-021 05728-020 AD8352 This broadband optimization was also performed at 180 MHz. Table 7. Distortion Cancellation Selection Components As with differential input drive, the resulting distortion levels (R and C ) for Required Gain, 200 Ω Load D D at lower frequencies are based on the C and R specified in D D A (dB) R (Ω) C (pF) R (kΩ) V G D D Table 7 and Table 8. As with differential input drive, relative 3 4.3 k Open 4.3 third-order reduction improvement at frequencies below 6 540 Open 4.3 140 MHz is realized with proper selection of CD and RD. 9 220 0.1 4.3 –60 12 120 0.3 4.3 15 68 0.6 4.3 18 43 0.9 4.3 –70 2V p-p OUT Table 8. Distortion Cancellation Selection Components –80 (R and C ) for Required Gain, 1 kΩ Load D D 1V p-p OUT A (dB) R (Ω) C (pF) R (kΩ) V G D D –90 6 3 k Open 4.3 9 470 Open 4.3 –100 12 210 0.2 4.3 15 120 0.3 4.3 18 68 0.5 4.3 –110 10 70 140 190 240 FREQUENCY (MHz) NARROW-BAND, THIRD-ORDER Figure 29. Single-Ended, Third-Order Harmonic Distortion (HD3) vs. INTERMODULATION CANCELLATION Frequency, 200 Ω Load –60 Broadband single tone, third-order harmonic optimization does not necessarily result in optimum (minimum) two tone, third- order intermodulation levels. The specified values for CD and –70 RD in Table 5 and Table 6 were determined for minimizing broadband, single tone third-order levels. –80 Due to phase-related distortion coefficients, optimizing single 2V p-p OUT tone third-order distortion does not result in optimum in-band –90 (2f − f and 2f − f ), third-order distortion levels. By proper 1 2 2 1 selection of CD (using a fixed 4.3 kΩ RD), IP3s of better than 1V p-p OUT 45 dBm are achieved. This results in degraded out-of-band, –100 third-order frequencies (f2 + 2f1, f1 + 2f2, 3f1 and 3f2). Thus, careful frequency planning is required to determine the trade-offs. –110 10 70 140 190 240 Figure 32 shows narrow-band (2 MHz spacing) OIP3 levels FREQUENCY (MHz) optimized at 32 MHz, 70 MHz, 100 MHz, and 180 MHz using Figure 30. Single-Ended, Second-Order Harmonic Distortion (HD2) vs. the C values specified in Figure 33. These four data points (the D Frequency, 1 kΩ Load C value and associated OIP3 levels) are extrapolated to provide D –60 close estimates of OIP3 levels for any specific frequency between 30 MHz and 180 MHz. For frequencies below ~140 MHz, narrow- –70 band tuning of OIP3 results in relatively higher OIP3s (vs. the broadband results shown in Table 2 of the specifications). Though not shown, frequencies below 30 MHz also result in improved –80 2V p-p OUT OIP3s when using proper values for C . D –90 1V p-p OUT –100 –110 10 70 140 190 240 FREQUENCY (MHz) Figure 31. Single-Ended, Third-Order Harmonic Distortion (HD3) vs. Frequency, 1 kΩ Load Rev. B | Page 13 of 20 HD3 (dBc) HD2 (dBc) HD3 (dBc) 05728-025 05728-023 05728-022 AD8352 48 Refer to the Layout and Transmission Line Effects section for R = 200Ω L R = 4.3kΩ 47 D more information. The circuit in Figure 35 represents a single- C = 0.3pF D ended input to differential output configuration for driving the 46 AD9445. In this case, the input 50 Ω resistor with RN (typically 45 200 Ω) provide the input impedance match for a 50 Ω system. 44 Again, if input reflections are minimal, this impedance match is A = 6dB V 43 10dB not required. A fixed 200 Ω resistor (RN) is required to balance 15dB 42 18dB the output voltages that are required for second-order distortion 41 cancellation. R is the gain setting resistor for the AD8352 with G the R and C components providing distortion cancellation. D D 40 The AD9445 presents approximately 2 kΩ in parallel with 39 5 pF/differential load to the AD8352 and requires a 2.0 V p-p 38 0 50 100 150 200 differential signal (VREF = 1 V) between VIN+ and VIN− for a FREQUENCY (MHz) full-scale output operation. Figure 32. Third-Order Intermodulation Distortion, OIP3 vs. These AD8352 simplified circuits provide the gain, isolation, Frequency for Various Gain Settings and distortion performance necessary for efficiently driving 6.0 high linearity converters, such as the AD9445. This device also R = 200Ω L 5.5 R = 4.3kΩ D provides balanced outputs whether driven differentially or single- 5.0 ended, thereby maintaining excellent second-order distortion 4.5 levels. However, at frequencies above ~100 MHz, due to phase- 4.0 related errors, single-ended, second-order distortion is relatively 3.5 higher. The output of the amplifier is ac-coupled to allow for an A = 6dB V 3.0 10dB optimum common-mode setting at the ADC input. Input ac 15dB 2.5 18dB coupling can be required if the source also requires a common- 2.0 mode voltage that is outside the optimum range of the AD8352. 1.5 A VCM common-mode pin is provided on the AD8352 that 1.0 equally shifts both input and output common-mode levels. 0.5 Increasing the gain of the AD8352 increases the system noise and, 0 30 50 70 90 110 130 150 170 190 thus, decreases the SNR (3.5 dB at 100 MHz input for Av = 10 dB) FREQUENCY (MHz) of the AD9445 when no filtering is used. Note that amplifier gains Figure 33. Narrow-Band C vs. Frequency for Various Gain Settings D from 3 dB to 18 dB, with proper selection of C and R , do not D D appreciably affect distortion levels. These circuits, when configured HIGH PERFORMANCE ADC DRIVING properly, can result in SFDR performance of better than 87 dBc The AD8352 provides the gain, isolation, and balanced low at 70 MHz and 82 dBc at 180 MHz input. Single-ended drive, with distortion output levels for efficiently driving wideband ADCs appropriate CD and RD, give similar results for SFDR and third- such as the AD9445. order intermodulation levels shown in these figures. Figure 34 and Figure 35 (single and differential input drive) Placing antialiasing filters between the ADC and the amplifier illustrate the typical front-end circuit interface for the AD8352 is a common approach for improving overall noise and broad- differentially driving the AD9445 14-bit ADC at 105 MSPS. The band distortion performance for both band-pass and low-pass AD8352, when used in the single-ended configuration, shows little applications. For high frequency filtering, matching to the filter or no degradation in overall third-order harmonic performance is required. The AD8352 maintains a 100 Ω output impedance (vs. differential drive). See the Single-Ended Input Operation well beyond most applications and is well-suited to drive most section. The 100 MHz FFT plots shown in Figure 36 and Figure 37 filter configurations with little or no degradation in distortion. display the results for the differential configuration. Though not shown, the single-ended, third-order levels are similar. The 50 Ω resistor shown in Figure 34 provides a 50 Ω differential input impedance to the source for matching considerations. When the driver is less than one eighth of the wavelength from the AD8352, impedance matching is not required thereby negating the need for this termination resistor. The output 24 Ω resistors provide isolation from the analog-to-digital input. Rev. B | Page 14 of 20 C (pF) OIP3 (dBm) D 05728-031 05728-030 AD8352 V 0 CC SNR = 61.98dBc –10 NOISE FLOOR = –111.2dB FUND1 = –7.072dBFS –20 0.1µF FUND2 = –7.043dBFS 0.1µF –30 IMD (2F2-F1) = –89dBc 0Ω 16 IMD (2F1-F2) = –88dBc 8, 13 –40 0.1µF 1 11 24Ω –50 IF/RF INPUT 2 –60 –70 50Ω R R AD8352 AD9445 D G –80 C D 3 ADT1-1WT –90 4 24Ω –100 10 0.1µF 5 14 –110 0Ω 0.1µF –120 0.1µF –130 –140 Figure 34. Differential Input to the AD8352 Driving the AD9445 –150 05 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.252.50 0.1µF 0.1µF FREQUENCY (MHz) 33Ω VIP VOP Figure 37. Two Tone Distortion AD8352 Driving AD9445, 50Ω 50Ω Encode Clock @ 105 MHz with f @ 100 MHz (A = 10 dB), C V VIN+ Analog In = 98 MHz and 101 MHz, See Figure 34 AC C R R AD8352 AD9445 D D G VIN– VIN LAYOUT AND TRANSMISSION LINE EFFECTS 33Ω VON High Q inductive drives and loads, as well as stray transmission 0.1µF 0.1µF 25Ω R N line capacitance in combination with package parasitics, can 200Ω potentially form a resonant circuit at high frequencies resulting Figure 35. Single-Ended Input to the AD8352 Driving the AD9445 in excessive gain peaking or possible oscillation. If RF transmission 0 SNR = 67.26dBc lines connecting the input or output are used, they should be –10 SFDR = 83.18dBc NOISE FLOOR = –110.5dB designed such that stray capacitance at the input/output pins is –20 FUND = –1.074dBFS –30 SECOND = –83.14dBc minimized. In many board designs, the signal trace widths should THIRD = –85.39dBc –40 be minimal where the driver/ receiver is more than one-eighth –50 of the wavelength from the AD8352. This nontransmission line –60 –70 configuration requires that underlying and adjacent ground and –80 low impedance planes be dropped from the signal lines. In a –90 similar fashion, stray capacitance should be minimized near the –100 R , C , and R components and associated traces. This also G D D –110 –120 requires not placing low impedance planes near these components. –130 Refer to the evaluation board layout (Figure 39 and Figure 40) –140 for more information. Excessive stray capacitance at these nodes –150 0 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 results in unwanted high frequency distortion. The 0.1 μF supply FREQUENCY (MHz) decoupling capacitors need to be close to the amplifier. This Figure 36. Single Tone Distortion AD8352 Driving AD9445, includes Signal Capacitor C2 through Signal Capacitor C5. Encode Clock @ 105 MHz with f @ 100 MHz (A = 10 dB), See Figure 34 C V Parasitic suppressing resistors (R5, R6, R7, and R11) can be used at the device input/output pins. Use 25 Ω series resistors (Size 0402) to adequately de-Q the input and output system from most parasitics without a significant decrease in gain. In general, if proper board layout techniques are used, the suppression resistors are not necessarily required. Output Parasitic Suppression Resistor R7 and Output Parasitic Suppression Resistor R11 can be required for driving some switch capacitor ADCs. These suppressors, with Input C of the converter (and possibly added External Shunt C), help provide charge kickback isolation and improve overall distortion at high encode rates. Rev. B | Page 15 of 20 AMPLITUDE (dBFS) 05728-034 05728-012 05728-033 AMPLITUDE (dBFS) 05728-035 AD8352 EVALUATION BOARD An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are shown in Figure 38, Figure 39, and Figure 40. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B). Table 9. Evaluation Board Circuit Components and Functions Additional Component Name Function Information C8, C9, C10 Capacitors C8, C9, and C10 are bypass capacitors. C8 = C9 = C10 = 0.1 μF R , C Distortion Distortion Adjustment Components. Allows for third-order distortion Typically, both are open D D tuning adjustment HD3. above 300 MHz components C = 0.2 pF, R = 4.32 kΩ D D CD is Panasonic High-Q (microwave) multilayer chip 402 capacitor R1, R2, R3, Resistors, Input Interface. R1 and R4 ground one side of the differential drive interface R1 = open, R2 = 25 Ω, R4, R5, R6, transformer, for single-ended applications. T2 is a 1-to-1 impedance ratio balun to transform a R3 = 25 Ω, R4 = 0 Ω, T2, C2, C3 capacitors single-ended input into a balanced differential signal. R2 and R3 provide R5 = 0 Ω, R6 = 0 Ω, a differential 50 Ω input termination. R5 and R6 can be increased to reduce T2 = M/A-COM ETC1-1-13, gain peaking when driving from a high source impedance. The 50 Ω C2 = 0.1 μF, C3 = 0.1 μF termination provides an insertion loss of 6 dB. C2 and C3 provide ac-coupling. R7, R8, R9, Resistors, Output Interface. R13 and R14 ground one side of the differential output R7 = 0 Ω, R8 = 86.6 Ω, R11, R12, transformer, interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun to R9 = 57.6 Ω, R11 = 0 Ω, R13, R14, capacitors transform a balanced differential signal to a single-ended signal. R8, R9, and R12 = 86.6 Ω, R13 = 0 Ω, T1, C4, C5 R12 are provided for generic placement of matching components. R7 and R14 = open, R11 allow additional output series resistance when driving capacitive loads. T1 = M/A-COM ETC1-1-13, The evaluation board is configured to provide a 200 Ω to 50 Ω impedance C4 = 0.1 μF, C5 = 0.1 μF transformation with an insertion loss of 11.6 dB. C4 and C5 provide ac-coupling. R7 and R11 provide additional series resistance when driving capacitive loads. RG Resistor Gain Setting Resistor. Resistor RG is used to set the gain of the device. Refer RG = 115 Ω (Size 0402) for to Table 5 and Table 6 when selecting the gain resistor. a gain of 10 dB SW1, R18, Switch, Enable Interface. R10 connects the enable pin, ENB, to the supply for constant SW1 = installed R19, R20 resistors enable operation. The enable function can be toggled by removing R10 and R18 = R19 = R20 = 0 Ω using SW1 to switch between enable and disable modes. C1, C6, C7 Capacitors Power Supply Decoupling. The supply decoupling consists of a 10 μF capacitor C1 = 10 μF, C6 = 0.1 μF, (C1) to ground. C6 and C7 are bypass capacitors. C7 = 0.1 μF T3, T4, Transformer, Calibration Circuit. T3 and T4 are dummy baluns which may be used to T3 = T4 = M/A-COM ETC1-1-13 C11, C12 capacitors calibrate the insertion loss across the transformers in the AD8352 signal chain. C11 = C12 = 0.1 μF EVALUATION BOARD LOADING SCHEMES Table 10. Values Used for 200 Ω and 1000 Ω Loads The AD8352 evaluation board is characterized with two load Component 200 Ω Load (Ω) 1000 Ω Load (Ω) configurations representing the most common ADC input R8 86.6 487 resistance. The loads chosen are 200 Ω and 1000 Ω using a R9 57.6 51.1 broadband resistive match. The loading can be changed via R8, R12 86.6 487 R9, and R12 giving the flexibility to characterize the AD8352 evaluation board for the load in any given application. These SOLDERING INFORMATION loads are inherently lossy and thus must be accounted for in On the underside of the chip scale package, there is an exposed overall gain/loss for the entire evaluation board. Measure the compressed paddle. This paddle is internally connected to the gain of the AD8352 with an oscilloscope using the following ground of the chip. Solder the paddle to the low impedance procedure to determine the actual gain: ground plane on the PCB to ensure the specified electrical 1. Measure the peak-to-peak voltage at the input node (C2 or C3). performance and to provide thermal relief. To further reduce thermal impedance, it is recommended that the ground planes 2. Measure the peak-to-peak voltage at the output node (C4 or C5). on all layers under the paddle be stitched together with vias. 3. Compute gain using the following formula: Gain = 20log(VOUT/VIN) Rev. B | Page 16 of 20 AD8352 EVALUATION BOARD SCHEMATICS Figure 38. AD8352 Evaluation Board, Version A01212A Rev. B | Page 17 of 20 VCM ENBL YELLOW R19 YELLOW 0Ω C10 VCM SWITCH_SPDT GND VPOS 0.1µF SW1 ENB BLACK R18 C9 0Ω R20 0.1µF 0Ω C8 VPOS 0.1µF C2 R5 VINP 0.1µF VOUTP 0Ω VIP C4 R7 R8 16 15 14 13 R1 R2 RDP 1 GND 0.1µF R14 0Ω 86.6Ω 12 OPEN 25Ω OPEN RGP 11 VOP 2 5 1 3 2 4 C R R D D R9 G T1 Z1 T2 0.2pF 4.32kΩ 115Ω 57.6Ω RGN 3 VON 4 23 15 10 RDN GND 4 AD8352 M/A_COM M/A_COM 9 R11 R12 C5 ETC1-1-13 56 7 8 ETC1-1-13 VINN 0Ω 86.6Ω VOUTN 0.1µF VIN R6 C3 R4 R3 R13 0Ω 0.1µF 0Ω 25Ω 0Ω VPOS HIGH IMPEDANCE TRACES 50Ω TRACES 50Ω TRACES (OPEN PLANES UNDER TRACES) CALIBRATION CIRCUIT BYPASS CIRCUIT VPOS J1 J2 RED VPOS C11 51 0.1µF 51 + C1 C6 C7 T3 T4 10µF 0.1µF 0.1µF 42 3 42 3 C12 0.1µF LOCATE CAPS NEAR DUT GND ENB GND VCM VCC VCC 05728-017 AD8352 Figure 39. Component Side Silkscreen Figure 40. Far Side Showing Ground Plane Pull Back Around Critical Features Rev. B | Page 18 of 20 05728-019 05728-018 AD8352 OUTLINE DIMENSIONS 0.50 0.40 0.30 3.00 0.60 MAX BSC SQ * 1.65 13 16 0.45 1 12 1.50 SQ PIN 1 1.35 2.75 TOP EXPOSED INDICATOR BSC SQ VIEW PAD (BOTTOM VIEW) 9 4 8 5 0.50 BSC 0.25 MIN 1.50 REF 0.80 MAX 12° MAX 0.65 TYP 0.90 0.85 0.05 MAX 0.80 0.02 NOM SEATING 0.30 PLANE 0.20 REF 0.23 0.18 * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Ordering Package Model Temperature Range Package Description Quantity Option Branding 1 AD8352ACPZ-WP −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 50 CP-16-3 Q0R Waffle Pack 1 AD8352ACPZ-R7 −40°C to +85°C 3000 CP-16-3 Q0R 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel 1 AD8352ACPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 CP-16-3 Q0R 7” Tape and Reel 1 AD8352-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 19 of 20 PIN 1 INDICATOR AD8352 NOTES ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05728-0-7/08(B) Rev. B | Page 20 of 20