ANALOG DEVICES AD8340

700 MHz to 1000 MHz RF Vector Modulator AD8340 FEATURES FUNCTIONAL BLOCK DIAGRAM VPRF QBBP QBBM VPS2 Cartesian amplitude and phase modulation 700 MHz to 1.0 GHz frequency range 90° Continuous magnitude control of −2 dB to −32 dB RFOP RFIP Continuous phase control of 0° to 360° RFIM Output third-order intercept 24 dBm RFOM Output 1 dB compression point 11 dBm 0° Output noise floor −149 dBm/Hz @ full gain Adjustable modulation bandwidth up to 230 MHz CMOP IBBP IBBM DSOP Fast output power disable Figure 1. 4.75 V to 5.25 V single-supply voltage APPLICATIONS RF PA linearization/RF predistortion Amplitude and phase modulation Variable attenuators and phase shifters CDMA2000, GSM/EDGE linear power amplifiers Smart antennas GENERAL DESCRIPTION The AD8340 vector modulator performs arbitrary amplitude Both the RF inputs and outputs can be used differentially or and phase modulation of an RF signal. Because the RF signal single-ended and must be ac-coupled. The RF input and output path is linear, the original modulation is preserved. This part impedances are nominally 50 Ω over the operating frequency can be used as a general-purpose RF modulator, a variable range. The DSOP pin allows the output stage to be disabled attenuator/phase shifter, or a remodulator. The amplitude can quickly to protect subsequent stages from overdrive. The be controlled from a maximum of −2 dB to less than −32 dB, AD8340 operates off supply voltages from 4.75 V to 5.25 V and the phase can be shifted continuously over the entire 360° while consuming approximately 130 mA. range. For maximum gain, the AD8340 delivers an OP1dB The AD8340 is fabricated using the Analog Devices, Inc. of 11 dBm, an OIP3 of 24 dBm, and an output noise floor of proprietary, high performance 25 GHz SOI complementary −149 dBm/Hz, independent of phase. It operates over a fre- bipolar IC process. It is available in a 24-lead RoHS-compliant quency range of 700 MHz to 1.0 GHz. LFCSP package and operates over a −40°C to +85°C tempera- The baseband inputs in Cartesian I and Q format control the ture range. Evaluation boards are available. amplitude and phase modulation imposed on the RF input signal. Both I and Q inputs are dc-coupled with a ±500 mV differential full-scale range. The maximum modulation band- width is 230 MHz, which can be reduced by adding external capacitors to limit the noise bandwidth on the control lines. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 04699-001 AD8340 TABLE OF CONTENTS Features .............................................................................................. 1 Noise and Distortion.................................................................. 11 Applications....................................................................................... 1 Gain and Phase Accuracy.......................................................... 11 Functional Block Diagram .............................................................. 1 RF Frequency Range .................................................................. 11 General Description ......................................................................... 1 Applications Information .............................................................. 12 Revision History ............................................................................... 2 Using the AD8340 ...................................................................... 12 Specifications..................................................................................... 3 RF Input and Matching ............................................................. 12 Absolute Maximum Ratings............................................................ 4 RF Output and Matching .......................................................... 13 ESD Caution.................................................................................. 4 Driving the I-Q Baseband Controls......................................... 13 Pin Configuration and Function Descriptions............................. 5 Interfacing to High Speed DACs.............................................. 14 Typical Performance Characteristics ............................................. 6 CDMA2000 Application ........................................................... 14 Theory of Operation ...................................................................... 10 Evaluation Board ............................................................................ 16 RF Quadrature Generator ......................................................... 10 Schematic and Artwork............................................................. 18 I-Q Attenuators and Baseband Amplifiers.............................. 11 Outline Dimensions....................................................................... 20 Output Amplifier........................................................................ 11 Ordering Guide .......................................................................... 20 REVISION HISTORY 8/07—Rev. A to Rev B Replaced Pin Configuration and Function Descriptions Section ........................................................................ 5 Changes to Figure 30...................................................................... 12 Changes to Figure 39...................................................................... 18 7/07—Rev. 0 to Rev. A Replaced Pin Configuration and Function Descriptions Section ........................................................................ 5 Changes to Ordering Guide .......................................................... 20 6/04—Revision 0: Initial Version Rev. B | Page 2 of 20 AD8340 SPECIFICATIONS VS = 5 V, TA = 25°C, ZO = 50 Ω, f = 880 MHz, single-ended, ac-coupled source drive to RFIP through 5.6 nH series inductor, RFIM ac-coupled through 5.6 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun. Table 1. Parameter Conditions Min Typ Max Unit OVERALL FUNCTION Frequency Range 700 1000 MHz Maximum Gain Maximum gain setpoint for all phase setpoints −2 dB Minimum Gain VBBI = VBBQ = 0 V −32 dB Gain Control Range Relative to maximum gain 30 dB Phase Control Range Over 30 dB control range 360 Degrees Gain Flatness Over any 60 MHz bandwidth 0.25 dB Group Delay Flatness Over any 60 MHz bandwidth 10 ps RF INPUT STAGE RFIM, RFIP (Pin 21 and Pin 22) Input Return Loss From RFIP to CMRF (with 5.6 nH series inductors) 20 dB CARTESIAN CONTROL INTERFACE (I and Q) IBBP, IBBM, QBBP, QBBM (Pin 16, Pin 15, Pin 3, Pin 4) Gain Scaling 2 1/V Modulation Bandwidth 250 mV p-p sinusoidal baseband input single-ended 230 MHz Second Harmonic Distortion 250 mV p-p, 1 MHz, sinusoidal baseband input differential 47 dBc Third Harmonic Distortion 250 mV p-p, 1 MHz, sinusoidal baseband input differential 45 dBc Step Response For gain setpoint from 0.1 to 0.9 45 ns (V = 0.5 V, V = 0.55 V to 0.95 V) BBP BBM For gain setpoint from 0.9 to 0.1 47 ns (VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V) RF OUTPUT STAGE RFOP, RFOM (Pin 9 and Pin 10) Output Return Loss Measured through balun 7.5 dB f = 880 MHz Gain Maximum gain setpoint −2 dB Output Noise Floor Maximum gain setpoint, no input −149 dBm/Hz PIN = 0 dBm, frequency offset = 20 MHz −147 dBm/Hz Output IP3 f1 = 880 MHz, f2 = 877.5 MHz, maximum gain setpoint 24 dBm ACPR IS-95, single carrier, P = 0 dBm, maximum gain, 62 dBc OUT phase setpoint = 45° Output 1 dB Compression Point Maximum gain 11 dBm POWER SUPPLY VPS2 (Pin 5, Pin 6, Pin 14); RFOP, RFOM (Pin 9 and Pin 10) Positive Supply Voltage 4.75 5 5.25 V Total Supply Current Includes load current 110 130 150 mA OUTPUT DISABLE DSOP (Pin 13) Disable Threshold 2.5 V Maximum Attenuation DSOP = 5 V 40 dB Enable Response Time Delay following high-to-low transition until device 15 ns meets full specifications Disable Response Time Delay following low-to-high transition until device 10 ns produces full attenuation Rev. B | Page 3 of 20 AD8340 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage VPRF, VPS2 5.5 V other conditions above those indicated in the operational DSOP 5.5 V section of this specification is not implied. Exposure to absolute IBBP, IBBM, QBBP, QBBM 2.5 V maximum rating conditions for extended periods may affect RFOP, RFOM 5.5 V device reliability. RF Input Power at Maximum Gain (50 Ω) 13 dBm (RFIP or RFIM, Single-Ended Drive) Equivalent Voltage 2.8 V p-p ESD CAUTION Internal Power Dissipation 825 mW θJA (with Pad Soldered to Board) 59°C/W Maximum Junction Temperature 125°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Rev. B | Page 4 of 20 AD8340 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS QFLP IFLP 1 18 PIN 1 QFLM 2 17 IFLM INDICATOR QBBP 3 16 IBBP AD8340 QBBM 4 15 IBBM TOP VIEW VPS2 VPS2 5 14 (Not to Scale) DSOP VPS2 6 13 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1; 2 QFLP; QFLM Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass corner frequency. 3; 4 QBBP; QBBM Q Channel Differential Baseband Inputs. 5, 6, 14; 19, 24 VPS2; VPRF Positive Supply Voltage, 4.75 V to 5.25 V. 7, 8, 11, 12; 20, 23 CMOP; CMRF Device Common. Connect via lowest possible impedance to external circuit common. 9; 10 RFOP; RFOM Differential RF Outputs. Must be ac-coupled. Differential impedance 50 Ω nominal. 13 DSOP Output Disable. Pull high to disable output stage. 15; 16 IBBM; IBBP I Channel Differential Baseband Inputs. 17; 18 IFLM; IFLP I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass corner frequency. 21; 22 RFIM; RFIP Differential RF Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal. Rev. B | Page 5 of 20 24 VPRF CMOP 7 CMRF CMOP 8 23 RFIP RFOP 9 22 RFIM 10 21 RFOM 20 CMRF CMOP 11 19 VPRF CMOP 12 04699-002 AD8340 TYPICAL PERFORMANCE CHARACTERISTICS 0 0.4 PHASE SETPOINT = 0° 0.2 –5 GAIN SETPOINT = 1.0 0.0 PHASE SETPOINT = 90° –10 –0.2 –0.4 –15 –0.6 PHASE SETPOINT = 270° –20 –0.8 GAIN SETPOINT = 0.5 –1.0 –25 –1.2 –30 –1.4 –1.6 GAIN SETPOINT = 0.1 –35 PHASE SETPOINT = 180° –1.8 –40 –2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 45 90 135 180 225 270 315 360 GAIN SETPOINT PHASE SETPOINT (Degrees) Figure 3. Gain Magnitude vs. Gain Setpoint at Different Phase Setpoints, Figure 6. Gain Conformance Error vs. Phase Setpoint at Different Gain RF Frequency = 880 MHz Setpoints 4 360 PHASE SETPOINT = 135° 3 330 PHASE SETPOINT = 45° 300 2 PHASE SETPOINT = 90° 270 1 PHASE SETPOINT = 0° GAIN SETPOINT = 1.0 240 0 210 –1 PHASE SETPOINT = 315° 180 –2 PHASE SETPOINT = 270° GAIN SETPOINT = 0.1 150 –3 GAIN SETPOINT = 0.5 120 –4 PHASE SETPOINT = 180° 90 –5 60 PHASE SETPOINT = 225° –6 30 –7 0 00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 30 60 90 120 150 180 210 240 270 300 330 360 GAIN SETPOINT PHASE SETPOINT (Degrees) Figure 4. Gain Conformance Error vs. Gain Setpoint at Figure 7. Phase vs. Phase Setpoint at Different Gain Setpoints Different Phase Setpoints 6 0 –2 4 GAIN SETPOINT = 0.1 GAIN SETPOINT = 1.0 –4 2 –6 0 –8 GAIN SETPOINT = 0.5 –10 –2 –12 GAIN SETPOINT = 1.0 –4 –14 GAIN SETPOINT = 0.5 –6 –16 –18 –8 –20 GAIN SETPOINT = 0.1 –10 –22 –12 –24 0 45 90 135 180 225 270 315 360 0 45 90 135 180 225 270 315 360 PHASE SETPOINT (Degrees) PHASE SETPOINT (Degrees) Figure 5. Gain Magnitude vs. Phase Setpoint at Different Gain Setpoints Figure 8. Phase Error vs. Phase Setpoint at Different Gain Setpoints Rev. B | Page 6 of 20 GAIN (dB) GAIN (dB) GAIN CONFORMANCE ERROR (dB) 04699-004 04699-005 04699-003 GAIN CONFORMANCE ERROR (dB) PHASE (Degrees) PHASE ERROR (Degrees) 04699-008 04699-007 04699-006 AD8340 –142 0 –143 –144 –0.5 –145 RF P = +5dBm IN –146 –1.0 –147 RF P = –5dBm IN –148 –1.5 RF P = 0dBm IN –149 –150 –2.0 NO RF INPUT –151 –152 –2.5 0.1 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 700 750 800 850 900 950 1000 GAIN SETPOINT FREQUENCY (MHz) Figure 9. Output Noise Floor vs. Gain, Noise in dBm/Hz, No Carrier, Figure 12. Gain Flatness vs. Frequency, Maximum Gain, Phase Setpoint = 0° With Carrier (20 MHz Offset) PIN = −5 dBm, 0 dBm, and +5 dBm 0 0 –2 –10 GAIN SETPOINT = 1.0 –4 –20 –6 –30 FUNDAMENTAL POWER, 879MHz, 881MHz –8 GAIN SETPOINT = 0.5 –40 –10 SECOND BASEBAND HARMONIC PRODUCT, –12 –50 878MHz, 882MHz –14 –60 –16 –70 –18 THIRD BASEBAND HARMONIC PRODUCT, –80 GAIN SETPOINT = 0.1 877MHz, 883MHz –20 –90 –22 –24 –100 700 750 800 850 900 950 1000 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) DIFFERENTIAL BASEBAND INPUT LEVEL (mV p-p) (I OR Q CHANNEL DRIVEN AT 1MHz) Figure 10. Gain vs. Frequency at Different Gain Setpoints Figure 13. Baseband Harmonic Distortion (700 MHz to 1000 MHz), Phase Setpoint = 0° (I and Q Channel, RF Input = 0 dBm, Balun and Cable Losses of Approximately 2 dB Not Accounted for in Plot) –145 14 TEMP = +25°C TEMP = –40°C –146 12 –147 10 TEMP = +85°C –148 8 –149 6 –150 4 –151 2 –152 0 700 750 800 850 900 950 1000 700 750 800 850 900 950 1000 RF FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Output Noise Floor vs. Frequency, Maximum Gain, Figure 14. Output 1 dB Compression Point vs. Frequency and Temperature, No RF Carrier, Phase Setpoint = 0° Maximum Gain, Phase Setpoint = 0° Rev. B | Page 7 of 20 NOISE (dBm/Hz) NOISE FLOOR (dBm/Hz) GAIN (dB) 04699-010 04699-011 04699-009 RF OUTPUT AM SIDEBAND POWER (dBm) GAIN FLATNESS (dB) OP1dB (dBm) 04699-014 04699-013 04699-012 AD8340 30 30 28 TEMP = –40°C GAIN SETPOINT = 1.0 25 26 24 20 GAIN SETPOINT = 0.5 22 TEMP = +85°C TEMP = +25°C 20 15 18 10 16 GAIN SETPOINT = 0.1 14 5 12 0 10 0 45 90 135 180 225 270 315 360 700 750 800 850 900 950 1000 PHASE SETPOINT (Degrees) FREQUENCY (MHz) Figure 15. Output IP3 vs. Frequency and Temperature, Maximum Gain, I Only Figure 18. Output IP3 vs. Gain and Phase Setpoints, 2.5 MHz Carrier Spacing RBW 30kHz RF ATT 20dB REF LVL VBW 30kHz MIXER –10dBm 0 dBm SWT 100ms UNIT dBm 0 0 A –10 –5 –20 1V p-p BB INPUT –30 –10 1 RM –40 500mV p-p BB INPUT –15 –50 –60 –20 –70 –80 –25 200mV p-p BB INPUT –90 –30 –100 CENTER 880 MHz 500 kHz/DIV SPAN 5 MHz 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. I/Q Modulation Bandwidth vs. Baseband Magnitude Figure 19. Single-Sideband Performance, 880 MHz, −10 dBm RF Input; 1 MHz, 500 mV p-p Differential BB Drive 90 60 120 14 GAIN SETPOINT = 1.0 12 30 150 10 8 GAIN SETPOINT = 0.5 6 180 0 1.5GHz 4 500MHz 2 1.5GHz 0 210 330 –2 500MHz –4 –6 240 300 GAIN SETPOINT = 0.1 –8 270 –10 IMPEDANCE CIRCLE –12 225 315 0 45 90 135 180 270 360 S11 RF PORT WITH 5.6nH INDUCTORS PHASE SETPOINT (Degrees) S11 RF PORT WITHOUT INDUCTORS Figure 17. Output 1dB Compression Point vs. Gain and Phase Setpoints Figure 20. Input and Output Impedance Smith Chart (with Frequency Markers) Rev. B | Page 8 of 20 RF OUTPUT AM SIDEBAND POWER (dBm) OP1dB (dBm) OIP3 (dBm) 04699-015 04699-017 04699-016 OUTPUT POWER (dBm) OIP3 (dBm) SECOND BASEBAND HARMONIC DESIRED SIDEBAND RF FEEDTHROUGH UNDESIRED SIDEBAND SECOND BASEBAND HARMONIC 04699-020 04699-019 04699-018 AD8340 90 60 120 0 30 150 1.5GHz 500MHz –5 –10 0 180 –15 500MHz 1.5GHz –20 –25 210 330 –30 –35 240 300 –40 270 –45 IMPEDANCE CIRCLE –50 S22 PORT WITH 1 TO 1 TRANSFORMER 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SDD22 PORT DIFFERENTIAL DSOP VOLTAGE (V) Figure 21. Output Impedance Smith Chart (with Frequency Markers) Figure 24. Power Shutdown Attenuation TEK FAST ACQ SAMPLE 6 4 PHASE SETPOINT = 45° 2 2V/DIV PHASE SETPOINT = 0° 0 –2 DSOP 200mV/DIV –4 3 –6 –8 PHASE SETPOINT = 90° –10 RF OUTPUT –12 CH1 200mVΩ M 10.0ns 5.0GS/s ET 200ps/pt 74.0ns –14 CH3 2.0V A CH2 160mV 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 GAIN SETPOINT TIME (10ns/DIV) Figure 25. Power Shutdown Response Time Figure 22. Phase Error vs. Gain Setpoint by Phase Setpoint, 5 V DC, 25°C, 880 MHz 135 134 133 132 5.25V 131 130 129 5V 128 127 4.75V 126 125 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) Figure 23. Supply Current vs. Temperature Rev. B | Page 9 of 20 PHASE ERROR (Degrees) SUPPLY CURRENT (mA) 04699-022 04699-021 04699-023 CHA1/CHA3 (V) RF OUTPUT POWER (dBm) 04699-024 04699-025 AD8340 THEORY OF OPERATION The AD8340 is a linear RF vector modulator with Cartesian Pure amplitude modulation is represented by radial movement baseband controls. In the simplified block diagram shown in of the gain vector tip at a fixed angle, while pure phase modula- Figure 26, the RF signal propagates from the left to the right tion is represented by rotation of the tip around the circle at a while baseband controls are placed above and below. The RF fixed radius. Unlike traditional I-Q modulators, the AD8340 is input is first split into in-phase (I) and quadrature (Q) compo- designed to have a linear RF signal path from input to output. nents. The variable attenuators independently scale the I and Q Traditional I-Q modulators provide a limited LO carrier path components of the RF input. The attenuator outputs are then through which any amplitude information is removed. summed and buffered to the output. V BBI I CHANNEL INPUT By controlling the relative amounts of I and Q components that LINEAR are summed, the AD8340 allows continuous magnitude and ATTENUATOR phase control of the gain. Consider the vector gain representa- V-I tion of the AD8340 expressed in polar form in Figure 27. The SINGLE-ENDED OR SINGLE-ENDED OR DIFFERENTIAL 0°/90° I-V DIFFERENTIAL attenuation factors for the I and Q signal components are 50Ω INPUT Z 50Ω OUTPUT represented on the x- and y-axis, respectively, by the baseband V-I OUTPUT inputs, V and V . The resultant vector sum represents the BBI BBQ LINEAR DISABLE ATTENUATOR vector gain, which can also be expressed as a magnitude and Q CHANNEL INPUT phase. By applying different combinations of baseband inputs, V BBQ any vector gain within the unit circle can be programmed. Figure 26. Simplified Architecture of the AD8340 A change in sign of VBBI or VBBQ can be viewed as a change V q in sign of the gain or as a 180° phase change. The outermost +0.5 circle represents the maximum gain magnitude of unity. The MAX GAIN = 0dB circle origin implies, in theory, a gain of 0. In practice, circuit mismatches and unavoidable signal feedthrough limit the A |A| minimum gain to approximately −40 dB. The phase angle θ between the resultant gain vector and the positive x-axis is V i –0.5 +0.5 defined as the phase shift. Note that there is a nominal, systematic insertion phase through the AD8340 to which the phase shift is added. In the following discussions, the MIN GAIN < –30dB systematic insertion phase is normalized to 0°. –0.5 The correspondence between the desired gain and phase setpoints, Gain and Phase , and the Cartesian inputs, V SP SP BBI Figure 27. Vector Gain Representation and VBBQ, is given by simple trigonometric identities. RF QUADRATURE GENERATOR 2 2 Gain =() V /V +() V /V The RF input is directly coupled differentially or single-endedly SP BBI O BBQ O to the quadrature generator, which consists of a multistage RC Phase = arctan(V /V ) SP BBQ BBI polyphase network tuned over the operating frequency range of 700 MHz to 1000 MHz. The recycling nature of the polyphase where: network generates two replicas of the input signal, which are VO is the baseband scaling constant (500 mV). in precise quadrature, that is, 90°, to each other. Because the V and V are the differential I and Q baseband voltages, BBI BBQ passive network is perfectly linear, the amplitude and phase respectively. information contained in the RF input is transmitted faithfully Note that when evaluating the arctangent function, the proper to both channels. The quadrature outputs are then separately phase quadrant must be selected. For example, if the principal buffered to drive the respective attenuators. The characteristic value of the arctangent (known as the arctangent(x)) is used, impedance of the polyphase network is used to set the input Quadrant 2 and Quadrant 3 would be interpreted mistakenly impedance to the AD8340. as Quadrant 4 and Quadrant 1, respectively. In general, both VBBI and VBBQ are needed in concert to modulate the gain and the phase. Rev. B | Page 10 of 20 04699-027 04699-026 AD8340 I-Q ATTENUATORS AND BASEBAND AMPLIFIERS GAIN AND PHASE ACCURACY The proprietary linear-responding attenuator structure is an There are numerous ways to express the accuracy of the AD8340. active solution with differential inputs and outputs that offer Ideally, the gain and phase should precisely follow the setpoints. excellent linearity, low noise, and greater immunity from mis- Figure 4 illustrates the gain error in decibels (dB) from a best fit matches than other variable attenuator methods. The gain, in line, normalized to the gain measured at the gain setpoint = 1.0, linear terms, of the I and Q channels is proportional to its control for the different phase setpoints. Figure 6 shows the gain error voltage with a scaling factor designed to be 2/V, that is, a full-scale in a different form; the phase setpoint is swept from 0° to 360° gain setpoint of 1.0 (−2 dB) for VBBI (Q) of 500 mV. The control for different gain setpoints. Figure 8 and Figure 22 show analo- voltages can be driven differentially or single-endedly. The gous errors for the phase error as a function of gain and phase combination of the baseband amplifiers and attenuators allows setpoints. The accuracy clearly depends on the region of operation for maximum modulation bandwidths in excess of 200 MHz. within the vector gain unit circle. Operation very close to the origin generally results in larger errors as the relative accuracy OUTPUT AMPLIFIER of the I and Q vectors degrades. The output amplifier accepts the sum of the attenuator outputs RF FREQUENCY RANGE and delivers a differential output signal into the external load. The output pins must be pulled up to an external supply, The frequency range on the RF input is limited by the internal preferably through RF chokes. When the 50 Ω load is taken polyphase quadrature phase-splitter. The phase-splitter splits differentially, an OP1dB of 11 dBm and OIP3 of 24 dBm are the incoming RF input into two signals, 90° out of phase, as achieved at 880 MHz. The output can be taken in single-ended previously described in the RF Quadrature Generator section. fashion, albeit at lower performance levels. This polyphase network has been designed to ensure robust quadrature accuracy over standard fabrication process NOISE AND DISTORTION parameter variations for the 700 MHz to 1 GHz specified RF The output noise floor and distortion levels vary with the gain frequency range. Using the AD8340 as a single-sideband magnitude but do not vary significantly with the phase. At the modulator and measuring the resulting sideband suppression is higher gain magnitude setpoints, the OIP3 and the noise floor a good gauge of how the quadrature accuracy is maintained vary in direct proportion with the gain. At lower gain magni- over RF frequency. A typical plot of sideband suppression from tude setpoints, the noise floor levels off while the OIP3 continues 500 MHz to 1.5 GHz is shown in Figure 28. The level of to vary with the gain. sideband suppression degradation outside the 700 MHz to 1 GHz specified range is subject to manufacturing process variations. 0 –5 –10 –15 –20 –25 –30 –35 500 600 700 800 900 1000 1100 1200 1300 1400 1500 FREQUENCY (MHz) Figure 28. Sideband Suppression vs. Frequency Rev. B | Page 11 of 20 SB SUPPRESSION (dBc) 04699-028 AD8340 APPLICATIONS INFORMATION RFIM, a 50 Ω match is achieved with a return loss of >10 dB USING THE AD8340 over the operating frequency range. Different matching The AD8340 is designed to operate in a 50 Ω impedance inductors can improve matching over a narrower frequency system. Figure 30 illustrates where the RF input is driven in range. The single-ended and differential input impedances are a single-ended fashion while the differential RF output is exactly the same. converted to a single-ended output with an RF balun. The 100pF 5.6nH baseband controls for the I and Q channels are typically driven RFIM from differential DAC outputs. The power supplies, VPRF and RC ~1VDC PHASE VPS2, should be bypassed appropriately with 0.1 μF and 100 pF 5.6nH 100pF RF capacitors. Low inductance grounding of the CMOP and CMRF RFIP common pins is essential to prevent unintentional peaking of 50Ω the gain. Figure 29. RF Input Interface to the AD8340 Showing Coupling Capacitors and Matching Inductors RF INPUT AND MATCHING The RFIP and RFIM should be ac-coupled through low loss The input impedance of the AD8340 is defined by the characteris- series capacitors as shown in Figure 29. The internal dc levels tics of the polyphase network. The capacitive component of the are at approximately 1 V. For single-ended operation, one input network causes its impedance to roll off with frequency, albeit at is driven by the RF signal and the other input is ac grounded. a slower rate than 6 dB/octave. With matching inductors on the order of 5.6 nH in series with each of the RF inputs, RFIP and VP C2 C1 100pF 0.1µF IBBM VP IBBP C12 A (SEE TEXT) OUTPUT DISABLE B C8 C7 IFLP 0.1µF 100pF DSOP VP VPRF CMOP CMRF CMOP C17 C6 L3 100pF 5.6nH 100pF ETC1-1-13 RF RFIM RFOM OUTPUT AD8340 RF RFIP RFOP INPUT L4 C5 C18 5.6nH L1 L2 100pF 100pF CMRF CMOP 120nH 120nH VP VPRF CMOP C14 C3 C4 VPS2 0.1µF 0.1µF 100pF VP C11 C10 (SEE TEXT) 0.1µF QBBP C9 QBBM 100pF Figure 30. Basic Connections Rev. B | Page 12 of 20 QFLP IFLM QFLM IBBP QBBP QBBM IBBM VPS2 VPS2 04699-0-030 04699-029 AD8340 The RF output signal can be disabled by raising the DSOP pin RF OUTPUT AND MATCHING to the positive supply. The shutdown function provides >40 dB The RF outputs of the AD8340, RFOP, and RFOM, are open attenuation of the input signal even at full gain. The interface collectors of a transimpedance amplifier that needs to be pulled to DSOP is high impedance, and the shutdown and turn-on up to the positive supply, preferably with RF chokes, as shown response times are <100 ns. If the disable function is not in Figure 31. The nominal output impedance looking into each needed, the DSOP should be tied to ground. individual output pin is 25 Ω. Consequently, the differential output impedance is 50 Ω. DRIVING THE I-Q BASEBAND CONTROLS V P The I and Q inputs to the AD8340 set the gain and phase between input and output. These inputs are differential and should normally have a common-mode level of 0.5 V. However, 120nH R T when differentially driven, the common mode can vary from 100pF RFOM 250 mV to 750 mV while still allowing full gain control. Each 1:1 RF OUTPUT ±I G input pair has a nominal input swing of ±0.5 V differential SIG M 100pF around the common-mode level. The maximum gain of unity RFOP 50Ω is achieved if the differential voltage is equal to +500 mV or DIFFERENTIAL R T −500 mV. Therefore, with a common-mode level of 500 mV, IBBP and IBBM each swings between 250 mV and 750 mV. Figure 31. RF Output Interface to the AD8340 Showing Coupling Capacitors, Pull-Up RF Chokes, and Balun The I and Q inputs can also be driven with a single-ended Because the output dc levels are at the positive supply, ac signal. In this case, one side of each input should be tied to a coupling capacitors are usually needed between the AD8340 low noise 0.5 V voltage source (a 0.1 μF decoupling capacitor outputs and the next stage in the system. located close to the pin is recommended), while the other input swings from 0 V to 1 V. Differential drive generally offers A 1:1 RF broadband output balun, such as the ETC1-1-13 superior even-order distortion and lower noise than single- (M/A-COM), converts the differential output of the AD8340 ended drive. into a single-ended signal. Note that the loss and balance of the balun directly impact the apparent output power, noise floor, The bandwidth of the baseband controls exceeds 200 MHz even and gain/phase errors of the AD8340. In critical applications, at full-scale baseband drive. This allows for very fast gain and narrow-band baluns with low loss and superior balance are phase modulation of the RF input signal. In cases where lower recommended. modulation bandwidths are acceptable or desired, external filter capacitors can be connected across Pin IFLP to Pin IFLM, and If the output is taken in a single-ended fashion directly into a across Pin QFLP to Pin QFLM, to reduce the ingress of base- 50 Ω load through a coupling capacitor, there is an impedance band noise and spurious signal into the control path. mismatch. This can be resolved with a 1:2 balun to convert the single-ended 25 Ω output impedance to 50 Ω. If loss-of-signal The 3 dB bandwidth is set by choosing CFLT according to the swing is not critical, a 25 Ω back termination in series with the following equation: output pin can also be used. The unused output pin must still be 45 kHz×10 nF pulled up to the positive supply. The user can load it through a f ≈ 3 dB C + 0.5 pF coupling capacitor with a dummy load to preserve balance. The EXTERNAL gain of the AD8340 when the output is single-ended varies This equation has been verified for values of CFLT from 10 pF to slightly with the dummy load value, as shown in Figure 32. 0.1 μF (bandwidth settings of approximately 4.5 kHz to 43 MHz). –0.5 –1.0 R = SHORT L2 –1.5 –2.0 –2.5 –3.0 R = 50Ω L2 –3.5 –4.0 –4.5 –5.0 –5.5 R = OPEN L2 –6.0 700 800 900 1000 FREQUENCY (MHz) Figure 32. Gain of the AD8340 Using a Single-Ended Output with Different Dummy Loads, RL2 on the Unused Output Rev. B | Page 13 of 20 GAIN (dB) 04699-031 04699-032 AD8340 1.15 INTERFACING TO HIGH SPEED DACs 1.13 1.10 The AD977x family of dual DACs is well suited for driving the 1.08 1.05 I and Q vector controls of the AD8340. While these inputs can 1.02 in general be driven by any DAC, the differential outputs and 1.00 0.97 bias level of the Analog Devices TxDAC® family allow for a 0.95 direct connection between DAC and modulator. 0.92 0.90 The AD977x family of dual DACs has differential current 0.88 0.85 outputs. The full-scale current is user programmable and is 0.82 usually set to 20 mA, that is, each output swings from 0 mA 0.80 0.77 to 20 mA. 0.75 0.72 The basic interface between the AD9777 DAC outputs and the 0.70 AD8340 I and Q inputs is shown in Figure 33. The resistors R1 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 R3 and R2 set the dc bias level according to the equation: Figure 34. Peak-to-Peak DAC Output Swing vs. Bias Level = Average Output Current × R1 Swing Scaling Resistor R3 (R1 = R2 = 50 Ω) For example, if the full-scale current from each output is 20 mA, Figure 34 shows the relationship between the value of R3 and each output will have an average current of 10 mA. Therefore, the peak baseband voltage with R1 and R2 equal to 50 Ω. Figure 34 to set the bias level to the recommended 0.5 V, R1 and R2 shows that a value of 100 Ω for R3 provides a peak-to-peak should be set to 50 Ω each. R1 and R2 should always be equal. swing of 1 V p-p differential into the AD8340 I and Q inputs. If R3 is omitted, this results in an available swing from the DAC When using a DAC, low-pass image reject filters are typically of 2 V p-p differential, which is twice the maximum voltage used to eliminate the Nyquist images produced by the DAC. range required by the AD8340. DAC resolution can be They also provide the added benefit of eliminating broadband maximized by adding R3, which scales down this voltage noise that might feed into the modulator from the DAC. according to the following equation: CDMA2000 APPLICATION Full− Scale Swing= To test the compliance to the CDMA2000 base station standard, R2 ⎛ ⎞ a single-carrier CDMA2000 test model signal (forward pilot, sync, 2× I() R1() R2+ R3 × 1− ⎜ ⎟ MAX ⎝ R2+ R3⎠ paging, and six traffic as per 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the AD8340. A cavity-tuned filter was used to AD9777 AD8340 reduce noise from the signal source being applied to the device. The 4.6 MHz pass band of this filter is apparent in the IBBP I OUTA1 OPTIONAL R1 subsequent spectral plots (see Figure 35 to Figure 38). LOW-PASS R3 FILTER R2 Figure 35 shows a plot of the spectrum of the output signal I IBBM OUTB1 under nominal conditions. POUT is equal to −5 dBm and VI = VQ = 0.353 V, that is, VIBBP − VIBBM = VQBBP − VQBBM = 0.353 V. Adjacent channel power is measured in 30 kHz I QBBP OUTA2 resolution bandwidth at 750 kHz and 1.98 MHz carrier offset. R1 OPTIONAL LOW-PASS R3 Noise floor is measured at ±4 MHz carrier offset. R2 FILTER I QBBM OUTB2 Figure 33. Basic AD9777 to AD8340 Interface Rev. B | Page 14 of 20 04699-033 DIFFERENTIAL PEAK-TO-PEAK SWING (R3) 04699-034 AD8340 BS, 1X, C0 : ADJ CHANNEL *RBW 30kHz MARKER 2 [T1 NOI] 10 –50 *VBW 30kHz –148.76dBm/Hz REF –12dBm *ATT 5dB *SWT 100ms 876.009615385MHz P vs. V OUT IN 0 –55 OFFSET 0.5 dB CH PWR –5.17dBm –20 ACP LOW –60.94dB ACP UP –60.08dB –10 –60 ALT1 LOW –86.40dB –30 ALT1 UP –86.80dB LVL ACP – 750kHz OFFSET, 30kHz RBW MARKER 1 [T1 NOI] –20 –65 –40 –148.89dBm/Hz NOR 884.006410256MHz –50 –30 –70 –60 –40 –75 SWP 50 OF 50 –70 ACP – 1.98MHz OFFSET, 30kHz RBW –80 –50 –80 NOISE – 4MHz OFFSET, 1MHz RBW –60 –85 –90 –100 1 2 –90 –70 0 50 100 150 200 250 300 350 400 450 500 –110 V = V =V (mV) I Q IN CENTER 880MHz 1MHz/DIV SPAN 10MHz Figure 37. Output Power, Noise, and ACP vs. I and Q Control Voltages, Figure 35. Output Spectrum, Single-Carrier CDMA2000 Test Model at −5 dBm CDMA2000 Test Model, VI = VQ, ACP Measured in 30 kHz RBW at ±750 kHz V = V = 0.353 V, ACP Measured at 750 kHz and 1.98 MHz Carrier Offset, I Q and ±1.98 MHz Carrier Offset, Noise Measured at ±4 MHz Carrier Offset Noise Measured at ±4 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter (Pass Band = 4.6 MHz) In contrast to Figure 36, Figure 37 shows that for a fixed input power, ACP remains fairly constant as gain and phase are Holding the I and Q control voltages steady at 0.353 V, input changed (this is not true for very high input powers). The noise power was swept. Figure 36 shows the resulting output power, floor still drops with decreasing gain, but it never reaches the noise floor, and adjacent channel power ratio. Noise floor is −90 dBm level shown in Figure 37. presented as noise in a 1 MHz bandwidth as defined by the 3GPP2 specification. Figure 38 shows the output spectrum for a 3-carrier CDMA2000 –30 –30 spectrum. Again, the signal being applied to the AD8340 is filtered by a cavity-tuned filter with a −3 dB bandwidth of –40 –40 4.6 MHz. To reduce distortion, the total output carrier power was reduced to approximately −8 dBm (per-carrier power = –50 –50 −12.6 dBm). Adjacent channel power ratios of −61 dBc (2 MHz –60 from center of spectrum) and −82 dBc (3.23 MHz from center –60 of spectrum) were measured. The noise floor, measured at ACP – 750kHz OFFSET, 30kHz RBW –70 –70 5.25 MHz carrier offset, is approximately −149 dBm/Hz (−89 dBm in a 1 MHz bandwidth). While some dynamic range is lost due ACP – 1.98MHz OFFSET, 30kHz RBW –80 –80 to output power back-off, ACP stays approximately equal and noise floor improves slightly. –90 –90 NOISE – 4MHz OFFSET, 1MHz RBW *RBW 30kHz MARKER 1 [T1 NOI] *VBW 300kHz –148.83dBm/Hz –100 –100 REF –15 dBm *ATT 5dB *SWT 5s 885.252403846MHz –30 –25 –20 –15 –10 –5 0 5 OFFSET 0.5dB CH1 –12.65dBm OUTPUT POWER (dBm) –20 CH2 –12.58dB A CH3 –12.87dB Figure 36. Noise and ACP vs. Output Power, SOL –30 TOTAL –7.93dB Single-Carrier CDMA2000 Test Model, V = V = 0.353, I Q ACP LOW –61.41dB ACP UP –61.87dB LVL ACP Measured in 30 kHz RBW at ±750 kHz and ±1.98 MHz Carrier Offset, –40 ALT1 LOW –82.36dB Noise Measured at ±4 MHz Carrier Offset ALT1 UP –81.92dB NOR –50 The results show that at an output power of 3 dBm, ACP is still –60 in compliance with the standard (<−45 dBc @ 750 MHz and –70 <−60 dBc @ 1.98 MHz). At low output power levels, ACP at –80 1.98 MHz, carrier offset degrades as the noise floor of the –90 AD8340 becomes the dominant contributor to measured ACP. 1 –100 Measured noise at 4 MHz carrier offset begins to increase sharply above 0 dBm output power. This increase is not due to noise. –110 but results from increased carrier-induced distortion. As output CENTER 880MHz 1.5MHz/ SPAN 15MHz power drops below 0 dBm, the noise floor drops towards −90 dBm. Figure 38. Output Spectrum, 3-Carrier CDMA2000 Test Model at −12.5 dBm/Carrier, V = V = 0.353 V, ACP Measured at 2 MHz and 3.23 kHz I Q With a fixed input power of 2.4 dBm, the output power was Offset from Center of Spectrum, Noise Measured at 5.25 MHz Carrier Offset, Input Signal Filtered Using a Cavity-Tuned Filter (Pass Band = 4.6 MHz) and V were again swept by exercising the I and Q inputs. VI Q kept equal and were swept from 10 mV to 500 mV. The resulting output power, ACP, and noise floor are shown in Figure 37. Rev. B | Page 15 of 20 ACP – dBc (30kHz RBW) 04699-035 NOISE – dBm @ 4MHz CARRIER OFFSET (1MHz RBW) 04699-036 OUTPUT POWER (dBm) 04699-038 ACP – dBc (30kHz RBW) NOISE – 4MHz CARRIER OFFSET – dBm (1MHz RBW) 04699-037 AD8340 EVALUATION BOARD The baseband input of the AD8340 requires a differential The evaluation board circuit schematic for the AD8340 is voltage drive. The evaluation board is set up to allow such a shown in Figure 39. drive by connecting the differential voltage source to QBBP and The evaluation board is configured to be driven from a QBBM. The common-mode voltage should be maintained at single-ended 50 Ω source. Although the input of the AD8340 approximately 0.5 V. For this configuration, Jumper W1 to is differential, it may be driven single-ended with no loss of Jumper W4 should be removed. performance. The baseband input of the evaluation board can also be driven The low-pass corner frequency of the baseband I and Q with a single-ended voltage. In this case, a bias level is provided channels can be reduced by installing capacitors in the C11 and to the unused input from Potentiometer R10 by installing either C12 positions. The low-pass corner frequency for either W1 or W2. channel is approximated by Setting SW1 in Position B disables the AD8340 output 45 kHz×10 nF amplifier. With SW1 set to Position A, the output amplifier is f ≈ 3 dB C + 0.5 pF enabled and an external voltage signal, such as a pulse, can be EXTERNAL applied to the DSOP SMA connector to exercise the output On the evaluation board, the I and Q baseband circuits are amplifier enable/disable function. identical, so the following description applies equally to each. The connections and circuit configuration for the Q baseband inputs are described in Table 4. Rev. B | Page 16 of 20 AD8340 Table 4. Evaluation Board Configuration Options Components Description Default Conditions R7, R9, R11, R14, I Channel Baseband Interface. Resistor R7 and Resistor R9 can be R7, R9 = open R15, R19, R20, R21, installed to accommodate a baseband source that requires a R11 = potentiometer, 2 kΩ, 10 turns (Bourns) C15, C19, W3, W4 specific terminating impedance. C15 and C19 are bypass R14 = 4 kΩ (Size 0603) capacitors. For single-ended baseband drive, Potentiometer R11 R15 = 44 kΩ (Size 0603) can be used to provide a bias level to the unused input (install R19, R20, R21 = 0 Ω (Size 0603) either W3 or W4). C15, C19 = 0.1 μF (Size 0603) W3 = jumper (installed) W4 = jumper (open) R1, R3, R10, R12, Q Channel Baseband Interface. See the I Channel Baseband R1, R3 = open R13, R16, R17, R18, Interface description. R10 = potentiometer, 2 kΩ, 10 turns (Bourns) C16, C20, W1, W2 R12 = 4 kΩ (Size 0603) R13 = 44 kΩ (Size 0603) R16, R17, R18 = 0 Ω (Size 0603) C16, C20 = 0.1 μF (Size 0603) W1 = jumper (installed) W2 = jumper (open) C11, C12 Baseband Low-Pass Filtering. By adding Capacitor C11 between C11, C12 = open QFLP and QFLM, and Capacitor C12 between IFLP and IFLM, the 3 dB low-pass corner frequency of the baseband interface can be reduced from 230 MHz (nominal). See the equation in the Evaluation Board section. T1, C17, C18, L1, L2 Output Interface. The 1:1 balun transformer, T1, converts the 50 Ω C17, C18 = 100 pF (Size 0603) differential output to 50 Ω single-ended. C17 and C18 are dc T1 = ETC1-1-13 (M/A-COM) blocks. L1 and L2 provide dc bias for the output. L1, L2 = 120 nH (Size 0603) L3, L4, C5, C6 Input Interface. The input impedance of the AD8340 requires 5.6 nH L3, L4 = 5.6 nH (Size 0402) inductors in series with RFIP and RFIM for optimum return loss C5, C6 = 100 pF (Size 0603) when driven by a single-ended 50 Ω line. C5 and C6 are dc blocks. C2, C4, C7, C9, C14, Supply Decoupling. C2, C4, C7, C9 = open (Size 0603) C1, C3, C8, C10, C1, C3, C8, C10, C14 = 0.1 μF (Size 0603) R2, R4, R5, R6 R2, R4, R5, R6 = 0 Ω (Size 0603) R8, SW1 Output Disable Interface. The output stage of the AD8340 is R8 = 10 kΩ (Size 0603) disabled by applying a high voltage to the DSOP pin by moving SW1 = SPDT (Position A, output enabled) SW1 to Position B. The output stage is enabled by moving SW1 to Position A. The output disable function can also be exercised by applying an external high or low voltage to the DSOP SMA connector with SW1 in Position A. Rev. B | Page 17 of 20 AD8340 SCHEMATIC AND ARTWORK IBBP IBBM C19 R9 R7 0.1µF VP GND (OPEN) (OPEN) TEST POINT TEST POINT R19 0Ω W4 W3 C2 R21 R20 C15 (OPEN) 0Ω 0Ω 0.1µF R2 VS 0Ω R14 R11 R15 4kΩ 2kΩ 44kΩ C1 0.1µF C12 B (OPEN) SW1 R8 A C7 C8 R5 10kΩ DSOP (OPEN) 0.1µF IFLP DSOP 0Ω VP VPRF CMOP T1 CMRF CMOP C6 L3 C17 ETC1-1-13 5.6nH 100pF 100pF M/A-COM RFIM RFOM RFOP AD8340 RFIN RFIP RFOP L4 C5 C18 5.6nH L1 L2 100pF 100pF CMRF CMOP 120nH 120nH VP VPRF CMOP R4 C4 C3 C14 VPS2 0Ω (OPEN) 0.1µF 0.1µF VP C11 R6 C10 C9 (OPEN) 0Ω 0.1µF (OPEN) R12 R10 R13 4kΩ 2kΩ 44kΩ VS C16 0.1µF W2 W1 R17 R18 R16 0Ω 0Ω 0Ω R1 R3 C20 OPEN OPEN 0.1µF QBBP QBBM Figure 39. Evaluation Board Schematic Rev. B | Page 18 of 20 QFLP IFLM QFLM IBBP QBBP QBBM IBBM VPS2 VPS2 04699-039 AD8340 Figure 41. Component Side Silkscreen Figure 40. Component Side Layout Rev. B | Page 19 of 20 04699-040 04699-0-041 AD8340 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 19 24 1 18 0.50 2.25 PIN 1 BSC TOP 3.75 BOTTOM INDICATOR 2.10 SQ VIEW BSC SQ VIEW 1.95 0.50 13 6 0.40 12 7 0.30 0.25 MIN 2.50 REF 0.80 MAX 1.00 12° MAX 0.65TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY 0.30 0.08 0.20 REF 0.23 SEATING 0.18 PLANE COMPLIANT TOJEDECSTANDARDSMO-220-VGGD-2 Figure 42. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters ORDERING GUIDE Package Ordering Model Temperature Range Package Description Option Quantity 1, 2 AD8340ACPZ-WP −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1 64 1 AD8340ACPZ-REEL7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-24-1 1,500 1 AD8340-EVALZ Evaluation Board 1 1 Z = RoHS Compliant Part. 2 WP = Waffle pack. ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04699-0-8/07(B) Rev. B | Page 20 of 20