ANALOG DEVICES AD8337

General-Purpose, Low Cost, DC-Coupled VGA AD8337 FEATURES FUNCTIONAL BLOCK DIAGRAM VPOS Low noise 8 8 Voltage noise = 2.2 nV/√Hz AD8337 Current noise = 4.8 pA/√Hz (positive input) GAIN CONTROL Wide bandwidth (−3 dB) = 280 MHz GAIN 7 18dB 1 VOUT INTERFACE Nominal gain range: 0 dB to 24 dB (preamp gain = 6 dB) Gain scaling: 19.7 dB/V PREAMP DC-coupled (PrA) EIGHT SECTIONS 3 INPP + Single-ended input and output High speed uncommitted op amp input – 4 INPN Supplies: +5 V, ±2.5 V, or ±5 V VCOM 2 Low power: 78 mW with ±2.5 V supplies 5 6 PRAO VNEG APPLICATIONS Figure 1. Gain trim PET scanners High performance AGC systems I/Q signal processing Video Industrial and medical ultrasound Radar receivers GENERAL DESCRIPTION The AD8337 is a low noise, single-ended, linear-in-dB, general- The AD8337 includes an uncommitted operational current- purpose variable gain amplifier (VGA) usable at frequencies feedback preamplifier (PrA) that operates in inverting or from dc to 100 MHz; the −3 dB bandwidth is 280 MHz. noninverting configurations. Using external resistors, the device Excellent bandwidth uniformity across the entire gain range can be configured for gains of 6 dB or greater. The AD8337 is and low output-referred noise makes the AD8337 ideal for characterized by a noninverting PrA gain of 2× using two external gain trim applications and for driving high speed analog-to- 100 Ω resistors. The attenuator has a range of 24 dB, and the digital converters (ADCs). output amplifier has a fixed gain of 8× (18.06 dB). The lowest nominal gain range is 0 dB to 24 dB and can be shifted up or down Excellent dc characteristics combined with high speed make the by adjusting the preamp gain. Multiple AD8337 devices can be AD8337 particularly suited for industrial ultrasound, PET connected in series for larger gain ranges, interstage filtering to scanners, and video applications. Dual-supply operation enables suppress noise and distortion, and nulling offset voltages. gain control of negative-going pulses, such as those generated by photodiodes or photomultiplier tubes. The operating temperature range of the AD8337 is −40°C to +85°C, and is available in an 8-lead, 3 mm × 3 mm LFCSP. The AD8337 uses the popular and versatile X-AMP® architecture, exclusively from Analog Devices, Inc., with a gain range of 24 dB. The gain control interface provides precise linear-in-dB scaling of 19.7 dB/V, referenced to VCOM. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2005–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 05575-001 AD8337 TABLE OF CONTENTS Features .............................................................................................. 1  Single-Supply Operation and AC Coupling ........................... 19  Applications ....................................................................................... 1  Noise ............................................................................................ 19  Functional Block Diagram .............................................................. 1  Applications Information .............................................................. 20  General Description ......................................................................... 1  Preamplifier Connections ......................................................... 20  Revision History ............................................................................... 2  Driving Capacitive Loads .......................................................... 20  Specif ica t ions ..................................................................................... 3  Gain Control Considerations ................................................... 21  Absolute Maximum Ratings ............................................................ 5  Thermal Considerations ............................................................ 22  ESD Caution .................................................................................. 5  PSI (Ψ) ......................................................................................... 22  Pin Configuration and Function Descriptions ............................. 6  Board Layout ............................................................................... 22  Typical Performance Characteristics ............................................. 7  Evaluation Boards ........................................................................... 23  Test Circuits ..................................................................................... 14  Circuit Options ........................................................................... 24  Theory of Operation ...................................................................... 18  Output Protection ...................................................................... 24  Overview ...................................................................................... 18  Measurement Setup.................................................................... 25  Preamplifier ................................................................................. 18  Board Layout Considerations ................................................... 25  V GA .............................................................................................. 18  Bill of Materials ........................................................................... 27  Gain Control ............................................................................... 18  Outline Dimensions ....................................................................... 29  Output Stage ................................................................................ 19  Ordering Guide .......................................................................... 29  A ttenuator .................................................................................... 19  REVISION HISTORY 9/08—Rev. B to Rev. C 6/06—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Updated Format .................................................................. Universal Added Exposed Pad Note to Figure 2 and Table 3 ....................... 6 Changes to Table 3 ............................................................................. 6 Changes to Figure 49 ...................................................................... 14 Changes to Figure 22, Figure 25, and Figure 26 ......................... 10 Changes to Evaluation Boards Section ........................................ 23 Changes to Figure 39 and Figure 40............................................. 13 Changes to Circuit Options Section ............................................. 24 Changes to Figure 74 and Figure 75............................................. 23 Changes to Output Protection Section ........................................ 24 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 Changes to Measurement Setup Section ..................................... 25 Changes to Board Layout Considerations Section ..................... 25 9/05—Revision 0: Initial Version Changes to Bill of Materials Section ............................................ 27 Updated Outline Dimensions, Changes to Ordering Guide .... 29 2/07—Rev. A to Rev. B Changes to Figure 30, Figure 31, and Figure 32 ......................... 11 Changes to Single-Supply Operation and AC Coupling Section ..................................................................... 19 Moved Noise Section to Page ........................................................ 19 Changes to Ordering Guide .......................................................... 24 Rev. C | Page 2 of 32 AD8337 SPECIFICATIONS VS = ±2.5 V, TA = 25°C, PrA gain = +2, VCOM = GND, f = 10 MHz, CL = 5 pF, RL = 500 Ω, including a 20 Ω snubbing resistor, unless otherwise specified. Table 1. Parameter Conditions Min Typ Max Unit GENERAL PARAMETERS −3 dB Small Signal Bandwidth VOUT = 10 mV p-p 280 MHz −3 dB Large Signal Bandwidth VOUT = 1 V p-p 100 MHz Slew Rate VOUT = 2 V p-p 625 V/μs V = 1 V p-p 490 V/μs OUT Input Voltage Noise f = 10 MHz 2.15 nV/√Hz Input Current Noise f = 10 MHz 4.8 pA/√Hz Noise Figure VGAIN = 0.7 V, RS = 50 Ω, unterminated 8.5 dB VGAIN = 0.7 V, RS = 50 Ω, shunt terminated with 50 Ω 14 dB Output-Referred Noise VGAIN = 0.7 V (gain = 24 dB) 34 nV/√Hz V = −0.7 V (gain = 0 dB) 21 nV/√Hz GAIN Output Impedance DC to 10 MHz 1 Ω Output Signal Range V RL ≥ 500 Ω, VS = ±2.5 V, +5 V VCOM ± 1.3 V RL ≥ 500 Ω, VS = ±5 V VCOM ± 2.4 Output Offset Voltage V = 0.7 V (gain = 24 dB) −25 ±5 +25 mV GAIN DYNAMIC PERFORMANCE Harmonic Distortion VGAIN = 0 V, VOUT = 1 V p-p HD2 f = 1 MHz −72 dBc HD3 −66 dBc HD2 f = 10 MHz −62 dBc HD3 −63 dBc HD2 f = 45 MHz −58 dBc HD3 −56 dBc Input 1 dB Compression Point V = −0.7 V, f = 10 MHz (preamp limited) 8.2 dBm GAIN V = +0.7 V, f = 10 MHz (VGA limited) −9.4 dBm GAIN Two-Tone Intermodulation Distortion (IMD3) VGAIN = 0 V, VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz −71 dBc VGAIN = 0 V, VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −57 dBc VGAIN = 0 V, VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −58 dBc V = 0 V, V = 2 V p-p, f = 45 MHz, f = 46 MHz −45 dBc GAIN OUT 1 2 Output Third-Order Intercept V = 0 V, V = 1 V p-p, f = 10 MHz 34 dBm GAIN OUT V = 0 V, V = 1 V p-p, f = 45 MHz 28 dBm GAIN OUT VGAIN = 0 V, VOUT = 2 V p-p, f = 10 MHz 35 dBm VGAIN = 0 V, VOUT = 2 V p-p, f = 45 MHz 26 dBm Overload Recovery V = 0.75 V, V = 50 mV p-p to 500 mV p-p 50 ns GAIN IN Group Delay Variation 1 MHz < f < 100 MHz, full gain range ±1 ns Rev. C | Page 3 of 32 AD8337 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE VS = ±5 V Harmonic Distortion VGAIN = 0 V, VOUT = 1 V p-p HD2 f = 1 MHz −85 dBc HD3 −75 dBc HD2 f = 10 MHz −90 dBc HD3 −80 dBc HD2 f = 35 MHz −75 dBc HD3 −76 dBc Input 1 dB Compression Point V = −0.7 V, f = 10 MHz 14.5 dBm GAIN V = +0.7 V, f = 10 MHz −1.7 dBm GAIN Two-Tone Intermodulation Distortion (IMD3) V = 0 V, V = 1 V p-p, f = 10 MHz, f = 11 MHz −74 dBc GAIN OUT 1 2 VGAIN = 0 V, VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz −60 dBc VGAIN = 0 V, VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz −64 dBc VGAIN = 0 V, VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz −49 dBc Output Third-Order Intercept V = 0 V, V = 1 V p-p, f = 10 MHz 35 dBm GAIN OUT V = 0 V, V = 1 V p-p, f = 45 MHz 28 dBm GAIN OUT V = 0 V, V = 2 V p-p, f = 10 MHz 36 dBm GAIN OUT VGAIN = 0 V, VOUT = 2 V p-p, f = 45 MHz 28 dBm Overload Recovery VGAIN = 0.7 V, VIN = 0.1 V p-p to 1 V p-p 50 ns ACCURACY Absolute Gain Error −0.7 V < VGAIN < −0.6 V 0.7 to 3.5 dB −0.6 V < VGAIN < −0.5 V −1.25 ±0.35 +1.25 dB −0.5 V < V < +0.5 V −1.0 ±0.25 +1.0 dB GAIN 0.5 V < V < 0.6 V −1.25 ±0.35 +1.25 dB GAIN 0.6 V < V < 0.7 V −0.7 to −3.5 dB GAIN GAIN CONTROL INTERFACE Gain Scaling Factor −0.6 V < V < +0.6 V 19.7 dB/V GAIN Gain Range 24 dB Intercept VGAIN = 0 V 12.65 dB Input Voltage (VGAIN) Range No foldover −VS +VS V Input Impedance 70 MΩ Bias Current −0.7 V < V < +0.7 V 0.3 μA GAIN Response Time 24 dB gain change 200 ns POWER SUPPLY Supply Voltage V to V (dual- or single-supply operation) 4.5 5 10 V POS NEG V = ±2.5 V S Quiescent Current Each supply (VPOS and VNEG) 10.5 15.5 23.5 mA Power Dissipation No signal, VPOS to VNEG = 5 V 78 mW PSRR VGAIN = 0.7 V, f = 1 MHz −40 dB V = ±5 V S Quiescent Current Each supply (VPOS and VNEG) 13.5 18.5 25.5 mA Power Dissipation No signal, VPOS to VNEG = 10 V 185 mW PSRR VGAIN = 0.7 V, f = 1 MHz −40 dB Rev. C | Page 4 of 32 AD8337 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Voltage rating only; functional operation of the device at these or any Supply Voltage (VPOS, VNEG) ±6 V other conditions above those indicated in the operational Input Voltage (INPx) VPOS, VNEG section of this specification is not implied. Exposure to absolute GAIN Voltage VPOS, VNEG maximum rating conditions for extended periods may affect Power Dissipation 866 mW (Exposed Pad Soldered to PCB) device reliability. Temperature ESD CAUTION Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C Thermal Data, 4-Layer JEDEC Board No Air Flow Exposed Pad Soldered to PCB θ 75.4°C/W JA θ 47.5°C/W JB θJC 17.9°C/W ΨJT 2.2°C/W ΨJB 46.2°C/W Rev. C | Page 5 of 32 AD8337 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 VOUT 1 8 VPOS VCOM 2 AD8337 7 GAIN TOP VIEW 3 6 INPP VNEG (Not to Scale) INPN 4 5 PRAO NOTES 1. FOR BEST THERMAL PERFORMANCE, EXPOSED PAD MUST BE SOLDERED TO PCB. Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 VOUT VGA Output. 2 VCOM Common Ground When Using Plus and Minus Supply Voltages. For single-supply operation, provide half the positive supply voltage at the VPOS pin to VCOM pin. 3 INPP Positive Input to Preamplifier. 4 INPN Negative Input to Preamplifier. 5 PRAO Preamplifier Output. 6 VNEG Negative Supply (−VPOS for Dual-Supply; GND for Single-Supply). 7 GAIN Gain Control Input Centered at VCOM. 8 VPOS Positive Supply. EP Exposed Pad For best thermal performance, exposed pad must be soldered to PCB. Rev. C | Page 6 of 32 05575-002 AD8337 TYPICAL PERFORMANCE CHARACTERISTICS V = ±2.5 V, T = 25°C, R = 500 Ω, including a 20 Ω snubbing resistor, f = 10 MHz, C = 2 pF, V = 10 mV p-p, noninverting S A L L IN configuration, unless otherwise noted. 30 60 500 UNITS +85°C V = –0.4V +25°C GAIN 25 –40°C 50 V =0V GAIN V = +0.4V GAIN 20 40 15 30 10 20 5 10 0 –5 0 –800 –600 –400 –200 0 200 400 600 800 V (mV) GAIN GAIN ERROR (dB) Figure 6. Gain Error Histogram for Three Values of VGAIN Figure 3. Gain vs. V at Three Temperatures GAIN (See Figure 44) 50 2.0 500 UNITS +85°C –0.4V≤ V ≤ +0.4V GAIN +25°C 1.5 –40°C 40 1.0 0.5 30 0 20 –0.5 –1.0 10 –1.5 0 –2.0 19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.0 20.1 –800 –600 –400 –200 0 200 400 600 800 GAIN SCALING (dB/V) (mV) V GAIN Figure 4. Gain Error vs. V at Three Temperatures Figure 7. Gain Scaling Histogram GAIN (See Figure 44) 2.0 50 f = 1MHz 500 UNITS RELATIVE TO BEST FIT f = 10MHz LINE FOR 10MHz 1.5 f = 70MHz f = 100MHz 40 f = 150MHz 1.0 0.5 30 0 20 –0.5 –1.0 10 –1.5 0 –2.0 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13.0 –800 –600 –400 –200 0 200 400 600 800 INTERCEPT (dB) V (mV) GAIN Figure 5. Gain Error vs. V at Five Frequencies Figure 8. Intercept Histogram GAIN (See Figure 44) Rev. C | Page 7 of 32 GAIN ERROR (dB) GAIN ERROR (dB) GAIN (dB) 05575-003 05575-005 05575-004 % OF UNITS % OF UNITS % OF UNITS –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 05575-008 05575-007 05575-006 AD8337 30 30 V = 0V GAIN e = 10mV p-p IN 25 25 V = +0.7 GAIN V = +0.5 GAIN 20 20 V = +0.2 GAIN 15 15 V = 0 GAIN 10 10 V = –0.2 GAIN 5 5 V = –0.5 GAIN C = 47pF L C = 22pF L 0 0 C = 10pF V = –0.7 L GAIN C = 0pF L –5 –5 100k 1M 10M 100M 500M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 9. Frequency Response for Various Values of V Figure 12. Frequency Response for Three Values of CL GAIN (See Figure 45) with a 20 Ω Snubbing Resistor (See Figure 45) 20 10 V = +0.7 V = ±2.5V GAIN S V = ±5V S 15 V = +0.5 GAIN 8 V = +0.2 GAIN 10 V = 0 GAIN 6 5 V = –0.2 GAIN 0 4 V = –0.5 GAIN –5 V = –0.7 GAIN 2 –10 e = 10mV p-p IN –15 0 100k 1M 10M 100M 500M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 10. Frequency Response for Various Values of V —Inverting Input Figure 13. Frequency Response—Preamp GAIN (See Figure 58) (See Figure 46) 30 25 V = 0V GAIN e = 10mV p-p IN 25 20 20 15 15 10 10 5 5 0 C = 47pF L C = 22pF L 0 –5 C = 10pF L C = 0pF L –5 –10 100k 1M 10M 100M 500M 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Frequency Response for Three Values of CL Figure 14. Group Delay vs. Frequency (See Figure 45) (See Figure 47) Rev. C | Page 8 of 32 GAIN (dB) GAIN (dB) GAIN (dB) 05575-011 05575-010 05575-009 GROUP DELAY (ns) GAIN (dB) GAIN (dB) 05575-014 05575-013 05575-012 AD8337 10 40 +85°C V = ±5V S +25°C 8 –40°C 6 35 4 2 30 0 –2 25 V = ±2.5V S –4 –6 20 +85°C –8 +25°C –40°C –10 15 –800 –600 –400 –200 0 200 400 600 800 –800 –600 –400 –200 0 200 400 600 800 V (mV) V (mV) GAIN GAIN Figure 15. Offset Voltage vs. VGAIN at Three Temperatures Figure 18. Output-Referred Noise vs. VGAIN at Three Temperatures (See Figure 48) (See Figure 50) 80 25 500 UNITS +85°C +25°C V = –0.4V GAIN 70 –40°C V =0V GAIN 20 V = +0.4V GAIN 60 50 15 40 10 30 20 5 10 0 0 –15 –10 –5 0 5 10 15 20 25 –800 –600 –400 –200 0 200 400 600 800 OUTPUT OFFSET VOLTAGE (mV) V (mV) GAIN Figure 16. Output Offset Voltage Histogram for Three Values of V Figure 19. Short-Circuit, Input-Referred Noise at Three Temperatures GAIN (See Figure 50) 1k 7 V = 0.7V GAIN V = ±2.5V S R = R = 100Ω FB1 FB2 V = ±5V S 6 100 5 PREAMP GAIN = –1 4 10 3 PREAMP GAIN = +2 2 1 1 0.1 0 1M 10M 100M 500M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. VGA Output Impedance vs. Frequency Figure 20. Short-Circuit, Input-Referred Noise vs. Frequency at Maximum (See Figure 49) Gain—Inverting and Noninverting Preamp Gain = −1 and +2 (See Figure 50) Rev. C | Page 9 of 32 IMPEDANCE (Ω) OFFSET VOLTAGE (mV) % OF UNITS 05575-016 05575-017 05575-015 NOISE (nV/√Hz) NOISE (nV/√Hz) NOISE (nV/√Hz) 05575-020 05575-019 05575-018 AD8337 10 –40 f = 10MHz, HD3 V = 0.7V GAIN HD2 –50 INPUT-REFERRED NOISE 1 –60 R THERMAL NOISE ALONE S –70 –80 0.1 05 10 15 20 25 30 35 40 45 50 11 10 100k LOAD CAPACITANCE (pF) SOURCE RESISTANCE (Ω) Figure 21. Input-Referred Noise vs. RS Figure 24. Harmonic Distortion vs. Load Capacitance (See Figure 61) (See Figure 52) 35 –30 50Ω SOURCE 30 –40 25 –50 WITH 50Ω SHUNT TERMINATION AT INPUT 20 UNTERMINATED –60 15 –70 1MHz 10 10MHz 35MHz 100MHz 5 –80 –800 –600 –400 –200 0 200 400 600 800 –800 –600 –400 –200 0 200 400 600 800 V (mV) V (mV) GAIN GAIN Figure 25. HD2 vs. V at Four Frequencies Figure 22. Noise Figure vs. V GAIN GAIN (See Figure 52) (See Figure 51) –30 –40 1MHz V = 1V p-p HD3 V = ±2.5V S 10MHz OUT HD3 V = ±5V S V = 0V 35MHz GAIN HD2 V = ±2.5V S 100MHz HD2 V = ±5V –40 S –50 –50 –60 –60 –70 –70 –80 –80 –800 –600 –400 –200 0 200 400 600 800 0 200 400 600 800 1.0k 1.2k 1.4k 1.6k 1.8k 2.0k V (mV) GAIN LOAD RESISTANCE (Ω) Figure 26. HD3 vs. V at Four Frequencies Figure 23. Harmonic Distortion vs. R and Supply Voltage GAIN L (See Figure 52) (See Figure 52) Rev. C | Page 10 of 32 INPUT-REFERRED NOISE (nV/√Hz) NOISE FIGURE (dB) HARMONIC DISTORTION (dBc) 05575-023 05575-022 05575-021 SECOND-ORDER HARMONIC DISTORTION (dBc) THIRD-ORDER HARMONICDISTORTION (dBc) HARMONIC DISTORTION (dBc) 05575-026 05575-025 05575-024 AD8337 –30 50 V = 2V p-p OUT V = 1V p-p OUT V = 0.5V p-p OUT –40 LIMITED BY 40 MAXIMUM PREAMP OUTPUT SWING –50 30 –60 20 –70 10 1MHz –80 10MHz 45MHz V = 1V p-p OUT 70MHz TONES SEPARATED BY 100kHz 100MHz –90 0 –800 –600 –400 –200 0 200 400 600 800 –800 –600 –400 –200 0 200 400 600 800 V (mV) V (mV) GAIN GAIN Figure 27. HD2 vs. VGAIN for Three Levels of Output Voltage Figure 30. Output-Referred IP3 (OIP3) vs. VGAIN (See Figure 52) at Five Frequencies (See Figure 64) –30 50 V = 2V p-p OUT V = 1V p-p OUT V = 0.5V p-p LIMITED BY OUT –40 MAXIMUM PREAMP 40 OUTPUT SWING –50 30 –60 20 –70 10 1MHz –80 10MHz V = ±5V S 45MHz V = 1V p-p 70MHz OUT TONES SEPARATED BY 100kHz 100MHz –90 0 –800 –600 –400 –200 0 200 400 600 800 –800 –600 –400 –200 0 200 400 600 800 V (mV) V (mV) GAIN GAIN Figure 28. HD3 vs. VGAIN for Three Levels of Output Voltage Figure 31. Output-Referred IP3 (OIP3) vs. VGAIN, VS = ±5 V (See Figure 52) at Five Frequencies (See Figure 64) 20 –20 V = 1V p-p OUT V = ±2.5V S PREAMP LIMITED V = 0V GAIN V = ±5V S TONES SEPARATED BY 100kHz 15 –30 10 –40 5 –50 0 –60 –5 –70 –10 V = ±2.5V S V = ±5V S –80 –15 1M 10M 100M –800 –600 –400 –200 0 200 400 600 800 V (mV) FREQUENCY (Hz) GAIN Figure 29. IMD3 vs. Frequency Figure 32. Input-Referred P1dB (IP1dB) vs. V GAIN (See Figure 64) (See Figure 63) Rev. C | Page 11 of 32 IMD3 (dBc) THIRD-ORDER HARMONIC DISTORTION (dBc) SECOND-ORDER HARMONIC DISTORTION (dBc) 05575-028 05575-029 05575-027 INPUT-REFERRED P1dB (dBm) OUTPUT-REFERRED IP3 (dBm) OUTPUT-REFERRED IP3 (dBm) 05575-032 05575-031 05575-030 AD8337 80 8 800 80 V = 0.7V C = 0pF L GAIN C = 10pF L 60 6 600 60 C = 22pF L C = 47pF L 40 4 400 40 20 2 200 20 0 0 0 0 –20 –2 –200 –20 INPUT INPUT –40 –400 –4 –40 OUTPUT OUTPUT –60 –6 –600 –60 V = ±2.5V S V = 0.7V GAIN –8 –80 –80 –800 –20 –10 0 10 20 30 40 50 60 70 –20 –10 0 10 20 30 40 50 60 70 TIME (ns) TIME (ns) Figure 33. Small Signal Pulse Response Figure 36. Large Signal Pulse Response for Three Capacitive Loads (See Figure 53) (See Figure 53) 800 80 80 8 C = 0pF V = 0.7V L GAIN C = 10pF L 600 60 60 6 C = 22pF L INPUT C = 47pF L 400 40 40 4 20 2 200 20 0 0 0 0 –20 –2 –200 –20 INPUT –400 –40 –4 –40 OUTPUT OUTPUT –60 –6 –600 –60 V = ±5V S V = 0.7V GAIN –80 –80 –8 –800 –20 –10 0 10 20 30 40 50 60 70 –20 –10 0 10 20 30 40 50 60 70 TIME (ns) TIME (ns) Figure 34. Small Signal Pulse Response—Inverting Feedback Figure 37. Large Signal Pulse Response for Three Capacitive Loads, VS = ±5 V (See Figure 59) (See Figure 53) 800 80 0.8 V = 0.7V GAIN 600 60 0.6 V OUT 400 40 0.4 200 20 0.2 0 0 0 –200 –20 –0.2 INPUT –400 –40 –0.4 OUTPUT –600 –60 –0.6 V GAIN –80 –800 –0.8 –20 –10 0 10 20 30 40 50 60 70 –0.5 0 0.5 1.0 1.5 2.0 TIME (ns) TIME (µs) Figure 35. Large Signal Pulse Response Figure 38. Gain Response (See Figure 53) (See Figure 54) Rev. C | Page 12 of 32 V (mV) OUT V (mV) V (mV) OUT OUT V (mV) V (mV) IN IN V (mV) IN 05575-034 05575-033 05575-035 V (mV) V (mV) OUT OUT (V) 05575-038 V (mV) V (mV) IN IN 05575-037 05575-036 AD8337 1.5 10 V (V) V = +0.7V, V = ±2.5V V = 0.7V IN GAIN S GAIN V (V) V = +0.7V, V = ±5V OUT GAIN S 0 V = 0V, V = ±2.5V GAIN S 1.0 V = 0V, V = ±5V GAIN S –10 V = –0.7V, V = ±2.5V GAIN S V = –0.7V, V = ±5V GAIN S 0.5 –20 –30 0 –40 –0.5 –50 –60 –1.0 –70 –1.5 –80 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 100k 1M 10M 100M FREQUENCY (Hz) TIME (µs) Figure 39. Preamp Overdrive Recovery Figure 42. PSRR vs. Frequency of Negative Supply (See Figure 55) (See Figure 60) 1.5 24 V (V) V = 0.7V IN V = ±5V GAIN S V (V) OUT V = ±2.5V S 1.0 22 0.5 20 0 18 –0.5 16 –1.0 14 –1.5 12 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 –50 –30 –10 10 30 50 70 90 TEMPERATURE (°C) TIME (µs) Figure 43. Quiescent Supply Current vs. Temperature Figure 40. VGA Overdrive Recovery (See Figure 57) (See Figure 56) 10 V = +0.7V, V = ±2.5V GAIN S V = +0.7V, V = ±5V GAIN S 0 V = 0V, V = ±2.5V GAIN S V = 0V, V = ±5V GAIN S –10 V = –0.7V, V = ±2.5V GAIN S V = –0.7V, V = ±5V GAIN S –20 –30 –40 –50 –60 –70 –80 100k 1M 10M 100M FREQUENCY (Hz) Figure 41. PSRR vs. Frequency of Positive Supply (See Figure 60) Rev. C | Page 13 of 32 (V) (V) PSRR (dB) 05575-041 05575-040 05575-039 QUIESCENT SUPPLY CURRENT (mA) PSRR (dB) 05575-043 05575-042 AD8337 TEST CIRCUITS NETWORK ANALYZER NETWORK ANALYZER OUT IN OUT IN 50Ω 50Ω 50Ω 50Ω AD8337 AD8337 3 + 20Ω 453Ω 453Ω PrA 1 + 3 20Ω 49.9Ω – 4 PrA 1 49.9Ω 56.2Ω 4 – 56.2Ω 5 7 100Ω 5 7 V 100Ω GAIN 100Ω 100Ω Figure 47. Group Delay Figure 44. Gain and Gain Error vs. VGAIN NETWORK ANALYZER OSCILLOSCOPE FUNCTION GENERATOR OUT IN OUT CH1 CH2 50Ω 50Ω 50Ω 50Ω 50Ω V GAIN DIFFERENTIAL 7 453Ω FET PROBE AD8337 AD8337 3 453Ω + 20Ω 3 + 49.9Ω PrA 1 PrA 1 4 – 4 – 50Ω 57 5 OPTIONAL 100Ω 100Ω POSITIONS FOR C L V GAIN 100Ω 100Ω Figure 45. Frequency Response Figure 48. Offset Voltage NETWORK ANALYZER NETWORK ANALYZER CONFIGURE TO MEASURE Z CONVERTED S11 IN OUT IN 50Ω 50Ω 50Ω 0Ω AD8337 NC NC AD8337 3 3 0Ω + 20Ω 453Ω + PrA 1 PrA 1 49.9Ω 49.9Ω 4 4 – – 5 7 5 7 100Ω 100Ω NC 453Ω NC 100Ω 100Ω Figure 49. Output Impedance vs. Frequency Figure 46. Frequency Response—Preamp Rev. C | Page 14 of 32 05575-046 05575-045 05575-044 05575-048 05575-049 05575-047 AD8337 OSCILLOSCOPE PULSE SPECTRUM ANALYZER POWER GENERATOR SPLITTER OUT CH1 CH2 IN 50Ω 50Ω 50Ω 0Ω AD8337 AD8337 3 + 20Ω 453Ω PrA 1 3 + 0Ω 4 – PrA 1 49.9Ω – 4 56.2Ω 49.9Ω 5 7 100Ω 5 7 0.7V 100Ω V 100Ω GAIN 100Ω Figure 53. Pulse Response Figure 50. Input-Referred and Output-Referred Noise DUAL FUNCTION GENERATOR OSCILLOSCOPE POWER NOISE FIGURE METER SPLITTER SINE SQUARE NOISE CH1 CH2 WAVE WAVE SOURCE INPUT 50Ω 50Ω DRIVE NOISE SOURCE V GAIN DIFFERENTIAL 0Ω 7 FET PROBE AD8337 AD8337 3 20Ω 453Ω 3 + + 0Ω 49.9Ω PrA 1 NC PrA 1 (OR∞) 49.9Ω 4 – 4 – 5 5 7 100Ω 100Ω V GAIN 100Ω 100Ω Figure 54. Gain Response Figure 51. Noise Figure vs. VGAIN SPECTRUM ANALYZER FUNCTION GENERATOR OSCILLOSCOPE R INPUT L SIGNAL GENERATOR 50Ω CH2 OUTPUT CH1 LOW- 50Ω PASS FILTER NC AD8337 7 AD8337 3 + 20Ω 49.9Ω PrA 1 4 – 3 + C L PrA 1 NC 49.9Ω 4 – 5 7 100Ω 5 V GAIN 100Ω 100Ω 100Ω 100Ω Figure 52. Harmonic Distortion Figure 55. Preamp Overdrive Recovery Rev. C | Page 15 of 32 05575-051 05575-050 05575-052 05575-053 05575-055 05575-054 AD8337 FUNCTION GENERATOR OSCILLOSCOPE POWER OSCILLOSCOPE SPLITTER PULSE POWER GENERATOR OUTPUT SPLITTER CH1 CH2 OUT 50Ω 50Ω CH1 CH2 50Ω 50Ω AD8337 AD8337 3 + 20Ω 453Ω NC PrA 1 3 20Ω 453Ω + 49.9Ω 4 – PrA 1 4 – 100Ω 56.2Ω 100Ω 5 100Ω 5 7 100Ω 100Ω 0.7V Figure 56. VGA Overdrive Recovery Figure 59. Pulse Response—Inverting Feedback +SUPPLY TO NETWORK ANALYZER BIAS PORT NETWORK ANALYZER BENCH POWER SUPPLY DMM OUT IN (+I) 50Ω 50Ω 8 BYPASS CAPACITORS AD8337 VPOS REMOVED FOR MEASUREMENT 3 + AD8337 DMM PrA 1 (V) 4 – 3 + PrA 1 DIFFERENTIAL 49.9Ω 4 – FET PROBE 5 7 6 100Ω 5 7 DMM 100Ω (–I) 100Ω V GAIN 100Ω Figure 57. Supply Current Figure 60. PSRR SPECTRUM ANALYZER NETWORK ANALYZER IN OUT IN 50Ω 50Ω 50Ω 453Ω AD8337 AD8337 3 + 3 + 20Ω PrA 1 PrA 1 100Ω 4 – 4 – 100Ω 5 7 5 7 100Ω 100Ω V GAIN V 100Ω GAIN Figure 58. Frequency Response—Inverting Feedback Figure 61. Input-Referred Noise vs. RS Rev. C | Page 16 of 32 05575-057 05575-058 05575-056 05575-061 05575-060 05575-059 AD8337 NETWORK ANALYZER POWER SWEEP SPECTRUM ANALYZER 22dB OUT IN IN 50Ω 50Ω 50Ω 453Ω AD8337 AD8337 + 3 20Ω 3 + PrA 1 PrA 1 49.9Ω 4 – 4 – 5 7 5 7 100Ω 100Ω V GAIN 0.7V 100Ω 100Ω Figure 63. IP1dB vs. VGAIN Figure 62. Short-Circuit Input Noise vs. Frequency SPECTRUM ANALYZER INPUT 50Ω +22dB –6dB –6dB SIGNAL GENERATOR COMBINER AD8337 –6dB 453Ω 3 + 20Ω PrA 1 49.9Ω +22dB –6dB 4 – SIGNAL GENERATOR 5 7 100Ω V GAIN 100Ω Figure 64. IMD and OIP3 Rev. C | Page 17 of 32 05575-062 05575-064 05575-063 AD8337 THEORY OF OPERATION VPOS 8 R = R = 100Ω FB1 FB2 INPP + 3 + + PrA ATTENUATOR 18dB 1 VOUT INPN 6dB –24dB TO 0dB (8x) R G 4 – – – 749Ω PRAO 5 R FB2 GAIN INTERPOLATOR BIAS INTERFACE R FB1 107Ω 2 6 7 VCOM VNEG GAIN Figure 65. Circuit Block Diagram VGA OVERVIEW This X-AMP, with its linear-in-dB gain characteristic The AD8337 is a low noise, single-ended, linear-in-dB, general- architecture, yields the optimum dynamic range for receiver purpose variable gain amplifier (VGA) usable at frequencies up applications. Referring to Figure 65, the signal path consists of to 100 MHz. It is fabricated using a proprietary Analog Devices a −24 dB variable attenuator followed by a fixed gain amplifier of dielectrically isolated, complementary bipolar process. The 18 dB, for a total VGA gain range of −6 dB to +18 dB. With the bandwidth is dc to 280 MHz and features low dc offset voltage preamplifier configured for a gain of 6 dB, the composite gain and an ideal nominal gain range of 0 dB to 24 dB. Requiring range is 0 dB to 24 dB. about 15.5 mA, the power consumption is only 78 mW from either a single +5 V or a dual ±2.5 V supply. Figure 65 is the The VGA plus preamp, with 6 dB of gain, implements the circuit block diagram of the AD8337. following exact gain law: PREAMPLIFIER dB ⎡ ⎤ Gain(dB)= 19.7 ×V + ICPT(dB) ⎢ ⎥ GAIN V An uncommitted current-feedback op amp included in the ⎣ ⎦ AD8337 can be used as a preamplifier to buffer the ladder where the nominal intercept (ICPT) = 12.65 dB. network attenuator of the X-AMP. As with any op amp, the gain The ICPT increases as the gain of the preamp is increased. For is established using external resistors, and the preamplifier is example, if the gain of the preamp is increased by 6 dB, ICPT specified with a noninverting gain of 6 dB (2×) and gain resistor increases to 18.65 dB. Although the previous equation shows values of 100 Ω. The preamplifier gain can be increased using the exact gain law as based on statistical data, a quick estimation larger values of R , trading off bandwidth and offset voltage. FB2 of signal levels can be made using the default slope of 20 dB/V The value of R is to be ≥100 Ω because the value and an FB2 for a particular gain setting. For example, the change in gain for internal compensation capacitor determine the 3 dB bandwidth, a V change of 0.3 V is 6 dB using a slope of 20 dB/V and GAIN and smaller values can compromise preamplifier stability. 5.91 dB using the exact slope of 19.6 dB/V. This is a difference Because the AD8337 is dc-coupled, larger preamp gains increase of only 0.09 dB. the offset voltage. The offset voltage can be compensated by GAIN CONTROL connecting a resistor between the INPN input and the supply The gain control interface provides a high impedance input and voltage. If the offset is negative, the resistor value connects to the negative supply. For ease of adjustment, a trimmer network is referenced to the VCOM pin (in a single-supply application to can be used. midsupply at [VPOS + VNEG]/2 for optimum swing). When dual supplies are used, VCOM is connected to ground. The voltage For larger gains, the overall noise is reduced if a low value of on the VCOM pin determines the midpoint of the gain range. For RFB1 is selected. For values of RFB1 = 20 Ω and RFB2 = 301 Ω, the a ground referenced design, the VGAIN range is from −0.7 V to preamp gain is 16× (24.1 dB), and the input-referred noise is +0.7 V with the most linear-in-dB section of the gain control approximately 1.5 nV/√Hz. For this value of gain, the overall between −0.6 V and +0.6 V. In the center 80% of the VGAIN gain range increases by 18 dB; therefore, the gain range is 18 dB range, the gain error is typically less than ±0.2 dB. The gain to 42 dB. control voltage can be increased or decreased to the positive or negative rails without gain foldover. Rev. C | Page 18 of 32 05575-065 AD8337 The gain scaling factor (gain slope) is designed for 20 dB/V. This NOISE relatively low slope ensures that noise on the GAIN input is not The total input-referred voltage and current noise of the positive unduly amplified. Because a VGA functions as a multiplier, it is input of the preamplifier are about 2.2 nV/√Hz and 4.8 pA/√Hz. important that the GAIN input does not inadvertently modulate The VGA output-referred noise is about 21 nV/√Hz at low gains. the output signal with unwanted noise. Because of its high input This result is divided by the VGA fixed gain amplifier gain of 8× impedance, a simple low-pass filter can be added to the GAIN and results in a voltage noise density of 2.6 nV/√Hz referred to input to filter unwanted noise. the VGA input. This value includes the noise of the VGA gain OUTPUT STAGE setting resistors as well. If this voltage is again divided by the preamp gain of 2, the VGA noise referred all the way to the The output stage is a Class AB, voltage-feedback, complementary preamp input is about 1.3 nV/√Hz. From this, it is determined emitter-follower with a fixed gain of 18 dB, similar to the pream- that the preamplifier, including the 100 Ω gain setting resistors, plifier in speed and bandwidth. Because of the ac-beta roll-off of the output devices and the inherent reduction in feedback contributes about 1.8 nV/√Hz. The two 100 Ω resistors contribute beyond the −3 dB bandwidth, the impedance looking into the 1.29 nV/√Hz each at the output of the preamp. With the gain output pin of the preamp and output stages appears to be inductive resistor noise subtracted, the preamplifier noise is approximately (increasing impedance with increasing frequency). The high 1.55 nV/√Hz. speed output amplifier used in the AD8337 can drive large Equation 2 shows the calculation that determines the output- currents, but its stability is susceptible to capacitive loading. referred noise at maximum gain (24 dB or 16×). A small series resistor mitigates the effects of capacitive loading where: (see the Applications Information section). At is the total gain from preamp input to VGA output. ATTENUATOR R is the source resistance. S The input resistance of the VGA attenuator is nominally 265 Ω. e is the input-referred voltage noise of the preamp. n − PrA For example, if the default preamplifier feedback network RFB1 + i is the current noise of the preamp at the INPP pin. n − PrA RFB2 is 200 Ω, the effective preamplifier load is approximately en − is the voltage noise of RFB1. R FB1 114 Ω. The attenuator is composed of eight 3.01 dB sections for en − is the voltage noise of RFB2. R FB2 a total attenuation range of −24.08 dB. Following the attenuator e is the input-referred voltage noise of the VGA (low gain, n − VGA is a fixed gain amplifier with 8× (18.06 dB) gain. Because of this output-referred noise divided by a fixed gain of 8×). relatively low gain, the output offset is kept well below 20 mV over temperature; the offset is largest at maximum gain when Assuming RS = 0 Ω, RFB1 = RFB2 = 100 Ω, At = 16×, and AVGA = the preamplifier offset is amplified. The VCOM pin defines the 8×, the noise simplifies to common-mode reference for the output, as shown in Figure 65. 2 2 2 e = (1.75 × 16) + 2(1.29 × 8) + (1.9 × 8) = 35 nV Hz (1) n − out SINGLE-SUPPLY OPERATION AND AC COUPLING Dividing the result by 16 gives the total input-referred noise with If the AD8337 is to be operated from a single 5 V supply, the a short-circuited input as 2.2 nV/√Hz. When the preamplifier is bias supply for VCOM must be a very low impedance 2.5 V used in the inverting configuration with the same R and R = FB1 FB2 reference, especially if dc coupling is used. If the device is dc- 100 Ω as previously noted, e does not change. However, n − out coupled, the VCOM source must be able to handle the preamplifier because the gain dropped by 6 dB, the input-referred noise and VGA dynamic load currents in addition to the bias currents. increases by a factor of 2 to about 4.4 nV/√Hz. The reason for this When ac coupling the preamplifier input, a bias network and increase is that the noise gain to the output of the noise generators bypass capacitor must be connected to the opposite polarity stays the same, yet the preamp in the inverting configuration has a input pin. The bias generator for the VCOM pin must provide gain of −1 compared to the +2 in the noninverting configuration; the dynamic current to the preamplifier feedback network and this increases the input-referred noise by 2. the VGA attenuator. For many single 5 V applications, a refer- ence, such as the ADR391, and a good op amp provide an adequate VCOM source if a 2.5 V supply is unavailable. R 2 2 2 2 2 2 FB2 (2) e = (e R × A ) + (e × A ) + (i × R ) + (e × × A ) + (e × A ) + (e × A ) n− out n− PrA n− PrA n− R n− R n− VGA t t n S S FB1 VGA FB2 VGA VGA R FB1 Rev. C | Page 19 of 32 AD8337 APPLICATIONS INFORMATION PREAMPLIFIER CONNECTIONS DRIVING CAPACITIVE LOADS Noninverting Gain Configuration Because of the large bandwidth of the AD8337, stray capacitance at the output pin can induce peaking in the frequency response as the The AD8337 preamplifier is an uncommitted current-feedback gain of the amplifier begins to roll off. Figure 68 shows peaking op amp that is stable for values of RFB2 ≥ 100 Ω. See Figure 66 with two values of load capacitance using ±2.5 V supplies and for the noninverting feedback connections. VGAIN = 0 V. PREAMPLIFIER 25 INPP V = 0V GAIN 3 + C = 0pF L C = 10pF L R INPN G 20 C = 22pF L 4 – NO SNUBBING RESISTOR PRAO 5 15 R FB2 R FB1 10 5 Figure 66. AD8337 Preamplifier Configured for Noninverting Gain Two surface-mount resistors establish the preamplifier gain. 0 Equal values of 100 Ω configure the preamplifier for a 6 dB gain and the device for a default gain range of 0 dB to 24 dB. –5 100k 1M 10M 100M 500M FREQUENCY (Hz) For preamplifier gains ≥2, select a value of RFB2 ≥ 100 Ω and Figure 68. Peaking in the Frequency Response for Two Values of Output RFB1 ≤ 100 Ω. Higher values of RFB2 reduce the bandwidth and Capacitance with ±2.5 V Supplies and No Snubbing Resistor increase the offset voltage, but smaller values compromise 25 stability. If R ≤ 100 Ω, the gain increases and the input- V = 0V FB1 GAIN C = 0pF L referred noise decreases. C = 10pF L 20 C = 22pF L Inverting Gain Configuration WITH 20Ω SNUBBING RESISTOR 15 For applications requiring polarity inversion of negative pulses, or for waveforms that require current sinking, the preamplifier can 10 be configured as an inverting gain amplifier. When configured with bipolar supplies, the preamplifier amplifies positive or 5 negative input voltages with no level shifting of the common- mode input voltage required. Figure 67 shows the AD8337 0 configured for inverting gain operation. Because the AD8337 is a very high frequency device, stability –5 100k 1M 10M 100M 500M issues can occur unless the circuit board on which it is used is FREQUENCY (Hz) carefully laid out. The stability of the preamp is affected by Figure 69. Frequency Response for Two Values of Output Capacitance with a 20 Ω Snubbing Resistor parasitic capacitance around the INPN pin. To minimize stray capacitance position the preamp gain resistors, R and R , as FB1 FB2 In the time domain, stray capacitance at the output pin can close as possible to the INPN pin. induce overshoot on the edges of transient signals, as shown in Figure 70 and Figure 72. The amplitude of the overshoot is also a PREAMPLIFIER INPP function of the slewing of the transient (not shown in Figure 70 3 + and Figure 72). The transition time of the input pulses used for R FB1 INPN 4 – Figure 70 and Figure 72 is deliberately set high at 300 ps to demon- PRAO strate the fast response time of the amplifier. Signals with longer 5 R FB2 transition times generate less overshoot. Figure 67. The AD8337 Preamplifier Configured for Inverting Gain Rev. C | Page 20 of 32 05575-067 05575-066 GAIN (dB) GAIN (dB) 05575-068 05575-069 AD8337 800 80 800 80 V = ±5V S 600 60 600 60 400 40 400 40 200 20 200 20 C = 0pF L C = 10pF L 0 0 C = 22pF L 0 0 NO SNUBBING RESISTOR –200 –20 INPUT –200 –20 INPUT –400 –40 OUTPUT –400 OUTPUT –40 C = 0pF –600 –60 L C = 10pF –600 L –60 C = 22pF L –800 –80 WITH 20Ω SNUBBING RESISTOR –20 –10 0 10 20 30 40 50 60 70 80 –800 –80 TIME (ns) –20 –10 0 10 20 30 40 50 60 70 80 TIME (ns) Figure 70. Pulse Response for Two Values of Output Capacitance Figure 73. Pulse Response for Two Values of Output Capacitance with ±2.5 V Supplies and No Snubbing Resistor with ±5 V Supplies and a 20 Ω Snubbing Resistor 800 80 The effects of stray output capacitance are mitigated with a 600 60 small value snubbing resistor, R , placed in series with, and SNUB as near as possible to, the VOUT pin. Figure 69, Figure 71, and 400 40 Figure 73 show the improvement in dynamic performance with 200 20 a 20 Ω snubbing resistor. RSNUB reduces the gain slightly by the ratio of RL/(RSNUB + RL), a very small loss when used with high 0 0 impedance loads, such as ADCs. For other loads, alternate values –200 –20 INPUT of R can be determined empirically. The data for the curves in SNUB the Typical Performance Characteristics section are derived using –400 OUTPUT –40 C = 0pF L a 20 Ω snubbing resistor. C = 10pF L –600 –60 C = 22pF L The best way to avoid the effects of stray capacitance is to WITH 20Ω SNUBBING RESISTOR –800 –80 exercise care in the PCB layout. Locate the passive components –20 –10 0 10 20 30 40 50 60 70 80 TIME (ns) or devices connected to the AD8337 output pins as close as Figure 71. Pulse Response for Two Values of Output Capacitance possible to the package. with ±2.5 V Supplies and a 20 Ω Snubbing Resistor Although a nonissue, the preamplifier output is also sensitive to 800 80 V = ±5V S load capacitance. However, the series connection of R and FB1 600 60 R is typically the only load connected to the preamplifier. If FB2 overshoot appears, it can be mitigated by inserting a snubbing 400 40 resistor, the same way as the VGA output. 200 20 GAIN CONTROL CONSIDERATIONS 0 0 In typical applications, voltages applied to the GAIN input are dc –200 –20 INPUT or relatively low frequency signals. The high input impedance of the AD8337 enables several devices to be connected in parallel. –400 OUTPUT –40 C = 0pF L This is useful for arrays of VGAs, such as those used for calibra- C = 10pF L –600 –60 C = 22pF L tion adjustments. WITH NO SNUBBING RESISTOR –800 –80 –20 –10 0 10 20 30 40 50 60 70 80 Under dc or slowly changing ramp conditions, the gain tracks TIME (ns) the gain control voltage, as shown in Figure 3. However, it is often Figure 72. Large Signal Pulse Response for Two Values of Output necessary to consider other effects influenced by the V input. GAIN Capacitance with ±5 V Supplies and No Snubbing Resistor Rev. C | Page 21 of 32 V (mV) OUT V (mV) OUT V (mV) OUT V (mV) IN 05575-070 V (mV) IN V (mV) IN 05575-072 05575-071 V (mV) OUT V (mV) IN 05575-073 AD8337 The offset voltage effect of the AD8337, as with all VGAs, can Under certain circumstances, the product of V and the GAIN appear as a complex waveform when observed across the range offset profile plus spikes is a coherent spurious signal within the of V voltage. Generated by multiple sources, each device has signal band of interest and indistinguishable from desired GAIN a unique offset voltage (VOS) profile while the GAIN input is signals. In general, the slower the ramp applied to the GAIN swept through its voltage range. The offset voltage profile seen Pin, the smaller the spikes are. In most applications, these in Figure 15 is a typical example. If the VGAIN input voltage is effects are benign and not an issue. modulated, the output is the product of the VGAIN and the dc THERMAL CONSIDERATIONS profile of the offset voltage. This is observed on a scope as a The thermal performance of LFCSPs, such as the AD8337, small ac signal, as shown in Figure 74. In Figure 74, the signal departs significantly from that of leaded devices such as the applied to the V input is a 1 kHz ramp, and the output voltage GAIN larger TSSOP or QFSP. In larger packages, heat is conducted signal is slightly less than 4 mV p-p. away from the die by the path provided by the bond wires and 10 V = ±2.5V S the device leads. In LFCSPs, the heat transfer mechanisms are � 8 INPUT �2.5 VS = surface-to-air radiation from the top and side surfaces of the OUTPUT 6 package and conduction through the metal solder pad on the 4 mounting surface of the device. 2 θJC is the traditional thermal metric used for integrated circuits. 0 Heat transfer away from the die is a three-dimensional dynamic, and the path is through the bond wires, leads, and the six –2 surfaces of the package. Because of the small size of LFCSPs, the –4 θ is not measured conventionally. Instead, it is calculated using JC –6 thermodynamic rules. –8 The θ value of the AD8837 listed in Table 2 assumes that the JC –10 tab is soldered to the board and that there are three additional –800 –600 –400 –200 0 200 400 600 800 V (mV) GAIN ground layers beneath the device connected by at least four vias. Figure 74. Offset Voltage vs. V for a 1 kHz Ramp GAIN For a device with an unsoldered pad, the θJC nearly doubles, becoming 138°C/W. The profile of the waveform shown in Figure 74 is consistent over a wide range of signals from dc to about 20 kHz. Above PSI (Ψ) 20 kHz, secondary artifacts can be generated due to the effects Table 2 lists a subset of the classic theta specification, ΨJT (Psi of minor internal circuit tolerances, as shown in Figure 75. junction to top). θJC is the metric of heat transfer from the die to These artifacts are caused by settling and time constants of the the case, involving the six outside surfaces of the package. Ψ(XY) interpolator circuit and appear at the output as the voltage is a subset of the theta value and the thermal gradient from the spikes, as shown in Figure 75. junction (die) to each of the six surfaces. Ψ can be different for 10 V = ±2.5V each of the surfaces, but since the top of the package is a fraction of S 8 INPUT a millimeter from the die, the surface temperature of the package is V = 2.5 S OUTPUT 6 very close to the die temperature. The die temperature is calculated 4 as the product of the power dissipation and ΨJT. Since the top SPIKE surface temperature and power dissipation are easily measured, it 2 follows that the die temperature is easily calculated. For example, 0 for a dissipation of 180 mW and a Ψ of 5.3°C/W, the die JT –2 temperature is slightly less than 1°C higher than the surface SPIKE –4 temperature. –6 BOARD LAYOUT –8 Because the AD8337 is a high frequency device, board layout is –10 critical. It is very important to have a good ground plane –800 –600 –400 –200 0 200 400 600 800 V (mV) GAIN connection to the VCOM pin. Coupling through the ground Figure 75. VOS Profile for a 50 kHz Ramp plane, from the output to the input, can cause peaking at higher frequencies. Rev. C | Page 22 of 32 OFFSET VOLTAGE (mV) OFFSET VOLTAGE (mV) 05575-074 05575-075 AD8337 EVALUATION BOARDS The AD8337evaluation boards provide a family of platforms for testing and evaluating the AD8337 VGA. Three circuit configu- rations are available: • AD8337-EVALZ, dc-coupled, with noninverting gain and dual power supplies • AD8337-EVALZ-INV, dc-coupled, with inverting gain and dual power supplies • AD8337-EVALZ-SS, ac-coupled, with noninverting gain configuration and a single supply These fully assembled and tested boards are ready to use. Only the appropriate power supply and signal source connections need to be made. SMA connectors are provided for the pream- plifier (PrA) and VGA outputs. Photos of fully assembled boards are shown in Figure 76 and Figure 77. The board component side layouts are shown in Figure 78 and Figure 79. Figure 78. Assembly, Dual-Supply Evaluation Board Figure 76. AD8337 Evaluation Board for dual Supplies Figure 79. Assembly, Single-Supply Evaluation Board Schematic diagrams of the dual-supply board for noninverting and inverting configurations are shown in Figure 80 and Figure 81. The dual-supply boards require ±2.5 V to ±5 V supplies capable of supplying 20 mA or greater. A schematic diagram of the single-supply board is shown in Figure 82. The single supply version accepts a +5 V to +10 V supply with 20 mA or greater capability. Figure 77. AD8337 Evaluation Board for Single Supply Rev. C | Page 23 of 32 05575-177 05575-176 05575-179 05575-178 AD8337 +V –V S S GND1 G GND ND2 GND3 GND4 CIRCUIT OPTIONS Part numbers for fully assembled boards are listed in Table 4. + C1 C2 RVO1 10µF + 10µF VOUT 453Ω Table 4. AD8337 Evaluation Board Variations L2 L1 120nH 120nH Part Number Configuration AD8337-EVALZ Dual-supply noninverting C3 TP1 1 8 VOUT VPOS 0.1µF U1 AD8337-EVALZ-INV Dual-supply inverting RVO3 GAIN AD8337 0Ω 2 7 AD8337-EVALZ-SS Single-supply noninverting VCOM GAIN CG R1 J1 3 6 1nF 49.9Ω Figure 80, Figure 81, and Figure 82 are schematics for the INPP VNEG R4 IN various circuit configurations. Within limits, the AD8337 0Ω 4 5 INPN PRAO preamplifier gain is controlled by Resistor RFB1 and Resistor C4 R2 0.1µF 49.9Ω RFB2. For simple guidelines applying to the current-feedback R RPO2 FB2 R5 453Ω 100Ω preamplifier, see the Theory of Operation section. 100Ω PRAO R FB1 OUTPUT PROTECTION 100Ω DO NOT INSTALL PARTS IN GRAY The AD8337 VGA output stage is specified for driving loads of Figure 80. Schematic—AD8337-EVALZ - Noninverting Configuration 500 Ω or greater. To protect the stage from an accidental +V –V GND1 G GND ND2 GND3 GND4 S S overload, a 453 Ω resistor is provided, which when connected to 50 Ω test equipment inputs, enables safe operation. In certain + + high load impedance situations, the value of this resistor can be C1 C2 RVO1 10µF 10µF VOUT 453Ω reduced. However, if load capacitance values greater than L2 L1 120nH 120nH approximately 20 pF are anticipated, such as a BNC cable, the minimum series resistor value is not to be less than 20 Ω. C3 TP1 1 8 VOUT VPOS 0.1µF U1 An alternate test pin is also provided for direct access to the RVO3 GAIN AD8337 0Ω 2 7 output of the AD8337 VGA. The pin is typically used for a VCOM GAIN CG 100Ω R1 probe, and a 0 Ω resistor is provided between the test loop and J1 3 6 1nF 49.9Ω INPP VNEG the output pin. If the test loop is connected to loads ≤500 Ω, R4 IN 0Ω 4 5 then the 0 Ω resistor is to be changed to an appropriate value. INPN PRAO C4 R2 0.1µF 49.9Ω R FB2 RPO2 R5 100Ω 453Ω 100Ω PRAO R FB1 100Ω DO NOT INSTALL PARTS IN GRAY Figure 81. Schematic—AD8337-EVALZ-INV Inverting Configuration L1 120nH FB +V S + C1 C3 10µF 0.1µF 10V 8 GND1 GND2 GND3 GND4 C6 RVO1 IN VPOS VOUT 0.1µF 3 453Ω 1 INPP VOUT C4 U1 0.1µF AD8337 GAIN 7 GAIN CG 1nF INPN PRAO VCOM VNEG R1 C10 49.9Ω 4 5 2 6 0.1µF 2 1 R FB2 AD8541AR C7 R VIN SHDN FB1 100Ω 0.1µF R6 3 3 7 100Ω VOUT 100Ω 6 U3 U2 2 + 4 4 C2 C5 1µF 0.1µF GND C9 16V C8 5 0.1µF 0.22µF R4 ADR391AUJZ-R2 10kΩ Figure 82. Evaluation Board Schematic—Single-Supply Version Rev. C | Page 24 of 32 05575-180 05575-181 05575-182 AD8337 TOP: SIGNAL GENERATOR 10.05MHz, 500mV p-p BOTTOM: SIGNAL GENERATOR 9.95MHz, 500mV p-p POWER AMPLIFIERS SPECTRUM ANALYZER POWER SPLITTER SIGNAL INPUT PREAMP VGAIN OUTPUT +5V –5V POWER SUPPLY Figure 83. Typical Board Test Connections For ease of assembly, all board components are located on the MEASUREMENT SETUP primary side and are 0603 size surface mounts. Higher density Figure 83 shows board connections for two generators. In this applications may require components on both sides of the board example, the experiment illustrates IMD measurements using and present no problem to the AD8337, as demonstrated in standard off-the-shelf test equipment used by Analog Devices. unreleased versions of the board that featured secondary-side However, any equivalent equipment can be used. components and vias. Not evident in the figures are thermal vias within the pad that solder to the mating pad of the AD8337 BOARD LAYOUT CONSIDERATIONS chip-scale package. These vias serve as a thermal path and are The AD8337 evaluation board is designed using four layers. the primary means of removing heat from the device. The thermal Interconnecting circuitry is located on the component and specifications for the AD8337 are predicated on the use of multi- wiring sides, with the inner layers dedicated to power and layer board construction with these thermal vias to enable heat ground planes. Figure 84 through Figure 88 show the copper conductivity from the die. layouts. Rev. C | Page 25 of 32 05575-183 AD8337 Figure 84. Dual-Supply Component Side Copper Figure 88. Dual-Supply Power Plane Figure 85. Dual-Supply Wiring Side Copper Figure 89. Single-Supply Component Side Copper Figure 86. Dual-Supply Component Side Silk-Screen Figure 90. Single-Supply Wiring Side Copper Figure 91. Single-Supply Component Side Silkscreen Figure 87. Dual-Supply Ground Plane Rev. C | Page 26 of 32 05575-112 05575-110 05575-109 05575-111 05575-113 05575-115 05575-116 05575-114 AD8337 Figure 93. Single-Supply Power Plane Figure 92. Single-Supply Ground Plane BILL OF MATERIALS Table 5. Dual-Supply Noninverting Bill of Materials Qty. Reference Designator Description Manufacturer Mfg. Part Number 1 +VS Red test loop, 0.125” diameter Bisco Industries TP-104-01-02 4 GND1 to GND4 Black test loop, 0.125” diameter Bisco Industries TP-104-01-00 1 −V Blue test loop, 0.125” diameter Bisco Industries TP-104-01-06 S 1 TP1 Purple test loop, 0.125” diameter Bisco Industries TP-104-01-07 2 C3, C4 SM 0.1 μF, 16 V, 0603, X7R capacitors KEMET C0603C104K4RACTU 1 CG SM 1 nF, 50 V, X7R, 10%, 0603 capacitor Panasonic ECJ-1VB2A102K 2 C1, C2 SM tantalum, 10 μF, 10 V, A size capacitors Nichicon T491A106M010AS 1 U1 Integrated circuit VGA Analog Devices, Inc. AD8337BCPZ-WP 4 GAIN, IN, PRAO, VOUT SMA fem PC mount RA connectors Amphenol 901-143-6RFX 2 L1, L2 120 nH, 0603 ferrite beads Murata BLM18BA750SN1D 1 R2 49.9 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF49R9V 2 R4, RVO3 0 Ω, 5%, 1/10 W, 0603 resistors Panasonic ERJ-2GE0R00X 2 RFB1, RFB2 100 Ω, 1%, 1/16 W, 0603 resistors Panasonic ERJ-3EKF1000V 2 RPO2, RVO1 453 Ω, 1/16 W, 1%, 0603 resistors Panasonic ERJ-3EKF4530V Table 6. Dual-Supply Inverting Gain Bill of Materials Qty. Reference Designator Description Manufacturer Mfg. Part Number 1 +V Red test loop, 0.125” diameter Bisco Industries TP-104-01-02 S 4 GND1 to GND4 Black test loop, 0.125” diameter Bisco Industries TP-104-01-00 1 −VS Blue test loop, 0.125” diameter Bisco Industries TP-104-01-06 1 TP1 Purple test loop, 0.125” diameter Bisco Industries TP-104-01-07 2 C3, C4 SM 0.1 μF, 16 V, 0603, X7R capacitors KEMET C0603C104K4RACTU 1 CG SM 1 nF, 50 V, X7R, 10%, 0603 capacitor Panasonic ECJ-1VB2A102K 2 C1, C2 SM tantalum, 10 μF, 10 V, A size capacitors Nichicon T491A106M010AS 1 U1 Integrated circuit VGA Analog Devices, Inc. AD8337BCPZ-WP 4 GAIN, IN, PRAO, VOUT SMA fem PC mount RA connectors Amphenol 901-143-6RFX 2 L1, L2 120 nH, 0603 ferrite beads Murata BLM18BA750SN1D 1 R2 49.9 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF49R9V 1 RVO3 0 Ω, 5%, 1/10 W, 0603 resistor Panasonic ERJ-2GE0R00X 3 RFB2, R5, J1 (J1 POSITION) 100 Ω, 1%, 1/16 W, 0603 resistors Panasonic ERJ-3EKF1000V 2 RPO2, RVO1 453 Ω, 1/16 W, 1%, 0603 resistors Panasonic ERJ-3EKF4530V Rev. C | Page 27 of 32 05575-117 05575-118 AD8337 Table 7. Single-Supply Bill of Materials Qty. Reference Designator Description Manufacturer Mfg. Part Number 1 +VS Red test point, 0.125” diameter Bisco Industries TP-104-01-02 1 C1 Tantalum, 10 μF, 10 V, A size capacitor Nichicon T491A106M010AS 1 C2 Tantalum, 1 μF, P size capacitor Nichicon F921C105MPA 7 C3, C4, C5, C6, C7, C9, C10 0.1 μF, 16 V, 0603, X7R capacitors KEMET C0603C104K4RACTU 1 C8 0.22 μF, 10%, 0603, X7R capacitor Panasonic ECJ-1VB1H223K 1 CG 1 nF, 50 V, X7R, 10%, 0603 capacitor Panasonic ECJ-1VB2A102K 3 GAIN, IN, VOUT SMA fem PC mount RA connectors Amphenol 901-143-6RFX 4 GND1 to GND4 Loop, 0.125” diameter, black test points Bisco Industries TP-104-01-00 1 L1 120 nH, 0603 ferrite bead Murata BLM18BA750SN1D 1 R1 49.9 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF49R9V 1 R4 10 kΩ, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF1002V 3 RFB1, RFB2, R6 100 Ω, 1%, 1/16 W, 0603 resistors Panasonic ERJ-3EKF1000V 1 RVO1 453 Ω, 1%, 1/16 W, 0603 resistor Panasonic ERJ-3EKF4530V 1 U1 VGA integrated circuit Analog Devices, Inc. AD8337BCPZ-WP 1 U2 2.5 V regulator integrated circuit Analog Devices, Inc. ADR391AUJZ-R2 1 U3 SS rail-to-rail op amp integrated circuit Analog Devices, Inc. AD8541AR Rev. C | Page 28 of 32 AD8337 OUTLINE DIMENSIONS 3.25 0.60 MAX 3.00 SQ 0.50 2.75 BSC 0.60 MAX 5 8 2.95 1.60 EXPOSED 2.75 SQ TOP 1.45 PIN 1 PAD VIEW 2.55 INDICATOR (BOTTOM VIEW) 1.30 4 1 PIN 1 0.50 INDICATOR 1.89 0.40 1.74 12° MAX 0.30 0.70 MAX 1.59 0.90 MAX 0.65 TYP 0.85 NOM 0.05 MAX FOR PROPER CONNECTION OF 0.01 NOM THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.30 SEATING FUNCTION DESCRIPTIONS PLANE 0.23 0.20 REF SECTION OF THIS DATA SHEET. 0.18 Figure 94. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD8337BCPZ-R2 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB 1 AD8337BCPZ-REEL −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB 1 AD8337BCPZ-REEL7 −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB 1 AD8337BCPZ-WP −40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 HVB 1 AD8337-EVALZ Evaluation Board with Noninverting Gain Configuration 1 AD8337-EVALZ-INV Evaluation Board with Inverting Gain Configuration 1 AD8337-EVALZ-SS Evaluation Board with Single-Supply Operation 1 Z = RoHS Compliant Part. Rev. C | Page 29 of 32 072408-B AD8337 NOTES Rev. C | Page 30 of 32 AD8337 NOTES Rev. C | Page 31 of 32 AD8337 NOTES ©2005–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05575-0-9/08(C) Rev. C | Page 32 of 32