ANALOG DEVICES AD8331

Ultralow Noise VGAs with Preamplifier and Programmable R IN AD8331/AD8332/AD8334 FEATURES FUNCTIONAL BLOCK DIAGRAM LON LOP VIP VIN VCM HILO Ultralow noise preamplifier (preamp) Voltage noise = 0.74 nV/√Hz 3.5dB OR 15.5dB V MID LNA Current noise = 2.5 pA/√Hz – VOH 48dB 3 dB bandwidth 19dB 21dB PA INH ATTENUATOR + VOL AD8331: 120 MHz AD8332, AD8334: 100 MHz CLAMP LMD VCM GAIN Low power VGA BIAS AND BIAS CONTROL RCLMP INTERPOLATOR INTERFACE AD8331: 125 mW/channel AD8332, AD8334: 145 mW/channel AD8331/AD8332/AD8334 Wide gain range with programmable postamp ENB GAIN −4.5 dB to +43.5 dB in LO gain mode Figure 1. Signal Path Block Diagram 7.5 dB to 55.5 dB in HI gain mode 60 Low output-referred noise: 48 nV/√Hz typical V = 1V GAIN HI GAIN MODE Active input impedance matching 50 V = 0.8V GAIN Optimized for 10-bit/12-bit ADCs Selectable output clamping level 40 V = 0.6V GAIN Single 5 V supply operation 30 AD8332 and AD8334 available in lead frame chip scale package V = 0.4V GAIN APPLICATIONS 20 V = 0.2V GAIN Ultrasound and sonar time-gain controls 10 V = 0V GAIN High performance automatic gain control (AGC) systems I/Q signal processing 0 High speed, dual ADC drivers –10 100k 1M 10M 100M 1G GENERAL DESCRIPTION FREQUENCY (Hz) The AD8331/AD8332/AD8334 are single-, dual-, and quad- Figure 2. Frequency Response vs. Gain channel, ultralow noise linear-in-dB, variable gain amplifiers Differential signal paths result in superb second- and third- (VGAs). Optimized for ultrasound systems, they are usable as a order distortion performance and low crosstalk. low noise variable gain element at frequencies up to 120 MHz. The low output-referred noise of the VGA is advantageous in Included in each channel are an ultralow noise preamp (LNA), driving high speed differential ADCs. The gain of the postamp an X-AMP® VGA with 48 dB of gain range, and a selectable gain can be pin selected to 3.5 dB or 15.5 dB to optimize gain range postamp with adjustable output limiting. The LNA gain is 19 dB and output noise for 12-bit or 10-bit converter applications. The with a single-ended input and differential outputs. Using a single output can be limited to a user-selected clamping level, preventing resistor, the LNA input impedance can be adjusted to match a input overload to a subsequent ADC. An external resistor adjusts signal source without compromising noise performance. the clamping level. The 48 dB gain range of the VGA makes these devices suitable The operating temperature range is −40°C to +85°C. The for a variety of applications. Excellent bandwidth uniformity is AD8331 is available in a 20-lead QSOP package, the AD8332 is maintained across the entire range. The gain control interface available in 28-lead TSSOP and 32-lead LFCSP packages, and provides precise linear-in-dB scaling of 50 dB/V for control the AD8334 is available in a 64-lead LFCSP package. voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 03199-002 03199-001 AD8331/AD8332/AD8334 TABLE OF CONTENTS Features .............................................................................................. 1 Ultrasound TGC Application ................................................... 34 Applications ....................................................................................... 1 High Density Quad Layout ....................................................... 34 General Description ......................................................................... 1 AD8331 Evaluation Board ............................................................ 39 Functional Block Diagram .............................................................. 1 General Description ................................................................... 39 Revision History ............................................................................... 2 User-Supplied Optional Components ..................................... 39 Specif ica t ions ..................................................................................... 4 Measurement Setup.................................................................... 39 Absolute Maximum Ratings ............................................................ 7 Board Layout ............................................................................... 39 ESD Caution .................................................................................. 7 AD8331 Evaluation Board Schematics .................................... 40 Pin Configurations and Function Descriptions ........................... 8 AD8331 Evaluation Board PCB Layers ................................... 42 Typical Performance Characteristics ........................................... 12 AD8332 Evaluation Board ............................................................ 43 Test Circuits ..................................................................................... 20 General Description ................................................................... 43 Measurement Considerations ................................................... 20 User-Supplied Optional Components ..................................... 43 Theory of Operation ...................................................................... 24 Measurement Setup.................................................................... 43 Overview ...................................................................................... 24 Board Layout ............................................................................... 43 Low Noise Amplifier (LNA) ..................................................... 25 Evaluation Board Schematics ................................................... 44 Variable Gain Amplifier ............................................................ 27 AD8332 Evaluation Board PCB Layers ................................... 46 Postamplifier ............................................................................... 28 AD8334 Evaluation Board ............................................................ 47 Applications Information .............................................................. 30 General Description ................................................................... 47 LNA—External Components .................................................... 30 Configuring the Input Impedance ........................................... 48 Driving ADCs ............................................................................. 32 Measurement Setup.................................................................... 48 Overload ...................................................................................... 32 Board Layout ............................................................................... 48 Optional Input Overload Protection ....................................... 32 Evaluation Board Schematics ................................................... 49 Layout, Grounding, and Bypassing .......................................... 33 AD8334 Evaluation Board PCB Layers ................................... 51 Multiple Input Matching ........................................................... 33 Outline Dimensions ....................................................................... 53 Disabling the LNA ...................................................................... 33 Ordering Guide .......................................................................... 55 REVISION HISTORY 10/10—Rev. F to Rev. G Deleted AD8331 Bill of Materials Section and Table 11; Renumbered Sequentially ............................................................. 43 Changes to Quiescent Current per Channel Parameter, Table 1 ................................................................................................ 6 Changes to Figure 104 ................................................................... 43 Changes to Pin 1, Table 3 ................................................................. 8 Changes to Figure 106 ................................................................... 45 Changes to Pin 1 and Pin 28, Table 4 and Pin 4 and Pin 5, Changes to Figure 107 ................................................................... 46 Table 5 ................................................................................................ 9 Changes to Figure 113 ................................................................... 47 Changes to Figure 6 and Table 6 ................................................... 10 Changes to Figure 114 and Board Layout Section ..................... 48 Changes to Figure 33 ...................................................................... 16 Deleted AD8332 Bill of Materials Section and Table 13; Changes to Figure 64 ...................................................................... 22 Renumbered Sequentially ............................................................. 48 Changes to Figure 70 ...................................................................... 24 Changes to Figure 115 ................................................................... 49 Changes to Low Noise Amplifier (LNA) Section and Changes to Figure 116 ................................................................... 50 Figure 74 .......................................................................................... 25 Changes to Figure 117 to Figure 120 ........................................... 51 Changes to Figure 94 ...................................................................... 38 Changes to Figure 121 ................................................................... 52 Changes to General Descriptions Section, Figure 95 Caption, Deleted AD8334 Bill of Materials Section and Table 15; Table 10, and Board Layout Section ............................................. 39 Renumbered Sequentially ............................................................. 54 Changes to Figure 96 ...................................................................... 40 Changes to Figure 97 ...................................................................... 41 Changes to Figure 98 and Figure 103 ........................................... 42 Rev. G | Page 2 of 56 AD8331/AD8332/AD8334 4/08—Rev. E to Rev. F Changes to Figure 23 and Figure 24 ............................................. 14 Changed R to R Throughout ..................................................... 4 Changes to Figure 25 through Figure 27 ...................................... 15 FB IZ Changes to Figure 1 ........................................................................... 1 Changes to Figure 31 and Figure 33 through Figure 36 ............ 16 Changes to Figure 37 through Figure 42 ...................................... 17 Changes to Table 1, LNA and VGA Characteristics, Output Offset Voltage, Conditions ............................................................... 4 Changes to Figure 43, Figure 44, and Figure 48 .......................... 18 Changes to Quiescent Current per Channel and Power Down Changes to Figure 49, Figure 50, and Figure 54 .......................... 19 Current Parameters ........................................................................... 6 Inserted Figure 56 and Figure 57 .................................................. 20 Changes to Table 2 ............................................................................ 7 Inserted Figure 58, Figure 59, and Figure 61 ............................... 21 Changes to Table 3, Pin 1 Description ........................................... 8 Changes to Figure 60 ...................................................................... 21 Changes to Table 4, Pin 1 and Pin 28 Descriptions ...................... 9 Inserted Figure 63 and Figure 65 .................................................. 22 Changes to Table 5, Pin 4 and Pin 5 Descriptions ........................ 9 Changes to Figure 64 ...................................................................... 22 Moved Measurement Considerations Section ............................ 23 Changes to Table 6, Pin 2, Pin 15, and Pin 20 Descriptions ...... 10 Changes to Table 6, Pin 61 Description ....................................... 11 Inserted Figure 67 and Figure 68 .................................................. 23 Changes to Typical Performance Characteristics Section, Inserted Figure 70 and Figure 71 .................................................. 24 Default Conditions .......................................................................... 12 Change to Figure 72 ........................................................................ 24 Changes to Figure 25 ...................................................................... 15 Changes to Figure 73 and Low Noise Amplifier Section ........... 25 Changes to Figure 39 ...................................................................... 17 Changes to Postamplifier Section ................................................. 28 Changes to Figure 55 Through Figure 68 ................................... 20 Changes to Figure 80 ...................................................................... 29 Changes to Theory of Operation, Overview Section ................. 24 Changes to LNA—External Components Section ...................... 30 Changes to Logic Inputs—ENB, MODE, and HILO Section ... 31 Changes to Low Noise Amplifier Section and Figure 74 ........... 25 Changes to Active Impedance Matching Section, Figure 75, Changes to Output Decoupling and Overload Sections ............ 32 and Figure 77 ................................................................................... 26 Changes to Layout, Grounding, and Bypassing Section ............ 33 Changes to Figure 78 ...................................................................... 27 Changes to Ultrasound TGC Application Section ..................... 34 Changes to Equation 6, Table 7, Figure 81, and Figure 82 ......... 30 Added High Density Quad Layout Section ................................. 34 Changes to Figure 83 ...................................................................... 31 Inserted Figure 94 ........................................................................... 38 Changes to Figure 88 ...................................................................... 32 Updated Outline Dimensions ........................................................ 39 Changes to Ordering Guide ........................................................... 40 Switched Figure 89 and Figure 90 ................................................. 33 Changes to Figure 89 ...................................................................... 33 3/06—Rev. C to Rev. D Changes to Ultrasound TGC Application Section...................... 34 Updated Format ................................................................. Universal Incorporated AD8331-EVAL Data Sheet, Rev. A ....................... 39 Changes to Features and General Description .............................. 1 Changes to User-Supplied Optional Components Section Changes to Table 1 ............................................................................ 3 and Measurement Setup Section ................................................... 39 Changes to Table 2 ............................................................................ 6 Changes to Figure 95 ...................................................................... 39 Changes to Ordering Guide ........................................................... 34 Changes to Figure 97 ...................................................................... 41 11/03—Rev. B to Rev. C Added Figure 98 .............................................................................. 42 Addition of New Part ......................................................... Universal Incorporated AD8332-EVALZ Data Sheet, Rev. D ..................... 44 Changes to Figures ............................................................. Universal Incorporated AD8334-EVAL Data Sheet, Rev. 0 ........................ 49 Updated Outline Dimensions ........................................................ 32 Updated Outline Dimensions ........................................................ 55 Changes to Ordering Guide ........................................................... 57 5/03—Rev. A to Rev. B Edits to Ordering Guide ................................................................. 32 4/06—Rev. D to Rev. E Edits to Ultrasound TGC Application Section ........................... 25 Added AD8334 ................................................................... Universal Added Figure 71, Figure 72, and Figure 73.................................. 26 Changes to Figure 1 and Figure 2 .................................................... 1 Updated Outline Dimensions ........................................................ 31 Changes to Table 1 ............................................................................ 4 2/03—Rev. 0 to Rev. A Changes to Table 2 ............................................................................ 7 Changes to Figure 7 through Figure 9 and Figure 12 ................. 12 Edits to Ordering Guide ................................................................. 32 Changes to Figure 13, Figure 14, Figure 16, and Figure 18 ....... 13 Rev. G | Page 3 of 56 AD8331/AD8332/AD8334 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating, −4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. Table 1. 1 Parameter Test Conditions/Comments Min Typ Max Unit LNA CHARACTERISTICS Gain Single-ended input to differential output 19 dB Input to output (single-ended) 13 dB Input Voltage Range AC-coupled ±275 mV Input Resistance R = 280 Ω 50 Ω IZ R = 412 Ω 75 Ω IZ R = 562 Ω 100 Ω IZ RIZ = 1.13 kΩ 200 Ω RIZ = ∞ 6 kΩ Input Capacitance 13 pF Output Impedance Single-ended, either output 5 Ω −3 dB Small Signal Bandwidth V = 0.2 V p-p 130 MHz OUT Slew Rate 650 V/μs Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.74 nV/√Hz Input Current Noise RIZ = ∞, HI or LO gain, f = 5 MHz 2.5 pA/√Hz Noise Figure f = 10 MHz, LOP output Active Termination Match R = R = 50 Ω 3.7 dB S IN Unterminated R = 50 Ω, R = ∞ 2.5 dB S IZ Harmonic Distortion at LOP1 or LOP2 VOUT = 0.5 V p-p, single-ended, f = 10 MHz HD2 −56 dBc HD3 −70 dBc Output Short-Circuit Current Pin LON, Pin LOP 165 mA LNA AND VGA CHARACTERISTICS −3 dB Small Signal Bandwidth VOUT = 0.2 V p-p AD8331 120 MHz AD8332, AD8334 100 MHz −3 dB Large Signal Bandwidth VOUT = 2 V p-p AD8331 110 MHz AD8332, AD8334 90 MHz Slew Rate AD8331 LO gain 300 V/μs HI gain 1200 V/μs AD8332, AD8334 LO gain 275 V/μs HI gain 1100 V/μs Input Voltage Noise RS = 0 Ω, HI or LO gain, RIZ = ∞, f = 5 MHz 0.82 nV/√Hz Noise Figure V = 1.0 V GAIN Active Termination Match R = R = 50 Ω, f = 10 MHz, measured 4.15 dB S IN R = R = 200 Ω, f = 5 MHz, simulated 2.0 dB S IN Unterminated RS = 50 Ω, RIZ = ∞, f = 10 MHz, measured 2.5 dB RS = 200 Ω, RIZ = ∞, f = 5 MHz, simulated 1.0 dB Output-Referred Noise AD8331 VGAIN = 0.5 V, LO gain 48 nV/√Hz VGAIN = 0.5 V, HI gain 178 nV/√Hz AD8332, AD8334 V = 0.5 V, LO gain 40 nV/√Hz GAIN V = 0.5 V, HI gain 150 nV/√Hz GAIN Output Impedance, Postamplifier DC to 1 MHz 1 Ω Rev. G | Page 4 of 56 AD8331/AD8332/AD8334 1 Parameter Test Conditions/Comments Min Typ Max Unit Output Signal Range, Postamplifier RL ≥ 500 Ω, unclamped, either pin VCM ± 1.125 V Differential 4.5 V p-p Output Offset Voltage AD8331 Differential, V = 0.5 V −50 ±5 +50 mV GAIN Common mode −125 −25 +100 mV AD8332, AD8334 Differential, 0.05 V ≤ V ≤ 1.0 V −20 ±5 +20 mV GAIN Common mode −125 –25 +100 mV Output Short-Circuit Current 45 mA Harmonic Distortion V = 0.5 V, V = 1 V p-p, HI gain GAIN OUT AD8331 HD2 f = 1 MHz −88 dBc HD3 −85 dBc HD2 f = 10 MHz −68 dBc HD3 −65 dBc AD8332, AD8334 HD2 f = 1 MHz −82 dBc HD3 −85 dBc HD2 f = 10 MHz −62 dBc HD3 −66 dBc Input 1 dB Compression Point VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz to 10 MHz 1 dBm Two-Tone Intermodulation Distortion (IMD3) AD8331 V = 0.72 V, V = 1 V p-p, f = 1 MHz −80 dBc GAIN OUT V = 0.5 V, V = 1 V p-p, f = 10 MHz −72 dBc GAIN OUT AD8332, AD8334 VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz −78 dBc VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz −74 dBc Output Third-Order Intercept AD8331 V = 0.5 V, V = 1 V p-p, f = 1 MHz 38 dBm GAIN OUT V = 0.5 V, V = 1 V p-p, f = 10 MHz 33 dBm GAIN OUT AD8332, AD8334 VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz 35 dBm VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz 32 dBm Channel-to-Channel Crosstalk (AD8332, AD8334) VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz −98 dB Overload Recovery V = 1.0 V, V = 50 mV p-p/1 V p-p, f = 10 MHz 5 ns GAIN IN Group Delay Variation 5 MHz < f < 50 MHz, full gain range ±2 ns ACCURACY 2 Absolute Gain Error 0.05 V < V < 0.10 V −1 +0.5 +2 dB GAIN 0.10 V < V < 0.95 V −1 ±0.3 +1 dB GAIN 0.95 V < VGAIN < 1.0 V −2 −1 +1 dB 3 Gain Law Conformance 0.1 V < VGAIN < 0.95 V ±0.2 dB Channel-to-Channel Gain Matching 0.1 V < VGAIN < 0.95 V ±0.1 dB GAIN CONTROL INTERFACE (Pin GAIN) Gain Scaling Factor 0.10 V < VGAIN < 0.95 V 48.5 50 51.5 dB/V Gain Range LO gain −4.5 to +43.5 dB HI gain 7.5 to 55.5 dB Input Voltage (V ) Range 0 to 1.0 V GAIN Input Impedance 10 MΩ Response Time 48 dB gain change to 90% full scale 500 ns COMMON-MODE INTERFACE (PIN VCMx) 4 Input Resistance Current limited to ±1 mA 30 Ω Output CM Offset Voltage VCM = 2.5 V −125 −25 +100 mV Voltage Range VOUT = 2.0 V p-p 1.5 to 3.5 V Rev. G | Page 5 of 56 AD8331/AD8332/AD8334 1 Parameter Test Conditions/Comments Min Typ Max Unit ENABLE INTERFACE (PIN ENB, PIN ENBL, PIN ENBV) Logic Level to Enable Power 2.25 5 V Logic Level to Disable Power 0 1.0 V Input Resistance Pin ENB 25 kΩ Pin ENBL 40 kΩ Pin ENBV 70 kΩ Power-Up Response Time VINH = 30 mV p-p 300 μs VINH = 150 mV p-p 4 ms HILO GAIN RANGE INTERFACE (PIN HILO) Logic Level to Select HI Gain Range 2.25 5 V Logic Level to Select LO Gain Range 0 1.0 V Input Resistance 50 kΩ OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR LO GAIN) Accuracy HILO = LO R = 2.74 kΩ, V = 1 V p-p (clamped) ±50 mV CLMP OUT HILO = HI RCLMP = 2.21 kΩ, VOUT = 1 V p-p (clamped) ±75 mV MODE INTERFACE (PIN MODE) Logic Level for Positive Gain Slope 0 1.0 V Logic Level for Negative Gain Slope 2.25 5 V Input Resistance 200 kΩ POWER SUPPLY (PIN VPS1, PIN VPS2, PIN VPSV, PIN VPSL, PIN VPOS) Supply Voltage 4.5 5.0 5.5 V Quiescent Current per Channel AD8331 20 25 mA AD8332 22 27.5 32 mA AD8334 24 29.5 34 Power Dissipation per Channel No signal AD8331 125 mW AD8332, AD8334 138 mW Power-Down Current VGA and LNA disabled AD8331 50 240 400 μA AD8332 50 300 600 μA AD8334 50 600 1200 μA LNA Current AD8331 (ENBL) Each channel 7.5 11 15 mA AD8332, AD8334 (ENBL) Each channel 7.5 12 15 mA VGA Current AD8331 (ENBV) 7.5 14 20 mA AD8332, AD8334 (ENBV) 7.5 17 20 mA PSRR V = 0 V, f = 100 kHz −68 dB GAIN 1 All dBm values are referred to 50 Ω. 2 The absolute gain refers to the theoretical gain expression in Equation 1. 3 Best-fit to linear-in-dB curve. 4 The current is limited to ±1 mA typical. Rev. G | Page 6 of 56 AD8331/AD8332/AD8334 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Voltage other conditions above those indicated in the operational Supply Voltage (VPSn, VPSV, VPSL, VPOS) 5.5 V section of this specification is not implied. Exposure to absolute Input Voltage (INHx) V + 200 mV S maximum rating conditions for extended periods may affect ENB, ENBL, ENBV, HILO Voltage VS + 200 mV device reliability. GAIN Voltage 2.5 V Power Dissipation ESD CAUTION 1 RU Package (AD8332) 0.96 W CP-32 Package (AD8332) 1.97 W 1 RQ Package (AD8331) 0.78 W CP-64 Package (AD8334) 0.91 W Temperature Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 60 sec) 300°C θ JA 1 RU Package (AD8332) 68°C/W 2 CP-32 Package2 (AD8332) 33°C/W 1 RQ Package (AD8331) 83°C/W 3 CP-64 Package (AD8334) 24.2°C/W 1 4-layer JEDEC board (2S2P). 2 Exposed pad soldered to board, nine thermal vias in pad—JEDEC, 4-layer board J-STD-51-9. 3 Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, 4-layer board J-STD-51-9. Rev. G | Page 7 of 56 AD8331/AD8332/AD8334 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LMD 1 20 COMM PIN 1 INH 2 INDICATOR 19 ENBL VPSL 3 18 ENBV LON 4 17 COMM AD8331 LOP 5 16 VOL TOP VIEW COML 6 15 VOH (Not to Scale) VIP 7 14 VPOS 8 13 HILO VIN 9 12 RCLMP MODE 10 11 VCM GAIN Figure 3. 20-Lead QSOP Pin Configuration (AD8331) Table 3. 20-Lead QSOP Pin Function Description (AD8331) Pin No. Mnemonic Description 1 LMD LNA Midsupply Bypass Pin; Connect a Capacitor for Midsupply HF Bypass 2 INH LNA Input 3 VPSL LNA 5 V Supply 4 LON LNA Inverting Output 5 LOP LNA Noninverting Output 6 COML LNA Ground 7 VIP VGA Noninverting Input 8 VIN VGA Inverting Input 9 MODE Gain Slope Logic Input 10 GAIN Gain Control Voltage 11 VCM Common-Mode Voltage 12 RCLMP Output Clamping Level 13 HILO Gain Range Select (HI or LO) 14 VPOS VGA 5 V Supply 15 VOH Noninverting VGA Output 16 VOL Inverting VGA Output 17 COMM VGA Ground 18 ENBV VGA Enable 19 ENBL LNA Enable 20 COMM VGA Ground Rev. G | Page 8 of 56 03199-003 AD8331/AD8332/AD8334 1 LMD2 28 LMD1 PIN 1 2 INDICATOR INH2 27 INH1 32 31 30 29 28 27 26 25 3 VPS2 26 VPS1 LON1 1 COMM 24 4 PIN 1 LON2 25 LON1 INDICATOR 5 VPS1 2 23 VOH1 LOP2 24 LOP1 AD8332 6 COM2 23 COM1 INH1 3 VOL1 22 TOP VIEW 7 VIP2 (Not to Scale) 22 VIP1 LMD1 4 21 VPSV AD8332 8 VIN2 21 VIN1 TOP VIEW LMD2 5 20 NC 9 (Not to Scale) VCM2 20 VCM1 INH2 6 19 VOL2 10 GAIN 19 HILO 11 RCLMP 18 ENB VPS2 7 18 VOH2 12 VOH2 17 VOH1 8 LON2 17 COMM 13 VOL2 16 VOL1 91 10 112 13 14 15 16 14 COMM 15 VPSV NC = NO CONNECT Figure 4. 28-Lead TSSOP Pin Configuration (AD8332) Figure 5. 32-Lead LFCSP Pin Configuration (AD8332) Table 4. 28-Lead TSSOP Pin Function Description (AD8332) Table 5. 32-Lead LFCSP Pin Function Description (AD8332) Pin No. Pin No. Mnemonic Description Mnemonic Description 1 LMD2 CH 2 LNA Midsupply Pin; Connect a 1 LON1 CH1 LNA Inverting Output Capacitor for Midsupply HF Bypass 2 VPS1 CH1 LNA Supply 5 V 2 INH2 CH2 LNA Input 3 INH1 CH1 LNA Input 3 VPS2 CH2 Supply LNA 5 V 4 LMD1 CH 1 LNA Midsupply Pin; Connect a 4 LON2 CH2 LNA Inverting Output Capacitor for Midsupply HF Bypass 5 LOP2 CH2 LNA Noninverting Output 5 LMD2 CH 2 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass 6 COM2 CH2 LNA Ground 6 INH2 CH2 LNA Input 7 VIP2 CH2 VGA Noninverting Input 7 VPS2 CH2 LNA Supply 5 V 8 VIN2 CH2 VGA Inverting Input 8 LON2 CH2 LNA Inverting Output 9 VCM2 CH2 Common-Mode Voltage 9 LOP2 CH2 LNA Noninverting Output 10 GAIN Gain Control Voltage 10 COM2 CH2 LNA Ground 11 RCLMP Output Clamping Resistor 11 VIP2 CH2 VGA Noninverting Input 12 VOH2 CH2 Noninverting VGA Output 12 VIN2 CH2 VGA Inverting Input 13 VOL2 CH2 Inverting VGA Output 13 VCM2 CH2 Common-Mode Voltage 14 COMM VGA Ground (Both Channels) 14 MODE Gain Slope Logic Input 15 VPSV VGA Supply 5 V (Both Channels) 15 GAIN Gain Control Voltage 16 VOL1 CH1 Inverting VGA Output 16 RCLMP Output Clamping Level Input 17 VOH1 CH1 Noninverting VGA Output 17 COMM VGA Ground 18 ENB Enable—VGA/LNA 18 VOH2 CH2 Noninverting VGA Output 19 HILO VGA Gain Range Select (HI or LO) 19 VOL2 CH2 Inverting VGA Output 20 VCM1 CH1 Common-Mode Voltage 20 NC No Connect 21 VIN1 CH1 VGA Inverting Input 21 VPSV VGA Supply 5 V 22 VIP1 CH1 VGA Noninverting Input 22 VOL1 CH1 Inverting VGA Output 23 COM1 CH1 LNA Ground 23 VOH1 CH1 Noninverting VGA Output 24 LOP1 CH1 LNA Noninverting Output 24 COMM VGA Ground 25 LON1 CH1 LNA Inverting Output 25 ENBV VGA Enable 26 VPS1 CH1 LNA Supply 5 V 26 ENBL LNA Enable 27 INH1 CH1 LNA Input 27 HILO VGA Gain Range Select (HI or LO) 28 LMD1 CH 1 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass 28 VCM1 CH1 Common-Mode Voltage 29 VIN1 CH1 VGA Inverting Input 30 VIP1 CH1 VGA Noninverting Input 31 COM1 CH1 LNA Ground 32 LOP1 CH1 LNA Noninverting Output Rev. G | Page 9 of 56 03199-004 LOP2 LOP1 COM2 COM1 VIP2 VIP1 VIN2 VIN1 VCM2 VCM1 MODE HILO GAIN ENBL RCLMP ENBV 03199-005 AD8331/AD8332/AD8334 PIN 1 INH2 1 48 COM12 INDICATOR LMD2 2 47 VOH1 NC 3 46 VOL1 LON2 4 45 VPS12 LOP2 5 44 VOL2 VIP2 6 43 VOH2 VIN2 7 42 COM12 AD8334 VPS2 8 41 MODE TOP VIEW VPS3 9 40 NC (Not to Scale) VIN3 10 39 COM34 VIP3 11 38 VOH3 LOP3 12 37 VOL3 LON3 13 36 VPS34 NC 14 35 VOL4 LMD3 34 VOH4 15 INH3 16 33 COM34 NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 2. NC = NO CONNECT. Figure 6. 64-Lead LFCSP Pin Configuration (AD8334) Table 6. 64-Lead LFCSP Pin Function Description (AD8334) Pin No. Mnemonic Description 1 INH2 CH2 LNA Input. 2 LMD2 CH 2 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass. 3 NC Not Connected. 4 LON2 CH2 LNA Feedback Output (for RIZ). 5 LOP2 CH2 LNA Output. 6 VIP2 CH2 VGA Positive Input. 7 VIN2 CH2 VGA Negative Input. 8 VPS2 CH2 LNA Supply 5 V. 9 VPS3 CH3 LNA Supply 5 V. 10 VIN3 CH3 VGA Negative Input. 11 VIP3 CH3 VGA Positive Input. 12 LOP3 CH3 LNA Positive Output. 13 LON3 CH3 LNA Feedback Output (for R ). IZ 14 NC Not Connected. 15 LMD3 CH 3 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass. 16 INH3 CH3 LNA Input. 17 COM3 CH3 LNA Ground. 18 COM4 CH4 LNA Ground. 19 INH4 CH4 LNA Input. 20 LMD4 CH 4 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass. 21 NC Not Connected. 22 LON4 CH4 LNA Feedback Output (for RIZ). 23 LOP4 CH4 LNA Positive Output. 24 VIP4 CH4 VGA Positive Input. 25 VIN4 CH4 VGA Negative Input. 26 VPS4 CH4 LNA Supply 5 V. Rev. G | Page 10 of 56 COM3 17 64 COM2 COM4 18 63 COM1 INH4 19 62 INH1 LMD4 20 61 LMD1 NC 21 60 NC LON4 22 59 LON1 LOP4 23 58 LOP1 VIP4 24 57 VIP1 VIN4 25 56 VIN1 VPS4 26 55 VPS1 GAIN34 27 54 GAIN12 CLMP34 28 53 CLMP12 HILO 29 52 EN12 VCM4 30 51 EN34 VCM3 31 50 VCM1 NC 32 49 VCM2 03199-006 AD8331/AD8332/AD8334 Pin No. Mnemonic Description 27 GAIN34 Gain Control Voltage for CH3 and CH4. 28 CLMP34 Output Clamping Level Input for CH3 and CH4. 29 HILO Gain Select for Postamp 0 dB or 12 dB. 30 VCM4 CH4 Common-Mode Voltage—AC Bypass. 31 VCM3 CH3 Common-Mode Voltage—AC Bypass. 32 NC No Connect. 33 COM34 VGA Ground CH3 and CH4. 34 VOH4 CH4 Positive VGA Output. 35 VOL4 CH4 Negative VGA Output. 36 VPS34 VGA Supply 5 V CH3 and CH4. 37 VOL3 CH3 Negative VGA Output. 38 VOH3 CH3 Positive VGA Output. 39 COM34 VGA Ground CH3 and CH4. 40 NC No Connect. 41 MODE Gain Control Slope, Logic Input, 0 = Positive. 42 COM12 VGA Ground CH1 and CH2. 43 VOH2 CH2 Positive VGA Output. 44 VOL2 CH2 Negative VGA Output. 45 VPS12 CH2 VGA Supply 5 V CH1 and CH2. 46 VOL1 CH1 Negative VGA Output. 47 VOH1 CH1 Positive VGA Output. 48 COM12 VGA Ground CH1 and CH2. 49 VCM2 CH2 Common-Mode Voltage—AC Bypass. 50 VCM1 CH1 Common-Mode Voltage—AC Bypass. 51 EN34 Shared LNA/VGA Enable CH3 and CH4. 52 EN12 Shared LNA/VGA Enable CH1 and CH2. 53 CLMP12 Output Clamping Level Input CH1 and CH2. 54 GAIN12 Gain Control Voltage CH1 and CH2. 55 VPS1 CH1 LNA Supply 5 V. 56 VIN1 CH1 VGA Negative Input. 57 VIP1 CH1 VGA Positive Input. 58 LOP1 CH1 LNA Positive Output. 59 LON1 CH1 LNA Feedback Output (for R ). IZ 60 NC Not Connected. 61 LMD1 CH 1 LNA Midsupply Pin; Connect a Capacitor for Midsupply HF Bypass. 62 INH1 CH1 LNA Input. 63 COM1 CH1 LNA Ground. 64 COM2 CH2 LNA Ground. EPAD The exposed paddle must be soldered to the PCB ground to ensure proper heat dissipation, noise, and mechanical strength benefits. Rev. G | Page 11 of 56 AD8331/AD8332/AD8334 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RIZ = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating, −4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. 60 50 SAMPLE SIZE = 80 UNITS V = 0.5V GAIN 50 40 HILO = HI 40 30 30 20 20 10 HILO = LO 10 0 ASCENDING GAIN MODE DESCENDING GAIN MODE (WHERE AVAILABLE) –10 0 0 0.2 0.4 0.6 0.8 1.0 1.1 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 V (V) GAIN ERROR (dB) GAIN Figure 7. Gain vs. V and MODE (MODE Available on RU Package) Figure 10. Gain Error Histogram GAIN 25 2.0 SAMPLE SIZE = 50 UNITS V = 0.2V 20 GAIN 1.5 15 1.0 10 –40°C +25°C 0.5 5 0 0 25 V = 0.7V GAIN –0.5 20 +85°C 15 –1.0 10 –1.5 5 0 –2.0 0 0.2 0.4 0.6 0.8 1.0 1.1 V (V) GAIN CHANNEL TO CHANNEL GAIN MATCH (dB) Figure 8. Absolute Gain Error vs. V at Three Temperatures GAIN Figure 11. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V 2.0 50 V = 1V GAIN 1.5 40 V = 0.8V GAIN 1.0 30 V = 0.6V GAIN 0.5 1MHz 20 V = 0.4V GAIN 0 10 10MHz 30MHz V = 0.2V GAIN –0.5 0 –1.0 50MHz V = 0V GAIN –10 –1.5 70MHz –2.0 –20 0 0.2 0.4 0.6 0.8 1.0 1.1 100k 1M 10M 100M 500M V (V) FREQUENCY (Hz) GAIN Figure 9. Absolute Gain Error vs. VGAIN at Various Frequencies Figure 12. Frequency Response for Various Values of VGAIN Rev. G | Page 12 of 56 GAIN ERROR (dB) GAIN ERROR (dB) GAIN (dB) 03199-009 03199-008 03199-007 GAIN (dB) PERCENT OF UNITS (%) PERCENT OF UNITS (%) –0.17 –0.15 –0.13 –0.11 –0.09 –0.07 –0.05 –0.03 –0.01 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21 03199-012 03199-011 03199-010 AD8331/AD8332/AD8334 60 0 V = 1V GAIN V = 1V p-p OUT 50 V = 0.8V GAIN –20 V = 1.0V GAIN 40 V = 0.6V AD8332 GAIN –40 V = 0.7V GAIN AD8334 V = 0.4V GAIN 30 V = 0.4V GAIN –60 20 V = 0.2V GAIN –80 10 V = 0V GAIN –100 0 –10 –120 100k 1M 10M 100M 500M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Frequency Response for Various Values of VGAIN, HILO = HI Figure 16. Channel-to-Channel Crosstalk vs. Frequency for Various Values of V GAIN 30 50 V = 0.5V GAIN R = R = 75Ω IN S 45 R = R = 50Ω IN S 20 40 0.1µF 35 10 COUPLING R = R = 100Ω IN S 30 R = R = 200Ω IN S 1µF 0 25 COUPLING 20 R = R = 500Ω IN S –10 15 R = R = 1kΩ IN S 10 –20 5 –30 0 100k 1M 10M 100M 500M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Frequency Response for Various Matched Source Impedances Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling 20 30 HI GAIN T = +85°C V = 0.5V GAIN T = +25°C R =∞ IZ 10 T = –40°C 20 0 10 –10 –20 0 20 LO GAIN 10 –10 0 –20 T = +85°C –10 T = +25°C T = –40°C –30 –20 100k 1M 10M 100M 500M 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 FREQUENCY (Hz) V (V) GAIN Figure 15. Frequency Response, Unterminated LNA, R = 50 Ω Figure 18. Representative Differential Output Offset Voltage vs. S VGAIN at Three Temperatures Rev. G | Page 13 of 56 GAIN (dB) GAIN (dB) GAIN (dB) 03199-015 03199-014 03199-013 OFFSET VOLTAGE (mV) GROUP DELAY (ns) CROSSTALK (dB) 03199-018 03199-017 03199-016 AD8331/AD8332/AD8334 50j 100j 25j 35 SAMPLE SIZE = 100 R = 50Ω, IN 0.2V < V < 0.7V GAIN R = 270Ω IZ 30 25 R = 6kΩ, IN f = 100kHz R =∞ IZ 20 0Ω 17Ω 15 10 R = 75Ω, IN R = 412Ω IZ 5 R = 100Ω, IN R = 549Ω IZ R = 200Ω, IN 0 R = 1.1kΩ IZ 49.6 49.7 49.8 49.9 50.0 50.1 50.2 50.3 50.4 50.5 –25j –100j GAIN SCALING FACTOR –50j Figure 19. Gain Scaling Factor Histogram Figure 22. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz for Various Values of RIZ 100 20 SINGLE ENDED, PIN VOH OR PIN VOL V = 10mV p-p R = 50Ω IN IN R =∞ L R = 100Ω IN 15 10 10 R = 200Ω IN 5 R = 500Ω IN 0 R = 1kΩ 1 IN –5 –10 R = 75Ω IN 0.1 –15 100k 1M 10M 100M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. Output Impedance vs. Frequency Figure 23. LNA Frequency Response, Single-Ended, for Various Values of R IN 20 10k 15 R =∞ IZ 10 1k 5 0 100 –5 R = ∞, C = 0pF R = 549Ω, C = 8.2pF IZ SH IZ SH R = 6.65kΩ, C = 0pF R = 412Ω, C = 12pF –10 IZ SH IZ SH R = 3.01kΩ, C = 0pF R = 270Ω, C = 22pF IZ SH IZ SH R = 1.1kΩ, C = 1.2pF IZ SH 10 –15 100k 1M 10M 100M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. LNA Input Impedance vs. Figure 24. Frequency Response for Unterminated LNA, Single-Ended Frequency for Various Values of RIZ and CSH Rev. G | Page 14 of 56 INPUT IMPEDANCE (Ω) OUTPUT IMPEDANCE (Ω) % TOTAL 03199-021 03199-020 03199-019 GAIN (dB) GAIN (dB) 03199-022 03199-024 03199-023 AD8331/AD8332/AD8334 500 1.00 R = 0, R =∞, S IZ V = 1V, f = 10MHz f = 10MHz 0.95 GAIN 400 0.90 0.85 300 0.80 AD8332 HI GAIN AD8334 0.75 LO GAIN AD8331 200 0.70 0.65 100 0.60 0.55 0 0.50 0 0.2 0.4 0.6 0.8 1.0 –50 –30 –10 10 30 50 70 90 V (V) TEMPERATURE (°C) GAIN Figure 25. Output-Referred Noise vs. V GAIN Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature 2.5 10 R = 0, R =∞, V = 1V, f = 5MHz, R =∞, IZ S IZ GAIN HILO = LO OR HI V = 1V GAIN 2.0 1.5 1 1.0 R THERMAL NOISE S ALONE 0.5 0.1 100k 1M 10M 100M 1 10 100 1k FREQUENCY (Hz) SOURCE RESISTANCE (Ω) Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency Figure 29. Input-Referred Noise vs. R S 100 7 R = 0, R =∞, S IZ INCLUDES NOISE OF VGA HILO = LO OR HI, f = 10MHz 6 5 R = 50Ω 10 IN 4 R = 75Ω IN 3 R = 100Ω IN 1 R = 200Ω IN 2 R =∞ IZ 1 SIMULATED RESULTS 0.1 0 0 0.2 0.4 0.6 0.8 1.0 50 100 1k V (V) SOURCE RESISTANCE (Ω) GAIN Figure 30. Noise Figure vs. RS for Various Values of RIN Figure 27. Short-Circuit, Input-Referred Noise vs. VGAIN Rev. G | Page 15 of 56 OUTPUT-REFERRED NOISE (nV/ Hz) INPUT-REFERRED NOISE (nV/ Hz) INPUT-REFERRED NOISE (nV/ Hz) 03199-027 03199-026 03199-025 NOISE FIGURE (dB) INPUT-REFERRED NOISE (nV/ Hz) INPUT-REFERRED NOISE (nV/ Hz) 03199-029 03199-030 03199-028 AD8331/AD8332/AD8334 35 –30 PREAMP LIMITED f = 10MHz, R = 50Ω f = 10MHz, S V = 1V p-p OUT 30 –40 25 –50 HILO = LO, HD2 HILO = HI, HD2 20 –60 15 –70 10 HILO = HI, HD3 HILO = LO, HD3 HILO = LO, R = 50Ω IN HILO = LO, R =∞ –80 IZ 5 HILO = HI, R = 50Ω IN HILO = HI, R =∞ Iz 0 –90 0 0.1 0.20.30.40.50.60.70.80.91.01.1 0 200 400 600 800 1000 1200 1400 1600 1800 2000 V (V) R (Ω) GAIN LOAD Figure 31. Noise Figure vs. V Figure 34. Harmonic Distortion vs. R GAIN LOAD 30 –40 f = 10MHz, HILO = LO, R = 50Ω IN V = 1V p-p OUT HILO = LO, R =∞ FB 25 HILO = HI, R = 50Ω IN –50 HILO = HI, R =∞ FB HILO = LO, HD2 20 HILO = LO, HD3 –60 15 HILO = HI, HD2 –70 10 HILO = HI, HD3 –80 5 f = 10MHz, R = 50Ω S –90 0 10 15 20 25 30 35 40 45 50 55 60 0 10 203040 50 GAIN (dB) C (pF) LOAD Figure 35. Harmonic Distortion vs. C Figure 32. Noise Figure vs. Gain LOAD 0 –20 G = 30dB HILO = HI, HD2 f = 10MHz, V = 1Vp-p GAIN = 30dB OUT –10 HILO = HI, HD3 HILO = LO, HD2 –20 HILO = LO, HD3 –40 HILO = LO, HD3 –30 HILO = LO, HD2 –40 –60 –50 –60 HILO = HI, HD2 HILO = HI, HD3 –80 –70 –80 –100 –90 1M 10M 100M 01 234 V (V p-p) FREQUENCY (Hz) OUT Figure 36. Harmonic Distortion vs. Differential Output Voltage Figure 33. Harmonic Distortion vs. Frequency Rev. G | Page 16 of 56 HARMONIC DISTORTION (dBc) NOISE FIGURE (dB) NOISE FIGURE (dB) 03199-032 03199-031 03199-113 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 03199-036 03199-035 03199-034 AD8331/AD8332/AD8334 0 0 V = 1V p-p COMPOSITE (f + f ) OUT 1 2 V = 1V p-p OUT G = 30dB –10 –20 –20 INPUT RANGE LIMITED WHEN –40 –30 HILO = LO HILO = LO, HD3 HILO = LO HILO = LO, HD2 –40 –60 –50 –80 –60 –70 HILO = HI, HD3 –100 –80 HILO = HI, HD2 HILO = HI –120 –90 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1M 10M 100M V (V) FREQUENCY (Hz) GAIN Figure 37. Harmonic Distortion vs. V , f = 1 MHz Figure 40. IMD3 vs. Frequency GAIN 0 40 10MHz HILO = HI V = 1V p-p OUT 35 –20 1MHz HILO = LO 30 HILO = LO, HD2 INPUT RANGE LIMITED WHEN 10MHz HILO = LO –40 HILO = LO HILO = LO, HD3 25 1MHz HILO = HI –60 20 15 –80 HILO = HI, HD3 10 HILO = HI, HD2 –100 5 V = 1V p-p COMPOSITE (f + f ) OUT 1 2 –120 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 01 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9.0 V (V) V (V) GAIN GAIN Figure 41. Output Third-Order Intercept (IP3) vs. V Figure 38. Harmonic Distortion vs. VGAIN, f = 10 MHz GAIN 10 2mV 100 0 90 f = 10MHz HILO = LO HILO = HI –10 –20 10 0 –30 50mV 10ns –40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 V (V) GAIN Figure 39. IP1dB Compression vs. V GAIN Figure 42. Small Signal Pulse Response, G = 30 dB, Top: Input, Bottom: Output Voltage, HILO = HI or LO Rev. G | Page 17 of 56 IP1dB COMPRESSION (dBm) DISTORTION (dBc) DISTORTION (dBc) 03199-039 03199-038 03199-037 OUTPUT IP3 (dBm) IMD3 (dBc) 03199-042 03199-041 03199-040 AD8331/AD8332/AD8334 5.0 20mV 4.5 100 4.0 90 HILO = HI 3.5 HILO = LO 3.0 2.5 2.0 1.5 10 0 1.0 500mV 10ns 0.5 0 05 5 10 15 20 25 30 35 40 450 R (kΩ) CLMP Figure 43. Large Signal Pulse Response, G = 30 dB, Figure 46. Clamp Level vs. R CLMP HILO = HI or LO, Top: Input, Bottom: Output Voltage 2 4 C = 0pF L G = 40dB G = 30dB C = 10pF L R = 48.1kΩ 3 CLMP C = 22pF L R = 16.5kΩ CLMP C = 47pF L 1 2 INPUT 1 INPUT 0 0 R = 7.15kΩ CLMP R = 2.67kΩ –1 CLMP –1 –2 –3 INPUT IS NOT TO SCALE –2 –4 –50 –40 –30 –20 –10 0 10 20 30 40 50 –30 –20 –10 0 1020304050607080 TIME (ns) TIME (ns) Figure 44. Large Signal Pulse Response for Various Capacitive Loads, Figure 47. Clamp Level Pulse Response for Four Values of R CLMP C = 0 pF, 10 pF, 20 pF, 50 pF L 500mV 200mV 100 90 10 0 200mV 400ns 100ns Figure 48. LNA Overdrive Recovery, V 0.05 V p-p to 1 V p-p Burst, Figure 45. Pin GAIN Transient Response, INH V = 0.27 V VGA Output Shown Top: V , Bottom: Output Voltage GAIN GAIN Rev. G | Page 18 of 56 V (V) OUT 03199-045 03199-043 03199-044 V (V) V (V p-p) OUT OUT 03199-048 03199-047 03199-046 AD8331/AD8332/AD8334 1V 2V 100 90 10 0 100ns 1V 1ms Figure 49. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, Figure 52. Enable Response, Large Signal, VGAIN = 1 V VGA Output Shown Attenuated by 24 dB Top: VENB, Bottom: VOUT, VINH = 150 mV p-p 0 1V VPS1, V = 0.5V GAIN –10 100 90 –20 VPSV, V = 0.5V GAIN –30 –40 –50 VPS1, V = 0V GAIN 10 –60 0 –70 100ns –80 100k 1M 10M 100M FREQUENCY (Hz) Figure 50. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst, Figure 53. PSRR vs. Frequency (No Bypass Capacitor) VGAIN = 1 V VGA Output Shown Attenuated by 24 dB 140 V = 0.5V 2V GAIN 130 AD8334 120 110 100 90 80 70 AD8332 60 50 40 200mV 1ms AD8331 30 20 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 51. Enable Response, Top: V , Bottom: V , V = 30 mV p-p Figure 54. Quiescent Supply Current vs. Temperature ENB OUT INH Rev. G | Page 19 of 56 03199-051 03199-050 03199-049 QUIESCENT SUPPLY CURRENT (mA) PSRR (dB) 03199-052 03199-054 03199-053 AD8331/AD8332/AD8334 TEST CIRCUITS dividing the output noise by the numerical gain between Point A MEASUREMENT CONSIDERATIONS and Point B and accounting for the noise floor of the spectrum Figure 55 through Figure 68 show typical measurement analyzer. The gain should be measured at each frequency of configurations and proper interface values for measurements interest and with low signal levels because a 50 Ω load is driven with 50 Ω conditions. directly. The generator is removed when noise measurements Short-circuit input noise measurements are made as shown in are made. Figure 62. The input-referred noise level is determined by NETWORK ANALYZER 50Ω 50Ω OUT IN 18nF 270Ω 0.1µF 237Ω FB* 0.1µF 120nH 28Ω INH DUT 1:1 22pF 0.1µF 237Ω 0.1µF 28Ω LMD *FERRITE BEAD Figure 55. Test Circuit—Gain and Bandwidth Measurements NETWORK ANALYZER 50Ω 50Ω OUT IN 18nF 10kΩ 0.1µF 237Ω FB* 10kΩ 0.1µF 120nH 28Ω INH DUT 1:1 22pF 0.1µF 237Ω LMD 28Ω VGN 0.1µF *FERRITE BEAD Figure 56. Test Circuit—Frequency Response for Various Matched Source Impedances NETWORK ANALYZER 50Ω 50Ω OUT IN 0.1µF 237Ω FB* 0.1µF 120nH 28Ω INH DUT 1:1 22pF 0.1µF 237Ω LMD *FERRITE BEAD 28Ω VGN 0.1µF Figure 57. Test Circuit—Frequency Response for Unterminated LNA, RS = 50 Ω Rev. G | Page 20 of 56 03199-057 03199-055 03199-056 AD8331/AD8332/AD8334 NETWORK ANALYZER 50Ω 50Ω OUT IN 10kΩ 18nF 0.1µF OR 0.1µF 0.1µF 1µF 237Ω OR FB* 120nH 1µF 28Ω INH LNA VGA 1:1 22pF 237Ω LMD 0.1µF 0.1µF 0.1µF OR 28Ω *FERRITE BEAD 1µF Figure 58. Test Circuit—Group Delay vs. Frequency for Two Values of AC Coupling 18nF 270Ω NETWORK ANALYZER 0.1µF 237Ω FB* 0.1µF 120nH 28Ω 50Ω OUT INH DUT 1:1 50Ω 22pF LMD 0.1µF 237Ω 0.1µF 28Ω *FERRITE BEAD Figure 59. Test Circuit—LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) Formats NETWORK ANALYZER 50Ω 50Ω OUT IN 0.1µF 0.1µF 237Ω 0.1µF FB* 28Ω 0.1µF 120nH INH 1:1 LNA VGA 22pF 237Ω LMD 0.1µF 0.1µF 0.1µF 28Ω *FERRITE BEAD Figure 60. Test Circuit—Frequency Response for Unterminated LNA, Single-Ended NETWORK ANALYZER 18nF 270Ω 0.1µF 237Ω 50Ω IN 1:1 FB* 120nH 0.1µF 28Ω INH DUT 22pF 237Ω 0.1µF 0.1µF 28Ω LMD *FERRITE BEAD Figure 61. Test Circuit—Short-Circuit, Input-Referred Noise Rev. G | Page 21 of 56 03199-058 03199-061 03199-060 03199-059 AD8331/AD8332/AD8334 SPECTRUM ANALYZER A B GAIN 0.1µF 50Ω IN FERRITE BEAD 0.1µF 120nH 49.9Ω INH DUT 1:1 22pF 50Ω 1Ω 0.1µF 0.1µF SIGNAL GENERATOR LMD TO MEASURE GAIN DISCONNECT FOR NOISE MEASUREMENT Figure 62. Test Circuit—Noise Figure SPECTRUM ANALYZER 18nF 270Ω AD8332 50Ω 0.1µF 1kΩ –6dB 1:1 IN 0.1µF 28Ω INH –6dB DUT 1kΩ LPF 22pF LMD 0.1µF 28Ω 50Ω 0.1µF SIGNAL GENERATOR Figure 63. Test Circuit—Harmonic Distortion vs. Load Resistance SPECTRUM ANALYZER 18nF 270Ω AD8332 50Ω IN 0.1µF 237Ω –6dB 1:1 0.1µF 28Ω INH –6dB DUT LPF 237Ω 22pF LMD 0.1µF 28Ω 50Ω 0.1µF SIGNAL GENERATOR Figure 64. Test Circuit—Harmonic Distortion vs. Load Capacitance SPECTRUM ANALYZER –6dB +22dB 18nF 274Ω INPUT 0.1µF 237Ω 50Ω COMBINER –6dB –6dB FB* 50Ω 0.1µF 28Ω 120nH INH DUT 1:1 –6dB +22dB 22pF 237Ω 0.1µF 0.1µF 28Ω LMD 50Ω SIGNAL GENERATORS *FERRITE BEAD Figure 65.Test Circuit—IMD3 vs. Frequency Rev. G | Page 22 of 56 03199-063 03199-062 03199-065 03199-114 AD8331/AD8332/AD8334 OSCILLOSCOPE 18nF 270Ω 0.1µF 237Ω 50Ω FB* 0.1µF IN 120nH 28Ω INH DUT 1:1 22pF 237Ω 50Ω LMD 0.1µF 0.1µF 28Ω *FERRITE BEAD Figure 66. Test Circuit—Pulse Response Measurements OSCILLOSCOPE 18nF 270Ω 0.1µF CH1 CH2 DIFF FB* PROBE 0.1µF 255Ω 120nH INH DUT 22pF 50Ω RF LMD 0.1µF 255Ω SIGNAL 9.5dB 0.1µF GENERATOR 50Ω TO PIN GAIN OR PIN ENxx *FERRITE BEAD PULSE GENERATOR Figure 67. Test Circuit—Gain and Enable Transient Response NETWORK ANALYZER 50Ω 50Ω OUT IN TO POWER PINS 18nF 270Ω 0.1µF DIFF PROBE FB* PROBE POWER 0.1µF 255Ω 120nH INH DUT 22pF 50Ω LMD RF 0.1µF 255Ω SIGNAL 0.1µF GENERATOR *FERRITE BEAD Figure 68. Test Circuit—PSRR vs. Frequency Rev. G | Page 23 of 56 03199-066 03199-068 03199-067 AD8331/AD8332/AD8334 THEORY OF OPERATION LON1 LOP1 VIP1 VIN1 EN12 VCM1 OVERVIEW V CLAMP CLMP12 MID1 The AD8331/AD8332/AD8334 operate in the same way. INH1 LNA 1 VOH1 Figure 69, Figure 70, and Figure 71 are functional block – ATTENUATOR 21dB PA1 LMD1 –48dB VCM + diagrams of the three devices VOL1 BIAS LMD2 LON LOP VIP VIN VCM HILO VGA BIAS AND GAIN GAIN12 INTERPOLATOR INT 3.5dB/ HILO LNA 2 V INH2 15.5dB MID VOL2 + ATTENUATOR 21dB PA2 – VOH –48dB + LON2 – VOH2 ATTENUATOR 21dB PA INH LNA LOP2 –48dB – + VOL VIP2 V MID2 VCM2 VIN2 LMD GAIN UP/ VCM VGA BIAS AND MODE DOWN GAIN INT CLAMP BIAS RCLMP INTERPOLATOR V MID3 VCM3 VIN3 MODE AD8331 VIP3 VOH3 LOP3 – ATTENUATOR 21dB PA3 ENBL ENBV GAIN –48dB + LON3 VOL3 Figure 69. AD8331 Functional Block Diagram VGA BIAS AND GAIN GAIN34 INH3 LNA 3 INTERPOLATOR INT VOL4 LON1 LOP1 VIP1 VIN1 VCM1 HILO + ATTENUATOR LMD3 21dB PA4 VCM –48dB – BIAS VOH4 LMD4 3.5dB/ V MID +19dB 15.5dB AD8334 VOH1 INH4 LNA 4 CLAMP CLMP34 – INH1 LNA 1 ATTENUATOR V MID4 21dB PA1 + –48dB VOL1 LMD1 VGA BIAS AND LON4 LOP4 VIP4 VIN4 EN34 VCM4 GAIN LNA V MID GAIN INTERPOLATOR INT LMD2 Figure 71. AD8334 Functional Block Diagram VOH2 + ATTENUATOR 21dB PA2 INH2 LNA 2 Each channel contains an LNA that provides user-adjustable input –48dB – VOL2 impedance termination, a differential X-AMP VGA, and a pro- AD8332 V MID CLAMP RCLMP grammable gain postamp with adjustable output voltage limiting. Figure 72 shows a simplified block diagram with external LON2 LOP2 VIP2 VIN2 ENB VCM2 components. Figure 70. AD8332 Functional Block Diagram HILO LON VIN SIGNAL PATH POSTAMP 3.5dB/15.5dB PREAMPLIFIER 19dB VOH 48dB INH LNA 21dB ATTENUATOR VOL V MID LMD LOP VIP VCM CLAMP BIAS AND GAIN VCM INTERPOLATOR INTERFACE BIAS RCLMP GAIN Figure 72. Simplified Block Diagram Rev. G | Page 24 of 56 03199-069 03199-070 03199-071 03199-072 AD8331/AD8332/AD8334 The linear-in-dB, gain control interface is trimmed for slope and LOW NOISE AMPLIFIER (LNA) absolute accuracy. The gain range is +48 dB, extending from Good noise performance in the AD8331/AD8332/AD8334 −4.5 dB to +43.5 dB in LO gain and +7.5 dB to +55.5 dB in HI relies on a proprietary ultralow noise preamplifier at the beginning gain mode. The slope of the gain control interface is 50 dB/V, of the signal chain, which minimizes the noise contribution in the and the gain control range is 40 mV to 1 V. Equation 1 and following VGA. Active impedance control optimizes noise per- Equation 2 are the expressions for gain. formance for applications that benefit from input matching. GAIN (dB) = 50 (dB/V) × VGAIN − 6.5 dB, (HILO = LO) (1) A simplified schematic of the LNA is shown in Figure 74. INH or is capacitively coupled to the source. A bias generator establishes dc input bias voltages of 3.25 V and centers the output common- GAIN (dB) = 50 (dB/V) × V + 5.5 dB, (HILO = HI) (2) GAIN mode levels at 2.5 V. A capacitor CLMD (can be the same value as The ideal gain characteristics are shown in Figure 73. the input coupling capacitor CINH) is connected from the LMD 60 pin to ground to decouple the LMD bus. The LMD pin is not useable for configuring the LNA as a differential input amplifier. 50 C IZ R IZ HILO = HI 40 TO VGA VPOS LON 30 LOP 2.5V 2.5V 20 I I 0 0 10 HILO = LO –a –a C INH INH 3.25V 3.25V LMD ASCENDING GAIN MODE 0 Q1 Q2 60Ω 40Ω 80Ω DESCENDING GAIN MODE C LMD (WHERE AVAILABLE) C SH –10 R S 0 0.2 0.4 0.6 0.8 1.0 1.1 VCM I I 0 0 V (V) BIAS GAIN Figure 73. Ideal Gain Control Characteristics The gain slope is negative with MODE pulled high (where Figure 74. Simplified LNA Schematic available), as follows: The LNA supports differential output voltages as high as 5 V p-p, GAIN (dB) = −50 (dB/V) × V + 45.5 dB, (HILO = LO) (3) GAIN with positive and negative excursions of ±1.25 V, about a common-mode voltage of 2.5 V. Because the differential gain or magnitude is 9, the maximum input signal before saturation is GAIN (dB) = −50 (dB/V) × VGAIN + 57.5 dB, (HILO = HI) (4) ±275 mV or +550 mV p-p. Overload protection ensures quick The LNA converts a single-ended input to a differential output recovery time from large input voltages. Because the inputs are with a voltage gain of 19 dB. If only one output is used, the gain capacitively coupled to a bias voltage near midsupply, very large is 13 dB. The inverting output is used for active input impedance inputs can be handled without interacting with the ESD protection. termination. Each of the LNA outputs is capacitively coupled to Low value feedback resistors and the current-driving capability a VGA input. The VGA consists of an attenuator with a range of of the output stage allow the LNA to achieve a low input-referred 48 dB followed by an amplifier with 21 dB of gain for a net gain voltage noise of 0.74 nV/√Hz. This is achieved with a current range of −27 dB to +21 dB. The X-AMP, gain interpolation consumption of only 11 mA per channel (55 mW). On-chip technique results in low gain error and uniform bandwidth, and resistor matching results in precise single-ended gains of 4.5× differential signal paths minimize distortion. (9× differential), critical for accurate impedance control. The use The final stage is a logic programmable amplifier with gains of of a fully differential topology and negative feedback minimizes 3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for distortion. Low HD2 is particularly important in second harmonic 12-bit and 10-bit ADC applications, in terms of output-referred ultrasound imaging applications. Differential signaling enables noise and absolute gain range. Output voltage limiting can be smaller swings at each output, further reducing third-order programmed by the user. distortion. Rev. G | Page 25 of 56 GAIN (dB) 03199-073 03199-074 AD8331/AD8332/AD8334 UNTERMINATED Active Impedance Matching R The LNA supports active impedance matching through an external IN R S shunt feedback resistor from Pin LON to Pin INH. The input V OUT + resistance, RIN, is given in Equation 5, where A is the single- V IN – ended gain of 4.5, and 6 kΩ is the unterminated input impedance. RESISTIVE TERMINATION R R 6 kΩ × IZ IZ R = 6 kΩ = (5) R IN IN 1 + A 33 kΩ + R R IZ S V OUT + R C is needed in series with R because the dc levels at Pin LON S IZ IZ V IN – and Pin INH are unequal. Expressions for choosing R in terms IZ of R and for choosing C are found in the Applications IN IZ ACTIVE IMPEDANCE MATCH - R = R S IN R Information section. C and the ferrite bead enhance stability IZ SH R IN at higher frequencies, where the loop gain is diminished, and R S V prevent peaking. Frequency response plots of the LNA are shown OUT + V IN in Figure 23 and Figure 24. The bandwidth is approximately – 130 MHz for matched input impedances of 50 Ω to 200 Ω and R IZ R = declines at higher source impedances. The unterminated IN 1 + 4.5 bandwidth (when R = ∞) is approximately 80 MHz. IZ Figure 75. Input Configurations Each output can drive external loads as low as 100 Ω in addition 7 INCLUDES NOISE OF VGA to the 100 Ω input impedance of the VGA (200 Ω differential). 6 Capacitive loading up to 10 pF is permissible. All loads should RESISTIVE TERMINATION be ac-coupled. Typically, Pin LOP output is used as a single-ended (R = R ) 5 S IN driver for auxiliary circuits, such as those used for Doppler ultrasound imaging. Pin LON drives RIZ. Alternatively, a 4 differential external circuit can be driven from the two outputs 3 in addition to the active feedback termination. In both cases, ACTIVE IMPEDANCE MATCH important stability considerations discussed in the Applications 2 Information section should be carefully observed. 1 The impedance at each LNA output is 5 Ω. A 0.4 dB reduction UNTERMINATED SIMULATION in open circuit gain results when driving the VGA, and a 0.8 dB 0 reduction results with an additional 100 Ω load at the output. 50 100 1k R (Ω) S The differential gain of the LNA is 6 dB higher. If the load is less than 200 Ω on either side, a compensating load is recommended Figure 76. Noise Figure vs. RS for Resistive, Active Match, and Unterminated Inputs on the opposite output. 7 LNA Noise INCLUDES NOISE OF VGA 6 The input-referred voltage noise sets an important limit on system performance. The short-circuit input voltage noise of 5 the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain), R = 50Ω IN including the VGA noise. The open circuit, current noise is 4 R = 75Ω IN 2.5 pA/√Hz. These measurements, taken without a feedback R = 100Ω 3 resistor, provide the basis for calculating the input noise and IN noise figure performance of the configurations in Figure 75. R = 200Ω IN 2 Figure 76 and Figure 77 show simulations extracted from these R =∞ IZ results and the 4.1 dB noise figure (NF) measurement with the 1 input actively matched to a 50 Ω source. Unterminated (R = ∞) IZ (SIMULATED RESULTS) operation exhibits the lowest equivalent input noise and noise 0 50 100 1k figure. Figure 76 shows the noise figure vs. source resistance, R (Ω) S rising at low R , where the LNA voltage noise is large compared S Figure 77. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched to the source noise, and again at high RS due to current noise. The VGA input-referred voltage noise of 2.7 nV/√Hz is included in all of the curves. Rev. G | Page 26 of 56 NOISE FIGURE (dB) NOISE FIGURE (dB) 03199-075 03199-077 03199-076 AD8331/AD8332/AD8334 The primary purpose of input impedance matching is to X-AMP VGA improve the system transient response. With resistive termination, The input of the VGA is a differential R-2R ladder attenuator the input noise increases due to the thermal noise of the matching network with 6 dB steps per stage and a net input impedance of resistor and the increased contribution of the LNA input voltage 200 Ω differential. The ladder is driven by a fully differential noise generator. With active impedance matching, however, the input signal from the LNA and is not intended for single-ended contributions of both are smaller than they would be for resistive operation. LNA outputs are ac-coupled to reduce offset and isolate termination by a factor of 1/(1 + LNA Gain). Figure 76 shows their common-mode voltage. The VGA inputs are biased through their relative NF performance. In this graph, the input impedance the center tap connection of the ladder to VCM, which is typically is swept with R to preserve the match at each point. The noise S set to 2.5 V and is bypassed externally to provide a clean ac ground. figures for a source impedance of 50 Ω are 7.1 dB, 4.1 dB, and The signal level at successive stages in the input attenuator 2.5 dB, respectively, for the resistive, active, and unterminated falls from 0 dB to −48 dB in +6 dB steps. The input stages of the configurations. The noise figures for 200 Ω are 4.6 dB, 2.0 dB, X-AMP are distributed along the ladder, and a biasing interpolator, and 1.0 dB, respectively. controlled by the gain interface, determines the input tap point. Figure 77 is a plot of NF vs. RS for various values of RIN, which is With overlapping bias currents, signals from successive taps helpful for design purposes. The plateau in the NF for actively merge to provide a smooth attenuation range from 0 dB to matched inputs mitigates source impedance variations. For −48 dB. This circuit technique results in excellent linear-in-dB comparison purposes, a preamp with a gain of 19 dB and noise gain law conformance and low distortion levels and deviates spectral density of 1.0 nV/√Hz, combined with a VGA with ±0.2 dB or less from the ideal. The gain slope is monotonic with 3.75 nV/√Hz, yields a noise figure degradation of approximately respect to the control voltage and is stable with variations in 1.5 dB (for most input impedances), significantly worse than process, temperature, and supply. the AD8331/AD8332/AD8334 performance. The X-AMP inputs are part of a gain-of-12 feedback amplifier The equivalent input noise of the LNA is the same for single- that completes the VGA. Its bandwidth is 150 MHz. The input ended and differential output applications. The LNA noise figure stage is designed to reduce feedthrough to the output and to improves to 3.5 dB at 50 Ω without VGA noise, but this is ensure excellent frequency response uniformity across gain exclusive of noise contributions from other external circuits setting (see Figure 12 and Figure 13). connected to LOP. A series output resistor is usually recom- Gain Control mended for stability purposes when driving external circuits on Position along the VGA attenuator is controlled by a single-ended a separate board (see the Applications Information section). In analog control voltage, V , with an input range of 40 mV to GAIN low noise applications, a ferrite bead is even more desirable. 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V VARIABLE GAIN AMPLIFIER (20 mV/dB). Values of V beyond the control range saturate GAIN The differential X-AMP VGA provides precise input attenuation to minimum or maximum gain values. Both channels of the and interpolation. It has a low input-referred noise of 2.7 nV/√Hz AD8332 are controlled from a single gain interface to preserve and excellent gain linearity. A simplified block diagram is shown matching. Gain can be calculated using Equation 1 and Equation 2. in Figure 78. Gain accuracy is very good because both the scaling factor and GAIN GAIN INTERPOLATOR absolute gain are factory trimmed. The overall accuracy relative (BOTH CHANNELS) POSTAMP to the theoretical gain expression is ±1 dB for variations in + temperature, process, supply voltage, interpolator gain ripple, g m trim errors, and tester limits. The gain error relative to a best-fit 6dB VIP line for a given set of conditions is typically ±0.2 dB. Gain matching 48dB R 2R between channels is better than 0.1 dB (Figure 11 shows gain errors 200Ω in the center of the control range). When VGAIN < 0.1 or > 0.95, VIN gain errors are slightly greater. The gain slope can be inverted, as shown in Figure 73 (except for the AD8332 AR models). The gain drops with a slope of −50 dB/V – across the gain control range from maximum to minimum gain. POSTAMP This slope is useful in applications such as automatic gain control, Figure 78. Simplified VGA Schematic where the control voltage is proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin to HI gain mode. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. Rev. G | Page 27 of 56 03199-078 AD8331/AD8332/AD8334 VGA Noise Common-Mode Biasing In a typical application, a VGA compresses a wide dynamic An internal bias network connected to a midsupply voltage range input signal to within the input span of an ADC. While establishes common-mode voltages in the VGA and postamp. the input-referred noise of the LNA limits the minimum resolvable An externally bypassed buffer maintains the voltage. The bypass input signal, the output-referred noise, which depends primarily capacitors form an important ac ground connection because on the VGA, limits the maximum instantaneous dynamic range the VCM network makes a number of important connections that can be processed at any one particular gain control voltage. internally, including the center tap of the VGA differential input This limit is set in accordance with the quantization noise floor attenuator, the feedback network of the VGA fixed gain amplifier, of the ADC. and the feedback network of the postamp in both gain settings. For best results, use a 1 nF capacitor and a 0.1 μF capacitor in Output- and input-referred noise as a function of VGAIN are plotted parallel, with the 1 nF capacitor nearest to the VCM pin. Separate in Figure 25 and Figure 27 for the short circuited input conditions. VCM pins are provided for each channel. For dc coupling to a 3 V The input noise voltage is simply equal to the output noise divided ADC, the output common-mode voltage is adjusted to 1.5 V by by the measured gain at each point in the control range. biasing the VCM pin. The output-referred noise is flat over most of the gain range POSTAMPLIFIER because it is dominated by the fixed output-referred noise of the VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB in HI gain mode. At the high end of the gain control range, the (×6), set by the HILO logic pin. Figure 79 is a simplified block noise of the LNA and the noise of the source prevail. The input- diagram. referred noise reaches its minimum value near the maximum Gm2 + gain control voltage, where the input-referred contribution of VOH the VGA becomes very small. Gm1 At lower gains, the input-referred noise, and thus noise figure, F2 increases as the gain decreases. The instantaneous dynamic VCM F1 range of the system is not lost, however, because the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship Gm2 is the magnitude of the VGA output noise floor relative to that VOL of the ADC. – Gm1 With its low output-referred noise levels, these devices ideally Figure 79. Postamplifier Block Diagram drive low voltage ADCs. The converter noise floor drops 12 dB Separate feedback attenuators implement the two gain settings. for every two bits of resolution and drops at lower input full- These are selected in conjunction with an appropriately scaled scale voltages and higher sampling rates. ADC quantization input stage to maintain a constant 3 dB bandwidth between the noise is discussed in the Applications Information section. two gain modes (~150 MHz). The slew rate is 1200 V/μs in HI gain The preceding noise performance discussion applies to a mode and 300 V/μs in LO gain mode. The feedback networks differential VGA output signal. Although the LNA noise for HI and LO gain modes are factory trimmed to adjust the performance is the same in single-ended and differential absolute gains of each channel. applications, the VGA performance is not. The noise of the Noise VGA is significantly higher in single-ended usage because the contribution of its bias noise is designed to cancel in the differential The topology of the postamp provides constant input-referred signal. A transformer can be used with single-ended applications noise with the two gain settings and variable output-referred when low noise is desired. noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving Gain control noise is a concern in very low noise applications. converters with higher noise floors. The extra gain boosts the Thermal noise in the gain control interface can modulate the output signal levels and noise floor appropriately. When driving channel gain. The resultant noise is proportional to the output circuits with lower input noise floors, the LO gain mode optimizes signal level and usually only evident when a large signal is present. the output dynamic range. Its effect is observable only in LO gain mode where the noise floor is substantially lower. The gain interface includes an Although the quantization noise floor of an ADC depends on a on-chip noise filter, which reduces this effect significantly at number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are frequencies above 5 MHz. Care should be taken to minimize well suited to the average requirements of most 12-bit and 10-bit noise impinging at the GAIN input. An external RC filter can be converters, respectively. An additional technique, described in used to remove VGAIN source noise. The filter bandwidth should be the Applications Information section, can extend the noise floor sufficient to accommodate the desired control bandwidth. even lower for possible use with 14-bit ADCs. Rev. G | Page 28 of 56 03199-079 AD8331/AD8332/AD8334 5.0 Output Clamping 4.5 Outputs are internally limited to a level of 4.5 V p-p differential R =∞ CLMP 4.0 when operating at a 2.5 V common-mode voltage. The postamp 8.8kΩ implements an optional output clamp engaged through a resistor 3.5 3.5kΩ from RCLMP to ground. Table 8 shows a list of recommended 3.0 resistor values. 2.5 R = 1.86kΩ CLMP Output clamping can be used for ADC input overload protection, if 2.0 3.5kΩ needed, or postamp overload protection when operating from a 8.8kΩ 1.5 lower common-mode level, such as 1.5 V. The user should be 1.0 aware that distortion products increase as output levels approach R =∞ CLMP 0.5 the clamping levels, and the user should adjust the clamp resistor 0 accordingly. For additional information, see the Applications –3 –2 –1 0 1 2 3 Information section. V (V) INH The accuracy of the clamping levels is approximately ±5% in LO Figure 80. Output Clamping Characteristics or HI mode. Figure 80 illustrates the output characteristics for a few values of R . CLMP Rev. G | Page 29 of 56 V , V (V) OH OL 03199-080 AD8331/AD8332/AD8334 APPLICATIONS INFORMATION C LMD LNA 0.1µF LNA—EXTERNAL COMPONENTS FB SOURCE 1 28 The LMD pin (connected to the bias circuitry) must be bypassed to 0.1µF LMD2 LMD1 ground and signal sourced to the INH pin, which is capacitively C * SH 2 27 INH2 INH1 coupled using 2.2 nF to 0.1 μF capacitors (see Figure 81). C * 5V +5V IZ 26 3 VPS2 VPS1 The unterminated input impedance of the LNA is 6 kΩ. The R * IZ 1nF 0.1µF 4 25 user can synthesize any LNA input resistance between 50 Ω and LON2 LON1 LNA OUT 6 kΩ. RIZ is calculated according to Equation 6 or selected from 5 24 LOP2 LOP1 Table 7. 23 6 COM2 COM1 33 kΩ ×() R IN 7 22 R = (6) IZ VIP2 VIP1 6 kΩ –() R 0.1µF IN 0.1µF 1nF 8 21 VIN2 VIN1 Table 7. LNA External Component Values for Common 20 9 V VCM2 GAIN VCM1 Source Impedances 5V 1nF 0.1µF 1nF 10 19 GAIN HILO R (Ω) R (Nearest STD 1% Value, Ω) C (pF) IN IZ SH 11 18 50 280 22 RCLMP 5V ENB 0.1µF 1nF 75 412 12 17 * 12 VOH2 VGA OUT VOH1 100 562 8 13 16 * VOL2 VGA OUT 200 1.13 k 1.2 VOL1 500 3.01 k None 14 15 COMM VPSV 5V 1nF 0.1µF 6 k None ∞ *SEE TEXT When active input termination is used, a decoupling capacitor (C ) IS Figure 81. Basic Connections for a Typical Channel (AD8332 Shown) is required to isolate the input and output bias voltages of the LNA. LNA TO EXT DECOUPLING R RESISTOR CIRCUIT IZ The shunt input capacitor, C , reduces gain peaking at higher SH frequencies where the active termination match is lost due to 5Ω VIP 50Ω the gain roll-off of the LNA at high frequencies. The value of CSH diminishes as RIN increases to 500 Ω, at which point no capacitor is LON 100Ω 3.25V VCM 2.5V required. Suggested values for CSH for 50 Ω ≤ RIN ≤ 200 Ω are LNA shown in Table 7. C 2.5V SH 100Ω LOP 5Ω 50Ω When a long trace to Pin INH is unavoidable, or if both LNA 3.25V outputs drive external circuits, a small ferrite bead (FB) in series VIN with Pin INH preserves circuit stability with negligible effect on LNA TO EXT noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or DECOUPLING CIRCUIT RESISTOR equivalent). Other values can prove useful. Figure 82. Interconnections of the LNA and VGA Figure 82 shows the interconnection details of the LNA output. Both LNA outputs are available for driving external circuits. Capacitive coupling between the LNA outputs and the VGA Pin LOP should be used in those instances when a single-ended inputs is required because of the differences in their dc levels LNA output is required. The user should be aware of stray and the need to eliminate the offset of the LNA. Capacitor values capacitance loading of the LNA outputs, in particular LON. The of 0.1 μF are recommended. There is a 0.4 dB loss in gain LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is between the LNA output and the VGA input due to the 5 Ω routed to a remote PC board, it tolerates a load capacitance up output resistance. Additional loading at the LOP and LON to 100 pF with the addition of a 49.9 Ω series resistor or ferrite outputs affects LNA gain. 75 Ω/100 MHz bead. Rev. G | Page 30 of 56 03199-082 03199-081 AD8331/AD8332/AD8334 Gain Input Optional Output Voltage Limiting The GAIN pin is common to both channels of the AD8332. The The RCLMP pin provides the user with a means to limit the input impedance is nominally 10 MΩ, and a bypass capacitor output voltage swing when used with loads that have no from 100 pF to 1 nF is recommended. provisions for prevention of input overdrive. The peak-to-peak limited voltage is adjusted by a resistor to ground (see Table 8 Parallel connected devices can be driven by a common voltage for a list of several voltage levels and corresponding resistor source or DAC. Decoupling should take into account any band- values). Unconnected, the default limiting level is 4.5 V p-p. width considerations of the drive waveform, using the total distributed capacitance. Note that third harmonic distortion increases as waveform amplitudes approach clipping. For lowest distortion, the clamp level If gain control noise in LO gain mode becomes a factor, main- should be set higher than the converter input span. A clamp level taining ≤15 nV/√Hz noise at the GAIN pin ensures satisfactory of 1.5 V p-p is recommended for a 1 V p-p linear output range, noise performance. Internal noise prevails below 15 nV/√Hz at 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. the GAIN pin. Gain control noise is negligible in HI gain mode. The best solution is determined experimentally. Figure 84 shows VCM Input third harmonic distortion as a function of the limiting level for The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH a 2 V p-p output signal. A wider limiting level is desirable in HI defaults to 2.5 V dc. With output ac-coupled applications, the gain mode. VCM pin is unterminated; however, it must still be bypassed in –20 V = 0.75V GAIN close proximity for ac grounding of internal circuitry. The VGA outputs can be dc connected to a differential load, such as an –30 ADC. Common-mode output voltage levels between 1.5 V and 3.5 V can be realized at Pin VOH and Pin VOL by applying the –40 desired voltage at Pin VCM. DC-coupled operation is not recommended when driving loads on a separate PC board. –50 The voltage on the VCM pin is sourced by an internal buffer HILO = LO –60 with an output impedance of 30 Ω and a ±2 mA default output current (see Figure 83). If the VCM pin is driven from an external HILO = HI –70 source, its output impedance should be <<30 Ω, and its current drive capability should be >>2 mA. If the VCM pins of several –80 devices are connected in parallel, the external buffer should be 1.52.0 2.53.0 3.5 4.0 4.5 5.0 CLAMP LIMIT LEVEL (V p-p) capable of overcoming their collective output currents. When a Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input common-mode voltage other than 2.5 V is used, a voltage- Table 8. Clamp Resistor Values limiting resistor, RCLMP, is needed to protect against overload. Clamp Resistor Value (kΩ) INTERNAL CIRCUITRY Clamp Level (V p-p) HILO = LO HILO = HI 2mA MAX R << 30Ω NEW V O CM VCM 0.5 1.21 30Ω 1.0 2.74 2.21 100pF 0.1µF 1.5 4.75 4.02 AC GROUNDING FOR 2.0 7.5 6.49 INTERNAL CIRCUITRY 2.5 11 9.53 Figure 83. VCM Interface 3.0 16.9 14.7 Logic Inputs—ENB, MODE, and HILO 3.5 26.7 23.2 The input impedance of all enable pins is nominally 25 kΩ and 4.0 49.9 39.2 can be pulled up to 5 V (a pull-up resistor is recommended) or 4.4 100 73.2 driven by any 3 V or 5 V logic families. The enable pin, ENB, Output Decoupling powers down the VGA; when pulled low, the VGA output voltages When driving capacitive loads greater than about 10 pF, or long are near ground. Multiple devices can be driven from a common circuit connections on other boards, an output network of resistors source. Consult Table 3, Table 4, Table 5, and Table 6 for infor- and/or ferrite beads can be useful to ensure stability. These mation about circuit functions controlled by the enable pins. components can be incorporated into a Nyquist filter such as Pin HILO is compatible with 3 V or 5 V CMOS logic families. It the one shown in Figure 81. In Figure 81, the resistor value is is either connected to ground or pulled up to 5 V, depending on 84.5 Ω. For example, all the evaluation boards for this series the desired gain range and output noise. incorporate 100 Ω in parallel with a 120 nH bead. Lower value resistors are permissible for applications with nearby loads or Rev. G | Page 31 of 56 03199-083 HD3 (dBc) 03199-084 AD8331/AD8332/AD8334 with gains less than 40 dB. The exact values of these components Signals larger than ±275 mV at the LNA input are clipped to can be selected empirically. 5 V p-p differential prior to the input of the VGA. Figure 48 shows the response to a 1 V p-p input burst. The symmetric An antialiasing noise filter is typically used with an ADC. Filter overload waveform is important for applications, such as CW requirements are application dependent. Doppler ultrasound, where the spectrum of the LNA outputs When the ADC resides on a separate board, the majority of during overload is critical. The input stage is also designed to filter components should be placed nearby to suppress noise accommodate signals as high as ±2.5 V without triggering the picked up between boards and to mitigate charge kickback from slow-settling ESD input protection diodes. the ADC inputs. Any series resistance beyond that required for Both stages of the VGA are susceptible to overload. Post- output stability should be placed on the ADC board. Figure 85 amplifier limiting is more common and results in the clean- shows a second-order, low-pass filter with a bandwidth of 20 MHz. limited output characteristics found in Figure 49. Recovery is fast in The capacitor is chosen in conjunction with the 10 pF input all cases. The graph in Figure 87 summarizes the combinations of capacitance of the ADC. input signal and gain that lead to the different types of overload. OPTIONAL BACKPLANE POSTAMP X-AMP POSTAMP X-AMP OVERLOAD OVERLOAD OVERLOAD OVERLOAD 0.1µF 1.5µH 15mV 25mV 4mV 25mV 84.5Ω 158Ω 43.5 56.5 18pF 0.1µF ADC 84.5Ω 1.5µH 158Ω 41dB 29dB Figure 85. 20 MHz Second-Order, Low-Pass Filter 24.5dB 24.5dB LO GAIN HI GAIN DRIVING ADCs MODE MODE The output drive accommodates a wide range of ADCs. The noise floor requirements of the VGA depend on a number of application factors, including bit resolution, sampling rate, full- scale voltage, and the bandwidth of the noise/antialias filter. The –4.5 7.5 output noise floor and gain range can be adjusted by selecting 1m 10m 0.1 0.275 1 1m 10m 0.1 0.275 1 INPUT AMPLITUDE (V) INPUT AMPLITUDE (V) HI or LO gain mode. Figure 87. Overload Gain and Signal Conditions The relative noise and distortion performance of the two gain The clamp interface mentioned in the Output Clamping section modes can be compared in Figure 25 and Figure 31 through controls the maximum output swing of the postamp and its Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is overload response. When the clamp feature is not used, the suited to converters with higher sampling rates or resolutions output level defaults to approximately 4.5 V p-p differential (such as 12 bits). Both gain modes can accommodate ADC full- centered at 2.5 V common mode. When other common-mode scale voltages as high as 4 V p-p. Because distortion performance levels are set through the VCM pin, the value of R should be CLMP remains favorable for output voltages as high as 4 V p-p (see selected for graceful overload. A value of 8.3 kΩ or less is Figure 36), it is possible to lower the output-referred noise even recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ further by using a resistive attenuator (or transformer) at the for HI gain mode). This limits the output swing to just above output. The circuit in Figure 86 has an output full-scale range of 2 V p-p differential. 2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output noise floor of 24 nV/√Hz, making it suitable for some 14-bit OPTIONAL INPUT OVERLOAD PROTECTION ADC applications. Applications in which high transients are applied to the LNA 4V p-p DIFF, 2V p-p DIFF, 48nV/ Hz 24nV/ Hz input can benefit from the use of clamp diodes. A pair of back- to-back Schottky diodes can reduce these transients to manageable 187Ω levels. Figure 88 illustrates how such a diode protection scheme VOH ADC 2:1 374Ω LPF can be connected. AD6644 VOL OPTIONAL 187Ω SCHOTTKY COMM 20 OVERLOAD Figure 86. Adjusting the Noise Floor for 14-Bit ADCs CLAMP 0.1µF FB 2 INH ENBL 19 OVERLOAD C 3 R IZ SH 3 VPSL These devices respond gracefully to large signals that overload R C IZ SH its input stage and to normal signals that overload the VGA 4 LON when the gain is set unexpectedly high. Each stage is designed 2 1 BAS40-04 for clean-limited overload waveforms and fast recovery when Figure 88. Input Overload Clamping gain setting or input amplitude is reduced. Rev. G | Page 32 of 56 03199-086 03199-085 GAIN (dB) LNA OVERLOAD GAIN (dB) LNA OVERLOAD 03199-088 03199-087 AD8331/AD8332/AD8334 ADG736 When selecting overload protection, the important parameters 1.13kΩ are forward and reverse voltages and t (or τ ). The Infineon rr rr SELECT R IZ BAS40-04 series shown in Figure 88 has a τ of 100 ps and a V rr F 280Ω of 310 mV at 1 mA. Many variations of these specifications can be found in vendor catalogs. LON 18nF 5Ω LAYOUT, GROUNDING, AND BYPASSING 200Ω INH Due to their excellent high frequency characteristics, these LOP LNA devices are sensitive to their PCB environments. Realizing LMD 5Ω 50Ω expected performance requires attention to detail critical to 0.1µF AD8332 good, high speed, board design. Figure 89. Accommodating Multiple Sources A multilayer board with power and ground planes is recom- mended with blank areas in the signal layers filled with ground DISABLING THE LNA plane. Be certain that the power and ground pins provided for Where accessible, connection of the LNA enable pin to ground robust power distribution to the device are connected. Decouple powers down the LNA, resulting in a current reduction of about the power supply pins with surface-mount capacitors as close as half. In this mode, the LNA input and output pins can be left possible to each pin to minimize impedance paths to ground. unconnected; however, the power must be connected to all the Decouple the LNA power pins from the VGA supply using supply pins for the disabling circuit to function. Figure 90 illustrates ferrite beads. Together with the capacitors, ferrite beads the connections using AD8331 as an example. eliminate undesired high frequencies without reducing the 1 20 headroom. Use a larger value capacitor for every 10 chips to NC LMD COMM 20 chips to decouple residual low frequency noise. To minimize AD8331 voltage drops, use a 5 V regulator for the VGA array. 2 19 NC INH ENBL Several critical LNA areas require special care. The LON and LOP output traces must be as short as possible before connecting to the coupling capacitors connected to Pin VIN and Pin VIP. +5V 3 18 VPSL ENBV +5V RIZ must be placed near the LON pin as well. Resistors must be placed as close as possible to the VGA output pins, VOL and VOH, to mitigate loading effects of connecting traces. Values 4 17 NC LON COMM are discussed in the Output Decoupling section. Signal traces must be short and direct to avoid parasitic effects. Wherever there are complementary signals, symmetrical layout 5 16 NC LOP VOL should be employed to maintain waveform balance. PCB traces VOUT should be kept adjacent when running differential signals over a 6 15 long distance. COML VOH MULTIPLE INPUT MATCHING 0.1µF Matching of multiple sources with dissimilar impedances can be 7 14 VIP VPOS +5V accomplished as shown in Figure 89. A relay and low supply voltage analog switch can be used to select between multiple sources VIN 0.1µF and their associated feedback resistors. An ADG736 dual SPDT 8 13 VIN HILO HILO switch is shown in this example; however, multiple switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers. 9 12 MODE MODE RCLMP R CLMP 10 11 GAIN GAIN VCM VCM Figure 90. Disabling the LNA Rev. G | Page 33 of 56 03199-090 03199-089 AD8331/AD8332/AD8334 ULTRASOUND TGC APPLICATION HIGH DENSITY QUAD LAYOUT The AD8332 ideally meets the requirements of medical and The AD8334 is the ideal solution for applications with limited industrial ultrasound applications. The TGC amplifier is a key board space. Figure 94 represents four channels routed to and subsystem in such applications because it provides the means away from this very compact quad VGA. Note that none of the for echo location of reflected ultrasound energy. signal paths crosses and that all four channels are spaced apart to eliminate crosstalk. Figure 91 through Figure 93 are schematics of a dual, fully differential system using the AD8332 and the AD9238 12-bit In this example, all of the components shown are 0402 size; high speed ADC with conversion speeds as high as 65 MSPS. however, the same layout is executable at the expense of slightly more board area. The sketch also assumes that both sides of the printed circuit board are available for components and that the bypass and power supply decoupling circuitry is located on the wiring side of the board. Rev. G | Page 34 of 56 AD8331/AD8332/AD8334 S3 E IN2 TP5 AD8332ARU C50 1 28 0.1µF LMD1 LMD2 C49 TP6 C70 0.1µF L12 0.1µF L13 C60 120nH FB 120nH FB 0.1µF TP3 2 27 S1 (RED) +5V INH2 INH1 E C79 IN1 TB1 C80 JP5 JP6 22pF CFB2 +5V 22pF IN2 IN1 CFB1 18nF 18nF + +5VLNA 3 26 C46 TP4 VPS1 VPS2 RFB1 1µF (BLACK) C41 C74 +5VLNA 274Ω RFB2 0.1µF 1nF TB2 274Ω GND L7 4 25 120nH FB LON2 LON1 +5VGA 5 24 L6 LOP2 LOP1 120nH FB +5VLNA C42 C59 6 23 C51 C53 COM2 COM1 0.1µF 0.1µF 0.1µF 0.1µF 7 22 VIP2 VIP1 VCM1 8 21 VIN2 VIN1 VCM1 JP13 C78 C48 0.1µF 1nF 9 20 VCM2 VCM1 C43 C77 0.1µF 1nF +5VGA 10 19 HI GAIN TP2 GAIN GAIN HILO JP10 TP7 GND C83 +5VGA LO GAIN 1nF ENABLE 18 11 RCLMP ENB JP16 R3 C68 C69 DISABLE (R ) CLMP 1nF 0.1µF 12 17 VOH2 VOH1 JP8 R27 R24 DC2H JP9 100Ω 100Ω OPTIONAL 4-POLE LOW-PASS OPTIONAL 4-POLE LOW-PASS FILTER FILTER 13 16 C58 L9 L19 L17 C54 L11 L1 L15 VOL2 VOL1 0.1µF V +B 120nH FB SAT SAT 0.1µF 120nH FB SAT SAT IN V +A IN C64 C65 JP17 C66 C67 14 SAT SAT JP12 C55 15 L20 L18 L10 C56 SAT SAT L8 L14 L16 COMM VPSV 0.1µF SAT SAT 120nH FB 0.1µF 120nF FB SAT SAT V –B V –A IN IN JP7 R26 R25 DC2L 100Ω 100Ω +5VGA C45 C85 JP10 0.1µF 1nF Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238 Rev. G | Page 35 of 56 03199-091 AD8331/AD8332/AD8334 VR1 +3.3VAVDD ADP3339AKC-3.3 L5 C44 120nH FB 1µF +5V + C22 C21 C31 0.1µF 1nF 0.1µF 31 2 ADCLK IN OUT GND L4 R11 C2 + 120nH FB 100Ω 10µF R10 1 64 JP2 6.3V AGND AVDD 0Ω SHARED R5 OUT C30 REF 33Ω 2 0.1µF 63 V +_A VIN+_A CLK_A TAB IN Y C61 L3 N 18pF 3 62 120nH FB VIN–_A SHARED_REF V –_A IN R14 R6 4.7kΩ 33Ω 4 61 C29 AGND MUX_SELECT R12 R4 0.1µF C17 C18 +3.3VADDIG 1.5kΩ 1.5kΩ R15 0.1µF 1nF 5 60 0Ω C33 L2 AVDD PDWN_A C35 10µF 120nH FB 0.1µF 6.3V 6 59 REFT_A OEB_A + C40 C52 C1 0.1µF 10nF 7 58 0.1µF REFB_A OTR_A OTR_A C36 TP9 0.1µF 8 57 VREF D11_A (MSB) D11_A + VREF C12 C32 10µF 9 56 0.1µF C34 D10_A SENSE D10_A C38 6.3V 10µF 0.1µF 6.3V 10 55 D9_A REFB_B D9_A C39 C57 10µF 10nF 11 54 REFT_B D8_A D8_A C37 +3.3VADDIG 12 53 0.1µF AVDD DRGND C23 C25 C16 C15 1.5kΩ 1.5kΩ 13 0.1µF 1nF 0.1µF 1nF 52 AGND DRVDD R8 33Ω 14 51 V –_B VIN–_B D7_A D7_A IN C62 18pF 15 50 VIN+_B D6_A D6_A V +_B IN R7 +3.3VCLK 16 33Ω 49 AGND D5_A D5_A R18 17 48 S2 C63 499Ω AVDD D4_A D4_A C20 C19 EXT CLOCK 0.1µF 0.1µF 1nF 18 47 R16 CLK_B D3_A D3_A 5kΩ 19 46 R17 R19 DCS D2_A D2_A 49.9Ω 499Ω JP3 JP11 20 45 DFS D1_A D1_A R20 R41 21 44 4.7kΩ 4.7kΩ PDWN_B D0_A D0_A 22 43 OEB_B DNC DNC +3.3VCLK ADCLK 23 42 DNC DNC DNC DNC C47 + C86 10µF 0.1µF 24 41 ADCLK 6.3V DNC DNC DRVDD C11 TP 12 + C13 C14 10µF U5 U5 25 40 1nF 0.1µF EXT D0_B 6.3V 74VHC04 D0_B DRGND 74VHC04 R9 4 1 3 0Ω V OE 31 4 2 26 DD JP4 39 D1_B D1_B OTR_B OTR_B 20MHz 2 3 OUT 27 38 1 D2_B D2_B D11_B (MSB) D11_B GND TP 13 INT DATA 28 2 U5 U5 37 CLK DRGND D10_B D10_B 74VHC04 74VHC04 U6 3 29 5 6 9 8 36 D9_B DRVDD D9_B 1 SG-636PCE 2 JP1 D3_B 30 35 D3_B D8_B D8_B U5 D4_B 31 34 D4_B D7_B D7_B 74VHC04 13 12 D5_B 33 32 D5_B D6_B D6_B SPARES 11 10 +3.3VADDIG U5 C24 C26 74VHC04 1nF 0.1µF Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238 Rev. G | Page 36 of 56 U1 A/D CONVERTER AD9238 03199-092 HEADER UP MALE NO SHROUD HEADER UP MALE NO SHROUD AD8331/AD8332/AD8334 R40 1 20 22Ω DATACLKA G1 U10 VCC +3.3VDVDD + 74VHC541 C3 C28 19 10 2 1 0.1µF 10µF G2 GND 6.3V 22 × 4 18 22 × 4 2 18 4 3 1 8 A1 Y1 RP 9 2 7 RP 1 3 17 2 7 6 5 OTR_A A2 Y2 3 6 4 16 3 6 8 7 D11_A A3 Y3 4 5 4 5 5 15 10 9 D10_A A4 Y4 1 8 18 22 × 4 22 × 4 6 14 12 11 D9_A A5 Y5 RP 10 RP2 2 7 7 13 2 7 14 13 D8_A A6 Y6 3 6 8 12 3 6 16 15 D7_A A7 Y7 4 5 4 5 9 11 18 17 D6_A A8 Y8 18 22 × 4 20 19 RP 3 2 7 22 21 3 6 24 23 +3.3VDVDD 4 5 26 25 1 20 U7 G1 VCC + 18 28 27 22 × 4 74VHC541 C8 C10 C76 19 10 0.1µF 0.1µF 10µF G2 GND RP 4 2 7 30 29 6.3V 8 2 18 1 22 × 4 D5_A A1 Y1 3 6 32 31 RP 11 2 7 3 17 D4_A A2 Y2 4 5 33 34 3 6 4 16 D3_A A3 Y3 36 35 4 5 5 15 D2_A A4 Y4 38 37 1 8 6 14 22 × 4 D1_A A5 Y5 40 39 RP 12 2 7 7 13 D0_A A6 Y6 3 6 8 12 DNC A7 Y7 SAM080UPM 4 5 9 11 DNC A8 Y8 +3.3VDVDD 1 20 42 41 U2 G1 VCC ++ 74VHC541 C27 19 C7 C9 1 22 × 4 8 10 44 43 10µF 0.1µF 0.1µF G2 GND 6.3V RP 13 2 7 2 18 18 22 × 4 46 45 OTR_B A1 Y1 RP 5 3 6 3 2 7 48 47 17 D11_B A2 Y2 4 5 3 6 4 16 50 49 D10_B A3 Y3 4 5 22 × 4 5 15 52 51 1 8 D9_B A4 Y4 RP 14 8 6 14 1 22 × 4 54 53 2 7 D8_B A5 Y5 RP 6 7 2 7 56 55 13 3 6 D7_B A6 Y6 3 6 8 12 58 57 4 5 D6_B A7 Y7 18 4 5 22 × 4 9 11 60 59 D5_B A8 Y8 18 22 × 4 62 61 RP 7 2 7 64 63 +3.3VDVDD 3 6 66 65 1 20 RP 15 G1 VCC U3 + 4 5 68 67 C75 C4 C5 C6 19 74VHC541 10 10µF G2 GND 0.1µF 0.1µF 0.1µF 6.3V 18 70 69 22 × 4 2 7 2 18 D4_B A1 Y1 RP 8 2 7 72 71 3 6 3 17 D3_B A2 Y2 3 6 74 73 4 5 4 16 D2_B A3 Y3 4 5 76 75 1 22 × 4 8 5 15 D1_B A4 Y4 78 77 RP 16 2 7 6 14 D0_B A5 Y5 80 79 3 6 7 13 DNC A6 Y6 4 5 8 12 SAM080UPM DNC A7 Y7 R39 22Ω 9 11 A8 Y8 DATACLK Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238 Rev. G | Page 37 of 56 03199-093 CH1 LNA INPUT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CH2 LNA INPUT 1 48 INH2 COM12 47 2 LMD2 VOH1 CH1 DIFFERENTIAL 46 3 OUTPUT NC VOL1 4 45 LON2 VPS12 5 44 LOP2 VOL2 6 43 CH2 DIFFERENTIAL VIP2 VOH2 OUTPUT 7 42 VIN2 COM12 AD8334 8 41 VPS2 MODE POWER SUPPLY DECOUPLING LOCATED ON WIRING SIDE 9 40 NC VPS3 39 10 COM34 VIN3 11 38 CH3 DIFFERENTIAL VOH3 VIP3 OUTPUT 12 37 VOL3 LOP3 13 36 VPS34 LON3 14 35 VOL4 NC CH4 DIFFERENTIAL OUTPUT 15 34 VOH4 LMD3 16 33 COM34 INH3 NC = NO CONNECT CH3 LNA INPUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CH4 LNA INPUT AD8331/AD8332/AD8334 COM2 COM3 COM1 COM4 INH1 INH4 LMD1 LMD4 NC NC LON1 LON4 LOP1 LOP4 VIP1 VIP4 VIN1 VIN4 VPS1 VPS4 GAIN12 GAIN34 CLMP12 CLMP34 EN12 HILO EN34 VCM4 VCM1 VCM3 VCM2 NC 03199-094 Figure 94. Compact Signal Path and Board Layout for the AD8334 Rev. G | Page 38 of 56 AD8331/AD8332/AD8334 AD8331 EVALUATION BOARD GENERAL DESCRIPTION The AD8331 evaluation board is a platform for testing and evaluating the AD8331 variable gain amplifier (VGA). The board is provided completely assembled and tested; the user simply connects an input signal, VGAIN sources, and a 5 V power supply. The AD8331-EVALZ is lead free and RoHS compliant. Figure 95 is a photograph of the board. USER-SUPPLIED OPTIONAL COMPONENTS As shown in the schematic in Figure 96, the board provides for optional components. The components shown in black are for typical operation, and the components shown in gray are installed at the user’s discretion. As shipped, the LNA input impedance of the AD8331-EVALZ is configured for 50 Ω to accommodate most signal generators and Figure 95. Photograph of AD8331-EVALZ network analyzers. Input impedances up to 6 kΩ are realized by MEASUREMENT SETUP changing the values of RFB and CSH. Refer to the Theory of Operation section for details on this circuit feature. See Table 9 The basic board connection for measuring bandwidth is shown for typical values of input impedance and corresponding in Figure 97. A 5 V, 100 mA minimum power supply and a low components. noise, voltage reference supply for GAIN are required. Table 10 lists jumpers, and Figure 97 shows their functions and positions. Table 9. LNA External Component Values for Common The preferred signal detection method is a differential probe Source Impedances connected to VO, as shown in Figure 97. Single-ended loads can be R (Ω) RFB (Ω, Nearest 1% Value) CSH (pF) IN connected using the board edge SMA connector, VOH. Be sure to 50 274 22 take into account the 25.8 dB attenuation incurred when using the 75 412 12 board in this manner. For connection to an ADC, the 270 Ω series 100 562 8 resistors can be replaced with 0 Ω or other appropriate values. 200 1.13 k 1.2 500 3.01 k None Table 10. Jumper Functions 6 k ∞ None Switch Function LNA_EN Enables the LNA when in the top position The board is designed for 0603 size, surface-mount components. VGA_EN Enables the VGA when in the top position Back-to-back diodes can be installed at Location D3 if desired. W5, W6 Connects the AD8331 outputs to the SMA connectors To evaluate the LNA as a standalone amplifier, install optional GN_SLOPE Left = gain increases with V GAIN SMA connectors LON and LOP and capacitors C1 and C2; Right = gain decreases with VGAIN typical values are 0.1 μF or smaller. At R4 and R8, 0 Ω resistors GN_HI_LO Left = high gain are installed unless capacitive loads larger than 10 pF are connected Right = LO gain to the SMA connectors LON and LOP (such as coaxial cables). In that event, small value resistors (68 Ω to 100 Ω) must be BOARD LAYOUT installed at R4 and R8 to preserve the stability of the amplifier. The evaluation board circuitry uses four conductor layers. The A resistor can be inserted at RCLMP if output clamping is two inner layers are grounded, and all interconnecting circuitry desired. Refer to Table 8 for appropriate values. is located on the outer layers. Figure 99 to Figure 102 illustrate the copper patterns. Rev. G | Page 39 of 56 03199-115 AD8331/AD8332/AD8334 AD8331 EVALUATION BOARD SCHEMATICS GND1 GND2 GND +5V GND3 GND4 C3 1 20 LMD2 COMM 10µF CLMD 10V +5V 0.1µF C INH L1 0.1µF LNA2 120nH FB 19 ENABLE 2 LNA_EN INH ENB PROBE CSH DISABLE CFB 22pF 0.018µF 3D1 RFB INPUT L2 274µF CLAMP BAT64-04 120nH FB ENABLE 3 18 VGA_EN DIODES VPS ENBV DISABLE +5V C6 DUT 0.1µF AD8331ARQ LON C1 R4 4 17 LON COMM LO L3 C2 R8 120nH FB 5 16 LOP VOL C24 R44 R16 LOP 0.1µF W5 100Ω 237Ω T1 1:1 6 15 VO COML VOH C26 R43 R20 0.1µF 100Ω W6 C16 C14 237Ω 0.1µF 0.1µF VOH L4 7 14 120nH FB VIP VPOS +5V L5 C32 120nH FB 0.1µF HI 8 13 GN_HI_LO VIN HILO LO +5V RCLMP DOWN 9 12 GN_SLOPE MODE CLMP UP C17 RCLMP 0.1µF 10 11 GAIN GAIN VCM VCM C34 COMPONENTS IN GRAY ARE C18 1nF OPTIONAL AND USER SUPPLIED. 0.1µF Figure 96. Schematic of the AD8331 Evaluation Board Rev. G | Page 40 of 56 03199-116 + AD8331/AD8332/AD8334 4395A ANALYZER GND 1103 TEKPROBE POWER SUPPLY E3631A POWER SUPPLY +5V GND DIFFERENTIAL PROBE TO VO PINS DP8200 PRECISION VOLTAGE REFERENCE (FOR VGAIN) INSERT JUMPERS W5 AND W6 TO USE OUTPUT TRANSFORMER AND VOH SMA Figure 97. AD8331 Typical Board Test Connections Rev. G | Page 41 of 56 03199-117 AD8331/AD8332/AD8334 AD8331 EVALUATION BOARD PCB LAYERS Figure 98. AD8331-EVALZ Assembly Figure 101. Internal Layer Ground Figure 99. Primary Side Copper Figure 102. Power Plane Figure 103. Top Silkscreen Figure 100. Secondary Side Copper Rev. G | Page 42 of 56 03199-199 03199-200 03199-118 03199-202 03199-201 03199-119 AD8331/AD8332/AD8334 AD8332 EVALUATION BOARD GENERAL DESCRIPTION Table 11. LNA External Component Values for Common The AD8332-EVALZ is a platform for the testing and evaluation of Source Impedances the AD8332 variable gain amplifier (VGA). The board is shipped RIN (Ω) RFB1, RFB2 (Ω Std 1% Value) CSH1, CSH2 (pF) assembled and tested, and users need only connect the signal 50 274 22 and VGAIN sources to a single 5 V power supply. Figure 104 is a 75 412 12 photograph of the component side of the board, and Figure 105 100 562 8 shows the schematic. The AD8332-EVALZ is lead free and 200 1.13 k 1.2 RoHS compliant. 500 3.01 k None 6 k None ∞ SMA connectors, S2, S3, S6, and S7, are provided for access to the LNA outputs or the VGA inputs. If the LNA is used alone, 0.1 μF coupling capacitors can be installed at the C5, C9, C23, and C24 locations. Resistors of 68 Ω to 100 Ω may be required if the load capacitances, as seen by the LNA outputs, are larger than approximately 10 pF. A resistor can be inserted at RCLMP if output clamping is desired. The peak-to-peak clamping level is adjusted by installing one of the standard 1% resistor values listed in Table 8. A high frequency differential probe connected to the 2-pin headers, VOx, is the preferred method to observe a waveform at the VGA output. A typical setup is shown in Figure 106. Single-ended loads can be connected directly via the board edge SMA connectors. Note that the AD8332 output amplifier is buffered with 237 Ω resistors; therefore, be sure to compensate for attenuation if low impedances are connected to the output SMAs. MEASUREMENT SETUP Figure 104.Photograph of the AD8332-EVALZ The basic board connections for measuring bandwidth are shown in Figure 106. A 5 V, 100 mA (minimum) power supply USER-SUPPLIED OPTIONAL COMPONENTS is required, and a low noise voltage reference supply is required The board is built and tested using the components shown in for VGAIN. black in Figure 105. Provisions are made for optional components BOARD LAYOUT (shown in gray) that can be installed for testing at user discretion. The default LNA input impedance is 50 Ω to match various The evaluation board circuitry uses four conductor layers. signal generators and network analyzers. Input impedances up to The two inner layers are power and ground planes, and all 6 kΩ are realized by changing the values of RFBx and CSHx. For interconnecting circuitry is located on the outer layers. Figure 108 reference, Table 11 lists the common input impedance values to Figure 111 illustrate the copper patterns. and corresponding adjustments. The board is designed for 0603 size, surface-mount components. Rev. G | Page 43 of 56 03199-131 AD8331/AD8332/AD8334 EVALUATION BOARD SCHEMATICS +5V GND GND1 GND2 GND3 GND4 + C25 1 28 LMD2 LMD1 10µF C2 C1 0.1µF 0.1µF C4 C3 L1 CSH2 CSH1 L2 LNA2 0.1µF 0.1µF LNA1 120nH FB 22pF 22pF 120nH FB 2 27 INH2 INH1 CFB2 CAL2 CFB1 CAL1 18nF 18nF L8 120nH FB 3 26 +5V VPS2 VPS1 +5VLNA C6 C7 0.1µF 0.1µF +5VLNA RFB1 RFB2 AD8332ARUZ S2 S6 274Ω 274Ω LON1 LON2 C9 C23 4 25 LON2 LON1 R10 R9 W8 W9 5 24 LOP2 LOP1 C5 C24 S7 S3 R12 R11 6 23 LOP2 LOP1 COM2 COM1 C16 C14 C13 C15 0.1µF 0.1µF 0.1µF 0.1µF 7 22 VIP2 VIP1 8 21 VIN2 VIN1 C10 0.1µF 9 20 VCM2 VCM2 VCM1 VCM1 C17 0.1µF +5V 10 19 HI GAIN GAIN HILO W5 LO C8 +5V 1nF TP3 CLAMP 11 18 ENABLE W4 RCLMP ENB DISABLE C20 RCLMP 0.1µF L3 L6 120nH FB 120nH FB 12 17 VOH2 VOH1 C11 C19 T2 R13 R7 R15 R5 0.1µF 0.1µF W12 1:1 237Ω W10 100Ω 237Ω 100Ω T1 VOH2 VOH1 1:1 13 16 W6 W7 VOL2 VOL1 VO2 VO1 C18 R8 R6 R14 R16 0.1µF W13 100Ω 100Ω W11 237Ω 237Ω L5 C12 L4 14 15 120nH FB 0.1µF 120nH FB COMM VPSV L7 120nH FB COMPONENTS IN GRAY ARE +5V OPTIONAL AND USER SUPPLIED. C22 0.1µF Figure 105. Schematic of the AD8332 Evaluation Board Rev. G | Page 44 of 56 03199-096 AD8331/AD8332/AD8334 NETWORK ANALYZER 1103 TEKPROBE POWER SUPPLY VGAIN SUPPLY DIFFERENTIAL PROBE Figure 106. AD8332 Typical Board Test Connections Rev. G | Page 45 of 56 03199-120 AD8331/AD8332/AD8334 AD8332 EVALUATION BOARD PCB LAYERS Figure 107. AD8332-EVALZ Assembly Figure 110. Ground Plane Figure 108. Primary Side Copper Figure 111. Power Plane Figure 109. Secondary Side Copper Figure 112. Component Side Silkscreen Rev. G | Page 46 of 56 03199-099 03199-100 03199-121 03199-102 03199-101 03199-103 AD8331/AD8332/AD8334 AD8334 EVALUATION BOARD GENERAL DESCRIPTION The AD8334-EVALZ is a platform for the testing and evaluation of the AD8334 variable gain amplifier (VGA). The board is shipped assembled and tested, and users need only connect the signal and VGAIN sources and a single 5 V power supply. Figure 113 is a photograph of the board. The AD8334-EVALZ is lead free and RoHS compliant. Figure 113. AD8334-EVALZ Top View Rev. G | Page 47 of 56 03199-122 AD8331/AD8332/AD8334 Viewing Signals CONFIGURING THE INPUT IMPEDANCE The preferred signal detector is a high impedance differential The board is built and tested using the components shown in probe, such as the Tektronix P6247, 1 GHz differential probe, black in Figure 115. Provisions are made for optional components connected to the 2-pin headers (VO1, VO2, VO3, or VO4), as (shown in gray) that can be installed at user discretion. As shown in Figure 116. The low capacitance of this probe has the shipped, the input impedances of the low noise amplifiers (LNAs) least effect on the performance of the device of any detection are configured for 50 Ω to match the output impedances of most method tried. The probe can also be used for monitoring input signal generators and network analyzers. Input impedances up to signals at IN1, IN2, IN3, or IN4. It can be used for probing 6 kΩ can be realized by changing the values of the feedback other circuit nodes; however, be aware that the 200 kΩ input resistors, RFB1, RFB2, RFB3, RFB4, and shunt capacitors, C6, C8, C10, impedance can affect certain circuits. and C12. For reference, Table 12 lists standard values of 1% resistors for some typical values of input impedance. Of course, Differential-to-single-ended transformers are provided for if the user has determined that the source impedance falls single-ended output connections. Note that series resistors are between these values, the feedback resistor value can be provided to protect against accidental output overload should a calculated accordingly. Note that the board is designed to accept 50 Ω load be connected to the connector. Of course, the effect standard surface-mount, size 0603 components. of these resistors is to limit the bandwidth. If the load connected to the SMA is >500 Ω, the 237 Ω series resistors, RX1, RX2, RX3, Table 12. LNA External Component Values for Common RX4, RX5, RX6, RX7, and RX8, can be replaced with 0 Ω values. Source Impedances RIN (Ω) RFB1, RFB2, RFB3, RFB4 (Ω, ±1%) C6, C8, C10, C12 (pF) 50 274 22 75 412 12 100 562 8 200 1.13 k 1.2 500 3.01 k No capacitor 6 k No resistor No capacitor Driving the VGA from an External Source or Using the LNA to Drive an External Load Appropriate components can be installed if the user wants to drive the VGA directly from an external source or to evaluate the LNA output. If the LNA is used to drive off-board loads or cables, small value series resistors (47 Ω to 100 Ω) are recommended for LNA decoupling. These can be installed in the R10, R11, R14, R15, R18, R19, R22, and R23 spaces. Provisions are made for surface-mount SMA connectors that can be used for driving from either direction. If the LNA is not Figure 114. AD8334-EVALZ Assembly used, it is recommended that the capacitors, C16, C17, C21, C22, C26, C27, C31, and C32, be carefully removed to avoid MEASUREMENT SETUP driving the outputs of the LNAs. The basic board connections for measuring bandwidth are Using the Clamp Circuit shown in Figure 116. A 5 V, 200 mA (minimum) power supply is required, and a low noise voltage reference supply is required The board is shipped with no resistors installed in the spaces for VGAIN. provided for clamp-circuit operation. Note that each pair of channels shares a clamp resistor. If the output clamping is BOARD LAYOUT desired, the resistors are installed in R49 and R50. The peak-to- The evaluation board circuitry uses four conductor layers. The peak clamping level is application dependent. two inner layers are ground, and all interconnecting circuitry is located on the outer layers. Figure 117 to Figure 120 illustrate the copper patterns. Rev. G | Page 48 of 56 03199-123 AD8331/AD8332/AD8334 EVALUATION BOARD SCHEMATICS INH1 +5V +5V +5V GND1 GND2 GND3 GND4 GND5 GND6 L9 R49 120 nH 4.02kΩ + 1 LO1 C14 L5 RX1 10 µF 1 L1 120 nH 100Ω 1 R11 EN12 R10 120 nH EN34 IN1 ICR1 C17 E E CFB1 0.1 µF RFB1 RX2 18 nF 12 VO1 C5 100Ω 274Ω C57 0.1 µF D D 0.1 µF C16 CR1 C6 L10 C1 0.1 µF C59 22 pF 120 nH 0.1 µF 0.1 µF 3 L12 120 nH FB 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 +5V C7 L7 CFB2 C8 0.1 µF C75 INH2 120 nH 18 nF 22 pF 0.1 µF 1 48 INH2 COM12 2 47 L11 IN2 ICR2 LMD2 VOH1 120 nH RFB2 3 46 274Ω C2 1 2 NC VOL1 1 RX3 0.1 µF R14 100Ω 0Ω 4 45 CR2 LO N2 VPSV2 1 LO2 5 44 3 LO P2 VOL2 VO2 RX4 1 R15 C22 C21 100Ω 6 43 0Ω 0.1 µF 0.1 µF VIP2 VOH2 L13 7 42 +5V L2 C69 VIN2 COM12 120 nH 120 nH 0.1 µF +5V 8 D VPS2 AD8334 MODE 41 SLOPE L3 9 120 nH L14 +5V VPS3 U 3 NC 40 120 nH C71 10 0.1 µF VIN3 39 COMM34 C26 RX5 11 0.1 µF 100Ω VIP3 38 C27 1 VOH3 R18 12 0.1 µF 1 LO3 LO P3 37 VOL3 VO3 13 LO N3 36 RX6 VPS34 1 100Ω RFB3 R19 14 35 274Ω NC VOL4 L15 C9 CFB3 15 L6 LMD3 34 120 nH 0.1 µF 18 nF INH3 120 nH VOH4 16 INH3 33 COM34 L34 C10 120 nH 22 pF ICR3 C3 IN3 +5V 0.1µF 23 29 12 17 18 19 20 21 22 24 25 26 27 28 30 31 32 C77 0.1 µF C62 C4 L16 C12 0.1 µF 0.1 µF 120 nH C31 22 pF 3 CR3 0.1 µF RFB4 RX7 C11 CFB4 274Ω HI 100Ω +5V 18 nF 0.1 µF C32 IN4 HILO 0.1 µF VO4 L4 CLMP34 LO ICR4 RX8 120 nH L8 1 1 100Ω R22 R23 120 nH 12 R50 4.02kΩ L17 +5V 120 nH 1 LO4 3 CR4 NOTES 1 COMPONENTS IN GRAY ARE OPTIONAL USER SUPPLIED. 2 NC = NO CONNECT. Figure 115. AD8334-EVALZ Schematic Rev. G | Page 49 of 56 COM3 COM2 COM4 COM1 IN H4 IN H1 LMD4 LMD1 NC NC LON4 LON1 LOP4 LOP1 VIP4 VIP1 VIN4 VIN1 C67 0.1 µF VPS4 VPS1 C13 C82 0.1 µF 1nF GAIN34 GAIN34 GAIN12 C53 C8 0 1nF 0.1 µF CLMP12 CLMP34 CLMP12 C55 0.1 µF HILO EN12 C6 4 0.1 µF VCM4 EN34 VCM1 VCM3 3 NC VCM2 03199-124 AD8331/AD8332/AD8334 PROBE PRECISION VOLTAGE POWER REFERENCE (FOR VGAIN) SUPPLY GAIN CONTROL VOLTAGE GND NETWORK ANALYZER +5V DIFFERENTIAL PROBE POWER SUPPLY SIGNAL INPUT GND Figure 116. AD8334 Typical Board Test Connections (One Channel Shown) Rev. G | Page 50 of 56 03199-125 AD8331/AD8332/AD8334 AD8334 EVALUATION BOARD PCB LAYERS Figure 117. AD8334-EVALZ Primary Side Copper Figure 119. AD8334-EVALZ Inner Layer 1Copper Figure 118. AD8334-EVALZ Secondary Side Copper Figure 120. AD8334-EVALZ Inner Layer 2 Copper Rev. G | Page 51 of 56 03199-127 03199-126 03199-128 03199-129 AD8331/AD8332/AD8334 Figure 121. AD8334-EVALZ Component Side Silkscreen Rev. G | Page 52 of 56 03199-130 AD8331/AD8332/AD8334 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 8° 0.75 0.30 0.20 0° 0.60 SEATING COPLANARITY 0.19 0.09 0.45 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 122. 28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28) Dimensions shown in millimeters 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 20 11 0.158 (4.01) 0.154 (3.91) 0.244 (6.20) 0.150 (3.81) 0.236 (5.99) 1 10 0.228 (5.79) 0.010 (0.25) 0.020 (0.51) 0.065 (1.65) 0.069 (1.75) 0.006 (0.15) 0.010 (0.25) 0.049 (1.25) 0.053 (1.35) 0.010 (0.25) 0.041 (1.04) SEATING 8° 0.004 (0.10) REF PLANE 0.025 (0.64) 0.050 (1.27) 0° COPLANARITY 0.012 (0.30) BSC 0.016 (0.41) 0.004 (0.10) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MO-137-AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 123. 20-Lead Shrink Small Outline Package (QSOP) (RQ-20) Dimensions shown in Inches and (millimeters Rev. G | Page 53 of 56 081908-A AD8331/AD8332/AD8334 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 BSC TOP 4.75 EXPOSED 3.25 VIEW BSC SQ PAD 3.10 SQ (BOTTOM VIEW) 2.95 0.50 0.40 17 8 9 16 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 0.30 FUNCTION DESCRIPTIONS COPLANARITY 0.80 0.20 REF SECTION OF THIS DATA SHEET. 0.23 0.08 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 124. 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters 0.30 9.00 0.25 0.60 MAX BSC SQ 0.18 0.60 MAX PIN 1 49 64 INDICATOR 48 1 PIN 1 INDICATOR * 4.85 8.75 TOP EXPOSED PAD 4.70 SQ BSC SQ VIEW (BOTTOM VIEW) 4.55 0.50 33 16 0.40 32 17 0.30 7.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS SEATING SECTION OF THIS DATA SHEET. 0.50 BSC 0.20 REF PLANE * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION Figure 125. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 9 mm × 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters Rev. G | Page 54 of 56 011708-A 082908-B AD8331/AD8332/AD8334 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8331ARQ –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQ-REEL –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQ-REEL7 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQZ –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQZ-RL –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331ARQZ-R7 –40°C to +85°C 20-Lead Shrink Small Outline Package (QSOP) RQ-20 AD8331-EVALZ Evaluation Board with AD8331ARQ AD8332ACP-R2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACP-REEL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACP-REEL7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACPZ-R2 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACPZ-R7 –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ACPZ-RL –40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-2 AD8332ARU –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARU-REEL –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARU-REEL7 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARUZ –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARUZ-R7 –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332ARUZ-RL –40°C to +85°C 28-Lead Thin Shrink Small Outline Package (TSSOP) RU-28 AD8332-EVALZ Evaluation Board with AD8332ARU AD8334ACPZ –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD8334ACPZ-REEL –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD8334ACPZ-REEL7 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1 AD8334-EVALZ Evaluation Board with AD8334ACP 1 Z = RoHS Compliant Part. Rev. G | Page 55 of 56 AD8331/AD8332/AD8334 NOTES ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03199-0-10/10(G) Rev. G | Page 56 of 56