ANALOG DEVICES AD8330

Low Cost, DC to 150 MHz Variable Gain Amplifier AD8330 FUNCTIONAL BLOCK DIAGRAM FEATURES 16 15 14 13 ENBL OFST VPOS CNTR Fully differential signal path, also used with single-sided signals 1 VPSI VPSO 12 CM AND Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs BIAS AND V OFFSET REF CONTROL Differential R = 1 kΩ; R (each output) 75 Ω IN OUT Automatic offset compensation (optional) OPHI INHI 2 11 Linear-in-dB and linear-in-magnitude gain modes 0 dB to 50 dB, for 0 V < V < 1.5 V (30 mV/dB) OUTPUT DBS VGA CORE STAGES Inverted gain mode: 50 dB to 0 dB at −30 mV/dB OPLO INLO 3 10 ×0.03 to ×10 nominal gain for 15 mV < V < 5 V MAG Constant bandwidth: 150 MHz at all gains Low noise: 5 nV/√Hz typical at maximum gain MODE CMOP 9 OUTPUT 4 GAIN INTERFACE Low distortion: ≤−62 dBc typical CONTROL Low power: 20 mA typical at V of 2.7 V to 6 V S VDBS CMGN COMM VMAG Available in a space-saving, 3 mm × 3 mm LFCSP package 5 6 7 8 Figure 1. APPLICATIONS Pre-ADC signal conditioning 75 Ω cable driving adjust AGC amplifiers GENERAL DESCRIPTION The AD8330 is a wideband variable gain amplifier for applications Using VMAG, the basic 0 dB to 50 dB range can be reposi- requiring a fully differential signal path, low noise, well-defined tioned to any value from 20 dB higher (that is, 20 dB to 70 dB) gain, and moderately low distortion, from dc to 150 MHz. The to at least 30 dB lower (that is, –30 dB to +20 dB) to suit the input pins can also be driven from a single-ended source. The application, thereby providing an unprecedented gain range of peak differential input is ±2 V, allowing sine wave operation at over 100 dB. A unique aspect of the AD8330 is that its bandwidth 1 V rms with generous headroom. The output pins can drive and pulse response are essentially constant for all gains, over both single-sided loads essentially rail-to-rail. The differential output the basic 50 dB linear-in-dB range, but also when using the resistance is 150 Ω. The output swing is a linear function of the linear-in-magnitude function. The exceptional stability of the voltage applied to the VMAG pin that internally defaults to 0.5 V, HF response over the gain range is of particular value in those providing a peak output of ±2 V. This can be raised to 10 V p-p, VGA applications where it is essential to maintain accurate gain limited by the supply voltage. law-conformance at high frequencies. The basic gain function is linear-in-dB, controlled by the voltage An external capacitor at Pin OFST sets the high-pass corner of applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for an offset reduction loop, whose frequency can be as low as 5 Hz. control voltages between 0 V and 1.5 V—a slope of 30 mV/dB. When this pin is grounded, the signal path becomes dc-coupled. The gain linearity is typically within ±0.1 dB. By changing the When used to drive an ADC, an external common-mode control voltage at Pin CNTR can be driven to within 0.5 V of either ground logic level on Pin MODE, the gain decreases over the same range, with an opposite slope. A second gain control port is provided at or VS to accommodate a wide variety of requirements. By default, the VMAG pin and allows the user to vary the numeric gain from the two outputs are positioned at the midpoint of the supply, VS/2. a factor of 0.03 to 10. All the parameters of the AD8330 have low Other features, such as two levels of power-down (fully off and a sensitivities to temperature and supply voltages. hibernate mode), further extend the practical value of this excep- tionally versatile VGA. The AD8330 is available in 16-lead LFCSP and 16-lead QSOP packages and is specified for operation from −40°C to +85°C. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 03217-001 AD8330 TABLE OF CONTENTS Features .............................................................................................. 1  Applications Information .............................................................. 25  Applications ....................................................................................... 1  ADC Driving ............................................................................... 25  Functional Block Diagram .............................................................. 1  Simple AGC Amplifier .............................................................. 25  General Description ......................................................................... 1  Wide Range True RMS Voltmeter ............................................ 26  Revision History ............................................................................... 2  Evaluation Board ............................................................................ 28  Specif ica t ions ..................................................................................... 3  General Description ................................................................... 28  Absolute Maximum Ratings ............................................................ 5  Basic Operation .......................................................................... 28  ESD Caution .................................................................................. 5  Options ........................................................................................ 29  Pin Configurations and Function Descriptions ........................... 6  Measurement Setup.................................................................... 29  Typical Performance Characteristics ............................................. 7  AD8330-EVALZ Board Design ................................................ 29  Theory of Operation ...................................................................... 14  Outline Dimensions ....................................................................... 31  Circuit Description..................................................................... 14  Ordering Guide .......................................................................... 32  Using the AD8330 ...................................................................... 20  REVISION HISTORY 3/10—Rev. D to Rev. E 10/04—Rev. A to Rev. B Changes to Figure 2 and Table 3 ..................................................... 6 Changes to Absolute Maximum Ratings ........................................ 4 Changes to Figure 69 ...................................................................... 28 Changes to Ordering Guide ............................................................. 4 Changes to Figure 71 ...................................................................... 29 Change to TPC 14 ............................................................................. 8 Changes to Figure 72 ...................................................................... 30 Note added to CP-16 Package ....................................................... 26 Deleted Table 7 ................................................................................ 31 4/03—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 32 Updated Outline Dimensions ....................................................... 26 1/08—Rev. C to Rev. D Changes to Figure 28 and Figure 29 ............................................. 12 Added Evaluation Board Section ................................................. 28 Changes to Ordering Guide .......................................................... 33 6/06—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Figure 1 .......................................................................... 1 Deleted Figure 2 ................................................................................ 1 Changes to Specifications Section .................................................. 3 Change to Absolute Maximum Ratings ......................................... 5 Changes to Typical Performance Characteristics Summary Statement ......................................................................... 7 Changes to Figure 14 and Figure 15 ............................................... 8 Changes to Figure 31 and Figure 32 ............................................. 11 Updated Outline Dimensions ....................................................... 28 Rev. E | Page 2 of 32 AD8330 SPECIFICATIONS VS = 5 V, TA = 25°C, CL = 12 pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = Pin VMAG open circuit (0.5 V), VOFST = 0 V, differential operation, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit INPUT INTERFACE Pin INHI, Pin INLO Full-Scale Input VDBS = 0 V, differential drive ±1.4 ±2 V VDBS = 1.5 V ±4.5 ±6.3 mV Input Resistance Pin-to-pin 800 1 k 1.2 k Ω Input Capacitance Either pin to COMM 4 pF Voltage Noise Spectral Density f = 1 MHz, V = 1.5 V; inputs ac-shorted 5 nV/√Hz DBS Common-Mode Voltage Level 3.0 V Input Offset Pin OFST connected to Pin COMM 1 mV rms Drift 2 μV/°C 1 Permissible CM Range 0 VS V Common-Mode AC Rejection f = 1 MHz, 0.1 V rms −60 dB f = 50 MHz −55 dB OUTPUT INTERFACE Pin OPHI, Pin OPLO Small Signal –3 dB Bandwidth 0 V < V < 1.5 V 150 MHz DBS Peak Slew Rate V = 0 V 1500 V/μs DBS Peak-to-Peak Output Swing ±1.8 ±2 ±2.2 V VMAG ≥ 2 V (peaks are supply limited) ±4 ±4.5 V Common-Mode Voltage Pin CNTR O/C 2.4 2.5 2.6 V Voltage Noise Spectral Density f = 1 MHz, V = 0 V 62 nV/√Hz DBS Differential Output Impedance Pin-to-pin 120 150 180 Ω 2 HD2 V = 1 V p-p, f = 10 MHz, R = 1 kΩ −62 dBc OUT L 2 HD3 VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ −53 dBc OUTPUT OFFSET CONTROL Pin OFST AC-Coupled Offset CHPF on Pin OFST (0 V < VDBS < 1.5 V) 10 mV rms High-Pass Corner Frequency CHPF = 3.3 nF, from OFST to CNTR (scales as 1/CHPF) 100 kHz COMMON-MODE CONTROL Pin CNTR Usable Voltage Range 0.5 4.5 V Input Resistance From Pin CNTR to VS/2 4 kΩ DECIBEL GAIN CONTROL VDBS, CMGN, and MODE pins Normal Voltage Range CMGN connected to COMM 0 to 1.5 V Elevated Range CMGN O/C (VCMGN rises to 0.2 V) 0.2 to 1.7 V Gain Scaling Mode high or low 27 30 33 mV/dB Gain Linearity Error 0.3 V ≤ V ≤ 1.2 V −0.35 ±0.1 +0.35 dB DBS Absolute Gain Error V = 0 V −2 ±0.5 +2 dB DBS Bias Current Flows out of Pin VDBS 100 nA Incremental Resistance 100 MΩ Gain Settling Time to 0.5 dB Error VDBS stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V 250 ns Mode Up/Down Pin MODE Mode Up Logic Level Gain increases with V , MODE = O/C 1.5 V DBS Mode Down Logic Level Gain decreases with V 0.5 V DBS LINEAR GAIN INTERFACE Pin VMAG, Pin CMGN Peak Output Scaling, Gain vs. V See the Circuit Description section 3.8 4.0 4.2 V/V MAG Gain Multiplication Factor vs. V Gain is nominal when V = 0.5 V ×2 MAG MAG Usable Input Range 0 5 V Default Voltage VMAG O/C 0.48 0.5 0.52 V Incremental Resistance 4 kΩ Bandwidth For V ≥ 0.1 V 150 MHz MAG Rev. E | Page 3 of 32 AD8330 Parameter Conditions Min Typ Max Unit CHIP ENABLE Pin ENBL Logic Voltage for Full Shutdown 0.5 V Logic Voltage for Hibernate Mode Output pins remain at CNTR 1.3 1.5 1.7 V Logic Voltage for Full Operation 2.3 V Current in Full Shutdown 20 100 μA Current in Hibernate Mode 1.5 mA 3 Minimum Time Delay 1.7 μs POWER SUPPLY VPSI, VPOS, VPSO, COMM, and CMOP pins Supply Voltage 2.7 6 V Quiescent Current VDBS = 0.75 V 20 27 mA 1 The use of an input common-mode voltage significantly different from the internally set value is not recommended due to its effect on noise performance. See Figure 56. 2 See the Typical Performance Characteristics section for more detailed information on distortion in a variety of operating conditions. 3 For minimum sized coupling capacitors. Rev. E | Page 4 of 32 AD8330 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Supply Voltage 6 V other conditions above those indicated in the operational Power Dissipation 1 section of this specification is not implied. Exposure to absolute RQ-16 Package 0.62 W maximum rating conditions for extended periods may affect CP-16-3 Package 1.67 W device reliability. Input Voltage at Any Pin VS + 200 mV Storage Temperature Range −65°C to +150°C ESD CAUTION θ JA RQ-16 Package 105.4°C/W CP-16-3 Package 60°C/W θJC RQ-16 Package 39°C/W Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 60 sec) 300°C 1 Four-Layer JEDEC Board (252P). Rev. E | Page 5 of 32 AD8330 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 12 VPSO VPSI 1 INHI 2 11 OPHI AD8330 TOP VIEW INLO 3 10 OPLO (Not to Scale) OFST 1 16 VPOS MODE 4 9CMOP ENBL 2 15 CNTR VPSI 3 AD8330 14 VPSO INHI 4 TOP VIEW 13 OPHI (Not to Scale) INLO 5 12 OPLO NOTES MODE 6 11 CMOP 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. VDBS 7 10 VMAG FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED CMGN 8 9 COMM THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 2. 16-Lead LFCSP Pin Configuration Figure 3. 16-Lead QSOP Pin Configuration Table 3. 16-Lead LFCSP Pin Function Descriptions Table 4. 16-Lead QSOP Pin Function Descriptions Pin No. Mnemonic Description Pin No. Mnemonic Description 1 VPSI Positive Supply for Input Stages. 1 OFST Used in Offset Control Modes. 2 INHI Differential Signal Input, Positive 2 ENBL Power Enable, Active High. Polarity. 3 VPSI Positive Supply for Input Stages. 3 INLO Differential Signal Input, Negative 4 INHI Differential Signal Input, Positive Polarity. Polarity. 4 MODE Logic Input: Selects Gain Slope. 5 INLO Differential Signal Input, Negative High = gain up vs. V . DBS Polarity. 5 VDBS Input for Linear-in-dB Gain Control 6 MODE Logic Input: Selects Gain Slope. Voltage, VDBS. High = gain up vs. VDBS. 6 CMGN Common Baseline for Gain Control 7 VDBS Input for linear-in-dB Gain Control Interfaces. Voltage, V . DBS 7 COMM Ground for Input and Gain Control Bias 8 CMGN Common Baseline for Gain Control Circuitry. Interfaces. 8 VMAG Input for Gain/Amplitude Control, VMAG. 9 COMM Ground for Input and Gain Control Bias 9 CMOP Ground for Output Stages. Circuitry. 10 OPLO Differential Signal Output, Negative 10 VMAG Input for Gain/Amplitude Control, VMAG. Polarity. 11 CMOP Ground for Output Stages. 11 OPHI Differential Signal Output, Positive 12 OPLO Differential Signal Output, Negative Polarity. Polarity. 12 VPSO Positive Supply for Output Stages. 13 OPHI Differential Signal Output, Positive 13 CNTR Common-Mode Output Voltage Control. Polarity. 14 VPOS Positive Supply for Inner Stages. 14 VPSO Positive Supply for Output Stages. 15 OFST Used in Offset Control Modes. 15 CNTR Common-Mode Output Voltage Control. 16 ENBL Power Enable, Active High. 16 VPOS Positive Supply for Inner Stages. EPAD Exposed Pad. It is recommended that the pad be soldered to the ground plane. Rev. E | Page 6 of 32 03217-003 03217-004 VDBS 5 16 ENBL CMGN 6 15 OFST COMM 7 14 VPOS 13 CNTR VMAG 8 AD8330 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, CL = 12 pF, VDBS = 0.75 V, VMODE = high (or O/C) VMAG = O/C (0.5 V), RL = ∞, VOFST = 0, differential operation, unless otherwise noted. 50 2.0 NORMALIZED @V = 0.75V DBS 45 1.5 LO MODE HI MODE 40 1.0 35 50MHz 100MHz 0.5 10MHz, 50MHz 30 25 0 20 –0.5 1MHz 1MHz 15 –1.0 10 10MHz 100MHz –1.5 5 0 –2.0 0 0.25 0.50 0.75 1.00 1.25 1.50 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V (V) V (V) DBS DBS Figure 4. Gain vs. VDBS Figure 7. Gain Error vs. VDBS at Various Frequencies 10 20 2340 UNITS MODE = LO 9 15 8 10 7 5 6 0 5 –30.6 –30.5 –30.4 –30.3 –30.2 –30.1 –30.0 –29.9 –29.8 –29.7 –29.6 –29.5 –29.4 –29.3 –29.2 –29.1 –29.0 20 4 MODE = HI 15 3 10 2 5 1 0 0 29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 30.6 0 1 2 3 4 5 GAIN SCALING (mV/dB) V (V) MAG Figure 8. Gain Slope Histogram Figure 5. Linear Gain Multiplication Factor vs. VMAG 60 1.0 V = 1.5V DBS 50 0.8 1.2V 40 0.6 0.9V 30 0.4 0.6V 20 0.2 0.3V T = –40°C 10 0 0V 0 –0.2 –10 T = +85°C –0.4 –20 T = +25°C –0.6 –30 –0.8 –40 –1.0 –50 06 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1. 100k 1M 10M 100M 500M FREQUENCY (Hz) V (V) DBS Figure 9. Frequency Response in 10 dB Steps for Various Values of V Figure 6. Gain Linearity Error Normalized at 25°C vs. VDBS, DBS at Three Temperatures, f = 1 MHz Rev. E | Page 7 of 32 GAIN ERROR (dB) GAIN MULTIPLICATION FACTOR GAIN (dB) 03217-006 03217-005 03217-007 GAIN (dB) GAIN ERROR (dB) % OF UNITS 03217-009 03217-010 03217-008 AD8330 50 25 V = 4.8V MAG 1048 UNITS 40 ENABLE MODE 1.52V 20 30 0.48V 20 0.15V 15 10 0.048V 0 0.015V 10 –10 –20 5 –30 0 –40 100k 1M 10M 100M 500M FREQUENCY (Hz) DIFFERENTIAL OFFSET (mV) Figure 10. Frequency Response for Various Values of VMAG, Figure 13. Differential Input Offset Histogram VDBS = 0.75 V 10 10 V = 0.1V DBS 0 8 –10 –20 6 –30 –40 4 –50 –60 2 –70 –80 0 –90 100k 1M 10M 100M 300M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Group Delay vs. Frequency Figure 14. Output Balance Error vs. Frequency for a Representative Part 200 0 190 –1 180 –2 170 T = –40°C 160 –3 150 –4 T = +25°C 140 130 –5 120 –6 110 T = +85°C –7 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 100k 1M 10M 100M 300M V (V) FREQUENCY (Hz) DBS Figure 12. Differential Output Offset vs. VDBS for Three Temperatures, Figure 15. Output Impedance vs. Frequency for a Representative Part Rev. E | Page 8 of 32 GAIN (dB) GROUP DELAY (ns) OFFSETVOLTAGE (mV) 03217-013 03217-012 03217-011 OUTPUT IMPEDANCE (Ω) OUTPUT BALANCE ERROR (dB) % OF UNITS –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 03217-014 03217-016 03217-015 AD8330 6000 90 V DBS = 1.5V V = 1.5V OFST: ENABLED DBS 80 DISABLED f = 1MHz V = 0.75V DBS 5000 70 60 4000 50 V = 0V 3000 DBS 40 30 2000 20 10 1000 0 0 –10 001 .5 1.0.5 2.0 2.5 50k 100k 1M 10M 100M V (V) FREQUENCY (Hz) MAG Figure 16. CMRR vs. Frequency Figure 19. Output Referred Noise vs. VMAG 80 1500 V = 0.5V MAG T = +85°C f = 1MHz f = 1MHz V = 0.5V MAG 70 T = +25°C 1200 60 T = +85°C 50 900 40 T = +25°C T = –40°C 600 30 T = –40°C 20 300 10 0 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V (V) V (V) DBS DBS Figure 17. Output Referred Noise vs. VDBS for Three Temperatures Figure 20. Input Referred Noise vs. V for Three Temperatures DBS 700 180 f = 1MHz f = 1MHz 160 600 140 500 V = 0.125V MAG 120 400 100 V = 0.5V MAG 80 300 60 200 40 100 20 V = 2V MAG 0 0 001 .5 1.0.5 2.0 2.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V (V) V (V) DBS MAG Figure 18. Output Referred Noise vs. V MAG, Figure 21. Input Referred Noise vs. V for Three Values of V DBS MAG V = 0.75 V DBS Rev. E | Page 9 of 32 CMRR (dB) NOISE (nV/√Hz) NOISE (nV/√Hz) 03217-019 03217-018 03217-017 NOISE (nV/√Hz) NOISE (nV/√Hz) NOISE (nV/√Hz) 03217-022 03217-021 03217-020 AD8330 7 0 V = 1.5V DBS f = 10MHz –10 6 –20 5 –30 4 –40 HD3, R = 1kΩ L 3 –50 2 –60 HD2, R = 1kΩ L 1 –70 0 –80 0 0.3 0.6 0.9 1.2 1.5 100k 1M 10M 100M V (V p-p) OUT FREQUENCY (Hz) Figure 25. Harmonic Distortion vs. VOUT , VMAG = 0.5 V Figure 22. Input Referred Noise vs. Frequency 0 0 V = 0.75V DBS f = 10MHz V = 1V p-p OUT –10 –10 R = 1kΩ L –20 –20 1 HD2 AND HD3, R = 150Ω L –30 –30 –40 –40 HD3 HD3, R = 1kΩ L –50 –50 HD2 –60 –60 HD2, R = 1kΩ L –70 –70 1 OUTPUT AMPLITUDE HARD LIMITED –80 –80 0 123 4 5 100k 1M 10M 100M V (V p-p) OUT FREQUENCY (Hz) Figure 26. Harmonic Distortion vs. VOUT , VMAG = 2.0 V Figure 23. Harmonic Distortion vs. Frequency 0 0 V = 0.75V DBS f = 10MHz V = 1V p-p V = 1V p-p OUT OUT –10 –10 R = 1kΩ R = 1kΩ L L –20 –20 –30 –30 –40 HD3 –40 HD3 –50 –50 –60 HD2 HD2 –60 –70 –70 –80 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 C (pF) V (V) LOAD DBS Figure 24. Harmonic Distortion vs. C Figure 27. Harmonic Distortion vs. VDBS LOAD Rev. E | Page 10 of 32 DISTORTION (dBc) DISTORTION (dBc) NOISE (nV/√Hz) 03217-023 03217-025 03217-024 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 03217-028 03217-027 03217-026 AD8330 10 23 30 33 f = 10MHz f = 10MHz 0 13 25 28 –10 3 20 23 f = 50MHz –20 –7 15 18 –30 –17 10 13 8 5 –40 –27 0 3 –50 –37 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V (V) DBS V (V) DBS Figure 31. OIP3 vs. V DBS Figure 28. Input V1dB Compression vs. VDBS 20 33 40 43 f = 10MHz 35 38 10 23 f = 10MHz 30 33 0 13 25 28 20 23 –10 3 f = 50MHz 15 18 –20 –7 10 13 –30 –17 5 8 3 0 –40 –27 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 1 2 3 4 5 6 0.2 V (V) V (V) MAG MAG Figure 32. OIP3 vs. V Figure 29. Output V1dB Compression vs. VMAG MAG 1.5 0 V = 0.75V DBS V = 1V p-p –10 OUT 1.0 –20 0.5 –30 V = 0V DBS –40 0 –50 –0.5 –60 –70 –1.0 –80 –1.5 –90 1M 10M 100M –50 –25 0 255075 100 TIME (ns) FREQUENCY (Hz) Figure 33. Full-Scale Transient Response, V = 0 V Figure 30. IMD3 Distortion vs. Frequency DBS Rev. E | Page 11 of 32 INPUT V1dB COMPRESSION (dBV rms) INPUT V1dB COMPRESSION (dBV rms) IMD3 (dBc) P1dB (REF 50Ω) 03217-031 P1dB (REF 50Ω) 03217-029 03217-030 V (V) OUT OIP3 (dBV rms) OIP3 (dBV rms) OIP3 (dBm) 03217-033 OIP3 (dBm) 03217-032 03217-034 AD8330 1.5 1V 1.0 0.5 V = 0.75V DBS 0 –0.5 –1.0 1V 400ns –1.5 –50 –25 0 255075 100 TIME (ns) Figure 34. Full-Scale Transient Response, V = 0.75 V, Figure 37. VDBS Interface Response, Top: VDBS, Bottom: VOUT DBS f = 1 MHz, V = 2 V p-p OUT 1.5 2V 1.0 0.5 V = 1.5V DBS 0 –0.5 –1.0 1mV 400ns –1.5 –50 –25 0 255075 100 TIME (ns) Figure 35. Full-Scale Transient Response, V = 1.5 V, Figure 38. V Interface Response, Top: V , Bottom: V DBS MAG MAG OUT f = 1 MHz, V = 2 V p-p OUT 500mV 1V V = 5V MAG C = 12pF L V = 0.5V MAG C = 54pF L C = 24pF L V = 0.05V MAG 12.5ns 100mV 12.5ns Figure 36. Transient Response vs. Various Load Capacitances, G = 25 dB Figure 39. Transient Response vs. VMAG Rev. E | Page 12 of 32 V (V) V (V) OUT OUT 03217-037 03217-036 03217-035 03217-040 03217-039 03217-038 AD8330 26 4.00V OUTPUT 24 22 +85°C 20 +25°C INPUT 18 –40°C 16 50mV 25ns 14 0 0.20.40.60.81.01.21.4 1.6 V (V) DBS Figure 40. Overdrive Response, V = 1.5 V, V = 0.5 V, 18.5 dB Overdrive Figure 43. Supply Current vs. V at Three Temperatures DBS MAG DBS 2V 3.125V 2.5V 1.875V 3.125V 2.5V 1.875V 1V 400ns 100ns Figure 41. ENBL Interface Response. Top: VENBL; Bottom: VOUT, f = 10 MHz Figure 44. CNTR Transient Response, Top: Input to CNTR, Bottom: VOUT Single-Ended –10 V = 0.75V DBS –20 –30 V –40 PSI –50 –60 V PSO V POS –70 –80 –90 –100 –110 1M 10M 100M 200M FREQUENCY (Hz) Figure 42. PSRR vs. Frequency Rev. E | Page 13 of 32 PSRR (dB) 03217-041 03217-042 03217-043 SUPPLY CURRENT (mA) 03217-045 03217-044 AD8330 OUTPUT IS xl INPUT IS xl G = I /I D N D N LOOP THEORY OF OPERATION AMPLIFIER (1–x) I (1–x) I (1–x) I (1+x) I D D N N CIRCUIT DESCRIPTION 2 2 2 2 +– Many monolithic variable gain amplifiers use techniques that share common principles that are broadly classified as translinear. Q1 Q4 This term refers to circuit cells whose functions depend directly Q2 Q3 on the very predictable properties of bipolar junction transistors, notably the linear dependence of their transconductance on collec- tor current. Since the discovery of these cells in 1967, and their I DENOMINATOR NUMERATOR I D N BIAS CURRENT BIAS CURRENT commercial exploitation in products developed during the early Figure 45. Basic Core 1970s, accurate wide bandwidth analog multipliers, dividers, and variable gain amplifiers have invariably employed translinear EV NBL OFSTPOS CNTR principles. VPSO VPSI BIAS AND CM MODE AND Although these techniques are well understood, the realization V REF OFFSET CONTROL of a high performance variable gain amplifier (VGA) requires special technologies and attention to many subtle details in INHI OPHI AD8330 its design. The AD8330 is fabricated on a proprietary silicon- on-insulator, complementary bipolar IC process and draws OUTPUT STAGES on decades of experience in developing many leading edge products using translinear principles to provide an unprecedented INLO VGA CORE OPLO level of versatility. Figure 45 shows a basic representative cell comprising just four OUTPUT MODE GAIN INTERFACE CONTROL CMOP transistors. This, or a very closely related form, is at the heart of most translinear multipliers, dividers, and VGAs. The key VDBS CMGN COMM VMAG concepts are as follows: Figure 46. Block Schematic First, the ratio of the currents in the left-hand and right-hand pairs of transistors is identical, represented by the modulation Overall Structure factor, x, with values between −1 and +1. Second, the input Figure 46 shows a block schematic of the AD8330 locating the signal is arranged to modulate the fixed tail current, I , to cause D key sections. More detailed descriptions of its structure and the variable value of x, introduced in the left-hand pair, to be features are provided throughout the Theory of Operation replicated in the right-hand pair, and, thus, generate the output section; however, Figure 46 provides a general overview of its by modulating its nominally fixed tail current, IN. Third, the capabilities. current gain of this cell is exactly G = IN/ID over many decades The VGA core contains a more elaborate version of the cell of variable bias current. shown in Figure 45. The current, ID, is controlled exponentially In practice, the realization of the full potential of this circuit (linear-in-decibels) through the decibel gain interface at involves many other factors, but these three elementary ideas Pin VDBS and its local common, Pin CMGN. The gain span remain essential. (that is, the decibel difference between maximum and minimum values) provided by this control function is slightly By varying IN, the overall function is that of a two-quadrant more than 50 dB. The absolute gain from input to output is a analog multiplier, exhibiting a linear relationship to both the function of source and load impedance, and depends on the signal modulation factor (x) and this numerator current. On voltage on a second gain control pin (VMAG), explained in the the other hand, by varying ID, a two-quadrant analog divider Normal Operating Conditions section. is realized, having a hyperbolic gain function with respect to the input factor, x, controlled by this denominator current. The AD8330 exploits both modes of operation. However, because a hyperbolic gain function is generally of less value than one in which the decibel gain is a linear function of a control input, a special interface is included to provide either increasing or decreasing exponential control of ID. Rev. E | Page 14 of 32 03217-047 03217-046 AD8330 Normal Operating Conditions The differential impedance measured between OPHI and OPLO is 150 Ω ± 20%. It follows that both the gain and the To minimize confusion, normal operating conditions are full-scale voltage swing depend on the load impedance; both are defined as follows: nominally halved when this is also 150 Ω. A fixed impedance The input pins are voltage driven (the source impedance is output interface, rather than an op amp style voltage-mode assumed to be zero). output, is preferable in high speed applications because the The output pins are open circuited (the load impedance is effects of complex reactive loads on the gain and phase can be assumed to be infinite). better controlled. The top end of the AD8330 ac response is Pin VMAG is unconnected setting up the output bias current optimally flat for a 12 pF load on each pin, but this is not (I in the four-transistor gain cell) to its nominal value. N critical, and the system remains stable for any value of load capacitance including zero. Pin CMGN is grounded. MODE is either tied to a logic high or left unconnected, to set Another useful feature of this VGA in connection with the the up gain mode. driving of an ADC is that the peak output magnitude can be precisely controlled by the voltage on Pin VMAG. Usually, this The effects of other operating conditions are considered voltage is internally preset to 500 mV, and the peak differential separately. unloaded output swing is ±2 V ± 3%. However, any voltage Throughout this data sheet, the end-to-end voltage gain for the from zero to at least 5 V can be applied to this pin to alter the normal operating conditions is referred to as the basic gain. peak output in an exactly proportional way. Because either Under these conditions, it runs from 0 dB when V = 0 V DBS output pin can swing rail-to-rail, which in practice means down (where this voltage is more exactly measured with reference to at least 0.35 V and to within the same voltage below the to Pin CMGN, which is not necessarily tied to ground) up to supply, the peak-to-peak output between these pins can be as 50 dB for VDBS = 1.5 V. The gain does not fold over when the high as 10 V using VS = 6 V. VDBS pin is driven below ground or above its nominal full- CM MODE scale value. FEEDBACK VPSI VPSO The input is accepted at the INHI/INLO differential port. These TRANSIMPEDANCE OUTPUT STAGE pins are internally biased to roughly the midpoint of the supply, INHI 500Ω OPHI VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0 V, and 1.5 V for R = 150Ω ΔV = 0 ΔV = 0 OUT VS = 3 V), but the AD8330 is able to accept a forced common- INLO OPLO mode value, from zero to VS, with certain limitations. This 500Ω O/P CM-MODE interface provides good common-mode rejection up to high NORMALLY AT V /2 P frequencies (see Figure 16) and, thus, can be driven in either a CNTR single-sided or differential manner. However, operation using a LINEAR-IN-dB differential drive is preferable, and this is assumed in the INTERFACE MAGNITUDE 100µA INTERFACE specifications, unless otherwise stated. MODE VMAG The pin-to-pin input resistance is specified as 950 Ω ± 20%. The VDBS driving-point impedance of the signal source can range from V MAG V DBS 12.65µA–4mA OR zero up to values considerably in excess of this resistance, with a 4mA–12.65µA 5kΩ COMM COMM corresponding variation in noise figure (see Figure 53). In most cases, the input is coupled via two capacitors, chosen to provide Figure 47. Schematic of Key Components adequate low frequency transmission. This results in the minimum Linear-in-dB Gain Control (V ) DBS input noise that increases when some other common-mode volt- All Analog Devices, Inc., VGAs featuring a linear-in-dB gain age is forced onto these pins. The short-circuit, input-referred law, such as the X-AMP® family, provide exact, constant gain noise at maximum gain is approximately 5 nV/√Hz. scaling over the fully specified gain range, and the deviation Output Pin OPHI and Output Pin OPLO operate at a common- from the ideal response is within a small fraction of a dB. For mode voltage at the midpoint of the supply, VS/2, within a few the AD8330, the scaling of both of its gain interfaces is millivolts. This ensures that an analog-to-digital converter substantially independent of process, supply voltage, or (ADC) attached to these outputs operates within the often temperature. The basic gain, G , is simply B narrow range permitted by their design. When a common- V DBS mode voltage other than V /2 is required at this interface, it can S G() dB = (1) B 30 mV easily be forced by applying an externally provided voltage to the output centering pin, CNTR. This voltage can run from zero where VDBS is in volts. to the full supply, though the use of such extreme values leaves Alternatively, this can be expressed as a numerical gain only a small range for the differential output signal swing. magnitude Rev. E | Page 15 of 32 03217-048 AD8330 V DBS V MAG G = G 0.6 V (3) T BN G = 10 (2) BN 0.5 V The gain can be increased or decreased by changing the voltage, Using this to calculate the output voltage, VMAG, applied to the VMAG pin. The internally set default value V = 2 × G × V × V (4) OUT IN IN MAG of 500 mV is derived from the same band gap reference that determines the decibel scaling. The tolerance on this voltage, from which it is apparent that the AD8330 implements a linear, and mismatches in certain on-chip resistors, cause small gain two-quadrant multiplier with a bipolar VIN and a unipolar VMAG. errors (see the Specifications section). Though not all appli- Because the AD8330 is a dc-coupled system, it can be used in cations of VGAs demand accurate gain calibration, it is a many applications where a wideband two-quadrant multiplier valuable asset in many situations, for example, in reducing function is required, from dc up to about 100 MHz from either input (V or V ). design tolerances. IN MAG As V is varied, so also is the peak output magnitude, up to a Figure 47 shows the core circuit in more detail. The range and MAG point where this is limited by the absolute output limit imposed scaling of VDBS is independent of the supply voltage, and the gain control pin, VDBS, presents a high incremental input re- by the supply voltage. In the absence of the latter effect, the sistance (~100 MΩ) with a low bias current (~100 nA), making peak output into an open-circuited load is just the AD8330 easy to drive from a variety of gain control sources. VOUT_PK = ±4 VMAG (5) Inversion of the Gain Slope whereas for a load resistance of R directly across OPHI and L The AD8330 supports many features that further extend the OPLO, it is versatility of this VGA in wide bandwidth gain control systems. ±2 V R MAG L For example, the logic pin, MODE, allows the slope of the gain V = (6) OUT _ PK (R +150) L function to be inverted, so that the basic gain starts at +50 dB for a gain voltage, V , of zero and runs down to 0 dB when These capabilities are illustrated in Figure 49, where V = 6 V, DBS S this voltage is at its maximum specified value of 1.5 V. The basic RL = O/C, VDBS = 0 V, VIN is swept from −2.5 V dc to +2.5 V dc, and forms of these two gain control modes are shown in Figure 48. VMAG is set to 0.25 V, 0.5 V, 1 V, and 2 V. Except for the last value 50 of VMAG, the peak output follows Equation 5. This exceeds the MODE PIN MODE PIN supply-limited value when VMAG = 2 V and the peak output is LOW, GAIN HIGH, GAIN DECREASES INCREASES ±5.65 V, that is, ±6 V − 0.35 V. Figure 50 demonstrates the high WITH V WITH V 40 DBS DBS speed multiplication capability. The signal input is a 100 MHz, 0.1 V sine wave, V is set to 0.6 V, and V is a square wave at DBS MAG 30 5 MHz alternating from 0.25 V to 1 V. The output is ideally a sine wave switching in amplitude between 0.5 V and 2 V. 8 20 V = 2V 6 MAG 10 1V 4 0.5V 2 0 0 0.25 0.50 0.75 1.0 1.25 1.50 0.25V 0 V (V) DBS Figure 48. Two Gain Directions of the AD8330 –2 Gain Magnitude Control (V ) MAG –4 In addition to the basic linear-in-dB control, two more gain –6 control features are provided. The voltage applied to Pin VMAG provides accurate linear-in-magnitude gain control with a very –8 –3 –2 –102 1 3 rapid response. The bandwidth of this interface is >100 MHz. V ( V) IN When this pin is unconnected, V assumes its default value of MAG Figure 49. Effect of VMAG on Gain and Peak Output 500 mV (see Figure 47) to set up the basic 0 dB to 50 dB range. However, any voltage from ~15 mV to 5 V can be applied either to lower the gain by up to 30 dB or to raise it by 20 dB. The combined gain span is thus 100 dB, that is, the 50 dB basic gain span provided by V plus a 60 dB linear-in-magnitude span DBS provided by V . The latter modifies the basic numerical gain MAG G to generate a total gain, expressed here in magnitude terms. BN Rev. E | Page 16 of 32 GAIN (dB) 03217-049 V (V) OUT 03217-050 AD8330 V IN 0.10 Amplitude/Phase Response 0.05 The ac response of the AD8330 is remarkably consistent not 0 only over the full 50 dB of its basic gain range, but also with –0.05 changes of gain due to alteration of VMAG, as demonstrated in –0.10 V MAG Figure 51. This is an overlay of two sets of results: first, with a 1.2 1.0 very low V of 16 mV that reduces the overall gain by 30 dB MAG 0.8 0.6 [20 × log10(500 mV/16 mV)]; second, with V = 5 V that MAG 0.4 increases the gain by 20 dB = 20 × log10(5 V/0.5 V). 0.2 0 90 V OUT 2.5 70 2.0 1.5 50 1.0 0.5 30 0 –0.5 10 –1.0 –1.5 –10 –2.0 –400 –300 –200 –100 0 100 200 300 –30 TIME (ns) –50 100k 1M 10M 100M 300M Figure 50. Using VMAG in Modulation Mode 0 G = +70dB –50 Another gain related feature allows both gain control ranges –100 to be accurately raised by 200 mV. To enable this offset, open –150 circuit CMGN (Pin 6, LFCSP; Pin 8, LQFP) and add a 0.1 μF –200 –250 capacitor to ground. In use, the nominal range for VDBS extends –300 from 0.2 V to 1.7 V and VMAG from 0.2 V to 5.2 V. These G = –20dB –350 10k 100k 1M 10M 100M 300M specifications apply for any supply voltage. This allows the use FREQUENCY (Hz) of DACs whose output range does not include ground as sources Figure 51. AC Performance over a 100 dB Gain Range Obtained by for the gain control function(s). Using Two Values of V MAG Note that the 200 mV that appears on this pin affects the This 50 dB step change in gain produces two sets of gain curves, response to an externally applied V , but when Pin VMAG is MAG having a total gain span of 100 dB. It is apparent that the ampli- unconnected, the internally set default value of 0.5 V still applies. tude and phase response are essentially independent of the gain Furthermore, Pin CMGN can, if desired, be driven by a user- over this wide range, an aspect of the AD8330 performance supplied voltage to reposition the baseline for VDBS (or for an potential unprecedented in any prior VGA. externally applied VMAG) to any other voltage up to 500 mV. In It is unusual for an application to require such a wide range of all cases, the gain scaling, its law conformance, and temperature gains; and, as a practical matter, the peak output voltage for stability are unaffected. VMAG = 16 mV is reduced by the factor 16/500, compared to its Two Classes of Variable Gain Amplifiers nominal value of ±2 V, to only ±64 mV. As previously noted, Note that there are two broad classes of VGAs. The first type is most applications of VGAs require that they operate in a mode designed to cope with a very wide range of input amplitudes that is predominantly of either an IVGA or OVGA style, rather and, by virtue of its gain control function, compress this range than mixed modes. down to an essentially constant output. This is the function With this limitation in mind, and simply to illustrate the unusual needed in an AGC system. Such a VGA is called an IVGA, possibilities afforded by the AD8330, note that, with appropriate referring to a structure optimized to address a wide range of drive to VDBS and VMAG in tandem, the gain span is a remarkable input amplitudes. By contrast, an OVGA is optimized to deliver 120 dB, extending from −50 dB to +70 dB, as shown in Figure 52 a wide range of output values while operating with an essentially for operation at 1 MHz and 100 MHz. In this case, V and DBS constant input amplitude. This function might be needed, for V are driven from a common control voltage, V , that MAG GAIN example, in providing a variable drive to a power amplifier. varies from 1.2 mV to 5 V, with 30% (1.5/5) of V applied GAIN It is apparent from the foregoing sections that the AD8330 is to V , and 100% applied to V . DBS MAG both an IVGA and an OVGA in one package. This is an unusual The gain varies in a linear-in-dB manner with VDBS, although and possibly confusing degree of versatility for a VGA; therefore, the response from VMAG is linear-in-magnitude. Consequently, the these two distinct control functions are described at separate overall numerical gain as the product of these two functions is points throughout this data sheet to explain the operation and V GAIN applications of this product. It is, nevertheless, useful to briefly 0.6 V GAIN= V /0.5 V×0.3×10 (7) GAIN describe the capabilities of these features when used together. In rare cases where such a wide gain range is of value, the calibration is still accurate and the temperature is stable. Rev. E | Page 17 of 32 03217-051 PHASE (Degrees) GAIN (dB) 03217-052 AD8330 80 perfect, the noise figure cannot be better than 3 dB. The 1 kΩ 60 internal termination resistance would result in a minimum 40 noise figure of 3 dB for an R of 1 kΩ if the amplifier were S 20 0 noise-free. However, this is not the case, and the minimum –20 noise figure occurs at a slightly different value of RS (for an –40 example, see Figure 53 and the Using the AD8330 section). –60 100k 15 10k 14 1k 13 100 12 10 11 1 10 0.001 0.01 0.1 1 10 V (V) GAIN 9 Figure 52. Gain Control Function and Input Referred Noise Spectral Density 8 over a 120 dB Range 7 Noise, Input Capacity, and Dynamic Range 6 The design of variable gain amplifiers invariably incurs some 5 compromises in noise performance. However, the structure of 10 100 1k 10k R (Ω) S the AD8330 is such that this penalty is minimal. Examination Figure 53. Noise Figure for Source Resistance of 50 Ω to 5 kΩ, at f = 10 MHz of the simplified schematic (Figure 47) shows that the input (Lower) and 100 MHz (Simulation) voltage is converted to current-mode form by the two 500 Ω 144 resistors at Pin INHI and Pin INLO, whose combined Johnson noise contributes 4.08 nV/√Hz. The total input noise at full 140 CONSTANT 1V rms gain, when driven from a low impedance source, is typically OUTPUT, BOTH CASES 5 nV/√Hz after accounting for the voltage and current noise 136 contributions of the loop amplifier. For a 200 kHz channel X-AMP WITH 40dB 132 bandwidth, this amounts to 2.24 μV rms. The peak input at full OF GAIN AND AN INPUT NSD gain is ±6.4 mV, or +4.5 mV rms for a sine wave signal. The 128 OF nV/√Hz signal-to-noise ratio at full input, that is, the dynamic range, for these conditions is, thus, 20 log10(4.5 mV/2.24 μV), or 66 dB. 124 The value of VMAG has essentially no effect on the input referred 120 noise, but it is assumed to be 0.5 V. Below midgain (25 dB, V = 0.75 V), noise in the output DBS 116 00.1 0.20.30.40.5 0.60.70.80.91.01.11.21.31.41.5 section dominates, and the total input noise is 11 nV/√Hz, or V (V) DBS 4.9 μV rms in a 200 kHz bandwidth, and the peak input is Figure 54. Dynamic Range in dB/√Hz vs. VDBS (VMAG = 0.5 V, 1 V rms Output) 78 mV rms. Thus, the dynamic range increases to 84 dB. Compared with a Representative X-AMP (Simulation) At minimum gain, the input noise is up to 120 nV/√Hz, or Dynamic Range 53.7 mV rms in the assumed 200 kHz bandwidth, while the The ratio of peak output swing, expressed in rms terms, to the input capacity is ±2 V, or +1.414 V rms (sine), a dynamic range output-referred noise spectral density provides a measure of of 88.4 dB. In calculating the dynamic range for other channel dynamic range, in dB/√Hz. For a certain class of variable gain bandwidths, Δf, subtract 10 log10(Δf/200 kHz) from these amplifiers, exemplified by the Analog Devices X-AMP® family, illustrative values. A system operating with a 2 MHz bandwidth, the dynamic range is essentially independent of the gain setting for example, exhibits dynamic range values that are uniformly because the peak output swing and noise are both constant. The 10 dB lower; used in an audio application with a 20 kHz band- AD8330 provides a different dynamic range profile because width, they are 10 dB higher. there is no longer a constant relationship between these two Noise figure is a misleading metric for amplifiers that are not parameters. Figure 54 compares the dynamic range of the impedance matched at their input, which is the special condi- AD8330 to a representative X-AMP. tion resulting only when both the voltage and current components of a signal, that is, the signal power, are used at the input port. When a source of impedance (R ) is terminated using a resistor S of R (a condition that is not to be confused with matching), S only one of these components is used, either the current (as in the AD8330) or the voltage. Then, even if the amplifier is Rev. E | Page 18 of 32 NOISE (nV/√Hz) GAIN (dB) 03217-053 NOISE FIGURE DYNAMIC RANGE (dB/√Hz) 03217-055 03217-054 AD8330 Input Common-Mode Range and Rejection Ratio The scaling for V = 0 V is as follows: DBS Input Pin INHI and Pin INLO should be ac-coupled in most V = ±4 V (8) OUT_PK MAG applications to achieve the stated noise performance. In general, V = (85 + 70 V ) nV/√Hz (9) NOISE_OUT MAG when direct coupling is used, care must be taken in setting the For example, using a reduced value of VMAG = 0.25 V that lowers dc voltage level at these inputs, and particularly when minimizing all gain values by 6 dB, the peak output swing is ±1 V (differ- noise is critical. This objective is complicated by the fact that entially) and the output noise spectral density evaluates to the common-mode level varies with the basic gain voltage, V . DBS 102.5 nV/√Hz. The peak output swing is no different at full Figure 55 shows this relationship for a supply voltage of 5 V, for gain, but the noise becomes temperatures of −40°C, +25°C, and +85°C. Figure 56 shows the input noise spectral density (RS = 0) vs. the input common- V = (0.1 + 0.32 V ) μV/√Hz (10) NOISE_OUT MAG mode voltage, for VDBS = 0.5 V, 0.6 V, 0.75 V, and 1.5 V. It is for R = 0 and V = 1.5 V, assuming an input noise of 5 nV/√Hz. S DBS apparent that there is a broad range over which the noise is The output noise for very small values of VMAG (at or below 15 mV) unaffected by this dc level. The input CMRR is excellent (see is not precise, partly because the small input offset associated Figure 16). with this interface has a large effect on the gain. 3.2 T = +85°C Offset Compensation The AD8330 includes an offset compensation feature that is 3.1 T = +25°C operational in the default condition (no connection to Pin OFST). 3.0 This loop introduces a high-pass filter function into the signal T = –40°C path, whose −3 dB corner frequency is at 2.9 1 f = (11) HPF (2πR C) HP INT 2.8 where: C is the external capacitance added from OFST to CNTR. 2.7 HP RINT is an internal resistance of approximately 480 Ω, having a 2.6 maximum uncertainty of about ±20%. 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 V (V) DBS This evaluates to Figure 55. Common-Mode Voltage at Input Pins vs. V , for V = 5 V, DBS S 330μ T = −40°C, + 25°C, and + 85°C f = (C in μF) (12) HP HPF C HP A small amount of peaking at this corner when using small 26 capacitor values can be avoided by adding a series resistor. 24 V = 0.5V DBS Useful combinations are C = 3 nF, R = 180 Ω, f = 100 kHz; HP HP 22 CHP = 33 nF, RHP = 10 Ω, f = 10 kHz; CHP = 0.33 μF, RHP = 0 Ω, 20 f = 1 kHz; CHP = 3.3 μF, RHP = 0 Ω, f = 100 Hz. 18 V = 0.6V DBS The offset compensation feature can be disabled simply by 16 grounding the OFST pin. This provides a dc-coupled signal 14 V = 0.75V DBS path, with no other effects on the overall ac response. Input 12 offsets must be externally nulled in this mode of operation, as 10 shown in Figure 58. 8 SIMULATION V = 1.5V DBS Effects of Loading on Gain and AC Response 6 4 The differential output impedance (RO) is 150 Ω, and the fre- 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 quency response of the output stage is optimized for operation COMMON-MODE VOLTAGE AT INHI, INLO (V) with a certain load capacitance on each output pin (OPHI and Figure 56. Input Noise vs. Common-Mode Input Voltage for VDBS = 0.5 V, 0.6 V, 0.75 V, and 1.5 V OPLO) to ground, in combination with a load resistance (R ) L directly across these pins. In the absence of these capacitances, Output Noise and Peak Swing there is a small amount of peaking at the top extremity of the The output noise of the AD8330 is the input noise multiplied by ac response. Suitable combinations are: RL = ∞, CL = 12 pF; the overall gain, including any optional change to the voltage, RL = 150 Ω, CL = 25 pF; RL = 75 Ω, CL = 40 pF; or RL = 50 Ω, V , applied to Pin VMAG. The peak output swing is also MAG CL = 50 pF. proportional to this voltage, which, at low gains and high values of V , affects the output noise. MAG Rev. E | Page 19 of 32 DC VOLTAGE AT INHI, INLO (V) INPUT REFERRED NOISE (nV/√Hz) 03217-057 03217-056 AD8330 The gain calibration is specified for an open-circuited load, As in all high frequency circuits, careful observation of the such as the high input resistance of an ADC. When resistively ground nodes associated with each function is important. Three loaded, all gain values are nominally lowered as follows: positive supply pins are provided: VPSI supports the input cir- cuitry that often operates at a relatively high sensitivity; VPOS G R UNLOADED L G = (13) supports general bias sources and needs no decoupling; and LOADED ( ) 150 Ω+ R L VPSO biases the output stage where decoupling can be useful in maintaining a glitch-free output. Figure 57 shows the general Thus, when RL = 150 Ω, the gain is reduced by 6 dB; for case, where VPSI and VPSO are each provided with their own R = 75 Ω, the reduction is 9.5 dB; and for R = 50 Ω, it is 12 dB. L L decoupling network, but this is not needed in all cases. Gain Errors Due to On-Chip Resistor Tolerances V 2.7V TO 6V S In all cases where external resistors are used, keep in mind that RD1 CHPF CD2 RD2 all on-chip resistances, including the RO and the input resistance (RI), are subject to variances of up to ±20%. EV NBL OFSTPOS CNTR These variances need to be accounted for when calculating the CD1 CD3 gain with input and output loading. This sensitivity can be avoided VPSO VPSI BIAS AND CM MODE AND V-REF OFFSET CONTROL by adjusting the source and load resistances to bear an inverse relationship as follows: INHI OPHI If RS = αRI, then make RL = RO/α; or, if RL = αRO, then make RS = RI/α OUTPUT, INPUT, OUTPUT VGA CORE ±2V MAX 0V TO ±2V MAX STAGES The simplest case is when RS = 1 kΩ and RL = 150 Ω, therefore, OPLO INLO the gain is 12 dB lower than the basic value. The reduction of peak swing at the load can be corrected by using V = 1 V, MAG thereby restoring 6 dB of gain; using V = 2 V restores the full MAG OUTPUT MODE GAIN INTERFACE NC CMOP basic gain and doubles the peak available output swing. CONTROL VDBS CMGN COMM VMAG Output (Input) Common-Mode Control The output voltages are nominally positioned at the midpoint of NC BASIC GAIN BIAS V : 0V TO 1.5V the supply, V /2, over the range 2.7 V < V < 6 V, and this voltage S S DBS GROUND appears at Pin CNTR, which is not normally expected to be loaded (the source resistance is ~4 kΩ). However, some circum- Figure 57. Power Supply Decoupling and Basic Connections stances require a small change in this voltage, and a resistor Because of the differential nature of the signal path, power from CNTR to ground can lower this voltage, whereas a resistor supply decoupling is, in general, much less critical than in a to the supply raises it. On the other hand, this pin can be driven single-sided amplifier; and where the minimization of board- by an external voltage source to set the common-mode level to level components is especially crucial, it is possible that these satisfy, for example, the needs of a following ADC. Any value pins need no decoupling at all. On the other hand, when the from 0.5 V above ground to 0.5 V below the supply is permissible. signal source is single-sided, giving extra attention to the Of course, when using an extreme common-mode level, the decoupling on Pin VPSI is sometimes required. Likewise, available output swing is limited, and it is recommended that care is required in decoupling the VPSO pin if the output is a value equal or close to the default of V = V /2 be used. CNTR S loaded on only one of its two output pins. The general common There may be a few millivolts of offset between the applied (COMM) and the output stage common (CMOP) are usually voltage and the actual common-mode level at the output pins. grounded as shown in the Figure 57; however, the Applications The input common-mode voltage, VCMI, at Pin INHI and section shows how a negative supply can optionally be used. Pin INLO is slaved to the output, but with a shifted value of The AD8330 is enabled by taking the ENBL pin to a logical high V = 0.757 V + 1.12 V (14) CMI CNTR (or, in all cases, the supply). The UP gain mode is enabled either by leaving the MODE pin unconnected or taking it to a logical for V = 0.75 and T = 25°C. Thus, the default value for V DBS CMI high. When the opposite gain direction is needed, the MODE when V = 5 V is 3.01 V (see Figure 55). S pin should be grounded or driven to a logical low. The low-pass USING THE AD8330 corner of the offset loop is determined by Capacitor CHPF; this This section describes a few general aspects of using the is preferably tied to the CNTR pin that in turn, should be AD8330. Applying the AD8330 to a wide variety of circum- decoupled to ground. The gain interface common pin (CMGN) stances requires very few precautions. is grounded, and the output magnitude control pin (VMAG) is left unconnected, or can optionally be connected to a 500 mV source for basic gain calibration. Rev. E | Page 20 of 32 03217-058 AD8330 Connections to the input and output pins are not shown in Occasionally, it is possible to avoid the use of coupling Figure 57 because of the many options that are available. When capacitors when the dc level of the driving source is within a the AD8330 is used to drive an ADC, connect the OPHI and certain range, as shown in Figure 56. This range extends from OPLO pins directly to the differential inputs of a suitable converter, 3.5 V to 4.5 V when using a 5 V supply, and at high basic gains, such as an AD9214. If an adjustment is needed to this common- where the effect of an incorrect dc level degrades the noise level mode level, it can be introduced by applying that voltage to the due to internal aspects of the input stage. For example, suppose CNTR pin, or, more simply, by using a resistor from this pin to the driver, IC, is an LNA having an output topology in which its either ground or the supply (see the Applications section). The load resistors are taken to the supply, and the output is buffered CNTR pin can also supply the common-mode voltage to an by emitter followers. This presents a source for the AD8330 that ADC that supports such a feature. can readily be directly coupled. When the loads to be driven introduce a dc resistive path to DC-Coupled Signal Path ground, coupling capacitors must be used. These should be of In many cases, where the VGA is not required to provide its sufficient value to pass the lowest frequency components of the lowest noise, the full common-mode input range of zero to VS signal without excessive attenuation. Keep in mind that the can be used without problems, avoiding the need for any ac voltage swing on such loads alternates both above and below coupling means. However, such direct coupling at both the input ground, requiring that the subsequent component must be able and output does not automatically result in a fully dc-coupled to cope with negative signal excursions. signal path. The internal offset compensation loop must also be Gain and Swing Adjustments When Loaded disengaged by connecting the OFST pin to ground. Keep in mind that at the maximum basic gain of 50 dB (×316), every The output can also be coupled to a load via a transformer to millivolt of offset at the input, arising from whatever source, achieve a higher load power by impedance transformation. For causes an output offset of 316 mV, which is an appreciable example, using a 2:1 turns ratio, a 50 Ω final load presents a fraction of the peak output swing. 200 Ω load on the output. The gain loss (relative to the basic value with no termination) is 20 log10{(200+150)/200} or Because the offset correction loop is placed after the front-end 4.86 dB, which can be restored by raising the voltage on the variable gain sections of the AD8330, the most effective way 4.86/20 VMAG pin by a factor of 10 or × 1.75, from its basic value of dealing with such offsets is at the input pins, as shown in of 0.5 V to 0.875 V. This also restores the peak swing at the 200 Ω Figure 58. For example, assume, for illustrative purposes, that level to ±2 V, or ±1 V into the 50 Ω final load. the resistances associated with each side of the source in a cer- tain application are 50 Ω. If this source has a very low (op amp) Whenever a stable supply voltage is available, additional voltage output impedance, the extra resistors should be inserted, with a swing can be provided by adding a resistor from the VMAG pin negligible noise penalty and an attenuation of only 0.83 dB. The to the supply. The calculation is based on knowing that the in- resistor values shown provide a trim range of about ±2 mV. ternal bias is delivered via a 5 kΩ source; because an additional 0.375 V is needed, the current in this external resistor must be V 2.7V TO 6V S RD1 RD2 CD2 0.375 V/5 kΩ = 75 μA. Thus, using a 5 V supply, a resistor of 5 V − 0.875 V/75 μA = 55 kΩ is used. Based on this example, the corrections for other load conditions are easy to calculate. EV NBL OFSTPOS CNTR CD1 CD3 If the effects on gain and peak output swing due to supply VPSO VPSI BIAS AND CM MODE AND variations cannot be tolerated, VMAG must be driven by an V-REF OFFSET CONTROL accurate voltage. Input Coupling INHI OPHI R ASSUMED S 50kΩ The dc common-mode voltage at the input pins varies with TO BE 50Ω OUTPUT OUTPUT, VGA CORE ON EACH ±2V MAX STAGES the supply, the basic gain bias, and temperature (see Figure 55); SIDE for this reason, many applications need to use coupling capaci- INLO OPLO 75kΩ tors from the source that are large enough to support the lowest frequencies to be transmitted. Using one capacitor at each input OUTPUT MODE GAIN INTERFACE pin, their minimum values can be readily found from the expression CONTROL CMOP VDBS CMGN COMM VMAG 320 μF C = (15) IN_CPL f NC HPF BASIC GAIN BIAS V : 0V TO 1.5V DBS GROUND where fHPF is the –3dB frequency expressed in hertz. Thus, for an fHPF of 10 kHz, 33 nF capacitors are used. Figure 58. Input Offset Nulling in a DC-Coupled System Rev. E | Page 21 of 32 03217-059 AD8330 90 common-mode control loop appear in both the magnitude and V = 1.5V OFST: ENABLED DBS DISABLED 80 phase response. V = 0.75V DBS 70 Adding a dummy 75 Ω to OPLO results in Line 3: the gain is a 60 further 2.5 dB lower, at about 14 dB. The CM artifacts are no longer present but a small amount of peaking occurs. If objec- 50 V = 0V DBS tionable, this can be eliminated by raising both of the capacitors 40 on the output pins to 25 pF, as shown in Line 4 of Figure 60. 30 The gain reduction incurred both by using only one output and 20 by the additional effect of loading can be overcome by taking 10 advantage of the VMAG feature, provided primarily for just such 0 circumstances. Thus, to restore the basic gain in the first case –10 (Line 1), a 1 V source should be applied to this pin; to restore the 50k 100k 1M 10M 100M gain in the second case, this voltage should be raised by a factor FREQUENCY (Hz) of ×1.5 to 1.5 V. In Case 3 and Case 4, a further factor of ×1.33 Figure 59. Input CMRR vs. Frequency for Various Values of V DBS is needed to make up the 2.5 dB loss, that is, VMAG should be Using Single-Sided Sources and Loads raised to 2 V. With the restoration of gain, the peak output Where the source provides a single-sided output, either INHI swing at the load is, likewise restored to ±2 V. or INLO can be used for the input, with a polarity change when Pulse Operation using INLO. The unused pin must be connected either through When using the AD8330 in applications where its transient a capacitor to ground, or through a dc bias point that corresponds response is of greater interest and the outputs are conveyed to closely to the dc level on the active signal pin. The input CMRR their loads via coaxial cables, the added capacitances can slightly over the full frequency range is illustrated in Figure 59. In some differ in value, and can be placed either at the sending or load cases, an additional element such as a SAW filter (having a end of the cables, or divided between these nodes. Figure 61 single-sided balanced configuration) or a flux-coupled trans- shows an illustrative example where dual, 1 meter, 75 Ω cables former can be interposed. Where this element must be terminated are driven through dc-blocking capacitors and are independently in the correct impedance, other than 1 kΩ, it is necessary to add terminated at ground level. either shunt or series resistors at this interface. 30 Because of the considerable variation between applications, LINE 1 20 only general recommendations can be made with regard to LINE 3 10 minimizing pulse overshoot and droop. The former can be 0 optimized by adding small load capacitances, if necessary; LINE 4 –10 the latter requires the use of sufficiently large capacitors (C1). LINE 2 –20 V 2.7V–6V S –30 RD2 CD2 0 LINE 2 –100 LINE 3 –200 EV NBL OFSTPOS CNTR LINE 4 CD3 –300 VPSO VPSI BIAS AND CM MODE AND –400 LINE 1 V-REF OFFSET CONTROL –500 RL1 C1 –600 1M 10M 100M 500M INHI OPHI FREQUENCY (Hz) CL1 OUTPUT VGA CORE Figure 60. AC Gain and Phase for Various Loading Conditions STAGES C1 When driving a single-sided load, either OPHI or OPLO can be INLO OPLO CL2 RL2 used. These outputs are very symmetric, so the only effect of this choice is to select the desired polarity. However, when the OUTPUT MODE GAIN INTERFACE CMOP CONTROL frequency range of interest extends to the upper limits of the VDBS CMGN COMM VMAG AD8330, a dummy resistor of the same value should be attached to the unused output. Figure 60 illustrates the ac gain and phase NC response for various loads and VDBS = 0.75 V. Line 1 shows the unloaded (C = 12 pF) case for reference; the gain is 6 dB lower L (20 dB) using only the single-sided output. Adding a 75 Ω load Figure 61. Driving Dual Cables with Grounded Loads from OPHI to an ac ground results in Line 2. The gain becomes a factor of ×1.5 V or 3.54 dB lower, but artifacts of the output Rev. E | Page 22 of 32 PHASE (Degrees) GAIN (dB) CMRR (dB) 03217-060 03217-061 03217-062 AD8330 1.2 1.0 resistances. Furthermore, this fixed and predictable loss can be 0.8 0.6 corrected by an adjustment to V , as indicated in Table 5. MAG 0.4 0.2 0 –0.2 0.2 Table 5. Preserving Absolute Gain 0 –0.2 Uncorrected Loss –0.4 VMAG Required to –0.6 –0.8 R (Ω) R (Ω) Factor dB Correct Loss –1.0 S L –1.2 1.2 10 15 k 0.980 0.17 0.510 1.0 0.8 0.6 15 10 k 0.971 0.26 0.515 0.4 0.2 20 7.5 k 0.961 0.34 0.520 0 –0.2 0.2 30 5.0 k 0.943 0.51 0.530 0 –0.2 –0.4 50 3.0 k 0.907 0.85 0.551 –0.6 –0.8 75 2.0 k 0.865 1.26 0.578 –1.0 –1.2 100 1.5 k 0.826 1.66 0.605 0 5ns 10ns 15ns 20ns 25ns 150 1.0 k 0.756 2.43 0.661 Figure 62. Typical Pulse Response for Figure 61 200 750 0.694 3.17 0.720 Figure 62 shows typical results for V = 0.24 V, a square wave DBS 300 500 0.592 4.56 0.845 input amplitude of 450 mV (the actual combination is not 500 300 0.444 7.04 1.125 important), a rise time of 2 ns, and V raised to 2.0 V. In the MAG 750 200 0.327 9.72 1.531 upper waveforms, the load capacitors are both zero, and a small 1 k 150 0.250 12.0 2.000 amount of overshoot is visible; with 40 pF, the response is cleaner. 1.5 k 100 0.160 15.9 3.125 A shunt capacitance of 20 pF from OPHI to OPLO has a similar 2 k 75 0.111 19.1 4.500 effect. Coupling capacitors for this demonstration are suffi- ciently large to prevent any visible droop over this time scale. Calculation of Noise Figure The outputs at the load side eventually assume a mean value of The AD8330 noise is a consequence of its intrinsic voltage noise zero, with negative and positive excursions depending on the spectral density (E ) and the current noise spectral density NSD duty cycle. (I ). Their combined effect generates a net input noise, NSD The bandwidth from Pin VMAG to these outputs is somewhat VNOISE_IN, that is a function of the input resistance of the device higher than from the normal input pins. Thus, when this pin is (RI), nominally 1 kΩ, and the differential source resistance (RS) used to rapidly modulate the primary signal, some further as follows: experimentation with response optimization may be required. 2 2 2 In general, the AD8330 is very tolerant of a wide range of V ={E + I (R + R)} (16) NOISE_ IN NSD NSD I S loading conditions. Note that purely resistive source and input impedances as a conces- Preserving Absolute Gain sion to simplicity is assumed. A more thorough treatment of Although the AD8330 is not laser trimmed, its absolute gain noise mechanisms, for the case where the source is reactive, is calibration, based mainly on ratios, is very good. Full details are beyond the scope of these brief notes. Also note that VNOISE_IN is found in the Specifications section and in the typical performance the voltage noise spectral density appearing across INHI and curves (see the Typical Performance Characteristics section). INLO, the differential input pins. In preparing for the calculation Nevertheless, having finite input and output impedances, the of the noise figure, V is defined as the open-circuit signal SIG gain is necessarily dependent on the source and load conditions. voltage across the source, and V is defined as the differential IN The loss that is incurred when either of these is finite causes an input to the AD8330. The relationship is simply error in the absolute gain. The absolute gain can also be V R SIG I uncertain due to the approximately ±20% tolerance in the V = (17) IN R + R ( ) I S absolute value of the input and output impedances. At maximum gain, ENSD is 4.1 nV/√Hz, and INSD is 3 pA/√Hz. Often, such losses and uncertainties can be tolerated and Thus, the short-circuit voltage noise is accommodated by a correction to the gain control bias. On the other hand, the error in the loss can be essentially nulled by 2 2 2 V = {(4.1 n V/ Hz)+() 3pA / Hz (1 kΩ+ 0)}= NOISE _ IN using appropriate modifications to either the source impedance (RS) or the load impedance (RL), or both (in some cases by padding them with series or shunt components). 5.08 nV/√Hz (18) The formulation for this correction technique was previously Next, examine the net noise when R = R = 1 kΩ, often incor- S I described. However, to simplify its use, Table 5 shows spot rectly called the matching condition, rather than source impedance values for combinations of R and R resulting in an overall loss S L termination, which is the actual situation in this case. that is not dependent on sample-to-sample variations in on chip Rev. E | Page 23 of 32 03217-063 AD8330 Repeating the procedure, In practice, however, the effect of device mismatches and junc- tion resistances in the core cell, and other mechanisms in its 2 2 2 V =() 4.1 nV / Hz +() 3 pA / Hz(1 kΩ+1 kΩ) supporting circuitry inevitably cause distortion, further aggravated NOISE _ IN by other effects in the later output stages. Some of these effects = 7.3 nV/√Hz (19) are very consistent from one sample to the next, while those due The noise figure is the decibel representation of the noise factor, to mismatches (causing predominantly even-order distortion N , commonly defined as follows: FAC components) are quite variable. Where the highest linearity SNR at input (and lowest noise) is demanded, consider using one of the X- N = (20) FAC AMP products such as the AD603 (single-channel), AD604 SNRat output (dual-channel), or AD8332 (wideband dual-channel with However, this is equivalent to ultralow noise LNAs). SNR at the source (21) N = P1dB and V1dB FAC SNR at the input pins In addition to the nonlinearities that arise within the core of the Let V be the voltage noise spectral density √kTRS due to the NSD AD8330, at moderate output levels, another metric that is more source resistance. Using Equation 17 gives commonly stated for RF components that deliver appreciable power to a load is the 1 dB compression point. This is defined V {R /(R + R )}/V I I SIG S NSD N = FAC in a very specific manner: it is that point at which, with increasing V /{} V R /() R + R IN NOISE _ IN S I S output level, the power delivered to the load eventually falls to a R V I NOISE _ IN value that is 1 dB lower than it would be for a perfectly linear = (22) R V S NSD system. (Although this metric is sometimes called the 1 dB gain compression point, it is important to note that this is not the output level at which the incremental gain has fallen by 1 dB). Then, using the result from Equation 19 for a source resistance As shown in Figure 49, the output of the AD8330 limits quite of 1 kΩ, having a noise-spectral density of 4.08 nV/√Hz abruptly, and the gain drops sharply above the clipping level. produces The output power, on the other hand, using an external resistive () 1 kΩ(7.3 nV/ Hz) load, RL, continues to increase. In the most extreme case, the N = = 1.79 (23) FAC () 1 kΩ() 4.08 nV/ Hz waveform changes from the sinusoidal form of the test signal, with an amplitude just below the clipping level, VCLIP, to a Finally, converting this to decibels using square wave of precisely the same amplitude. The change in N = 10 log (N) (24) FIG 10 FAC 2 2 power over this range is from (V /√2) /R to (V ) /R , that CLIP L CLIP L Thus, the resultant noise figure in this example is 5.06 dB, is, a factor of 2, or 3 dB in power terms. It can be shown that for an ideal limiting amplifier, the 1 dB compression point occurs which is somewhat lower than the value shown in Figure 53 for this operating condition. for an overdrive factor of 2 dB. Noise as a Function of V For example, if the AD8330 is driving a 150 Ω load and VMAG is DBS set to 2 V, the peak output is nominally ±4 V (as noted previously, The chief consequence of lowering the basic gain using V is DBS the actual value, when loaded. can differ because of a mismatch that the current noise spectral density I increases with the NSD between on-chip and external resistors), or 2.83 V rms for a sine square root of the basic gain magnitude, G such that BN wave output that corresponds to a power of 53.3 mW, that is, INSD = (3 pA/√Hz)(√GBN) (25) 17.3 dBm in 150 Ω. Thus, the P1dB level, at 2 dB above Therefore, at the minimum basic gain of ×0, INSD rises to clipping, is 19.3 dBm. 53.3 pA/√Hz. However, the noise figure rises to 17.2 db if it Though not involving power transfer, it is sometimes useful is recalculated using the procedures in Equation 16 through to state the V1dB, which is the output voltage (unloaded or Equation 24. loaded) that is 2 dB above clipping for a sine waveform. In the Distortion Considerations above example, this voltage is still 2.83 V rms, which can be expressed as 9.04 dBV (0 dBV corresponds to a 1 V sine wave). Continuously variable gain amplifiers invariably employ Thus, the V1dB is at 11.04 dBV. nonlinear circuit elements; consequently, it is common for their distortion to be higher than well-designed fixed gain amplifiers. The translinear multiplier principles used in the AD8330, in theory, yield extremely low distortion, a result of the funda- mental linearization technique that is an inherent aspect of these circuits. Rev. E | Page 24 of 32 AD8330 APPLICATIONS INFORMATION The versatility of the AD8330, its very constant ac response over from VMAG to ground. An overrange condition is signaled by a a wide range of gains, the large signal dynamic range, output high state on Pin OR of the AD9214. DFS/GAIN is unconnected swing, single supply operation, and low power consumption in this example producing an offset-binary output. To provide a commend this VGA to a diverse variety of applications. Only a twos complement output, it should be connected to the REF pin. few can be described here, including the most basic uses and some For ADCs running at sampling rates substantially below the unusual ones. bandwidth of the AD8330, an intervening noise filter is recommended to limit the noise bandwidth. A one-pole filter ADC DRIVING can easily be created with a single differential capacitor between The AD8330 is well-suited to drive a high speed converter. the OPHI and OPLO outputs. For a corner frequency of fC, the There are many high speed converters available, but to illustrate capacitor should have a value of the general features, the example in this data sheet uses one of the least expensive, the AD9214. This is available in three CFILT = 1/942 fC (26) grades for operation at 65 MHz, 80 MHz, and 105 MHz; the For example, a 10 MHz corner requires about 100 pF. AD9214BRS-80 is a good complement to the general capabili- SIMPLE AGC AMPLIFIER ties of this VGA. Figure 64 illustrates the use of the inverted gain mode and the Figure 63 shows the connections to drive an ADC. A 3.3 V offset gain range (0.2 V < VDBS < 1.7 V) in supporting a low cost supply is used for both parts. The ADC requires that its input AGC loop. Q1 is used as a detector. When OPHI is sufficiently pins be positioned at one third of the supply, or 1.1 V. Given higher than CNTR, due to the signal swing, it conducts and that the default output level of the VGA is one-half the supply charges C1. This raises V and rapidly lowers the gain. Note DBS or 1.65 V, a small correction is introduced by the 8 kΩ resistor that MODE is grounded (see Figure 48). The minimum voltage from CNTR to ground. The ADC specifications require that the needed across R1 to set up the full gain is 0.2 V because CMGN common-mode input be within ±0.2 V of the nominal 1.1 V; is dc open-circuited (this does not alter VMAG) and the maxi- variations of up to ±20% in the AD8330 on-chip resistors change mum voltage is 1.7 V. this voltage by only ±70 mV. With the connections shown in Figure 63, the AD9214 is able to receive an input of 2 V p-p; the peak output of the AD8330 can be reduced if desired by adding a resistor V ,3.3V S 3.3Ω 3.3Ω 0.1µF 0.1µF OVER- 8kΩ RANGE CHPF 0.1µF 10Ω ENBL OFST VPOS CNTR OR AV DrV DD DD VPSO VPSI BIAS AND CM MODE AND D9 V-REF OFFSET CONTROL PWRDN 0.1µF D8 DFS/GAIN D7 A INHI OPHI IN D6 D5 INPUT, OUTPUT AD9214BRS-80 VGA CORE ±2V MAX STAGES D4 D3 A IN INLO OPLO D2 REFSENSE D1 REF D0 OUTPUT MODE GAIN INTERFACE NC CMOP CONTROL AGND DGND CLK VDBS CMGN COMM VMAG 0.1µF NC GAIN BIAS, CLOCK V , 0V–1.5V ANALOG GROUND DBS DIGITAL GROUND Figure 63. Driving an Analog-to-Digital Converter (Preliminary) Rev. E | Page 25 of 32 DATA OUTPUTS 03217-064 AD8330 V ,2.7V–6V S This simple detector exhibits a temperature variation in the 33nF differential output amplitude of about 4 mV/°C. It provides a fast attack time (an increase in the input is quickly leveled to the 10Ω 4.7Ω ENBL OFST VPOS CNTR nominal output, due to the high peak currents in Q1) and a VPSO VPSI slow release time (a decrease in the input is not restored as BIAS AND CM MODE AND 0.1µF V-REF OFFSET CONTROL 0.1µF quickly). The voltage at the VDBS pin can be used as an RSSI output, scaled 30 mV/dB. Note that the attack time can be INHI OPHI halved by adding a second transistor, labeled Q2 in Figure 64. INPUT, OUTPUT, OUTPUT SEE VGA CORE ~1V rms 5mV TO 1V rms STAGES For operation at lower frequencies, the AGC hold capacitor TEXT INLO must be increased. OPLO WIDE RANGE TRUE RMS VOLTMETER Q2 Q1 OUTPUT MODE GAIN INTERFACE CONTROL CMOP The AD8362 is an rms responding detector providing a COMM VDBS CMGN VMAG dynamic range of 60 dB from low frequencies to 2.7 GHz. 0.1µF NC This can increase to 110 dB using an AD8330 as a precondi- R1 C1 0.1µF tioner, provided the noise bandwidth is limited by an interstage 10kΩ 0.1µF low-pass or band-pass filter. Figure 64. Simple AGC Amplifier (Preliminary) The VGA also provides an input port that is easier to drive than the 200 Ω input of the AD8362. Figure 67 shows the When the loop is settled, the average current in Q1 is VDBS/R1, general scheme. which varies from 2 μA at maximum gain (VDBS = 0.2 V) to 17 μA at minimum gain (V = 1.7 V). This change in the Q1 DBS Both the AD8330 and AD8362 provide linear-in-decibel control current causes an increase of ~0.25 dB over the full gain range interfaces. Thus, when the output of the AD8362 is used to control in the differential output of nominally 0.75 dBV at midrange the gain of the AD8330, the functional form is unaffected. The (3.08 V p-p), corresponding to a 200:1 compression ratio. This overall scaling is 33 mV/dB. Figure 68 shows the time domain is plotted in Figure 65 for a representative 100 kHz input. response using a loop filter capacitor of 10 nF, for inputs rang- 1.0 ing from 10 μV to 1 V rms, that is, a 100 dB measurement range. 1.75 1.50 V 0.9 DBS 1.25 1.00 0.75 0.8 0.50 0.25 0 0.7 3 2 1 0.6 0 –1 –2 0.5 OUTPUT –50 –40 –30 –20 –10 0 –3 INPUT TO AD8330 (dBV) –4 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Figure 65. AGC Output vs. Input Amplitude (Simulation) TIME (µs) Figure 66. Time Domain Waveforms (Simulation) The upper panel in Figure 66 shows the time-domain output for fourteen 3 dB steps in input amplitude from 5.4 mV to 1.7 V. The waveforms in Figure 65 show the AGC voltage (V ). DBS Rev. E | Page 26 of 32 LEVELED OUTPUT (dBV) 03217-066 03217-065 GAIN ERROR (dB) 03217-067 AD8330 5V 3.3Ω 3.3Ω 3.3Ω AD8362 0.1µF 0.1µF 0.1µF 0.1µF 1 COMM ACOM 16 10µF 3.6V 2 15 CHPF VREF ENBL OFST VPOS CNTR VPS1 VPSO 3 DECL VTGT 14 INHI OPHI 4 13 INHI VPOS C FLT 3.6V INPUT AD8330 18nF INLO OPLO 5 INLO VOUT 12 VOUT 6 11 MODE CMOP DECL VSET 0.1µF VDBS CMGN COMM VMAG 7 10 PWDN ACOM 10µF 6.04kΩ 8 9 COMM CLPF 4.02kΩ Figure 67. Wide Range True RMS Voltmeter (Preliminary) 4 3 2 1 0 08 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4. TIME (ms) Figure 68. Time Domain Response of RMS Voltmeter (Simulation) Rev. E | Page 27 of 32 OUTPUT (V) 03217-069 03217-068 AD8330 EVALUATION BOARD GENERAL DESCRIPTION BASIC OPERATION The AD8330-EVALZ is an easy-to-use accessory that enables a The input SMA connector IN is terminated with a 49.9 Ω hands-on evaluation of the AD8330 variable gain amplifier resistor (see Figure 70). For convenience, the board includes an (VGA). It includes test pins for connections to all of the functional AD8131 high speed differential amplifier to convert a single- device inputs. Figure 69 is a full size photograph of the board. ended signal source to the differential input of the AD8330. If desired, the AD8131 can be removed and the AD8330 can be driven at one of its inputs from a single-ended source. The AD8330 output is observed at the SMA connectors OUT_HI and OUT_LO or by using the 2-pin header OUT_HI/ OUT_LO adjacent to the device. The AD8330 requires only a +5 V power supply; however, because of the AD8131 buffer bipolar power supply requirements, ±5 V supplies are required to power the board. The current required for the board is approximately 40 mA from the +5 V supply and 10 mA from the −5 V supply. Figure 69. Photograph of the AD8330 Evaluation Board C13 GND1 GND2 GND3 GND4 FILTER_OFFSET R3 1nF 1kΩ OFST FLTR 1 16 OFST VPOS +5V +5V ENBL C12 R4 0.1µF 0Ω 2 15 CNTR CNTR C1 ENBL + C19 10µF C2 0.1µF 10V 0.1µF C14 14 +5V 3 VPSI VPSO 10nF C15 C11 C4 0.1µF 0.1µF 0.1µF 4 C3 13 R2 IN OPHI OUT_HI 0.1µF INHI 49.9Ω 3 AD8131 8 C9 4 12pF 2 DUT1 OUT_TEST A1 IN_TEST C18 1 AD8330 5 C8 0.1µF 5 12 R1 12pF 6 INLO OPLO OUT_ LO C5 24.9Ω 0.1µF UP C10 +5V 0.1µF 6 11 GAIN_SLOPE MODE CMOP C16 DOWN 10nF 7 10 VDBS VDBS VMAG VMAG –5V C7 C6 0.1µF 0.1µF C17 C20 8 9 10µF + 0.1µF CMGN COMM 10V CMGN Figure 70. Schematic Diagram Rev. E | Page 28 of 32 03217-070 03217-071 AD8330 OPTIONS MEASUREMENT SETUP Table 6 lists the jumpers on the board and their functions. The basic board connections for a typical measurement are shown in Figure 71. To minimize circuit-loading effects, a low Table 6. Functions of Jumpers capacitance FET probe is recommended for observing input or Name Function output waveforms. Two-pin headers, IN_TEST and OUT_TEST, FLTR Connects a high-pass filter to the offset control loop are provided for this purpose. The SMA connectors OUT_HI pin. This jumper is normally not installed. and OUT_LO can also be used, but the user may need to OFST Disables the offset correction loop. This jumper is account for load capacitance effects. installed for dc or low frequency operation. UP Mode up. Install for ascending gain with increasing AD8330-EVALZ BOARD DESIGN VDBS gain control voltage. The AD8330-EVALZ is a 4-layer design for maximum ground- DOWN Mode down. Install for descending gain with plane area. The evaluation board side silkscreen and wiring increasing VDBS gain control voltage. patterns are shown in Figure 72 through Figure 77. NETWORK ANALYZER PROBE POWER SUPPLY SIGNAL DIFFERENTIAL INPUT PROBE +5V POWER SUPPLY GND PRECISION VOLTAGE REFERENCES (FOR VDBS, VMAG) Figure 71. Typical Connections Rev. E | Page 29 of 32 03217-072 AD8330 Figure 72. Component-Side Silkscreen Figure 75. Wiring-Side Silkscreen Figure 73. Component-Side Wiring Figure 76. Wiring-Side Pattern Figure 74. Ground Plane Figure 77. Inner Layer 2 Rev. E | Page 30 of 32 03217-075 03217-074 03217-073 03217-078 03217-077 03217-076 AD8330 OUTLINE DIMENSIONS 0.50 0.40 0.60 MAX 0.30 3.00 BSC SQ BOTTOM VIEW * 1.65 13 16 0.45 12 1 1.50 SQ PIN 1 2.75 1.35 TOP EXPOSED INDICATOR BSC SQ VIEW PAD 9 4 0.50 8 5 BSC 0.25 MIN 1.50 REF 0.80 MAX 12° MAX 0.65 TYP 0.90 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.85 THE PIN CONFIGURATION AND 0.05 MAX 0.80 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. SEATING 0.30 PLANE 0.20 REF 0.23 0.18 * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 78. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters 0.197 0.193 0.189 16 9 0.158 0.154 0.244 0.150 1 0.236 8 0.228 PIN 1 0.069 0.065 0.053 0.049 8° 0.010 0.025 0.012 0° 0.050 0.004 SEATING 0.010 BSC 0.008 0.016 PLANE COPLANARITY 0.006 0.004 COMPLIANT TO JEDEC STANDARDS MO-137-AB Figure 79. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches Rev. E | Page 31 of 32 PIN 1 INDICATOR 071708-A AD8330 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8330ACPZ-R2 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 JFZ AD8330ACPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 JFZ AD8330ACPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-3 JFZ AD8330ARQ −40°C to +85°C 16-Lead QSOP RQ-16 AD8330ARQ-REEL −40°C to +85°C 16-Lead QSOP RQ-16 AD8330ARQ-REEL7 −40°C to +85°C 16-Lead QSOP RQ-16 AD8330ARQZ −40°C to +85°C 16-Lead QSOP RQ-16 AD8330ARQZ-RL −40°C to +85°C 16-Lead QSOP RQ-16 AD8330ARQZ-R7 −40°C to +85°C 16-Lead QSOP RQ-16 AD8330-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03217-0-3/10(E) Rev. E | Page 32 of 32