ANALOG DEVICES AD8327

5 V CATV Line Driver Coarse Step a Output Power Control AD8327 FEATURES FUNCTIONAL BLOCK DIAGRAM Supports DOCSIS Standard for Reverse Path V (5 PINS) BYP CC Transmission Gain Programmable in 6.02 dB Steps over a 48.16 dB R1 AD8327 Range Low Distortion at 60 dBmV Output V IN+ DIFF OR –63 dBc SFDR at 21 MHz POWER VERNIER ATTENUATION V SINGLE OUT AMP CORE INPUT –57 dBc SFDR at 42 MHz V IN– AMP Output Noise Level 8 Z = 75� OUT –47 dBmV in 160 kHz DECODE R2 Maintains 75 � Output Impedance Z (SINGLE) = 800� IN 8 POWER-DOWN CXR Transmit Enable and Transmit Disable Modes Z (DIFF) = 1.6k� IN LOGIC DATA LATCH Upper Bandwidth: 160 MHz (Full Gain Range) 8 5 V Supply Operation SHIFT Supports SPI Interfaces REGISTER APPLICATIONS Gain-Programmable Line Driver DATEN DATA CLK GND (5 PINS) TXEN SLEEP DOCSIS High-Speed Data Modems Interactive Cable Set-Top Boxes PC Plug-in Cable Modems General-Purpose Digitally Controlled Variable Gain Block –50 GENERAL DESCRIPTION V = 60dBmV @ MAX GAIN OUT The AD8327 is a low-cost, digitally controlled, variable gain amplifier optimized for coaxial line driving applications such as –55 cable modems that are designed to the MCNS-DOCSIS HD3 upstream standard. An 8-bit serial word determines the desired –60 output gain over a 48.16 dB range resulting in gain changes of 6.02 dB/major carry. HD2 –65 The AD8327 comprises a digitally controlled variable attenuator of 0 dB to –48.16 dB, which is preceded by a low noise, fixed gain buffer and followed by a low distortion, high power amplifier. –70 The AD8327 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load, such as coaxial cable. –75 5 152535455565 Distortion performance of –63 dBc is achieved with an output FUNDAMENTAL FREQUENCY – MHz level up to 60 dBmV at 21 MHz bandwidth. A key performance Figure 1. Harmonic Distortion vs. Frequency and cost advantage of the AD8327 results from the ability to maintain a constant 75 Ω output impedance during Transmit Enable and Transmit Disable conditions. In addition, this device has a sleep mode function that reduces the quiescent current to 5 mA. The AD8327 is packaged in a low-cost 20-lead TSSOP, operates from a single 5 V supply, and has an operational temperature range of –40°C to +85°C. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001 DISTORTION – dBc AD8327–SPECIFICATIONS (T = 25�C, V = 5 V, R = 75 �, V = 30 dBmV) A S L IN(DIFFERENTIAL) Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Specified AC Voltage P = 60 dBmV, Max Gain 30 dBmV OUT Noise Figure Max Gain, f = 10 MHz 13.2 dB Input Resistance Single-Ended Input 800 Ω Differential Input 1600 Ω Input Capacitance 2pF GAIN CONTROL INTERFACE Gain Range 47.16 48.16 49.16 dB Maximum Gain Gain Code = 10000000 (128 Decimal) 29 30 31 dB Minimum Gain Gain Code = 00000000 (0 Decimal) –19.16 –18.16 –17.16 dB Gain Scaling Factor 6.02 dB/Major Carry OUTPUT CHARACTERISTICS Bandwidth (–3 dB) All Gain Codes 160 MHz Bandwidth Roll-Off f = 65 MHz 0.4 dB Bandwidth Peaking All Gain Codes 0 dB Output Noise Spectral Density Max Gain, f = 10 MHz –32 dBmV in 160 kHz Min Gain, f = 10 MHz –47 dBmV in 160 kHz Transmit Disable Mode (TXEN = 0), –66 dBmV in f = 10 MHz 160 kHz 1 dB Compression Point Max Gain, f = 10 MHz 14.8 dBm Differential Output Impedance Transmit Enable (TXEN = 1) and Transmit Disable Mode (TXEN = 0) 75 ± 20% Ω OVERALL PERFORMANCE Second Order Harmonic Distortion f = 21 MHz, V = 60 dBmV @ Max Gain –63 dBc OUT f = 42 MHz, V = 60 dBmV @ Max Gain –61 dBc OUT f = 65 MHz, V = 60 dBmV @ Max Gain –54 dBc OUT Third Order Harmonic Distortion f = 21 MHz, V = 60 dBmV @ Max Gain –63 dBc OUT f = 42 MHz, V = 60 dBmV @ Max Gain –57 dBc OUT f = 65 MHz, V = 60 dBmV @ Max Gain –57 dBc OUT Adjacent Channel Power Adjacent Channel Width = Transmit Channel –62 dBc Width = 160 K SYM/SEC Gain Linearity Error f = 10 MHz, Code to Code ±0.25 dB Output Settling Due to Gain Change (T ) Min to Max Gain 60 ns GS Due to Input Change Max Gain, V = 30 dBmV 30 ns IN Isolation in Transmit Disable Mode Max Gain, TXEN = 0 V, f = 42 MHz, –52 dBc V = 30 dBmV IN POWER CONTROL 1 Transmit Enable Settling Time (T ) Max Gain, V = 0 V 300 ns ON IN 1 Transmit Disable Settling Time (T ) Max Gain, V = 0 V 40 ns OFF IN 2 Transmit Enable Settling Time (T ) Max Gain, V = 0 V 2 µs ON IN 2 Transmit Disable Settling Time (T ) Max Gain, V = 0 V 1.7 µs OFF IN 2 Between Burst Transients Equivalent Output = 31 dBmV 3 mV p-p Equivalent Output = 60 dBmV 25 mV p-p 2 Ramp Setting 2 µs POWER SUPPLY Operating Range 4.75 5 5.25 V Quiescent Current Transmit Enable Mode (TXEN = 1) @ Dec 128 75 105 135 mA Transmit Enable Mode (TXEN = 1) @ Dec 0 40 60 80 mA Transmit Disable Mode @ All Gain Codes 10 15 20 mA Sleep Mode @ All Gain Codes 3 5 7 mA OPERATING TEMPERATURE –40 +85 °C RANGE NOTES 1 For Transmit Enable or Transmit Disable transitions using a 0 pF capacitor (at CXR pin) to ground. 2 For Transmit Enable or Transmit Disable transitions using a 100 pF capacitor (at CXR pin) to ground. Specifications subject to change without notice. –2– REV. 0 AD8327 LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V = 5 V: Full Temperature Range) CC Parameter Min Typ Max Unit Logic “1” Voltage 2.1 5.0 V Logic “0” Voltage 0 0.8 V Logic “1” Current (V = 5 V) CLK, SDATA, DATEN020nA INH Logic “0” Current (V = 0 V) CLK, SDATA, DATEN –600 –100 nA INL Logic “1” Current (V = 5 V) TXEN 50 190 µA INH Logic “0” Current (V = 0 V) TXEN –250 –30 µA INL Logic “1” Current (V = 5 V) SLEEP 50 190 µA INH Logic “0” Current (V = 0 V) SLEEP –250 –30 µA INL TIMING REQUIREMENTS (Full Temperature Range, V = 5 V, t = t = 4 ns, f = 8 MHz unless otherwise noted.) CC R F CLK Parameter Min Typ Max Unit Clock Pulsewidth (t ) 16.0 ns WH Clock Period (t ) 32.0 ns C Setup Time SDATA vs. Clock (t ) 5.0 ns DS Setup Time DATEN vs. Clock (t ) 15.0 ns ES Hold Time SDATA vs. Clock (t ) 5.0 ns DH Hold Time DATEN vs. Clock (t ) 3.0 ns EH Input Rise and Fall Times, SDATA, DATEN, Clock (t , t)10ns R F t DS VALID DATA WORD G1 VALID DATA WORD G2 SDATA MSB. . . .LSB t C t WH CLK t t ES EH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) t OFF TXEN t GS t ON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB-1 MSB-2 t t DS DH CLK Figure 3. SDATA Timing REV. 0 –3– AD8327 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION Supply Voltage +V S SDATA 1 20 DATEN Pins 4, 6, 11, 12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V CLK 2 19 SLEEP Input Voltages TXEN 3 18 V IN– Pins 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V V 4 17 V CC IN+ Pins 1, 2, 3, 19, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V AD8327 GND 5 16 V CC Internal Power Dissipation TOP VIEW (Not to Scale) V 6 15 CC GND TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 mW 7 14 CXR BYP Operating Temperature Range . . . . . . . . . . . –40°C to +85°C 8 13 GND GND Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C 9 12 V GND CC Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C V 10 11 V OUT CC *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. 2 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 3 TXEN Logic “0” disables transmission. Logic “1” enables transmission. Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin. 4, 6, 11, 12, 16 V CC 5, 8, 9, 13, 15 GND Common External Ground Reference 7 CXR Transmit Enable/Disable Timing Capacitor. This pin is decoupled with a 100 pF capacitor to GND. Output Signal 10 V OUT 14 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor). 17 V Noninverting Input. DC-biased to approximately V /2. Should be ac-coupled with a 0.1 µF IN+ CC capacitor. 18 V Inverting Input. DC-biased to approximately V /2. Should be ac-coupled with a 0.1 µF capacitor. IN– CC 19 SLEEP Low Power Sleep Mode. Logic 0 enables Sleep mode, where Z goes to 200 Ω and supply OUT current is reduced to 5 mA. Logic 1 enables normal operation. 20 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. ORDERING GUIDE Model Temperature Range Package Description � Package Option JA AD8327ARU –40°C to +85°C 20-Lead TSSOP 85°C/W* RU-20 AD8327ARU-REEL –40°C to +85°C 20-Lead TSSOP 85°C/W* RU-20 AD8327-EVAL Evaluation Board *Thermal Resistance measured on SEMI standard 4-layer board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8327 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. –4– REV. 0 Typical Performance Characteristics–AD8327 0 TXEN = 0 +V S –10 V = 30dBmV IN 10�F –20 –30 0.1�F –40 0.1�F V CC V –50 IN– V 165� AD8327 IN –60 0.1�F V IN+ –70 75� MAX GAIN BYP CXR GND 0.1�F –80 0.1�F 100pF MIN GAIN –90 100 1 10 1000 FREQUENCY – MHz TPC 4. Isolation in Transmit Disable Mode TPC 1. Basic Test Circuit vs. Frequency 40 0.6 f = 65MHz 128D 0.5 30 64D 0.4 32D 20 0.3 16D f = 42MHz 10 0.2 08D 04D 0.1 0 02D 0 f = 10MHz –10 01D –0.1 00D f = 5MHz –20 –0.2 –30 –0.3 1 10 0 16 32 48 64 80 96 112 128 100 1000 FREQUENCY – MHz GAIN CONTROL – Decimal Code TPC 2. Gain Error vs. Gain Control TPC 5. AC Response 160 90 155 TXEN = 0 85 150 TXEN = 0 TXEN = 1 80 145 TXEN = 1 75 140 135 70 +V S 0.1�F 130 V 65 IN– 125 165� OUT VIN AD8327 0.1�F V GND 60 IN+ 75� 120 0.1�F 55 115 1 10 100 1 10 100 FREQUENCY – MHz FREQUENCY – MHz TPC 3. Input Impedance vs. Frequency TPC 6. Output Impedance vs. Frequency REV. 0 –5– IMPEDANCE – � GAIN ERROR – dB IMPEDANCE – � ISOLATION – dBc GAIN – dB AD8327 –50 –50 V = 60dBmV @ MAX GAIN OUT –55 V = 61dBmV @ MAX GAIN OUT V = 61dBmV OUT –55 @ MAX GAIN –60 V = 60dBmV OUT @ MAX GAIN –65 –60 V = 59dBmV @ MAX GAIN OUT –70 V = 59dBmV OUT @ MAX GAIN –65 –75 V = 58dBmV @ MAX GAIN OUT V = 58dBmV OUT @ MAX GAIN –80 –70 53 15 255 45 55 65 56 15 25 35 45 555 FUNDAMENTAL FREQUENCY – MHz FUNDAMENTAL FREQUENCY – MHz TPC 7. Second Order Harmonic Distortion vs. Frequency TPC 10. Third Order Harmonic Distortion vs. Frequency for Various Output Levels for Various Output Levels –50 –50 F = 5MHz F = 21MHz O O V = 60dBmV @ MAX GAIN V = 60dBmV @ MAX GAIN –55 OUT OUT –55 –60 –60 –65 –65 HD2 HD2 –70 –70 –75 –75 HD3 –80 –80 HD3 –85 –85 –90 –90 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 GAIN CONTROL – Decimal Code GAIN CONTROL – Decimal Code TPC 8. Harmonic Distortion vs. Gain Control TPC 11. Harmonic Distortion vs. Gain Control –50 –50 F = 65MHz F = 42MHz O O V = 60dBmV @ MAX GAIN –55 OUT V = 60dBmV @ MAX GAIN –55 OUT HD2 –60 –60 HD2 –65 –65 HD3 –70 –70 –75 –75 HD3 –80 –80 –85 –85 –90 –90 04 16 328 64 80 96 112 128 0 16 32 48 64 80 96 112 128 GAIN CONTROL – Decimal Code GAIN CONTROL – Decimal Code TPC 9. Harmonic Distortion vs. Gain Control TPC 12. Harmonic Distortion vs. Gain Control –6– REV. 0 DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc AD8327 –10 60 CH PWR 9.0dBm V = 60dBmV OUT 50 –20 ACP UP –62dBc @ MAX GAIN ACP LOW –62.5dBc 40 –30 –40 30 20 –50 10 –60 0 –70 –10 –80 –20 –90 Cu1 Cu1 C0 –30 –100 C0 C11 C11 –40 –110 CENTER 21MHz 75kHz/DIV SPAN 750kHz 41.0 41.2 41.4 41.6 41.8 42.0 42.2 42.4 42.6 42.8 43.0 FREQUENCY – MHz TPC 13. Adjacent Channel Power TPC 16. Two-Tone Intermodulation Distortion –30 –25 f = 10MHz @ MAX GAIN, TXEN = 1 –30 TXEN = 1 –34 –35 –40 –38 –45 @ MIN GAIN, TXEN = 1 –50 –42 –55 –60 –46 –65 ALL GAIN CODES, TXEN = 0 –70 –50 –75 0 16 32 48 64 80 96 112 128 56 15 25 35 45 555 GAIN CONTROL – Decimal Code FREQUENCY – MHz TPC 14. Output Referred Noise vs. Gain Control TPC 17. Output Referred Noise vs. Frequency for Various Gain Codes 35 120 V = 60dBmV OUT C = 0pF TXEN = 1 L @ MAX GAIN 110 30 C = 10pF L 100 25 +V S C = 20pF 90 L 10�F 80 0.1�F 20 0.1�F VCC V IN– 0.1�F 70 VIN 165� AD8327 CL 15 V IN+ 75� BYP CXR GND 0.1�F 60 0.1�F 100pF C = 50pF L 10 50 100 1 10 1000 0 16 32 48 64 80 96 112 128 FREQUENCY – MHz GAIN CONTROL – Decimal Code TPC 15. AC Response for Various Capacitor Loads TPC 18. Supply Current vs. Gain Code REV. 0 –7– OUTPUT NOISE – dBmV in 160kHz GAIN – dB QUIESCENT SUPPLY CURRENT – mA V – dBmV OUTPUT NOISE – dBmV in 160kHz OUT AD8327 APPLICATIONS which amplifies these currents to the appropriate levels necessary to General Application drive a 75 Ω load. The output stage maintains 75 Ω output The AD8327 is primarily intended for use as the upstream power impedance, eliminating the need for external matching resistors. amplifier (PA), also known as a line driver, in DOCSIS (Data SPI Programming and Gain Adjustment Over Cable Service Interface Specification) certified cable The AD8327 is controlled through a serial peripheral interface modems and CATV set-top boxes. The upstream signal is either (SPI) of three digital data lines: CLK, DATEN, and SDATA. a QPSK or QAM signal generated by a DSP, a dedicated QPSK/ Changing the gain requires eight bits of data to be streamed into QAM modulator, or a DAC. the SDATA port. The sequence of loading the SDATA register In all cases the signal must be low-pass filtered before being begins on the falling edge of the DATEN pin, which activates applied to the PA in order to filter out-of-band noise and higher the CLK line. With the CLK line activated, data on the SDATA order harmonics from the amplified signal. Due to the varying line is clocked into the serial shift register, Most Significant Bit distances between the cable modem and the headend, the (MSB) first, on the rising edge of the CLK pulses. The 8-bit upstream PA must be capable of varying the output power by data word is latched into the attenuator core on the rising edge applying gain or attenuation. The varying output power of the of the DATEN line. This provides control over the changes in AD8327 ensures that the signal from the cable modem will have the output signal level. The serial interface timing for the AD8327 the proper level once it arrives at the headend. The upstream is shown in Figures 2 and 3. The programmable gain range of signal path commonly includes a diplexer and cable splitters. the AD8327 is –18.16 dB to +30 dB with steps of 6.02 dB per The AD8327 has been designed to overcome losses associated major carry. This provides a total gain range of 48.16 dB. with these passive components in the upstream cable path. The AD8327 was characterized with a TOKO transformer (TOKO#617DB-A0070) on the input, and the stated gain Circuit Description values account for the losses due to the transformer. Table I The AD8327 is composed of three analog functions in the power- shows the possible gain states. up or forward mode. The input amplifier (preamp) can be used single-ended or differentially. If the input is used in the differen- Input Bias, Impedance, and Termination tial configuration, it is imperative that the input signals be 180 The V and V inputs have a dc bias level of V /2, therefore IN+ IN– CC degrees out of phase and of equal amplitude. The preamp stage the input signal should be ac-coupled using 0.1 µF capacitors as drives a DAC, which provides the AD8327’s attenuation (eight seen in the typical application circuit (see Figure 4). The differ- bits or 48.16 dB). The signals in the preamp and DAC gain ential input impedance of the AD8327 is approximately 1.6 kΩ, blocks are differential to improve the PSRR and linearity. while the single-ended input impedance is 800 Ω. A differential current is fed from the DAC into the output stage, Table I. Gain States Decimal Code Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Gain 0 00000000 –18.16 1 00000001 –12.14 2 00000010 –6.12 4 00000100 –0.10 8 000010005.92 16 00010000 11.94 32 00100000 17.96 64 01000000 23.98 128 1000000030 –8– REV. 0 AD8327 V CC 10�F SLEEP ENB 0.1�F AD8327 1 20 V IN– SDATA SDATA ENB 2 19 CLK CLK SLEEP 3 18 Z = 150� IN TXEN TXEN V IN– 165� 4 17 0.1�F V V CC IN+ 5 16 0.1�F GND V CC 0.1�F 6 15 V GND 0.1�F CC V IN+ 7 14 100pF CXR BYP 0.1�F 8 13 GND GND 12 9 GND V 0.1�F CC 11 10 V V 0.1�F OUT CC 0.1�F TO DIPLEXER Z = 75� IN Figure 4. Typical Application Circuit Z � 1600� IN Single-Ended Inverting Input R13 = 1600� – Z IN When operating the AD8327 in a single-ended input mode V IN+ and V should be terminated as illustrated in Figure 5. On the IN– V + IN AD8327 evaluation boards, this termination method requires R13 AD8327 the removal of R13–R16 and R20, as well as the addition of a 0 Ω Z IN jumper at R17. Table II shows the correct values for R11 and R12 for some common input configurations. Other input imped- Figure 6. Single to Differential Input ance configurations may be accommodated using the equations Differential Signal Source in Figure 5. The inverting and noninverting inputs of the AD8327 The AD8327 evaluation board is also capable of accepting a must be balanced for all input configurations differential input signal. Remove R11–R12, R14–R15, and R20, Z � 800� Z � R12 IN IN R12 = R11 = and place 0 Ω jumpers for R16–R17. See Table II for common 800� – Z R12 + Z IN IN values of R13, or calculate other input configurations using the – equation in Figure 7. R12 AD8327 + Z � 1600� IN Z R13 = IN 1600� – Z R11 IN V + IN Figure 5. Single-Ended Inverting Input R13 Z AD8327 IN Differential Input from Single-Ended Source V – IN The default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. A Figure 7. Differential Input TOKO 1:1 transformer is included on the board for this purpose Output Bias, Impedance, and Termination (T3). Enabling the evaluation board for single to differential input The output of the AD8327 has a dc bias level of approximately conversion requires R11–R12 and R16–R17 to be removed, and V /2; therefore, it should be ac-coupled before being applied to 0 Ω jumpers must be installed on the placeholders for R14, R15, CC the load. The output impedance of the AD8327 is internally and R20. Table II provides typical R13 values for common maintained at 75 Ω, regardless of whether the amplifier is in input configurations. Other input impedances may be calculated transmit enable or transmit disable mode. This eliminates the using the equation in Figure 6. Refer to Figure 10 for evaluation need for external back termination resistors. If the output signal board schematic. To utilize the transformer for converting a single- is being evaluated using standard 50 Ω test equipment, a mini- ended source into a differential signal, the input signal must mum loss 75 Ω to 50 Ω pad must be used to provide the test be applied to V . IN+ circuit with the proper impedance match. REV. 0 –9– AD8327 Asynchronous Power-Down Table II. Common Input Terminations The asynchronous TXEN pin is used to place the AD8327 into Differential Input Termination between-burst mode, while maintaining a differential output ZIN (�) R11 R12 R13 (�) impedance of 75 Ω. Applying Logic 0 to the TXEN pin activates the on-chip reverse amplifier, providing an 86% reduction in 50 Open Open 52.1 consumed power. For 5 V operation, the supply current is typically 75 Open Open 78.7 reduced from 105 mA to 15 mA. In this mode of operation, 100 Open Open 107 between-burst noise is minimized and the amplifier can no longer 150 Open Open 165 transmit in the upstream direction. In addition to the TXEN Single-Ended Input Termination pin, the AD8327 also incorporates an asynchronous SLEEP pin, which may be used to further reduce the supply current to ZIN (�) R11 (�) R12 (�) R13 approximately 5 mA. Applying Logic 0 to the SLEEP pin places 50 25.5 53.6 Open the amplifier into SLEEP mode. Transitioning into or out of 75 39.2 82.5 Open SLEEP mode may result in a transient voltage at the output of the amplifier. Power Supply Distortion, Adjacent Channel Power, and DOCSIS The 5 V supply should be delivered to each of the V pins via a CC In order to deliver the DOCSIS required +58 dBmV of QPSK low impedance power bus to ensure that each pin is at the same signal and +55 dBmV of 16 QAM signal, the PA is required to potential. The power bus should be decoupled to ground using deliver up to +60 dBmV and +57 dBmV respectively. This level is a 10 µF tantalum capacitor located close to the AD8327ARU. required to compensate for losses associated with the diplex filter In addition to the 10 µF capacitor, each V pin should be CC or other passive components that may be included in the upstream individually decoupled to ground with 0.1 µF ceramic chip capaci- path of cable modems or set-top boxes. It should be noted that tors located close to the pins. The bypass pin, labeled BYP (Pin 14), the AD8327 was characterized with the TOKO 617DB-A0070 should also be decoupled with a 0.1 µF capacitor. The PCB transformer on the input to generate a differential input signal. should have a low impedance ground plane covering all unused TPC 7 and TPC 10 show the AD8327 second and third order portions of the board, except in areas of the board where input harmonic distortion performance versus fundamental frequency and output traces are in close proximity to the AD8327. All for various output power levels. These figures are useful for AD8327 ground pins must be connected to the ground plane to determining the in-band harmonic levels from 5 MHz to 65 MHz. ensure proper grounding of all internal nodes. Harmonics higher in frequency (above 42 MHz for DOCSIS and above 65 MHz for EuroDOCSIS) will be sharply attenuated CXR Pin by the low-pass filter function of the diplexer. The AD8327 features internal circuitry that controls burst transients. This feature uses a 100 pF capacitor connected to Another measure of signal integrity is adjacent channel power, Pin 7 of the AD8327, to slow down the turn-on transient and commonly referred to as ACP. DOCSIS section 4.2.10.1.1 states, minimize between-burst transients. “Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or Signal Integrity Layout Considerations different symbol rates.” TPC 13 shows the measured ACP for a Careful attention to printed circuit board layout details will +57 dBmV 16 QAM signal taken at the output of the AD8327 prevent problems due to board parasitics. Proper RF design evaluation board, through a 75 Ω to 50 Ω matching pad (5.7 dB of techniques are mandatory. The differential input and output loss). The transmit channel width and adjacent channel width in traces should be kept as short as possible. It is also critical that TPC 13 correspond to symbol rates of 160 K . Table III shows SYM/S all differential signal paths be symmetrical in length and width. the ACP results for the AD8327 driving a 16 QAM, +57 dBmV In addition, the input and output traces should be kept far apart, signal for all conditions in DOCSIS Table 4-7 “Adjacent Channel to minimize coupling (crosstalk) through the board. Following Spurious Emissions.” these guidelines will optimize the overall performance of the AD8327 in all applications. Table III. Adjacent Channel Power Initial Power-Up ADJACENT CHANNEL SYMBOL RATE When the supply voltage is first applied to the AD8327, the gain 160 K 320 K 640 K 1280 K 2560 K of the amplifier is initially set to gain code 0. As power is first SYM/SEC SYM/SEC SYM/SEC SYM/SEC SYM/SEC TRANSMIT ACP ACP ACP ACP ACP SYMBOL applied to the amplifier, the TXEN pin should be held low RATE (dBc) (dBc) (dBc) (dBc) (dBc) (Logic 0) to prevent forward signal transmission. After power 160 K –62 –63 –65 –66 –66 SYM/SEC has been applied to the amplifier, the gain can be set to the 320 K –62 –63 –64 –66 –66 SYM/SEC desired level by following the procedure provided in the SPI 640 K –63 –62 –63 –65 –66 SYM/SEC Programming and Gain Adjustment section. The TXEN pin 1280 K can then be brought from Logic 0 to Logic 1, enabling forward –64 –63 –63 –63 –64 SYM/SEC signal transmission at the desired gain level. 2560 K –66 –63 –63 –62 –63 SYM/SEC –10– REV. 0 AD8327 Noise and DOCSIS Running AD8327 Software At minimum gain, the AD8327 output noise spectral density is To load the control software, go to START, PROGRAMS, 11 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8,“Spurious CABDRIVE_27, or select the AD8327.exe from the installed Emissions in 5 MHz to 42 MHz,” specifies the output noise for directory. Once loaded, select the proper parallel port to com- various symbol rates. The calculated noise in dBmV for municate with the AD8327 (Figure 8). 160 is: KSYM/SECOND    2  11nV      20 log ×160 kHz += 60 –47 dBmV         Hz       Comparing the computed noise power of –47 dBmV to the +8 dBmV signal yields –55 dBc, which meets the required level set forth in DOCSIS Table 4-8. As the AD8327 gain is increased above this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal to noise ratio that improves with gain. In transmit disable mode, the output noise spectral density is 1.3 nV/√Hz, which results in –66 dBmV when computed . The noise power was measured directly at the over 160 K SYM/S output of the AD8327AR-EVAL board. Evaluation Board Features and Operation The AD8327 evaluation board (Part #AD8327AR-EVAL) and control software can be used to control the AD8327 upstream Figure 8. Parallel Port Selection cable driver via the parallel port of a PC. A standard printer Controlling Gain/Attenuation of the AD8327 cable connected between the parallel port of the personal com- The slide bar controls the gain/attenuation of the AD8327, puter is used to feed all the necessary data to the AD8327 using which is displayed in dB and in V/V. The gain scales 6 dB per the Windows-based control software. This package provides a major carry. The gain code from the position of the slide bar is means of evaluating the amplifier with a convenient way to displayed in decimal, binary, and hexadecimal (Figure 9). program the gain/attenuation, as well as offering easy control of the asynchronous TXEN and SLEEP pins. With this evaluation kit, the AD8327 can be evaluated in either a single-ended or differential input configuration. A schematic of the evaluation board is provided in Figure 10. Overshoot on PC Printer Ports The data lines on some PC parallel printer ports have excessive overshoot that may cause communications problems when pre- sented to the CLK pin of the AD8327. The evaluation board was designed to accommodate a series resistor and shunt capaci- tor (R2 and C5 in Figure 10) to filter the CLK signal if required. Installing Visual Basic Control Software Install the “CabDrive_27” software by running “setup.exe” on disk one of the AD8327 Evaluation Software. Follow on-screen directions and insert disk two when prompted. Choose installa- tion directory, and then select the icon in the upper left to complete installation. Figure 9. Control Software Interface REV. 0 –11– AD8327 Transmit Enable and Sleep Mode Memory Functions The Transmit Enable and Transmit Disable buttons select the The MEMORY section of the software provides a way to mode of operation of the AD8327 by asserting logic levels on alternate between two gain settings. The “X->M1” button the asynchronous TXEN pin. The Transmit Disable button stores the current value of the gain slide bar into memory applies Logic 0 to the TXEN pin, disabling forward transmis- while the “RM1” button recalls the stored value, returning sion while maintaining a 75 Ω back termination. The Transmit the gain slide bar to the stored level. The same applies to the Enable button applies Logic 1 to the TXEN pin, enabling the “X->M2” and “RM2” buttons. AD8327 for forward transmission. Checking the “Enable SLEEP Mode” checkbox applies logic “0” to the asynchronous SLEEP pin, setting the AD8327 for SLEEP mode. DATEN V TP9 CC TP10 SDATA TP11 C12 TP12 10�F C16 TP23 R17 R19 CLK AGND 0.1�F DNI DNI AGND C11 Z1 V IN– 0.1�F R12 R21 1 SDATADATEN 20 R15 TXEN AGND DNI DNI 0� 2 CLK SLEEP 19 3 TXEN V 18 SLEEP 4 3 4 6 IN– T4 T3 AGND AGND 4 V V 17 CC IN+ 2 2 5 GND 16 V CC 5 1 3 1 6 GND 15 V CC R13 7 BYP 14 TP1 CXR 78.7� PRI SEC PRI SEC C1 8 GND GND 13 0.1�F DNI C10 TOKO1 R20 TP24 C15 9 GND V 12 CC 0.1�F R14 0� 0.1�F 10 V 11 V CC 0� OUT C2 V TP2 IN+ 0.1�F C8 R16 R11 TSSOP20 0.1�F DNI DNI C7 TP22 0.1�F AGND AGND C3 0� 100pF HPF TP4 TP3 9 AGND R1 0� TB1 HPP TP6 V AGND CC 1 5 LPP CBL TP21 DEVICE = 2LUGPWR P1 19 COM P1 1 P1 20 3 CX6002 10–18 P1 2 P1 21 C4 DNI P1 3 DNI P1 22 AGND TP5 P1 4 P1 23 R6 P1 5 TP14 TP16 R8 P1 24 DNI R7 TP20 P1 6 DNI R2 P1 25 0� C5 P1 7 0� P1 26 DNI CABLE P1 8 P1 27 C14 P1 9 0.1�F P1 28 P1 10 P1 29 R9 R10 TP7 TP8 P1 11 R3 0� DNI P1 30 0� P1 12 P1 31 P1 13 C6 P1 32 TP15 P1 14 DNI R5 AGND P1 33 DNI P1 15 P1 34 P1 16 P1 35 P1 17 AGND P1 36 P1 18 AGND Figure 10. Evaluation Board Schematic –12– REV. 0 AD8327 Figure 11. Evaluation Board Layout—Top Silkscreen REV. 0 –13– AD8327 Figure 12. Evaluation Board Layout—Component Side –14– REV. 0 AD8327 Figure 13. Evaluation Board Layout—Internal Ground Plane REV. 0 –15– AD8327 Figure 14. Evaluation Board Layout—Internal Power and Ground Plane –16– REV. 0 AD8327 Figure 15. Evaluation Board Layout—Circuit Side REV. 0 –17– AD8327 Figure 16. Evaluation Board Layout—Bottom Silkscreen –18– REV. 0 AD8327 EVALUATION BOARD BILL OF MATERIALS AD8327 Evaluation Board Rev. B, Single-Ended-to-Differential Input—Revised–February 21, 2001 Qty. Description Ref Description 1 10 µF 25 V. ‘D’ size tantalum chip capacitor C12 1 100 pF 0603 ceramic chip capacitor C3 2 0.1 µF 50 V. 1206 size ceramic chip capacitor C15, C16 7 0.1 µF 25 V. 0603 size ceramic chip capacitor C1, C2, C7–C11 11 0 Ω 5% 1/8 W. 1206 size chip resistor R1–R3, R7, R9, R14, R15, R20 1 78.7 Ω 1% 1/8 W. 1206 size chip resistor R13 2 Yellow Test Point TP23, TP24 1 Red Test Point TP9 1 Black Test Point TP10–TP12 (GND) 1 Centronics-type 36-pin Right-Angle Connector P1 1 Terminal Block 2-Pos Green ED1973-ND TB1 4 SMA End launch Jack (E F JOHNSON # 142-0701-801) V , V , CABLE_0, HPF IN– IN+ 1 1:1 Transformer TOKO # 617DB – A0070 T3 1 PULSE Diplexer* Z2 1 AD8327 (TSSOP) UPSTREAM Cable Driver Z1 1 AD8327 REV. C Evaluation PC board Evaluation PC board 4#4–40 × 1/4 inch STAINLESS panhead machine screw 4#4–40 × 3/4 inch long aluminum round stand-off 2# 2–56 × 3/8 inch STAINLESS panhead machine screw (P1 Hardware) 2 # 2 steel flat washer (P1 Hardware) 2 # 2 steel internal tooth lockwasher (P1 Hardware) 2 # 2 STAINLESS STEEL hex. machine nut (P1 Hardware) NOTES *PULSE Diplexer part numbers B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz). DO NOT INSTALL C4, C5, C6, R6, R7, R8, R10–R12, R16, R17, R21, T9, TP1–TP8, TP14–TP16, TP20–TP22. SMA’s TXEN, CLK, SLEEP, DATEN, SDATA, HPF_0, Z2. REV. 0 –19– AD8327 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead TSSOP (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 10 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05) 8� 0.0256 (0.65) 0.0118 (0.30) 0� 0.028 (0.70) SEATING 0.0079 (0.20) BSC 0.0075 (0.19) 0.020 (0.50) PLANE 0.0035 (0.090) –20– REV. 0 PRINTED IN U.S.A. C02653–.8–10/01(0)