ANALOG DEVICES AD8326

High Output Power a Programmable CATV Line Driver AD8326 FEATURES FUNCTIONAL BLOCK DIAGRAM Supports DOCSIS Standard for Reverse Path V (7 PINS) BYP CC Transmission Gain Programmable in 0.75 dB Steps over a 53.5 dB Range AD8326 Low Distortion at 65 dBmV Output V IN+ V OUT+ –62 dBc SFDR at 21 MHz DIFF OR POWER ATTENUATION SINGLE VERNIER AMP –58 dBc SFDR at 65 MHz CORE INPUT V V IN– AMP OUT– 1 dB Compression of 25 dBm at 10 MHz Z DIFF = OUT 8 Output Noise Level 75� DECODE –45 dBmV in 160 kHz Z (SINGLE) = 800� IN 8 POWER-DOWN Maintains 75 � Output Impedance Z (DIFF) = 1.6k� IN LOGIC DATA LATCH Power-Up and Power-Down Condition Upper Bandwidth: 100 MHz (Full Gain Range) 8 SHIFT Single or Dual Supply Operation REGISTER APPLICATIONS Gain-Programmable Line Driver GND DATEN DATA CLK V (10 PINS) TXEN SLEEP EE CATV Telephony Modems CATV Terminal Devices General-Purpose Digitally Controlled Variable Gain Block – 40 ARP(V = +12V) S ARE(V = �5V) S – 45 – 50 ARP(V = 69dBmV) O – 55 ARP(V = 67dBmV) O GENERAL DESCRIPTION – 60 The AD8326 is a high-output power, digitally controlled, vari- ARE(V = 65dBmV) O – 65 able gain amplifier optimized for coaxial line driving applications such as data and telephony cable modems that are designed to – 70 the MCNS-DOCSIS upstream standard. An 8-bit serial word ARE(V = 62dBmV) O determines the desired output gain over a 53.5 dB range result- – 75 ing in gain changes of 0.75 dB/LSB. The AD8326 is offered in – 80 two models, each optimized to support the desired output power 5 15 25 35 45 55 65 and resulting performance. FREQUENCY – MHz The AD8326 comprises a digitally controlled variable attenuator Figure 1. Worst Harmonic Distortion vs. Frequency of 0 dB to –54 dB, that is preceded by a low noise, fixed-gain buffer and is followed by a low distortion high-power amplifier. The AD8326 accepts a differential or single-ended input signal. The differential output of the AD8326 is compliant with DOCSIS The output is designed to drive a 75 Ω load, such as coaxial paragraph 4.2.10.2 for “Spurious Emissions During Burst On/Off cable, although the AD8326 is capable of driving other loads. Transients.” In addition, this device has a sleep mode function When driving 67 dBm into a 75 Ω load, the AD8326ARP that reduces the quiescent current to 4 mA. provides a worst harmonic of only –59 dBc at 21 MHz and The AD8326 is packaged in a low-cost 28-lead TSSOP and a –57 dBc at 42 MHz. When driving 65 dBmV into a 75 Ω load, 28-lead P (power) SOIC. Both devices have an operational tem- the AD8326ARE provides a worst harmonic of only –62 dBc at perature range of –40°C to +85°C. 21 MHz and –60 dBc at 42 MHz. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2001 DISTORTION – dBc (T = 25�C, V = 12 V, R = R = 75 �, V = 259 mV p-p, V measured through a 1:1 A S L IN IN OUT AD8326–SPECIFICATIONS transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.) AD8326ARP Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Specified AC Voltage Output = 67 dBmV, Max Gain 259 mV p-p Noise Figure Max Gain, f = 10 MHz 16.6 dB Input Resistance Differential Input 1600 Ω Single-Ended Input 800 Ω Input Capacitance 2pF GAIN CONTROL INTERFACE Gain Range 52.5 53.5 54.5 dB Maximum Gain Gain Code = 71 Dec 26.5 27.5 28.5 dB Minimum Gain Gain Code = 0 Dec –27 –26 –25 dB Gain Scaling Factor 0.7526 dB/LSB Gain Linearity Error f = 10 MHz, Code-to-Code ±0.2 dB OUTPUT CHARACTERISTICS Bandwidth (–3 dB) All Gain Codes 100 MHz Bandwidth Roll-Off f = 65 MHz 1.2 dB Bandwidth Peaking f = 65 MHz 0 dB Output Noise Spectral Density Max Gain, f = 10 MHz –28 dBmV in 160 kHz Min Gain, f = 10 MHz –45.5 dBmV in 160 kHz Transmit Disable Mode, f = 10 MHz –65 dBmV in 160 kHz 1 dB Compression Point Max Gain, f = 10 MHz 26.5 dBm Differential Output Impedance Transmit Enable and Transmit Disable Mode 75 ± 20% Ω OVERALL PERFORMANCE = 67 dBmV @ Max Gain –59 dBc Worst Harmonic Distortion f = 14 MHz, V OUT f = 21 MHz, V = 67 dBmV @ Max Gain –59 dBc OUT f = 42 MHz, V = 67 dBmV @ Max Gain –57 dBc OUT = 67 dBmV @ Max Gain –55 dBc f = 65 MHz, V OUT Adjacent Channel Power 16 QAM, V = 67 dBmV –56 dBc OUT Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC Output Settling Due to Gain Change (T ) Min to Max Gain 60 ns GS Due to Input Step Change Max Gain, V = 0 V to 0.25 V p-p 30 ns IN = 0.25 V p-p –85 dBc Signal Isolation Min Gain, TXEN = 0, 65 MHz, V IN Max Gain, TXEN = 0, 42 MHz, V = 0.25 V p-p –31 dBc IN Max Gain, TXEN = 0, 65 MHz, V = 0.25 V p-p –28 dBc IN All Gains, SLEEP, 65 MHz, V = 0.25 V p-p –85 dBc IN POWER CONTROL Transmit Enable Response Time (t ) Max Gain, V = 0 250 ns ON IN Transmit Disable Response Time (t ) Max Gain, V = 0 40 ns OFF IN 1 Between Burst Transients Equivalent Output = 31 dBmV 5 mV p-p Equivalent Output = 61 dBmV 60 mV p-p POWER SUPPLY Operating Range 11.4 12 12.6 V Quiescent Current Transmit Enable Mode (TXEN = 1) 147 157 167 mA Transmit Disable Mode (TXEN = 0) 38 44 50 mA Sleep Mode 1.5 4.5 7.5 mA OPERATING TEMPERATURE –40 +85 °C RANGE NOTES 1 Between Burst Transients measured at the output of diplexer. Specifications subject to change without notice. –2– REV. 0 AD8326 (T = 25�C, V = �5 V, R = R = 75 �, V = 206 V p-p, V measured through a 1:1 A S L IN IN OUT SPECIFICATIONS transformer with an insertion loss of 0.5 dB @ 10 MHz, unless otherwise noted.) AD8326ARE Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Specified AC Voltage Output = 65 dBmV, Max Gain 206 mV p-p Noise Figure Max Gain, f = 10 MHz 16.6 dB Input Resistance Differential Input 1600 Ω Single-Ended Input 800 Ω Input Capacitance 2pF GAIN CONTROL INTERFACE Gain Range 52.5 53.5 54.5 dB Maximum Gain Gain Code = 71 Dec 26.5 27.5 28.5 dB Minimum Gain Gain Code = 0 Dec –27 –26 –25 dB Gain Scaling Factor 0.7526 dB/LSB Gain Linearity Error f = 10 MHz, Code-to-Code ±0.2 dB OUTPUT CHARACTERISTICS Bandwidth (–3 dB) All Gain Codes 100 MHz Bandwidth Roll-Off f = 65 MHz 1.1 dB Bandwidth Peaking f = 65 MHz 0 dB Output Noise Spectral Density Max Gain, f = 10 MHz –28 dBmV in 160 kHz Min Gain, f = 10 MHz –45.5 dBmV in 160 kHz Transmit Disable Mode, f = 10 MHz –65 dBmV in 160 kHz 1 dB Compression Point Max Gain, f = 10 MHz 25.0 dBm Differential Output Impedance Transmit Enable and Transmit Disable Mode 75 ± 20% Ω OVERALL PERFORMANCE Worst Harmonic Distortion f = 14 MHz, V = 65 dBmV @ Max Gain –62 dBc OUT = 65 dBmV @ Max Gain –62 dBc f = 21 MHz, V OUT f = 42 MHz, V = 65 dBmV @ Max Gain –60 dBc OUT f = 65 MHz, V = 65 dBmV @ Max Gain –58 dBc OUT = 65 dBmV –58 dBc Adjacent Channel Power 16 QAM, V OUT Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC Output Settling ) Min to Max Gain 60 ns Due to Gain Change (T GS Due to Input Step Change Max Gain, V = 0 V to 0.19 V p-p 30 ns IN Signal Isolation Min Gain, TXEN = 0, 65 MHz, V = 0.19 V p-p –85 dBc IN = 0.19 V p-p –31 dBc Max Gain, TXEN = 0, 42 MHz, V IN Max Gain, TXEN = 0, 65 MHz, V = 0.19 V p-p –28 dBc IN All Gains, SLEEP, 65 MHz, V = 0.19 V p-p –85 dBc IN POWER CONTROL Transmit Enable Response Time (t ) Max Gain, V = 0 250 ns ON IN Transmit Disable Response Time (t ) Max Gain, V = 0 40 ns OFF IN 1 Between Burst Transients Equivalent Output = 31 dBmV 5 mV p-p Equivalent Output = 61 dBmV 60 mV p-p POWER SUPPLY Operating Range ±4.75 ±5.0 ±5.25 V Quiescent Current Transmit Enable Mode (TXEN = 1) 140 150 160 mA Transmit Disable Mode (TXEN = 0) 36 42 48 mA Sleep Mode 1 4 7 mA OPERATING TEMPERATURE –40 +85 °C RANGE NOTES 1 Between Burst Transients measured at the output of diplexer. Specifications subject to change without notice. REV. 0 –3– AD8326 LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V = 12 V: Full Temperature Range) CC Parameter Min Typ Max Unit Logic “1” Voltage 2.1 5.0 V Logic “0” Voltage 0 0.8 V Logic “1” Current (V = 5 V) CLK, SDATA, DATEN020nA INH Logic “0” Current (V = 0 V) CLK, SDATA, DATEN –600 –100 nA INL Logic “1” Current (V = 5 V) TXEN 50 190 μA INH Logic “0” Current (V = 0 V) TXEN –250 –30 μA INL Logic “1” Current (V = 5 V) SLEEP 50 190 μA INH Logic “0” Current (V = 0 V) SLEEP –250 –30 μA INL Specifications subject to change without notice. TIMING REQUIREMENTS (Full Temperature Range, V = 12 V, t = t = 4 ns, f = 8 MHz unless otherwise noted.) CC R F CLK Parameter Min Typ Max Unit Clock Pulsewidth (t ) 16.0 ns WH Clock Period (t ) 32.0 ns C Setup Time SDATA vs. Clock (t ) 5.0 ns DS Setup Time DATEN vs. Clock (t ) 15.0 ns ES Hold Time SDATA vs. Clock (t ) 5.0 ns DH Hold Time DATEN vs. Clock (t ) 3.0 ns EH Input Rise and Fall Times, SDATA, DATEN, Clock (t , t)10ns R F Specifications subject to change without notice. t DS VALID DATA WORD G1 VALID DATA WORD G2 SDATA MSB. . . .LSB t C t WH CLK t t ES EH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) t OFF TXEN t GS t ON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB-1 MSB-2 t t DH DS CLK Figure 3. SDATA Timing –4– REV. 0 AD8326 ABSOLUTE MAXIMUM RATINGS* Supply Voltage V CC Pins 5, 9, 10, 19, 20, 23, 27 . For ARP, Max V = V + 13 V; CC EE . . . . . . . . . . . . . . . . . . . . . . . For ARE, Max V = V + 11 V CC EE Input Voltages Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 V Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V Internal Power Dissipation TSSOP EPAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W PSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 W Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description � Package Option JA AD8326ARP –40°C to +85°C 28-Lead Power SOIC with Slug 23°C/W* RP-28 AD8326ARP-REEL AD8326ARP-EVAL Evaluation Board AD8326ARE –40°C to +85°C 28-Lead TSSOP with Exposed Pad 39°C/W* RE-28 AD8326ARE-REEL AD8326ARE-EVAL Evaluation Board *Thermal Resistance measured on SEMI standard 4-layer board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8326 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. REV. 0 –5– AD8326 PIN CONFIGURATION 1 28 GND DATEN 2 SDATA 27 V CC 3 CLK 26 V IN– 4 GND 25 V IN+ 5 V 24 V CC EE 6 TXEN 23 V CC AD8326 7 22 V SLEEP EE TOP VIEW (Not to Scale) 8 NC 21 BYP 9 V 20 V CC CC 10 V 19 V CC CC 11 V 18 V EE EE 12 NC 17 NC 13 V 16 V EE EE 14 OUT– 15 OUT+ NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 2 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first and ignored. 3 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 4, 28 GND Common External Ground Reference 5, 9, 10, 19, V Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin. CC 20, 23, 27 6 TXEN Transmit Enable pin. Logic 1 powers up the part. 7 SLEEP Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A Logic 0 powers down the part (High Z State) and a Logic 1 powers up the part. OUT 8, 12, 17 NC No Connection to these pins. 11, 13, 16, 18, V Common Negative External Supply Voltage. A 0.1 μF capacitor must decouple each pin. EE 22, 24 14 OUT– Negative Output Signal 15 OUT+ Positive Output Signal 21 BYP Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor). 25 V Noninverting Input. DC-biased to approximately V /2. Should be ac-coupled with a IN+ CC 0.1 μF capacitor. 26 V Inverting Input. DC-biased to approximately V /2. Should be ac-coupled with a 0.1 μF capacitor. IN– CC –6– REV. 0 Typical Performance Characteristics–AD8326 V CC 10�F 0.1�F 0.1�F V CC 75� 0.1�F V IN+ OUT+ + +1/2 V IN C 165� AD8326 L 75� V O – 75� OUT– V 1:1 IN– 0.1�F TOKO 0.1�F V – 1/2 V BYP IN EE 617DB-A0070 0.1�F 0.1�F 10�F V EE TPC 1. Test Circuit 32.0 1.0 V = 12V S P = 67dBmV@ MAX GAIN V = 12V O S 30.5 P = 67dBmV @ MAX GAIN OUT 10MHz 0.5 29.0 C = 0pF L 5MHz 0 C = 10pF L 27.5 42MHz 26.0 – 0.5 C = 20pF L 24.5 C = 50pF L – 1.0 23.0 65MHz 21.5 – 1.5 1 10 100 0 9 18 27 36 45 54 63 72 GAIN CONTROL – Decimal FREQUENCY – MHz TPC 2. Gain Error vs. Gain Control TPC 4. AC Response for Various Capacitor Loads 40 – 26 V = 12V S V = 67dBmV @ MAX GAIN O f = 10MHz 30 TXEN = 1 – 30 71D V = 12V S 20 – 34 10 46D 0 – 38 – 10 23D – 42 – 20 – 46 00D – 30 – 40 – 50 0.1 1 10 100 1000 0 8 16 24 32 40 48 56 64 72 FREQUENCY – MHz GAIN CONTROL – Decimal TPC 3. AC Response TPC 5. Output Referred Noise vs. Gain Control REV. 0 –7– GAIN – dB GAIN ERROR – dB GAIN – dB OUTPUT NOISE – dBmV in 160 kHz AD8326 0 – 50 RBW 500Hz RF ATT 30dB CH PWR +12.27dBm V = 12V – 10 VBW 5kHz S ACP UP – 56.72dB – 55 SWT 20s UNIT dBm ACP LOW – 56.71dB f = 42MHz – 20 P = 67dBmV @ MAX GAIN O – 60 – 30 HD3 – 65 – 40 – 50 – 70 – 60 – 75 – 70 HD2 – 80 – 80 – 85 – 90 – 100 – 90 CENTER 21MHz 100kHz/ SPAN 1MHz 0 9 18 27 36 45 54 63 72 GAIN CODE – Decimal TPC 6. Harmonic Distortion vs. Gain Code for TPC 9. Adjacent Channel Power for AD8326-ARP AD8326-ARP – 50 190 V = 12V(ARP) S – 55 180 V = 69dBmV @ MAX GAIN – 60 O 170 V = 68dBmV @ MAX GAIN – 65 O SLEEP 160 – 70 150 POWER-UP POWER-DOWN – 75 V = 67dBmV @ MAX GAIN 140 O – 80 V = 65dBmV @ MAX GAIN 130 O – 85 120 – 90 110 1 10 100 1000 5 15 25 35 45 55 65 FREQUENCY – MHz FREQUENCY – MHz TPC 7. Second Order Harmonic Distortion vs. Frequency TPC 10. Input Impedance vs. Frequency (Inputs for Various Output Powers Shunted with 165 Ω) – 35 1000 V = +12V(ARP) S – 40 SLEEP – 45 POWER-DOWN 100 V = 69dBmV @ MAX GAIN O V = 68dBmV @ MAX GAIN – 50 O – 55 POWER-UP – 60 10 V = 67dBmV @ MAX GAIN O – 65 V = 65dBmV @ MAX GAIN O – 70 1 – 75 5 15 25 35 45 55 65 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 8. Third Order Harmonic Distortion vs. Frequency TPC 11. Output Impedance vs. Frequency for Various Output Powers –8– REV. 0 DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc IMPEDANCE – � IMPEDANCE – � AD8326 0 – 50 RBW 500Hz RF ATT 30dB CH PWR +10.41dBm V = �5V – 10 VBW 5kHz S ACP UP – 58.83dB – 55 SWT 20s UNIT dBm ACP LOW – 59.06dB f = 42MHz – 20 P = 65dBmV @ MAX GAIN O – 60 – 30 – 65 – 40 HD3 – 50 – 70 – 60 – 75 – 70 – 80 – 80 HD2 – 85 – 90 – 90 – 100 CENTER 21MHz 100kHz/ SPAN 1MHz 0 9 18 27 36 45 54 63 72 DEC CODE TPC 12. Harmonic Distortion vs. Gain Control for TPC 15. Adjacent Channel Power for AD8326-ARE AD8326-ARE – 50 0 V = �5V(ARE) V = 12V S S – 55 – 20 – 60 TXEN = 1 – 40 V = 65dBmV @ MAX GAIN O – 65 V = 66dBmV @ MAX GAIN O – 70 – 60 – 75 V = 64dBmV @ MAX GAIN O – 80 TXEN = 0 – 80 V = 62dBmV @ MAX GAIN O – 100 – 85 SLEEP – 90 – 120 5 15 25 35 45 55 65 0 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 13. Second Order Harmonic Distortion vs. Frequency TPC 16. Signal Isolation vs. Frequency for Various Output Powers 200 – 40 V = 12V(ARP) V = �5V(ARE) S S 180 – 45 TRANSMIT ENABLE 160 – 50 V = 66dBmV @ MAX GAIN O 140 – 55 V = 65dBmV @ MAX GAIN O 120 – 60 100 – 65 80 – 70 V = 64dBmV @ MAX GAIN O 60 TRANSMIT DISABLE V = 62dBmV @ MAX GAIN O – 75 40 – 80 20 5 15 25 35 45 55 65 – 40 – 30 – 20 – 10 0 10 20 30 40 50 60 70 80 90 FREQUENCY – MHz TEMPERATURE – �C TPC 14. Third Order Harmonic Distortion vs. Frequency TPC 17. Quiescent Current vs. Temperature for Various Output Powers REV. 0 –9– DISTORTION – dBc DISTORTION – dBc DISTORTION – dBc ISOLATION – dBc SUPPLY CURRENT – mA AD8326 APPLICATIONS SPI Programming General Applications The AD8326 is controlled through a serial peripheral interface The AD8326 is primarily intended for use as the upstream (SPI) of three digital data lines, CLK, DATEN, and SDATA. power amplifier (PA), also known as a line driver, in DOCSIS Changing the gain requires 8 bits of data to be streamed into the (Data Over Cable Service Interface Specification) certified SDATA port. The sequence of loading the SDATA register cable modems, cable telephony systems, and CATV set-top begins on the falling edge of the DATEN pin, which activates boxes. The upstream signal is either a QPSK or QAM signal the CLK line. With the CLK line activated, data on the SDATA generated by a DSP, a dedicated QPSK/QAM modulator, or a line is clocked into the serial shift register, Most Significant Bit DAC. In all cases the signal must be low-pass filtered before (MSB) first, on the rising edge of the CLK pulses. Since a 7-bit being applied to the PA in order to filter out-of-band noise and shift register is used in the AD8326, the MSB of the 8-bit word higher order harmonics from the amplified signal. Due to the is a “don’t care” bit and is shifted out of the register on the eighth varying distances between the cable modem and the headend, clock pulse. The data is latched into the attenuator core on the the upstream PA must be capable of varying the output power rising edge of the DATEN line. This provides control over the by applying gain or attenuation. The varying output power of changes in the output signal level. The serial interface timing for the AD8326 ensures that the signal from the cable modem will the AD8326 is shown in Figures 2 and 3. The programmable have the proper level once it arrives at the headend. The upstream gain range of the AD8326 is –25.75 dB to +27.5 dB with steps signal path also contains a transformer, a diplexer, and cable split- of 0.75 dB. This provides a total gain range of 53.25 dB. The ters. The AD8326 has been designed to overcome losses associated AD8326 was characterized with a TOKO transformer (TOKO with these passive components in the upstream cable path, particu- #617DB-A0070), and the stated gain values include the losses larly in modems that support cable telephony. due to the transformer. AD8326ARP Applications For gain codes from 0 through 71 the gain transfer function is: The AD8326ARP is in a thermally enhanced PSOP2 package, A=× 27.5 dB –(. 0 75 dB (71– CODE) [] V and designed for single 12 V supply and output power applica- tions up to +69 dBmV. The AD8326ARP will provide maximum where A is the gain in dB and CODE is the decimal equivalent V performance in 12 V systems. of the 8-bit word. Gain codes 0 to 71 provide linear changes in AD8326ARE Applications gain. Figure 4 shows the gain characteristics of the AD8326 for The AD8326ARE is in a TSSOP package with an exposed ther- all possible values in an 8-bit word. Note that maximum gain is mal pad. It is designed for dual ±5 V or single 10 V supplies. For achieved at Code 71. From Code 72 through 127 the 5.25 dB applications requiring up to 65 dBmV of output power, lower of attenuation from the vernier stage is being applied over every cost, smaller package, and lower power dissipation, the TSSOP eight codes, resulting in the saw tooth characteristic at the top package is most appropriate. of the gain range. Because the eighth bit is shifted out of the register, the gain characteristics for Codes 128 through 255 are Operational Description identical to Codes 0 through 127, as depicted in Figure 4. The AD8326 consists of four analog functions in the transmit enable or forward mode. The input amplifier (preamp) can be 28 used single-ended or differentially. If the input is used in the 21 differential configuration, it is imperative that the input signals be 14 180 degrees out of phase and of equal amplitudes. This will 7 ensure proper gain accuracy and harmonic performance. The 0 – 7 preamp stage drives a vernier stage that provides the fine tune – 14 gain adjustment. The approximate step resolution of 0.75 dB is – 21 implemented in this stage and provides a total of approximately – 28 5.25 dB of accumulated attenuation. After the vernier stage, a 0 32 64 96 128 160 192 224 256 DAC provides the bulk of the AD8326’s attenuation (8 bits or GAIN CODE –Decimal 48 dB). The signals in the preamp and vernier gain blocks are Figure 4. Gain Code vs. Gain differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 Ω load. The output stage utilizes negative feedback to implement a differential 75 Ω output impedance, which eliminates the need for external matching resistors needed in typical video (or video filter) termination requirements. –10– REV. 0 GAIN – dB AD8326 V EE 10�F V CC 10�F 0.1�F AD8326 V 28 IN– 1 GND DATEN DATEN 27 2 SDATA SDATA V 0.1�F CC 26 3 Z = 150� IN CLK CLK V IN– 165� 25 4 GND1 V IN+ 24 5 0.1�F V V 0.1�F CC EE 23 6 TXEN V 0.1�F TXEN CC V IN+ 22 7 V 0.1�F SLEEP SLEEP EE 0.1�F 21 8 GND BYP 0.1�F 20 9 0.1�F V V 0.1�F CC CC 19 10 V V 0.1�F 0.1�F CC CC 18 11 V V 0.1�F 0.1�F EE EE 17 12 GND GND 16 13 0.1�F V V 0.1�F EE EE 15 14 V V OUT– OUT+ TOKO 617DB-A0070 TO DIPLEXER Z = 75� IN Figure 5. Typical Applications Circuit Input Bias, Impedance, and Termination Toko 1:1 transformer is included on the board for this purpose The V + and V – inputs have a dc bias level of approxi- (T3). Enabling the evaluation board for single to differential IN IN mately 1.47 V below V /2, therefore the input signal should input conversion requires R15–R17 to be removed, and 0 Ω CC be ac-coupled using 0.1 μF capacitors as seen in the typical jumpers must be installed on the placeholders for R13, R14, and application circuit (see Figure 5). R18. For a 75 Ω input impedance, R12 should be 78.7 Ω. Refer to Figure 11 for evaluation board schematic. In this configuration, The differential input impedance of the AD8326 is approxi- the input signal must be applied to V –. Other input imped- IN mately 1600 Ω, while the single-ended input is 800 Ω. ances may be calculated using the equation in Figure 7. Single-Ended Inverting Input When operating the AD8326 in a single-ended input mode V + DESIRED IMPEDANCE = R12||1600 IN and V – should be terminated as illustrated in Figure 6. On the IN V – IN AD8326 evaluation boards, this termination method requires the AD8326 R12 removal of R12, R13, R14, R16, R17, and R18. Install a 0 Ω jumper at R15, an 82.5 Ω resistor at R10 for a 75 Ω system, and a 39.2 Ω resistor at R11 to balance the inputs of the AD8326 Figure 7. Differential Signal from Single-Ended Source evaluation board (Figure 11). Other input impedance configura- Differential Signal Source tions may be calculated using the equations in Figure 6. The AD8326 evaluation board is also capable of accepting a differential input signal. This requires the installation of a 165 Ω Z = R10||800 IN R11 = Z ||R10 resistor in R12, the removal of R13–R14, R17–R18, and the IN installation of 0 Ω jumpers for R15–R16. This configuration V – – IN R10 AD8326 results in a differential input impedance of 150 Ω. Other differ- + ential input impedance configurations may be calculated with R11 the equation in Figure 8. DESIRED IMPEDANCE = R12||1600 Figure 6. Single-Ended Input Impedance V + IN The inverting and noninverting inputs of the AD8326 must be R12 AD8326 balanced for all input configurations. V – IN Differential Input from Single-Ended Source The default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. A Figure 8. Differential Input REV. 0 –11– AD8326 at +65 dBmV with ±5 V supplies. The AD8326ARP draws a Output Bias, Impedance, and Termination maximum of 2 W at +67 dBmV with a +12 V supply. The outputs have a dc bias level of approximately V /2, there- CC fore they should be ac-coupled before being applied to the load. The following guidelines should be used for both the AD8326ARE and AD8326ARP. The differential output impedance of the AD8326 is internally maintained at 75 Ω, regardless of whether the amplifier is in First and foremost, the exposed thermal pad should be soldered transmit enable mode or transmit disable mode, eliminating the directly to a substantial ground plane that adequately absorbs need for external back termination resistors. A 1:1 transformer heat away from the AD8326 package. This is the simplest, and is used to couple the amplifier’s differential output to the coaxial most important step in thermally managing the power dissipated in cable while maintaining a proper impedance match. If the out- the AD8326. Increasing the area of copper beneath the AD8326 put signal is being evaluated on standard 50 Ω test equipment, a will lower the thermal resistance in the PCB and more effectively minimum loss 75 Ω–50 Ω pad must be used to provide the test allow air to remove the heat from the PCB, and consequently, circuit with proper impedance match. from the AD8326. Single Supply Operation Secondly, thermal stitching is a method for increasing thermal The 12 V supply should be delivered to each of the V pins via CC capacity of the PCB. Additionally, thermal stitching can be used a low impedance power bus to ensure that each pin is at the to provide a thermally efficient area onto which the AD8326 same potential. The power bus should be decoupled to ground using may be soldered. Thermal stitching is accomplished by using a a 10 μF tantalum capacitor located close to the AD8326ARP. number of plated through holes (or vias) densely populated in In addition to the 10 μF capacitor, each V pin should be CC the solder pad area (but not confined to the size of the TSSOP individually decoupled to ground with 0.1 μF ceramic chip or PSOP2 exposed thermal pad). This technique maximizes the capacitors located close to the pins. The pin labeled BYP (Pin copper area where the package is attached to the PCB increas- 21) should also be decoupled with a 0.1 μF capacitor. The PCB ing the thermal mass or capacity by utilizing more than one should have a low-impedance ground plane covering all unused copper plane. This method of thermal management should be portions of the board, except in the area of the input and output applied in close proximity to the exposed thermal pad. traces in close proximity to the AD8326 and output transformer. All Another important guideline is to utilize a multilayer PCB with ground and V pins of the AD8326ARP must be connected to EE the AD8326. Lowering the PCB thermal resistance using several the ground plane to ensure proper grounding of all internal nodes. layers will generally increase thermal mass resulting in cooler Pin 28 and the exposed pad should be connected to ground. junction temperatures. Dual Supply Operation Using the techniques described above and dedicating 2.9 square The +5 V supply power should be delivered to each of the V CC inches of thermally enhanced PCB area, the AD8326 in either pins via a low impedance power bus to ensure that each pin is at package can operate at safe junction temperatures. Figures 12-17 the same potential. The –5 V supply should also be delivered to show the above practices in use on the AD8326ARE-EVAL board. each of the V pins with a low impedance bus. The power buses EE should be decoupled to ground with a 10 μF tantalum capacitor Initial Power-Up located close to the AD8326ARE. In addition to the 10 μF capaci- When the supply is first applied to the AD8326, the gain setting tor, all V , V and BYP pins should be individually decoupled to of the amplifier is indeterminate. Therefore, as power is first CC EE ground with 0.1 μF ceramic chip capacitors located close to the applied to the amplifier, the TXEN pin should be held low pins. The PCB should have a low-impedance ground plane (Logic 0), preventing forward signal transmission. After power covering all unused portions of the board, except in the area of has been applied to the amplifier, the gain can be set to the desired the input and output traces in close proximity to the AD8326 level by following the procedure in the SPI Programming and and output transformer. All ground pins of the AD8326ARE must Gain Adjustment section. The TXEN pin can then be brought be connected to the ground plane to ensure proper grounding of from Logic 0 to Logic 1, enabling forward signal transmission at all internal nodes. Pin 28 and the exposed thermal pad should the desired gain level. both be tied to ground. Asynchronous Power-Down Signal Integrity Layout Considerations The asynchronous TXEN pin is used to place the AD8326 into Careful attention to printed circuit board layout details will “Between Burst” mode while maintaining a differential output prevent problems due to board parasitics. Proper RF design impedance of 75 Ω. Applying Logic 0 to the TXEN pin acti- technique is mandatory. The differential input and output traces vates the on-chip reverse amplifier, providing a 72% reduction should be kept as short as possible. It is also critical to make in consumed power. For 12 V operation, the supply current is sure that all differential signal paths are symmetrical in length typically reduced from 159 mA to 44 mA. In this mode of and width. In addition, the input and output traces should be operation, between burst noise is minimized and the amplifier kept far apart in order to minimize coupling (crosstalk) through can no longer transmit in the upstream direction. In addition the board. Following these guidelines will improve the overall to the TXEN pin, the AD8326 also incorporates an asynchro- performance of the AD8326 in all applications. nous SLEEP pin, which may be used to further reduce the supply current to approximately 4 mA. Applying Logic 0 to the SLEEP pin Thermal Layout Considerations places the amplifier into SLEEP mode. Transitioning into or As integrated circuits become denser, smaller, and more power- out of SLEEP mode will result in a transient voltage at the ful, they often produce more heat. Therefore when designing PC output of the amplifier. boards, the layout must be able to draw heat away from the higher power devices. The AD8326ARE draws up to 1.5 W when running –12– REV. 0 AD8326 Distortion, Adjacent Channel Power, and DOCSIS rate than the noise, resulting in a signal to noise ratio that improves In order to deliver +58 dBmV of high fidelity output power with gain. In transmit disable mode, the output noise spectral required by DOCSIS, the PA is required to deliver up to density is 1.4 nV/√Hz, which results in –65 dBmV when computed +67 dBmV. This added power is required to compensate for over 160 . KSYM/SECOND losses associated with the transformer, diplexer, directional The noise power was measured directly at the output of the coupler, and splitters that may be included in the upstream transformer. In a typical cable telephony application there will path of the cable telephony. It should be noted that the AD8326 be a 6 dB pad, or splitter, which will further attenuate the noise was characterized with the TOKO 617DB-A0070 transformer. by 6 dB. TPC 7, TPC 8, TPC 13, and TPC 14 show the AD8326 second Evaluation Board Features and Operation and third harmonic distortion performance versus fundamental The AD8326 evaluation boards (Part # AD8326ARE-EVAL frequency for various output power levels. These figures are and AD8326ARP-EVAL) and control software can be used to useful for determining the in band harmonic levels from 5 MHz control the AD8326 upstream cable driver via the parallel port to 65 MHz. Harmonics higher in frequency will be sharply of a PC. A standard printer cable connected between the paral- attenuated by the low-pass filter function of the diplexer. lel port and the evaluation board is used to feed all the necessary Another measure of signal integrity is adjacent channel power, data to the AD8326 by means of the Windows 9X-based control commonly referred to as ACP. DOCSIS section 4.2.10.1.1 software. This package provides a means of evaluating the amplifier states, “Spurious emissions from a transmitted carrier may by providing a convenient way to program the gain/attenuation occur in an adjacent channel that could be occupied by a carrier as well as offering easy control of the asynchronous TXEN and of the same or different symbol rates.” TPC 9 shows the mea- SLEEP pins. With this evaluation kit, the AD8326 can be evalu- sured ACP for a +67 dBmV 16 QAM signal taken at the output ated in either a single-ended or differential input configuration. of the AD8326 evaluation board, through a 75 Ω to 50 Ω The amplifier can also be evaluated with or without the PULSE matching pad (5.7 dB of loss). The transmit channel width diplexer in the output signal path. A schematic of the evaluation and adjacent channel width in TPC 9 correspond to symbol board is provided in Figure 11. rates of 160 KSYM/SEC. Table I shows the ACP results for Output Transformer and Diplexer the AD8326 for all conditions in DOCSIS Table 4-7 “Adjacent A 1:1 transformer is needed to couple the differential outputs of Channel Spurious Emissions.” the AD8326 to the cable while maintaining a proper impedance match. The specified transformer is available from TOKO (Part Table I. Adjacent Channel Power # 617DB-A0070); however, M/A-COM part # ETC-1-1T may Adjacent Channel Symbol Rate also be used. The evaluation board is equipped with the TOKO transformer, but is also designed to accept the M/A-COM trans- Transmit 160K/s 320K/s 640K/s 1280K/s 2560K/s former. The PULSE diplexer included on the evaluation board Symbol ACP ACP ACP ACP ACP provides a high-order low-pass filter function, typically used in the Rate (dBc) (dBc) (dBc) (dBc) (dBc) upstream path. To remove the diplexer from the signal path, 160K/s –57 –59 –62 –63 –64 remove the 0 Ω chip resistors at R7 and R19, and install a 0 Ω 320K/s –57 –58 –60 –62 –64 chip resistor at R6 so the output signal is directed away from 640K/s –55 –58 –58 –60 –62 the diplexer and toward the CABLE port of the evaluation 1280K/s –55 –57 –58 –58 –60 board (Figure 11). The ability of the PULSE diplexer to achieve 2560K/s –53 –56 –57 –57 –57 DOCSIS compliance is neither expressed nor implied by Analog Devices Inc. Data on the diplexer should be obtained from Noise and DOCSIS PULSE. When using the diplexer, be sure to properly terminate At minimum gain, the AD8326 output noise spectral density is the cable port (75 Ω) so that the AD8326 draws minimal current. 13.3 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spuri- Overshoot on PC Printer Ports ous Emissions in 5 MHz to 42 MHz,” specifies the output noise The data lines on some PC parallel printer ports have excessive for various symbol rates. The calculated noise power in dBmV overshoot that may cause communications problems when pre- for 160 KSYM/SECOND is: sented to the CLK pin of the AD8326. The evaluation board was designed to accommodate a series resistor and shunt capaci-    2     13.3 nV  tor (R2 and C2 in Figure 11) to filter the CLK signal if required.   20 × log × 160 kHz += 60 – 45.5 dBmV         Hz Installing Visual Basic Control Software       Install the “CabDrive_26” software by running “setup.exe” on disk one of the AD8326 Evaluation Software. Follow on-screen Comparing the computed noise power of –45.5 dBmV to the directions and insert disk two when prompted. Choose instal- +8 dBmV signal yields –53.5 dBc, which meets the required level lation directory, and then select the icon in the upper left to set forth in DOCSIS Table 4-8. As the AD8326 gain is increased complete installation. from this minimum value, the output signal increases at a faster REV. 0 –13– AD8326 Running AD8326 Software Memory Functions To load the control software, go to START, PROGRAMS, The MEMORY section of the software provides a way to alter- CABDRIVE_26, or select the AD8326.exe from the installed nate between two gain settings. The “X->M1” button stores directory. Once loaded, select the proper parallel port to com- the current value of the gain slide bar into memory while the municate with the AD8326 (Figure 9). “RM1” button recalls the stored value, returning the gain slide bar to the stored level. The same applies to the “X->M2” and “RM2” buttons. Figure 9. Parallel Port Selection Controlling Gain/Attenuation of the AD8326 The slide bar controls the gain/attenuation of the AD8326, which is displayed in dB and in V/V. The gain scales 0.75 dB per LSB with valid codes from 0 to 71. The gain code from the position of the slide bar is displayed in decimal, binary, and hexadecimal (Figure 10). Figure 10. Control Software Interface Transmit Enable and Sleep Mode The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8326 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmis- sion while maintaining a 75 Ω back termination. The Transmit Enable button applies Logic 1 to the TXEN pin, enabling the AD8326 for forward transmission. Checking the “Enable SLEEP Mode” checkbox applies logic “0” to the asynchronous SLEEP pin, setting the AD8326 for SLEEP mode. –14– REV. 0 AD8326 Figure 11. Evaluation Board Schematic REV. 0 –15– TP15 V CC DATEN TP18 TP17 SDATA + C7 TP16 TP13 10�F C22 R15 CLK V – 0 IN DNI C20 0.1�F R10 1 Z1 28 R18 DNI R14 TXEN 27 0� 2 0.1�F 0� T4 T3 3 26 DNI R12 SLEEP 4 25 78.7� 4 6 4 6 5 24 C9 2 2 C4 6 23 3 1 3 1 C10 0.1�F 22 7 R17 0.1�F TOKO1 ETC1 AD8326 8 21 TP14 DNI R13 0.1�F C11 9 20 0� C23 R16 19 TOKO1 ETC1 C5 10 C12 0.1�F V + 0 IN 11 18 DNI 0.1�F R11 0.1�F 0.1�F DNI 12 17 C6 16 13 C13 14 15 0.1�F C14 0.1�F V CC HPF_O C15 0.1�F TP7 9 0.1�F V C16 TB1 EE V HPP EE CX6002 0.1�F AGND W1 1 5 CBL LPP TP2 TP1 P1 1 R1 P1 19 COM P1 2 P1 20 3, 10– 18 0� C19 C18 C17 AGND 10�F 0.1�F 0.1�F P1 21 P1 3 C1 + TP12 W2 DNI P1 4 P1 22 TP10 P1 5 P1 23 TP8 P1 6 P1 24 TP3 TP4 P1 7 P1 25 R4 R2 R7 T2 R19 P1 8 P1 26 T1 OPEN 0� TP11 0� C20 DNI 0� AGND P1 9 P1 27 C2 R8 4 6 4 6 P1 10 P1 28 DNI R6 0.1�F 2 2 0� R9 P1 11 P1 29 OPEN TP5 TP6 C21 3 1 3 1 OPEN CABLE_O P1 12 P1 30 R3 TOKO1 ETC1 0.1�F P1 13 P1 31 TP9 0� P1 14 P1 32 R5 P1 15 C3 P1 33 DNI P1 16 P1 34 OPEN P1 17 P1 35 P1 18 P1 36 AGND AD8326 Figure 12. Evaluation Board Layout (Component Side) –16– REV. 0 AD8326 Figure 13. Evaluation Board Layout (Silkscreen Top) REV. 0 –17– AD8326 Figure 14. Evaluation Board Layout (Circuit Side) –18– REV. 0 AD8326 Figure 15. Evaluation Board Layout (Silkscreen Bottom) REV. 0 –19– AD8326 Figure 16. Evaluation Board Layout (Internal Ground Plane) –20– REV. 0 AD8326 Figure 17. Evaluation Board Layout (Internal Power Planes) REV. 0 –21– AD8326 AD8326 Evaluation Board Rev. B – Revised - November 22, 2000 Qty. Description Vendor Ref Description 2 10 μF 16 V. B Size Tantalum Chip Capacitor ADS# 4-7-24 C7, C19 4 0.1 μF 50 V. 1206 Size Ceramic Chip Capacitor ADS# 4-5-18 C20–23 14 0.1 μF 25 V. 603 Size Ceramic Chip Capacitor ADS# 4-12-8 C4–C6, C8–C18 90 Ω 1/8 W. 1206 Size Chip Resistor ADS# 3-18- 88 R1–R3, R7, R8, R13, R14, R18, R19 1 78.7 Ω 1% 1/8 W. 1206 Size Chip Resistor ADS# 3-18-194 R12 2 Yellow Test Point [INPUTS] (Bisco TP104-01-04) ADS# 12-18-32 TP13, TP14 6 White Test Point [DATA] (Bisco TP104-0 -09) ADS# 12-18-42 TP1–TP6 1 Red Test Point [VCC] (Bisco TP104-01-02) ADS# 12-18-43 TP15 1 Blue Test Point [VEE] (Bisco TP104-01-06) ADS# 12-18-62 TP7 3 Black Test Point [AGND] (Bisco TP104-01-00) ADS# 12-18-44 TP16–TP18 4 End Launch SMA Connector ADS# 12-1-31 VIN–, VIN+, CABLE, HPF 1 Centronics Type 36 Pin Right-Angle Connector ADS# 12-3-50 P1 1 3 Terminal Power Block (Green) ADS# 12-19-14 TB1 1 1:1 Transformer TOKO # 617DB – A0070 TOKO T3, T1 1 Pulse # CX 6002 Diplexer PULSE Z2 1 AD 8326ARE (TSSOP ePad) UPSTREAM Cable Driver ADI# AD8326XRE Z1 1 AD 8326ARE REV. B Evaluation PC Board ADI# AD8326XRE-EVAL EVAL PCB 4#4–40 × 1/4 Inch STAINLESS Panhead Machine Screw ADS# 30-1-1 4#4–40 × 3/4 Inch Long Aluminum Round Standoff ADS# 30-16-3 2# 2–56 × 3/8 inch STAINLESS Panhead Machine Screw ADS# 30-1-17 (p1 hardware) 2 # 2 Steel Flat Washer ADS# 30-6-6 (p1 Hardware) 2 # 2 Steel Internal Tooth Lockwasher ADS# 30-5-2 (p1 Hardware) 2 # 2 STAINLESS STEEL Hex. Machine Nut ADS# 30-7-6 (p1 Hardware) Do not install C1–C3, R4–R6, R10, R11, R15–R17, T2, T4, TP8–TP12, W1–W2. –22– REV. 0 AD8326 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead PSOP (RP-28) 0.711 (18.06) 0.701 (17.81) 28 15 0.299 (7.59) 0.189 (4.80) HEAT SLUG 0.292 (7.42) ON BOTTOM 0.179 (4.55) 0.410 (10.41) 0.400 (10.16) 1 14 PIN 1 0.539 (13.69) 0.098 (2.49) 0.016 (0.41) 0.529 (13.44) 45° 0.090 (2.29) 0.010 (0.25) 8� 0� 0.004 (0.10) 0.050 (1.27) 0.019 (0.48) SEATING 0.040 (1.27) 0.0125 (0.32) BSC PLANE 0.000 (0.00) 0.014 (0.36) 0.024 (0.61) 0.0091 (0.23) STANDOFF 28-Lead HTSSOP (RE-28) 0.386 (9.80) 0.382 (9.70) 0.378 (9.60) 28 15 0.119 (3.05) 0.177 (4.50) 0.252 EXPOSED 0.117 (3.00) PAD 0.173 (4.40) (6.40) ON BOTTOM BSC 0.115 (2.95) 0.169 (4.30) 1 14 PIN 1 0.138 (3.55) 0.041 (1.05) 0.136 (3.50) 0.039 (1.00) 0.134 (3.45) 0.047 0.031 (0.80) (1.20) MAX 8� 0.006 (0.15) 0.0256 0.0118 (0.30) 0� 0.030 (0.75) SEATING 0.0079 (0.20) (0.65) 0.0075 (0.19) 0.024 (0.60) 0.000 (0.00) PLANE 0.0035 (0.09) BSC 0.177 (0.45) CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm) REV. 0 –23– –24– PRINTED IN U.S.A. C01856–1.5–7/01(0)