ANALOG DEVICES AD8324

3.3 V Upstream Cable Line Driver AD8324 FEATURES FUNCTIONAL BLOCK DIAGRAM BYP Supports DOCSIS 2.0 and Euro-DOCSIS standards for reverse path transmission systems Gain programmable in 1 dB steps over a 59 dB range V V IN+ OUT+ DIFF Low distortion at 61 dBmV output: ATTENUATION OUTPUT OR SINGLE VERNIER CORE STAGE INPUT –59 dBc SFDR at 21 MHz AMP V V IN– OUT– –54 dBc SFDR at 65 MHz Z DIFF = OUT Z (SINGLE) = 550Ω IN 8 75Ω Output noise level @ minimum gain 1.3 nV/√Hz Z (DIFF) = 1100Ω IN DECODE Maintains 75 Ω output impedance in TX-enable and POWER- Transmit-disable condition RAMP 8 DOWN LOGIC Upper bandwidth: 100 MHz (full gain range) AD8324 DATA LATCH 3.3 V supply operation 8 Supports SPI® interfaces SHIFT REGISTER APPLICATIONS GND DATEN DATA CLK TXEN SLEEP DOCSIS 2.0 and Euro-DOCSIS cable modems Figure 1. Functional Block Diagram CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers –40 GENERAL DESCRIPTION V = 61dBmV @ DEC 60 –50 OUT THIRD HARMONIC The AD8324 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8324 –60 ideally suited for DOCSIS 2.0 and Euro-DOCSIS applications. The gain of the AD8324 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, V = 61dBmV @ DEC 60 OUT –70 resulting in gain changes of 1 dB/LSB. SECOND HARMONIC The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 1:1 –80 515 25 35 45 55 65 transformer. FREQUENCY (MHz) Figure 2. Worst Harmonic Distortion vs. Frequency Distortion performance of –54 dBc is achieved with an output up to 61 dBmV at 65 MHz bandwidth. level This device has a sleep mode function that reduces the quies- cent current to 30 μA and a full power-down function that reduces power-down current to 2.5 mA. The AD8324 is packaged in a low cost 20-lead LFCSP package and a 20-lead QSOP package. The AD8324 operates from a single 3.3 V supply. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. DISTORTION (dBc) 04339-0-002 04339-0-001 AD8324 TABLE OF CONTENTS Specifications..................................................................................... 3 RAMP Pin and BYP Pin Features ............................................ 11 Logic Inputs (TTL/CMOS Compatible Logic)......................... 4 Power Saving Features ............................................................... 12 Timing Requirements .................................................................. 4 Distortion, Adjacent Channel Power, and DOCSIS .............. 12 Absolute Maximum Ratings............................................................ 5 Utilizing Diplex Filters............................................................... 12 Thermal Resistance ...................................................................... 5 Noise and DOCSIS..................................................................... 12 ESD Caution.................................................................................. 5 Evaluation Board Features and Operation.............................. 13 Pin Configurations and Functional Descriptions ........................ 6 Differential Signal Source ......................................................... 13 Typical Performance Characteristics ............................................. 7 Differential Signal from Single-Ended Source ....................... 13 Applications..................................................................................... 10 Single-Ended Source.................................................................. 13 General Applications.................................................................. 10 Overshoot on PC Printer Ports ................................................ 14 Circuit Description..................................................................... 10 Installing Visual Basic Control Software................................. 14 Gain Programming for the AD8324 ........................................ 10 Running AD8324 Software ....................................................... 14 Input Bias, Impedance, and Termination................................ 10 Controlling Gain/Attenuation of the AD8324 ....................... 14 Output Bias, Impedance, and Termination............................. 10 Transmit Enable and Sleep Mode............................................. 14 Power Supply............................................................................... 11 Memory Functions..................................................................... 14 Signal Integrity Layout Considerations................................... 11 Outline Dimensions....................................................................... 16 Initial Power-Up ......................................................................... 11 Ordering Guide .......................................................................... 16 REVISION HISTORY 7/05—Rev. 0 to Rev. A Updated Absolute Maximum Ratings Page ...................................5 Updated Outline Dimensions ....................................................... 16 Changes to Ordering Guide .......................................................... 16 Revision 0: Initial Version Rev. A | Page 2 of 16 AD8324 SPECIFICATIONS TA = 25°C, VCC = 3.3 V, RL = RIN = 75 Ω, VIN (Differential) = 27.5 dBmV, unless otherwise noted. The AD8324 is characterized using a 1:1 1 transformer at the device output. Table 1. Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Specified AC Voltage Output = 61 dBmV, Max Gain 27.5 dBmV Input Resistance Single-Ended Input 550 Ω Differential Input 1100 Ω Input Capacitance 2 pF GAIN CONTROL INTERFACE Voltage Gain Range 58 59.0 60 dB Max Gain Gain Code = 60 Dec 32.5 33.5 34.5 dB Min Gain Gain Code = 1 Dec –26.5 –25.5 –24.5 dB 2 Output Step Size 0.6 1.0 1.4 dB/LSB Output Step Size Temperature Coefficient T = –40°C to +85°C ±0.004 dB/°C A OUTPUT CHARACTERISTICS Bandwidth (–3 dB) All Gain Codes (1–60 Decimal Codes) 100 MHz Bandwidth Roll-Off f = 65 MHz 1.7 dB 3 1 dB Compression Point Max Gain, f = 10 MHz, Output Referred 19.6 21 dBm Min Gain, f = 10 MHz, Input Referred 2.1 3.7 dBm 2 Output Noise Max Gain f = 10 MHz 157 166 nV/√Hz Min Gain f = 10 MHz 1.3 1.5 nV/√Hz Transmit Disable f = 10 MHz 1.1 1.2 nV/√Hz 2 Noise Figure Max Gain f = 10 MHz 15.5 16.0 dB 4 Differential Output Impedance TX Enable and TX Disable 75 ± 30% Ω OVERALL PERFORMANCE 5, 3 Second-Order Harmonic Distortion f = 33 MHz, VOUT = 61 dBmV @ Max Gain –66 –60 dBc f = 65 MHz, VOUT = 61 dBmV @ Max Gain –58 –53 dBc 5 , 3 Third-Order Harmonic Distortion f = 21 MHz, VOUT = 61 dBmV @ Max Gain –59 –57.5 dBc f = 65 MHz, V = 61 dBmV @ Max Gain –54 –52.5 dBc OUT 2, 6 ACPR –61 –58 dBc 2 Isolation (Transmit Disable) Max Gain, f = 65 MHz –75 –70 dB POWER CONTROL TX Enable Settling Time Max Gain, V = 0 2.5 μs IN TX Disable Settling Time Max Gain, V = 0 3.8 μs IN 3 Output Switching Transients Equivalent Output = 31 dBmV 2.5 6 mV p-p Equivalent Output = 61 dBmV 27 71 mV p-p Output Settling Due to Gain Change Min to Max Gain 60 ns Due to Input Step Change Max Gain, V = 27.5 dBmV 30 ns IN POWER SUPPLY Operating Range 3.13 3.3 3.47 V Quiescent Current Max Gain 195 207 235 mA Min Gain 25 39 50 mA Transmit Disable (TXEN = 0) 1 2.5 4 mA SLEEP 30 500 μA Mode (Power-Down) OPERATING TEMPERATURE RANGE LFCSP –40 +85 °C QSOP –25 +70 °C 1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB @ 10 MHz. 2 Guaranteed by design and characterization to ±6 sigma for TA = 25°C. 3 Guaranteed by design and characterization to ±3 sigma for T = 25°C. A 4 Measured through a 1:1 transformer. 5 Specification is worst case over all gain codes. 6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate. Rev. A | Page 3 of 16 AD8324 LOGIC INPUTS (TTL/CMOS COMPATIBLE LOGIC) DATEN SLEEP , CLK, SDATA, TXEN, , VCC = 3.3 V, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Logic 1 Voltage 2.1 3.3 V Logic 0 Voltage 0 0.8 V 0 20 nA Logic 1 Current (V = 3.3 V), CLK, SDATA, DATEN INH DATEN −600 −100 nA Logic 0 Current (VINL = 0 V), CLK, SDATA, Logic 1 Current (VINH = 3.3 V), TXEN 50 190 μA Logic 0 Current (V = 0 V), TXEN −250 −30 μA INL SLEEP 50 190 μA Logic 1 Current (VINH = 3.3 V), SLEEP −250 −30 μA Logic 0 Current (VINL = 0 V), TIMING REQUIREMENTS V = 3.3 V, t = t = 4 ns, f = 8 MHz, unless otherwise noted. CC R F CLK Table 3. Parameter Min Typ Max Unit Clock Pulse Width (t ) 16.0 ns WH Clock Period (tC) 32.0 ns Setup Time SDATA vs. Clock (tDS) 5.0 ns DATEN 15.0 ns Setup Time vs. Clock (t ) ES Hold Time SDATA vs. Clock (t ) 5.0 ns DH DATEN 3.0 ns Hold Time vs. Clock (tEH) DATEN 10 ns Input Rise and Fall Times, SDATA, , Clock (t , t ) R F t DS VALID DATA BIT VALID DATA WORD G1 VALID DATA WORD G2 SDATA MSB . . . LSB t C t VUH SDATA MSB MSB-1 MSB-2 CLK t t ES EH t t DS DH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) CLK t OFF TXEN t GS Figure 4. SDATA Timng t CN ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) Figure 3. Serial Interface Timing Rev. A | Page 4 of 16 04339-0-0030 04339-0-004 AD8324 ABSOLUTE MAXIMUM RATINGS Table 4. AD8324 Stress Ratings Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage V 3.63 V CC rating only; functional operation of the device at these or any Input Voltage other conditions above those indicated in the operational VIN+, VIN– 1.5 V p-p section of this specification is not implied. Exposure to absolute DATEN SLEEP –0.5 V to +3.63 V , SDATA, CLK, , TXEN maximum rating conditions for extended periods may affect Internal Power Dissipation device reliability. QSOP, LFCSP 776 mW THERMAL RESISTANCE Operating Temperature Range LFCSP –40°C to +85°C Table 5. Thermal Resistance Ratings QSOP –25°C to +70°C Model θJA Unit Storage Temperature Range –65°C to +150°C 1 AD8324JRQ 83.2 °C/W Lead Temperature (Soldering, 60 sec) 300°C 2 AD8324ACP 30.4 °C/W 1 Thermal resistance measured on SEMI standard 4-layer board. 2 Thermal resistance measured on SEMI standard 4-layer board, paddle soldered to board. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 16 AD8324 PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS 1 GND 20 GND V 2 19 V CC CC 20 19 18 17 16 3 GND 18 TXEN GND 1 15 RAMP 4 GND 17 RAMP 2 V GND 14 AD8324 OUT+ AD8324 5 V V 16 IN+ OUT+ TOP VIEW 3 V V 13 TOP VIEW OUT– IN+ V 6 (Not to Scale) 15 V IN– (Not to Scale) OUT– V 4 12 BYP IN– GND 7 14 BYP 5 11 GND NC 8 DATEN 13 NC 67 8 9 10 9 SDATA 12 SLEEP 10 CLK 11 GND NC = NO CONNECT Figure 5. 20-Lead LFCSP Figure 6. 20-Lead QSOP Table 6. Pin Function Descriptions Pin No. Pin No. 20-Lead 20-Lead LFCSP QSOP Mnemonic Description 1, 2, 5, 9, 1, 3, 4, 7, GND Common External Ground Reference. 18, 19 11, 20 17, 20 2, 19 VCC Common Positive External Supply Voltage. 3 5 VIN+ Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. 4 6 V Inverting Input. DC-biased to approximately V /2. Should be ac-coupled with a 0.1 μF capacitor. IN– CC 6 8 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous and simultaneously enables the register for serial data load). 7 9 SDATA Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. 8 10 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master- slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. 10 12 SLEEP Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 μA. A Logic 0 powers down the part (high Z state), and a Logic 1 powers up the part. OUT 12 14 BYP Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor). 13 15 VOUT– Negative Output Signal. Must be biased to VCC. See Figure 23. 14 16 VOUT+ Positive Output Signal. Must be biased to VCC. See Figure 23. 15 17 RAMP External RAMP Capacitor (Optional). 16 18 TXEN Logic 0 disables forward transmission. Logic 1 enables forward transmission. Rev. A | Page 6 of 16 V DATEN CC SDATA GND CLK GND GND V CC SLEEP TXEN 04339-0-006 04339-0-005 AD8324 TYPICAL PERFORMANCE CHARACTERISTICS –40 –40 V = 62dBmV @ DEC 60 OUT V = 61dBmV @ DEC 60 OUT –50 –50 V = 62dBmV @ DEC 60 OUT V = 61dBmV @ DEC 60 OUT –60 –60 V = 60dBmV @ DEC 60 OUT –70 –70 V = 60dBmV @ DEC 60 OUT –80 –80 515 25 35 45 55 65 515 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Second-Order Harmonic Distortion vs. Frequency Figure 10. Third-Order Harmonic Distortion vs. Frequency for Various Output Powers for Various Output Powers –40 –40 V = 61dBmV @ DEC 60 V = 61dBmV @ DEC 60 OUT OUT T = +25°C A T = +85°C A –50 –50 T = –40°C A –60 T = –40°C –60 A T = +25°C A –70 –70 T = +85°C A –80 –80 5 15 25 35 45 55 65 515 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. LFSCP Second-Order Harmonic Distortion Figure 11. LFCSP Third-Order Harmonic Distortion vs. Frequency vs. Temperature vs. Frequency vs. Temperature –40 –40 V = 61dBmV @ DEC 60 V = 61dBmV @ DEC 60 OUT OUT T = +25°C A T = +70°C A –50 –50 T = +25°C A T = –25°C A –60 T = –25°C –60 A –70 –70 T = +70°C A –80 –80 5 15 25 35 45 55 65 515 25 35 45 55 65 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. QSOP Second-Order Harmonic Distortion Figure 12. QSOP Third-Order Harmonic Distortion vs. Frequency vs. Temperature vs. Frequency vs. Temperature Rev. A | Page 7 of 16 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 04339-0-009 04339-0-008 04339-0-007 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 04339-0-012 04339-0-011 04339-0-010 AD8324 0 60 CH PWR 12dBm V = 57dBmV/TONE OUT –10 50 WORST ACP –61dBc @ MAX GAIN –20 40 –30 30 –40 20 –50 10 –60 0 –70 –10 –80 –20 CU1 CU1 C0 C0 –90 –30 CL1 CL1 –100 –40 CENTER 21 MHz 100 kHz/DIV SPAN 1 MHz 41.6 41.7 41.8 41.9 42.0 42.1 42.2 42.3 42.4 42.5 FREQUENCY (MHz) Figure 13. Adjacent Channel Power Figure 16. Two-Tone Intermodulation Distortion 40 0 TXEN = 0 –10 V = 27.5dBmV IN 30 DEC60 –20 20 DEC54 –30 DEC48 10 DEC42 –40 DEC36 0 –50 DEC30 –60 –10 DEC24 DEC18 –70 –20 DEC12 –80 MAX GAIN DEC 1 TO DEC 6 –30 –90 MIN GAIN –40 –100 0.1 1 10 100 1000 0 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. AC Response Figure 17. Isolation in Transmit Disable Mode vs. Frequency 1.4 2.0 f = 10MHz 1.3 1.5 1.2 1.0 1.1 0.5 f = 5MHz 1.0 0 f = 10MHz 0.9 f = 42MHz –0.5 0.8 –1.0 f = 65MHz 0.7 –1.5 0.6 –2.0 0 6 12 18 24 30 36 42 48 54 60 0 6 12 18 24 30 36 42 48 54 60 GAIN CONTROL (Decimal Code) GAIN CONTROL (Decimal Code) Figure 15. Output Step Size vs. Gain Control Figure 18. Gain Error vs. Gain Control Rev. A | Page 8 of 16 P (dBm) OUT OUTPUT STEP SIZE (dB) GAIN (dB) 04339-0-014 04339-0-015 04339-0-013 V (dBmV) OUT GAIN ERROR (dB) ISOLATION (dB) 04339-0-017 04339-0-018 04339-0-016 AD8324 180 110 f = 10MHz 100 160 TXEN = 1 90 140 80 120 70 100 60 50 80 DOCSIS 2.0 BETWEEN BURST TRANSIENT SPECIFICATION 40 60 30 40 AD8324 20 20 10 0 0 0 6 12 18 24 30 36 42 48 54 60 0 6 12 18 24 3036 4248 54 60 GAIN CONTROL (Decimal Code) GAIN CONTROL (Decimal Code) Figure 19. Output Referred Voltage Noise vs. Gain Control Figure 21. Between Burst Transient vs. Gain Control 210 T = 25°C A 190 3.3V 170 0.1μF 10μF 150 18.7Ω V 130 CC V OUT+ IN+ 1:1 110 39.5Ω AD8324 75Ω R L 90 OUT– V IN– BYP GND 18.7Ω 70 1/2 V 1/2 V IN IN 0.1μF 0.1μF 50 30 0 6 12 18 24 3036 424854 60 GAIN CONTROL (Decimal Code) Figure 20. Supply Current vs. Gain Control Figure 22. Typical Characterization Circuit Rev. A | Page 9 of 16 QUIESCENT SUPPLY CURRENT (mA) OUTPUT REFERRED VOLTAGE NOISE (nV/ Hz) 04339-0-020 04339-0-019 BETWEEN BURSTS TRANSIENTS (mV p-p) 04339-0-021 04339-0-022 AD8324 APPLICATIONS GENERAL APPLICATIONS For existing software that uses 8-bits to program the cable driver, the 2 MSBs will be ignored. This allows the AD8324 to The AD8324 is primarily intended for use as the upstream be compatible with some existing system designs. power amplifier (PA) in DOCSIS (data over cable service interface specification) certified cable modems and CATV set- The AD8324 recognizes gain codes 1 through 60 (all gain codes top boxes. The upstream signal is either a QPSK or QAM signal are in decimal, unless otherwise noted). When the AD8324 is generated by a DSP, a dedicated QPSK/QAM modulator, or a programmed with 61 to 63, it will internally default to max gain DAC. In all cases, the signal must be low-pass filtered before (gain code 60). If the programmed gain code is above 63, the being applied to the PA in order to filter out-of-band noise and AD8324 will recognize only the 6 LSBs. For example, gain code higher order harmonics from the amplified signal. 75 (01001011 binary) will be interpreted as gain code 11 (001011 binary) since the 2 MSBs are ignored. Due to the varying distances between the cable modem and the head-end, the upstream PA must be capable of varying the The programming range of the AD8324 is from –25.5 dB (gain output power by applying gain or attenuation. The ability to code 1) to +33.5 dB (gain code 60). The 60 dB gain range is vary the output power of the AD8324 ensures that the signal linear with a 1 dB change in a 1 LSB change in gain code. from the cable modem will have the proper level once it arrives Figure 15 illustrates the gain step size of the AD8324 versus gain at the head-end. The upstream signal path commonly includes a code. The AD8324 was characterized with a differential input diplexer and cable splitters. The AD8324 has been designed to signal and a TOKO 458PT-1457 1:1 transformer at the output. overcome losses associated with these passive components in the upstream cable path. INPUT BIAS, IMPEDANCE, AND TERMINATION The V and V inputs have a dc bias level of V /2; therefore IN+ IN– CC CIRCUIT DESCRIPTION the input signal should be ac-coupled as seen in the typical The AD8324 is composed of three analog functions in the application circuit (Figure 23). The differential input impedance transmit-enable mode. The input amplifier (preamp) can be of the AD8324 is approximately 1.1 kΩ, while the single-ended used in a single-ended or differential configuration. If the input input is 550 Ω. The high input impedance of the AD8324 allows is used in the differential configuration, the input signals should flexibility in termination and properly matching filter networks. be 180 degrees out of phase and of equal amplitude. A vernier is The AD8324 will exhibit optimum performance when driven used in the input stage for controlling the fine 1 dB gain steps. with a pure differential signal. This stage then drives a DAC, which provides the bulk of the AD8324’s attenuation. The signals in the preamp and DAC OUTPUT BIAS, IMPEDANCE, AND TERMINATION. blocks are differential to improve the PSRR and linearity. A The output stage of the AD8324 requires a bias of 3.3 V. The differential current is fed from the DAC into the output stage. 3.3 V power supply should be connected to the center tap of the The output stage maintains 75 Ω differential output impedance output transformer. Also, the VCC that is being applied to the in all power modes. center tap of the transformer should be decoupled as seen in the typical application circuit (Figure 23). GAIN PROGRAMMING FOR THE AD8324 The output impedance of the AD8324 is 75 Ω, regardless of The AD8324 features a serial peripheral interface (SPI) for whether the amplifier is in transmit enable, transmit disable, or programming the gain code settings. The SPI interface consists sleep mode. This, when combined with a 1:1 voltage ratio trans- DATEN of three digital data lines: CLK, , and SDATA. The former, eliminates the need for external back termination DATEN pin should be held low while the AD8324 is being resistors. If the output signal is being evaluated using standard programmed. The SDATA pin accepts the serial data stream for 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad must programming the AD8324 gain code. The CLK pin accepts the be used to provide the test circuit with the proper impedance clock signal to latch in the data from the SDATA line. match. The AD8324 evaluation board provides a convenient The AD8324 utilizes a 6-bit shift register for clocking in the means to implement a matching attenuator. Soldering a 43.3 Ω data. The shift register is designed to be programmed MSB first. resistor in the R15 placeholder and an 86.6 Ω resistor in the R16 The timing interface for programming the AD8324 can be seen place-holder will allow testing on a 50 Ω system. When using a in Table 2, Table 3, Figure 3, and Figure 4. While the DATEN matching attenuator, it should be noted that there will be 5.7 dB of power loss (7.5 dB voltage) through the network. pin is held low, the serial bits on the SDATA line are shifted into the register on the rising edge of the CLK pin. Rev. A | Page 10 of 16 AD8324 V CC 10μF AD8324-JRQ 1 20 GND GND 2 19 V V 0.1μF CC CC 3 18 0.1μF V IN+ GND TXEN 4 17 GND RAMP TO DIPLEXER 1:1 5 16 Z = 75Ω V V IN IN+ OUT+ Z = 150Ω 174Ω IN 6 15 V V IN– OUT– TOKO 458PT-1556 7 14 GND BYP 8 13 0.1μF DATEN V NC IN– 9 12 0.1μF SDATA SLEEP 10 11 CLK GND 1kΩ DATEN 1kΩ SDATA 1kΩ CLK 1kΩ TXEN 1kΩ SLEEP Figure 23. Typical Application Circuit Table 7. Adjacent Channel Power Adjacent Channel Symbol Rate (kSym/s) Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120 160 –63 –64 –68 –71 –72 –66 320 –63 –64 –66 –70 –72 –67 640 –64 –64 –65 –67 –71 –67 1280 –67 –65 –65 –66 –68 –67 2560 –70 –67 –66 –66 –67 –65 5120 –72 –70 –67 –67 –64 –64 input and output traces should be adequately spaced to POWER SUPPLY minimize coupling (crosstalk) through the board. Following The 3.3 V supply should be delivered to each of the VCC pins via these guide-lines will optimize the overall performance of the a low impedance power bus. This ensures that each pin is at the AD8324 in all applications. same potential. The power bus should be decoupled to ground using a 10 μF tantalum capacitor located close to the AD8324. INITIAL POWER-UP In addition to the 10 μF capacitor, V pins should be decoupled CC When the supply voltage is first applied to the AD8324, the gain to ground with ceramic chip capacitors located close to the pins. of the amplifier is initially set to gain code 1. As power is first The bypass pin, labeled BYP, should also be decoupled. The applied to the amplifier, the TXEN pin should be held low PCB should have a low impedance ground plane covering all (Logic 0) to prevent forward signal transmission. After power unused portions of the board, except in areas of the board has been applied to the amplifier, the gain can be set to the where input and output traces are in close proximity to the desired level by following the procedure provided in the Gain AD8324 and the output transformer. All AD8324 ground pins Programming for the AD8324 section. The TXEN pin can then must be connected to the ground plane to ensure proper be brought from Logic 0 to Logic 1, enabling forward signal grounding of all internal nodes. transmission at the desired gain level. SIGNAL INTEGRITY LAYOUT CONSIDERATIONS RAMP PIN AND BYP PIN FEATURES Careful attention to printed circuit board layout details will The RAMP pin (Pin 15) is used to control the length of the burst prevent problems due to board parasitics. Proper RF design on and off transients. By default, leaving the RAMP pin techniques are mandatory. The differential input and output unconnected will result in a transient that is fully compliant with traces should be kept as short as possible. Keeping the traces DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst short will minimize parasitic capacitance and inductance, which On/Off Transients. DOCSIS requires that all between burst is most critical between the outputs of the AD8324 and the 1:1 transients must be dissipated no faster than 2 μs. Adding output transformer. It is also critical that all differential signal capacitance to the RAMP pin will slow the dissipation even more. paths be symmetrical in length and width. In addition, the Rev. A | Page 11 of 16 04339-0-023 AD8324 The BYP pin is used to decouple the output stage to ground. Another measure of signal integrity is adjacent channel power, Typically, for normal DOCSIS operation, the BYP pin should be commonly referred to as ACP. DOCSIS 2.0, section 6.2.21.1.1 decoupled to ground with a 0.1 μF capacitor. However, in states, “Spurious emissions from a transmitted carrier may applications that may require transient on/off times faster than occur in an adjacent channel that could be occupied by a carrier 2 μs, smaller capacitors may be used, but it should be noted that of the same or different symbol rates.” Figure 13 shows the the BYP pin should always be decoupled to ground. typical ACP for a 61 dBmV (approximately 12 dBm) QPSK signal taken at the output of the AD8324 evaluation board. The POWER SAVING FEATURES transmit channel width and adjacent channel width in Figure 13 The AD8324 incorporates three distinct methods of reducing correspond to the symbol rates of 160 kSym/s. Table 7 shows power consumption: transmit disable and sleep modes for the ACP results for the AD8324 driving a QPSK, 61 dBmV between-burst and shutdown modes, as well as gain dependent signal for all conditions in DOCSIS Table 6-9, Adjacent quiescent current for transmit enable mode. Channel Spurious Emissions. The asynchronous TXEN pin is used to place the AD8324 into UTILIZING DIPLEX FILTERS between-burst mode. In this reduced current state, the 75 Ω The AD8324 was designed to drive 61 dBmV without any output impedance is maintained. Applying Logic 0 to the TXEN external filtering and still meet DOCSIS spurious emissions and pin deactivates the on-chip amplifier, providing a 98.8% reduc- distortion requirements. However, in most upstream CATV tion in consumed power. For 3.3 V operation, the supply applications, a diplex filter is used to separate the upstream and current is typically reduced from 207 mA to 2.5 mA. In this downstream signal paths from one another. The diplex filter mode of operation, between-burst noise is minimized and high does have insertion loss that the upstream driver needs to over- input to output isolation is achieved. In addition to the TXEN come, but it also provides a low-pass filter. The addition of this SLEEP pin, the AD8324 also incorporates an asynchronous pin, low-pass filter to the signal chain can greatly attenuate second which may be used to further reduce the supply current to harmonic products of channels above 21 MHz and third SLEEP approximately 30 μA. Applying Logic 0 to the pin places harmonic products of channels at or above 14 MHz up for the amplifier into SLEEP mode. Transitioning into or out of diplexers with a 42 MHz upstream cutoff. Similar performance SLEEP mode may result in a transient voltage at the output of gains can be achieved using European-specified diplexers to the amplifier. filter second harmonics for channels above 33 MHz and third harmonics for channels above 22 MHz (65 MHz upstream In addition to the sleep and transmit disable functions, the cutoff). This filtering allows the AD8324 to drive up to AD8324 provides yet another means of reducing system power 63 dBmV of QPSK (this level can vary by application and consumption. While in the transmit enable state, the AD8324 modulation type). incorporates supply current scaling, which allows for lower power consumption at lower gain codes. Figure 20 shows the NOISE AND DOCSIS typical relationship between supply current and gain code. At minimum gain, the AD8324 output noise spectral density is 1.3 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, DISTORTION, ADJACENT CHANNEL POWER, AND Spurious Emissions in 5 MHz to 42 MHz, specifies the output DOCSIS noise for various symbol rates. The calculated noise power in To deliver the DOCSIS required 58 dBmV of QPSK signal and dBmV for 160 kSym/s is 55 dBmV of 16 QAM signal, the PA is required to deliver up to 2 61 dBmV. This added power is required to compensate for 20 × log [√(1.3 nV/√Hz) × 160 kHz] + 60 = –65.7 dBmV losses associated with the diplex filter or other passive compo- Comparing the computed noise power of –65.7 dBmV to the nents that may be included in the upstream path of cable +8 dBmV signal yields –73.7 dBc, which meets the required modems or set-top boxes. It should be noted that the AD8324 level set forth in DOCSIS Table 6-10. As the AD8324 gain is was characterized with a differential input signal. Figures 7 to increased above this minimum value, the output signal 10 show the AD8324 second and third harmonic distortion increases at a faster rate than the noise, resulting in a signal-to- performance versus the fundamental frequency for various noise ratio that improves with gain. In transmit disable mode, output power levels. These figures are useful for determining the output noise spectral density is 1.1 nV/√Hz, which results in the in-band harmonic levels from 5 MHz to 65 MHz. –67 dBmV when computed over 160 kSym/s. The noise power Harmonics higher in frequency (above 42 MHz for DOCSIS was measured directly at the AD8324AR-EVAL’s output. and above 65 MHz for Euro-DOCSIS) will be sharply attenuated by the low-pass filter function of the diplexer. Rev. A | Page 12 of 16 AD8324 Z × 1100Ω IN EVALUATION BOARD FEATURES AND OPERATION R4 = 1100Ω – Z IN The AD8324 evaluation board and control software can be used V IN+ to control the AD8324 upstream cable driver via the parallel port of a personal computer. A standard printer cable connected Z R4 IN AD8324 to the parallel port of the PC is used to feed all the necessary data to the AD8324 using the Windows® based control software. This package provides a means of controlling the gain and the power mode of the AD8324. With this evaluation kit, the Figure 25. Single-to-Differential Circuit AD8324 can be evaluated in either a single-ended or differential input configuration. A schematic of the evaluation board is SINGLE-ENDED SOURCE provided in Figure 29. Although the AD8324 was designed to have optimal DOCSIS DIFFERENTIAL SIGNAL SOURCE performance when used with a differential input signal, the AD8324 may also be used as a single-ended receiver, or as an IF Typical applications for the AD8324 use a differential input digitally controlled amplifier. However, as with the single-ended signal from a modulator or a DAC. Refer to Table 8 for to differential configuration noted previously, even order common values of R4, or calculate other input configurations harmonic distortion will be slightly degraded. using the equation in Figure 24. This circuit configuration will give optimal distortion results due to the symmetric input When operating the AD8324 in a single-ended input mode, signals. It should be noted that this is the configuration that was terminate the part as illustrated in Figure 26. On the AD8324 used to characterize the AD8324. evaluation boards, this termination method requires the removal and shorting of R2 and R3, the removal of R4, as well Z × 1100Ω IN R4 = as the addition of 86.6 Ω at R1 and 40.2 Ω at R17 for 75 Ω 1100Ω – Z IN termination. Table 8 shows the correct values for R11 and R12 V IN+ for some common input configurations. Other input impedance configurations may be accommodated using the equations in Z R4 AD8324 IN Figure 26. V IN– Z × 550 Z × R1 IN IN R1 = R17 = 550 – Z R1 – Z IN IN Figure 24. Differential Circuit V IN+ R1 DIFFERENTIAL SIGNAL FROM Z IN AD8324 SINGLE-ENDED SOURCE The default configuration of the evaluation board implements a R17 differential signal drive from a single-ended signal source. This configuration uses a 1:1 balun transformer to approximate a Figure 26. Single-Ended Circuit differential signal. Because of the non-ideal nature of real transformers, the differential signal is not purely equal and Table 8. Common Matching Resistors opposite in amplitude. Although this circuit slightly sacrifices Differential Input Termination even order harmonic distortion due to asymmetry, it does ZIN (Ω) R2/R3 (Ω) R4 (Ω) R1/R17 (Ω) provide a convenient way to evaluate the AD8324 with a single- 50 Open 52.3 Open/Open ended source. The AD8324 evaluation board is populated with 75 Open 80.6 Open/Open a TOKO 617DB-A0070 1:1 for this purpose (T1). 100 Open 110 Open/Open Table 8 provides typical R4 values for common input 150 Open 174 Open/Open configurations. R16 must be removed, and R2 and R3 should be Single-Ended Input Termination shorted. Other input impedances may be calculated using the Z (Ω) R2/R3 (Ω) R4 (Ω) R1/R17 (Ω) IN equation in Figure 25. Refer to Figure 29 for an evaluation 50 0/0 Open 54.9/26.1 board schematic. To use the transformer for converting a single 75 0/0 Open 86.6/40.2 ended source into a differential signal, the input signal must be applied to VIN+. Rev. A | Page 13 of 16 04339-0-024 04339-0-026 04339-0-025 AD8324 OVERSHOOT ON PC PRINTER PORTS CONTROLLING GAIN/ATTENUATION OF THE AD8324 The data lines on some PC parallel printer ports have excessive overshoot, which may cause communications problems when The slide bar controls the gain/attenuation of the AD8324, presented to the CLK pin of the AD8324. The evaluation board which is displayed in dB and in V/V. The gain scales 1 dB per was designed to accommodate a series resistor and shunt LSB. The gain code from the position of the slide bar is capacitor (R9 and C5 in Figure 29) to filter the CLK signal if displayed in decimal, binary, and hexadecimal (Figure 28). required. For parallel ports with logic levels above 3.3 V, R9 and C5 may be used as an attenuator. INSTALLING VISUAL BASIC CONTROL SOFTWARE Install the CabDrive_24 software by running the setup.exe file on disk one of the AD8324 evaluation software. Follow the on- screen directions and insert disk two when prompted. Choose the installation directory and then select the icon in the upper left to complete the installation. RUNNING AD8324 SOFTWARE To load the control software, go to START, PROGRAMS, CABDRIVE_24 or select the AD8324.exe file from the installed directory. Once loaded, select the proper parallel port to communicate with the AD8324 (Figure 27). Figure 28. Control Software Interface TRANSMIT ENABLE AND SLEEP MODE The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8324 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmis- sion. The Transmit Enable button applies Logic 1 to the TXEN pin, enabling the AD8324 for forward transmission. Checking the Enable SLEEP Mode checkbox applies Logic 0 to the asyn- chronous SLEEP pin, setting the AD8324 for SLEEP mode. Figure 27. Parallel Port Selection MEMORY FUNCTIONS The Memory section of the software provides a way to alternate between two gain settings. The X–>M1 button stores the current value of the gain slide bar into memory, while the RM1 button recalls the stored value, returning the gain slide bar to the stored level. The same applies to the X–>M2 and RM2 buttons. Rev. A | Page 14 of 16 04339-0-027 04339-0-028 AD8324 C1A R2A VIN+_A 0.1μF OPEN TP9A T1A 3 1 R1A OPEN 2 R4A VCC1 73.4Ω 6 4 C9A C8A VIN–_A TOKO1 DUT1 OPEN 10μF AD8324 R3A C2A R17A 1 20 C10A OPEN 0.1μF GND GND OPEN 0.1μF 2 19 V V CC CC 3 18 C11A TP1A GND TXEN OPEN 4 17 GND RAMP R5A R6A 5 16 1kΩ 0Ω V V OUT+ IN+ R15A P1 2 6 15 0Ω V T2A V C3A OUT– 1 IN– CABLE_0A 7 14 6 OPEN GND BYP 2 VCC1 R16A 8 13 C12A DATAEN NC 4 3 OPEN 0.1μF 12 9 TOKOB5F SDATA SLEEP TP2A 10 11 C13A CLK GND R7A R8A 0.1μF 1kΩ 0Ω P1 3 C4A P1 19 OPEN P1 20 TP3A P1 21 R9A R10A P1 22 1kΩ 0Ω P1 5 P1 23 C5A OPEN P1 24 P1 25 TP4A P1 26 R11A R12A 1kΩ 0Ω P1 27 P1 6 TP10A C6A P1 28 OPEN TP11A P1 29 TP12A TP5A P1 30 TP_AGND1 TP_VCC1 R13A R14A P1 31 1kΩ 0Ω AGND1 VCC1 P1 7 C7A OPEN P1 16 Figure 29. AD8324 Evaluation Board Schematic Rev. A | Page 15 of 16 04339-0-029 AD8324 OUTLINE DIMENSIONS 0.60 4.00 PIN 1 MAX BSC SQ INDICATOR 0.60 MAX 20 16 1 15 PIN 1 2.25 INDICATOR TOP 3.75 2.10 SQ VIEW BCS SQ 1.95 11 5 0.75 10 6 0.55 0.25 MIN 0.35 0.80 MAX 0.30 12° MAX 0.65 TYP 1.00 0.23 0.05 MAX 0.85 0.18 0.02 NOM 0.80 0.20 SEATING COPLANARITY 0.50 REF PLANE 0.08 BSC COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 30. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters 0.341 BSC 20 11 0.154 BSC 0.236 1 BSC 10 PIN 1 0.065 0.069 0.049 0.053 8° 0.010 0.025 0.012 0° SEATING 0.050 0.004 0.010 BSC 0.008 PLANE 0.016 0.006 COPLANARITY 0.004 COMPLIANT TO JEDEC STANDARDS MO-137-AD Figure 31. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches ORDERING GUIDE Model Temperature Range Package Description Package Option AD8324JRQ –25°C to +70°C 20-Lead QSOP RQ-20 AD8324JRQ-REEL –25°C to +70°C 20-Lead QSOP RQ-20 AD8324JRQ-REEL7 –25°C to +70°C 20-Lead QSOP RQ-20 1 AD8324JRQZ –25°C to +70°C 20-Lead QSOP RQ-20 1 AD8324JRQZ-REEL –25°C to +70°C 20-Lead QSOP RQ-20 1 AD8324JRQZ-REEL7 –25°C to +70°C 20-Lead QSOP RQ-20 AD8324ACP –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 AD8324ACP-REEL7 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 1 AD8324ACPZ –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 1 AD8324ACPZ-REEL7 –40°C to +85°C 20-Lead LFCSP_VQ CP-20-1 AD8324JRQ-EVAL Evaluation Board AD8324ACP-EVAL Evaluation Board 1 Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04339–0–7/05(A) Rev. A | Page 16 of 16