ANALOG DEVICES AD8321

Gain Programmable a CATV Line Driver AD8321 FEATURES FUNCTIONAL BLOCK DIAGRAM Linear in dB Gain Response Over >53 dB Range VCC GND Drives Low Distortion >11 dBm Signal into 75 � Load: –53 dBc SFDR at 42 MHz Very Low Output Noise Level PWR AMP Maintains Constant 75 � Output Impedance AD8321 VOUT Power-Up and Power-Down Condition No Line Transformer Required VIN+ REVERSE INV ATTENUATOR CORE AMP Upper Bandwidth: 235 MHz (Min Gain) VIN– 9V Single Supply Operation Power-Down Functionality DATA LATCH DATA SHIFT REGISTER Supports SPI Interface POWER- Low Cost DOWN/ PD SWITCH INTER DATA SHIFT REGISTER APPLICATIONS Gain Programmable Line Driver HFC High Speed Data Modems Interactive CATV Set-Top Boxes DATEN CLK SDATA CATV Plant Test Equipment General Purpose IF Variable Gain Block DESCRIPTION The AD8321 is packaged in a low cost 20-lead SOIC, operates The AD8321 is a low cost digitally controlled variable gain from a single +9 V supply, and has an operational temperature amplifier optimized for coaxial line driving applications such as range of –40∞C to +85∞C. cable modems that are designed to the DOCSIS* (upstream) standard. An 8-bit serial word determines the desired output gain –40 f = 42MHz O over a 53.4 dB range, resulting in gain changes of 0.75 dB/LSB. V = 137mV p-p IN (P = –15dBm) IN The AD8321 comprises a digitally controlled variable attenuator –50 (P = 11dBm @ OUT of 0 dB to –53.4 dB, which is preceded by a low noise, fixed MAX GAIN) gain buffer and followed by a low distortion high power ampli­ –60 fier. The AD8321 accepts a differential or single-ended input HD3 signal. The output is specified for driving a 75 W load, such as coaxial cable, although the AD8321 is capable of driving other –70 loads. Performance of –53 dBc is achieved with an output level HD2 up to 11 dBm at 42 MHz bandwidth using a 9 V supply. –80 A key performance and cost advantage of the AD8321 results from the ability to maintain a constant 75 W output impedance during power-up and power-down conditions. This eliminates –90 0 8 16 24 32 40 48 56 64 72 the need for external 75 W termination, resulting in twice the GAIN CONTROL – Decimal effective output voltage when compared to a standard opera­ Figure 1. Harmonic Distortion vs. Gain Control tional amplifier, thus eliminating the need for a transformer. *Data-Over-Cable Service Interface Specifications REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/461-3113 © 2005 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. DISTORTION – dBc (@ V = +9 V, T = +25�C, V = 0.137 V p-p, single-ended input, R = 75 �, R = CC A IN L IN 75 � unless otherwise noted) AD8321–SPECIFICATIONS Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Specified AC Voltage Output = 11 dBm, Max Gain 0.137 V p-p Noise Figure Max Gain, f = 10 MHz 15 dB Input Resistance Single-Ended Input 820 W Differential Input 900 W Input Capacitance 2.0 pF GAIN CONTROL INTERFACE Gain Range 52.4 53.4 54.4 dB Maximum Gain 25.25 26 26.75 dB Minimum Gain –28.15 –27.4 –26.4 dB Gain Scaling Factor 0.7526 dB/LSB OUTPUT CHARACTERISTICS Bandwidth (–3 dB) All Gain Codes 120 MHz Bandwidth Roll-Off f = 65 MHz 0.8 dB Bandwidth Peaking f = 65 MHz 0 dB Output Offset Voltage All Gain Codes, Full Temperature Range ± 30 mV Output Noise Spectral Density Max Gain, f = 10 MHz 60 nV/÷Hz Min Gain, f = 10 MHz 20 nV/÷Hz Output Noise Temperature Sensitivity 0 £ T £ +70∞C, Min Gain 0.02 nV/÷Hz/∞C A Power-Down Spectral Density 1 nV/÷Hz 1 dB Compression Point Max Gain, f = 10 MHz 19.5 dBm Output Impedance Power-Up and Power-Down 60 75 90 W OVERALL PERFORMANCE Worst Harmonic Distortion f = 42 MHz, P = 11 dBm, V = +9 V –53 dBc OUT CC f = 65 MHz, P = 11 dBm, V = +9 V –51 dBc OUT CC Distortion Temperature Sensitivity –40∞C £ T £ +85∞C 0.03 dBc/∞C A Gain Accuracy f = 10 MHz, All Gain Codes ± 0.2 dB Gain Temperature Sensitivity 0 £ T £ +70∞C 0.004 dB/∞C A Output Settling to 1 mV Gain Change @ T = 1 Min to Max Gain, V = 0 V 60 ns DATEN IN Input Change Max Gain, V = 0.15 V Step 30 ns IN Signal Feedthrough Power Down, 65 MHz, Min Gain –80 dBc V = 0.137 V p-p IN POWER CONTROL Power-Down Settling Time to 1 mV Max Gain, V = 0 40 ns IN Power-Up Settling Time to 1 mV Max Gain, V = 0 300 ns IN Power-Up/Down Pedestal Offset Max Gain, V = 0 ± 30 mV IN Power-Up/Down Glitch Max Gain, V = 0 40 mV p-p IN POWER SUPPLY Quiescent Current Power-Up, V = +9 V 82 90 97 mA CC Power-Down, V = +9 V 45 52 60 mA CC Specifications subject to change without notice. REV. A –2– AD8321 LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA, V = +9 V; Full Temperature Range) CC Parameter Min Typ Max Unit Logic “1” Voltage 2.1 5.0 V Logic “0” Voltage 0 0.8 V Logic “1” Current (V = 5 V) CLK, SDATA, DATEN 0 20 nA INH Logic “0” Current (V = 0 V) CLK, SDATA, DATEN –600 –100 nA INL Logic “1” Current (V = 5 V) PD 50 190 mA INH Logic “0” Current (V = 0 V) PD –250 –30 mA INL (Full Temperature Range, V = +9 V, T = T = 4 ns, f = 8 MHz unless otherwise noted.) TIMING REQUIREMENTS CC R F CLK Parameter Min Typ Max Unit Clock Pulsewidth (T ) 16.0 ns WH Clock Period (T ) 32.0 ns C Setup Time SDATA vs. Clock (T ) 5.0 ns DS Setup Time DATEN vs. Clock (T ) 15.0 ns ES Hold Time SDATA vs. Clock (T ) 5.0 ns DH Hold Time DATEN vs. Clock (T ) 3.0 ns EH Input Rise and Fall Times, SDATA, DATEN, Clock (T , T ) 10 ns R F Specifications subject to change without notice. T DS VALID DATA WORD G1 VALID DATA WORD G2 SDATA MSB. . . .LSB T C T WH CLK T T ES EH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) T OFF PD T GS T ON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PEDESTAL Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB-1 MSB-2 T T DS DH CLK Figure 3. SDATA Timing REV. A –3– AD8321 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION Supply Voltage +V S Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V SDATA 1 20 VCC Input Voltages CLK 2 19 VIN– Pins 18, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V 3 18 VIN+ DATEN Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V GND 4 17 VCC Internal Power Dissipation 5 16 Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W GND BYP1 AD8321 TOP VIEW Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C 6 15 PD GND (Not to Scale) Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C 7 14 VCC BYP2 Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300∞C 8 13 GND VCC *Stresses above those listed under Absolute Maximum Ratings may cause perma- 9 12 VCC GND nent damage to the device. This is a stress rating only; functional operation of the 10 11 VOUT GND device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description � Package Option JA 1 AD8321AR –40∞C to +85∞C 20-Lead SOIC 58∞C/W R-20 1 AD8321AR-REEL –40∞C to +85∞C 20-Lead SOIC 58∞C/W R-20 2 1 AD8321ARZ –40∞C to +85∞C 20-Lead SOIC 58∞C/W R-20 2 1 AD8321ARZ-REEL –40∞C to +85∞C 20-Lead SOIC 58∞C/W R-20 AD8321-EVAL Evaluation Board 1 Thermal Resistance measured on SEMI standard 4-layer board. 2 Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8321 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. PIN FUNCTION DESCRIPTIONS Pin Function Description 1 SDATA Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. 2 CLK Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. 3 DATEN Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to­ 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previ­ ous gain state) and simultaneously enables the register for serial data load. 4, 11, 12, 13, 15, 16 GND Common External Ground Reference. 5 BYP1 V /2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC). This CC port should be externally ac-decoupled (0.1 mF capacitor). For external use of this reference voltage, buffering is required. 6 PD Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and disables the reverse amplifier. 7, 8, 9, 17, 20 VCC Common Positive External Supply Voltage. 10 VOUT Output Signal Port. DC-biased to approximately V /2. CC 14 BYP2 Internal Bypass. This pin must be externally ac-decoupled (0.1 mF capacitor). 18 VIN+ Noninverting Input. DC-biased to approximately V /2. For single-ended inverting operation, use CC 0.1 mF decoupling capacitor between VIN+ and ground. 19 VIN– Inverting Input. DC-biased to approximately V /2. Should be ac-coupled with a 0.1 mF capacitor. CC REV. A –4– Typical Performance Characteristics–AD8321 30 70 0.6 f = 10MHz PD =1 20 71D 60 0.3 f = 10MHz 10 50 0 0 46D f = 42MHz 40 –0.3 –10 23D 30 –0.6 –20 f = 65MHz 20 –0.9 –30 00D –40 10 –1.2 0 8 16 24 32 40 48 56 64 72 0 8 16 24 32 40 48 56 64 72 0.1 1 10 100 1000 GAIN CONTROL – Decimal GAIN CONTROL – Decimal FREQUENCY – MHz Figure 4. Gain Error vs. Gain Control Figure 5. AC Response Figure 6. Output Referred Noise vs. Gain Control 70 –30 –47 P = –14dBm f = 65MHz IN P = –15dBm O PD = 1 IN (P = 12dBm @ OUT V = 0.137V p-p (P = 11dBm @ IN OUT 60 MAX GAIN) MAX GAIN) (P = –15dBm) –40 IN MAX GAIN –50 (P = 11dBm @ OUT (71D) P = –13dBm 50 MAX GAIN) IN (P = 13dBm @ OUT –50 MAX GAIN) 40 –53 HD3 –60 30 MIN GAIN –56 HD2 (00D) –70 P = –17dBm IN 20 (P = 9dBm @ OUT MAX GAIN) 10 –59 –80 0 8 16 24 32 40 48 56 64 72 5 15 25 35 45 55 65 1 10 100 GAIN CONTROL – Decimal FUNDAMENTAL FREQUENCY – MHz FREQUENCY – MHz Figure 7. Output Referred Noise vs. Figure 8. Harmonic Distortion vs. Figure 9. Second Order Harmonic Frequency Gain Control Distortion vs. Frequency for Various Input Levels 20 –47 30 P = –13dBm P = 11dBm IN OUT P = 11dBm OUT (P = 13dBm @ MAX GAIN 29 OUT MAX GAIN MAX GAIN) P = –14dBm 0 IN –50 28 (P = 12dBm @ OUT MAX GAIN) 27 –20 –53 26 P = –15dBm IN –40 (P = 11dBm @ 25 OUT MAX GAIN) –56 24 –60 P = –17dBm IN 23 (P = 9dBm @ OUT MAX GAIN) –59 –80 22 5 15 25 35 45 55 65 41.0 41.4 41.8 42.2 42.6 43.0 5 15 25 35 45 55 65 FUNDAMENTAL FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz Figure 10. Third Order Harmonic Figure 11. Two-Tone Intermodula- Figure 12. Third Order Intercept vs. Distortion vs. Frequency for Various tion Distortion Frequency Input Levels REV. A –5– GAIN ERROR – dB DISTORTION – dBc OUTPUT NOISE – nV/ Hz P – dBm OUT GAIN – dB DISTORTION – dBc 3RD ORDER INTERCEPT – dBm DISTORTION – dBc OUTPUT NOISE – nV/ Hz AD8321 34 5mV 15mV MIN GAIN MAX GAIN MAX GAIN V = 0V p-p IN V = 0V p-p IN P = 11dBm OUT 30 V V C = 10pF OUT L OUT C = 0pF L 26 C = 20pF L 22 C = 50pF L PD PD 18 5V 75ns 5V 75ns 14 1 10 100 FREQUENCY – MHz Figure 13. AC Response for Various Figure 14. Power Up/Power Down Figure 15. Power Up/Power Down Capacitor Loads Glitch Glitch 0 MAX GAIN 7.5mV 0.75V PD = 0 V = 0V p-p – 0.137V p-p IN –20 V OUT V OUT MAX GAIN V = 0V p-p –40 IN MAX GAIN tr(CLK) = 3ns –60 CLK V IN –80 DATEN MIN GAIN 5V 150ns 200mV 30ns –100 0.1 1 10 100 1000 FREQUENCY – MHz Figure 16. Clock Feedthrough Figure 17. Input Signal Feedthrough Figure 18. Output Settling Time Due vs. Frequency to Input Change 90 100 1.5V MAX GAIN PD =1 85 90 V OUT 80 80 PD = 0 75 70 PD = 1 70 60 V PD = 0 IN 65 50 0.5V 30ns 60 40 1 10 100 –50 –25 0 25 50 75 100 FREQUENCY – MHz TEMPERATURE – �C Figure 19. Overload Recovery Figure 20. Output Impedance vs. Figure 21. Supply Current vs. Frequency Temperature REV. A –6– GAIN – dB FEEDTHROUGH – dB IMPEDANCE – � +I – mA CC AD8321 OPERATIONAL DESCRIPTION The gain transfer function is as follows: The AD8321 is a digitally controlled variable gain power ampli­ A = 26 dB – ((71 – CODE) ¥ 0.7526 dB) for CODE £ 71 V fier that is optimized for driving a 75 W cable. As a multifunc­ A = 26 dB for 71 £ CODE £ 127 V tional bipolar device on a single silicon die, it incorporates all the A = 26 dB + ((199 – CODE) ¥ 0.7526 dB) for 128 £ V analog features necessary to accommodate reverse path (upstream) CODE £ 199 high speed (5 MHz to 65 MHz) cable data modem requirements. A = 26 dB for 199 £ CODE £ 255 V The AD8321 has an overall gain range of approximately 53 dB where CODE is the decimal equivalent of the 8-bit word loaded in and is capable of greater than 100 MHz operation at output the AD8321’s data latch (see Figure 23). signal levels exceeding 12 dBm. Overall, when considering the device’s wide gain range, low distortion, wide bandwidth 30 and variable load drive, the device can be used in many variable gain block applications. 20 VCC GND 10 PWR AMP 0 AD8321 VOUT VIN+ REVERSE –10 INV ATTENUATOR CORE AMP VIN– –20 DATA LATCH DATA SHIFT REGISTER POWER- –30 DOWN/ 0 32 64 96 128 160 192 224 256 PD SWITCH GAIN CODE – Decimal INTER DATA SHIFT REGISTER Figure 23. Linear-In dB Gain vs. Gain Control The AD8321 is composed of four analog functions in the DATEN CLK SDATA power-up or forward mode. The input amplifier (preamp) which can be used single-endedly or differentially and provides a maxi­ Figure 22. Functional Block Diagram mum of 12 dB of attenuation. If the input is used in the differ­ The digitally programmable gain is controlled by the three-wire ential configuration, it is imperative that the input signals are “SPI” compatible inputs. These inputs are called SDATA 180 degrees out of phase and of equal amplitudes. This will (serial data input port), DATEN (data enable low input port) ensure the proper gain accuracy and harmonic performance. and CLK (clock input port). See Pin Function Descriptions The preamp stage drives a vernier stage that provides the fine and Functional Block diagram. The AD8321 is programmed by tune gain adjustment. The 0.7526 dB step resolution is imple­ an 8-bit “attenuator” word. When a standard 8-bit word is mented in this stage. After the vernier stage, a DAC provides the used, the first data bit MSB will be shifted out of the 7-bit shift bulk of the AD8321’s attenuation (six bits or 36 dB). The signals register during the eighth rising CLK edge. The lower seven in the preamp and vernier gain blocks are differential to improve bits will then be loaded into the AD8321’s digital decode sec­ the PSRR and linearity. A single-ended current is fed from the tion when the DATEN input is taken high. DAC into the output stage, which amplifies this current to the The gain of the AD8321 is linear in steps of 0.7526 dB. The appropriate level necessary to drive a 75 W load. The output gain transfer function starts at –27.43 dB (at decimal code 0) stage utilizes negative feedback to implement a 75 W output and increases 0.7526 dB/LSB. The gain increases up to decimal impedance. This eliminates the need for an external 75 W match­ code 71. At this point the gain is at its maximum level of 26 dB. ing resistor needed in typical video (or video filter) termination If a decimal word between 71 and 127 is entered, the gain is no requirements. longer incremented and stays at 26 dB. Since the MSB of an 8-bit word is a “don’t care” bit, at decimal code 128, the AD8321’s gain returns to its minimum value. The gain vs. gain control relationship repeats itself as shown in Figure 23 for the upper 127 codes. REV. A –7– GAIN – dB AD8321 The attenuation setting in the AD8321 is determined by the APPLICATIONS 8-bit word in the data latch. The SDATA load sequence is General Application initiated by a falling edge on DATEN. The gain control data The AD8321 is primarily intended for use as the return path (SDATA) is serially loaded (MSB first) into the 7-bit shift register (also called upstream path) Power Amplifier (PA) or line driver at each rising edge of the clock. See Figure 24. While DATEN in cable modem applications. Upstream data is modulated in is low, the data latch holds the previous data word allowing the either QPSK or QAM format. This is done either in DSP or by attenuation level to remain unchanged. After eight clock cycles a dedicated QPSK/QAM modulator such as the AD9853 or the new data word is fully loaded and DATEN is switched high. other modem/modulator chip. The amplifier receives its input This enables the data latch and the loaded register data is passed to signal either from the dedicated QPSK/QAM modulator or from the attenuator with the updated gain value. Also at this DATEN a DAC. In both cases, the signal must be low-pass filtered transition, the internal clock is disabled, thus inhibiting new before being applied to the line driving amplifier. Because the serial input data. distance to the central office varies from cable modem sub­ scriber to subscriber, resulting in various line losses, signals from The power amplifier has two basic modes of operation. A for­ various subscribers will require attenuation while others may ward mode (or power-up mode) and a reverse mode (or power- require gain. As a result, the AD8321 line driver is required to down) mode. In the power-up mode (PD = 1), the power vary its output applying attenuation or gain as needed so that all amplifier stage is enabled and the AD8321 has a maximum gain signals arriving at the central office are of the same amplitude. of 20 V/V or 26 dB (into 75 W). With a total attenuation of 53.43 dB in the DAC, vernier and preamp, the AD8321’s total DOCSIS (Data Over Cable Service Interface Specifications) gain range is 26 dB to –27.43 dB. In both the forward or reverse requires a cable modem output signal ranging in power from a mode the single-ended output signal maintains a dc level of minimum of 8 dBmV to a maximum of 58 dBmV. In cable V /2. This dc output level provides for optimum large signal modem applications where DOCSIS compliance is desired, the CC linearity. AD8321 amplifier must be used in conjunction with a 75 W matching attenuator connected between the AD8321 output In the power-down mode (PD = 0), the power amplifier is and the low-pass input port of the diplexer. See the schematic in turned off and a “reverse” amplifier (the inner triangle in Figure Figure 28. The matching attenuator is used to achieve DOCSIS- 22) is enabled. During this 1-to-0 transition, the output power compliant noise levels at the lower end of the AD8321 output is disabled. This assures that S11 and S22 remain approximately power range. The insertion loss of a diplexer is typically less equal to zero thus minimizing line reflections. In the time domain, than 1 dB. As a result of these combined losses, the PA line as PD switches states, a transitional glitch and pedestal offset driver must be capable of delivering sufficient power into a 75 W results (See Figures 14 and 15). These anomalies have been load while maintaining reasonable distortion performance at the minimized by temperature compensated internal circuitry and output of the modem. (See sections containing “DOCSIS” for laser trimming. The powered down supply current drops to 52 mA further information. All references to DOCSIS pertain to versus 90 mA in the power-up mode. SP-RFI-I04-980724 entitled Radio Frequency Interface Specification.) T DS VALID DATA WORD G1 VALID DATA WORD G2 SDATA MSB. . . .LSB T C T WH CLK T T ES EH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) T OFF PD T GS T ON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PEDESTAL Figure 24. Serial Interface Timing REV. A –8– AD8321 Basic Connection Input Bias, Impedance and Termination Figure 25 shows the basic schematic for operating the AD8321 On the input side, the VIN+ and VIN– have a dc bias level in single-ended inverting mode. To operate in inverting mode, equal to (V /2) – 0.2 V. The input signal must therefore be CC connect the input signal through an ac coupling capacitor to ac-coupled before being applied to either input pin. The input VIN–; VIN+ should be decoupled to ground with a 0.1 mF impedance, when operated in single-ended mode is roughly capacitor. Because the amplifier operates from a single supply, 820 W (900 W in differential mode). An external shunt resis­ and the differential input pins are biased to approximately tance (R1) to ground of 82.5 W is required to create a single- V /2, the differential inputs must be ac-coupled using 0.1 mF ended input impedance of close to 75 W. If single-ended 50 W CC capacitors. For operation in the noninverting mode, the VIN– termination is required, a 53.6 W shunt resistor may be used. pin should be decoupled to ground via a 0.1 mF capacitor, with Differential input operation may be achieved by using a shunt the input signal being fed to the AD8321 through the (ac-coupled) resistor of 41 W to ground on each of the inputs, or 82.6 W VIN+ pin. Inverting mode should be chosen if the AD8321 is across the inputs resulting in a differential input impedance of being used as a drop-in replacement for the AD8320 (the approximately 75 W. Note: to avoid dc loading of either the AD8321 predecessor). Balanced differential inputs to the VIN+ or VIN– pin, the ac-coupling capacitor must be placed AD8321 may also be applied at an amplitude that is one-half between the input pin(s) and the shunt resistor(s). Refer to the the specified single-ended input amplitude. See the Differential Differential Inputs section for more details on this mode of Inputs section for more on this mode of operation. operation. Power Supply and Decoupling Output Bias, Impedance and Termination The AD8321 should be powered with a good quality (i.e., low On the output side, the VOUT pin is also dc-biased to V /2 or CC noise) single supply of 9 V. Although the AD8321 circuit will midway between the supply voltage and ground. The output function at voltages lower than 9 V, optimum performance will signal must therefore be ac-coupled before being applied to the not be achieved at lower supply settings. Careful attention must load. The dc-bias voltage is available on the BYP1 and BYP2 be paid to decoupling the power supply pins. A 10 mF capacitor pins (Pins 5 and 14 respectively) and can be used in dc-biasing located in near proximity to the AD8321 is required to provide schemes. These nodes must be decoupled to ground using a good decoupling for lower frequency signals. In addition, and 0.1 mF capacitor as shown in Figure 25. If the BYP1 and/or more importantly, five 0.1 mF decoupling capacitors should be BYP2 voltages are used externally, they should be buffered. located close to each of the five power supply pins (7, 8, 9, 17, External back termination resistors are not required when using and 20). A 0.1 mF capacitor must also be connected to the pins the AD8321. The output impedance of the AD8321 is 75 W and labeled BYP1 and BYP2 (Pins 5 and 14) to provide decoupling is maintained dynamically. This on chip back termination is to internal nodes of the device. All six ground pins should be maintained regardless of whether the amplifier is in forward connected to a common low impedance ground plane. transmit mode or reverse powered down mode. If the output signal is being evaluated on 50 W test equipment such as a spectrum analyzer, a 75 W to 50 W adapter (commonly called a minimum loss pad) should be used to maintain a properly matched circuit. VCC C4 C5 +9V C7 C8 C9 C10 C11 0.1�F 0.1�F C6 0.1�F 0.1�F 0.1�F 0.1�F 0.1�F 10�F VCC VCC VCC VCC VCC BYP1 BYP2 C2 Ce 0.1�F 0.1�F VIN+ VOUT TO AD8321 DIPLEXER R = 75� IN C1 0.1�F ATTENUATOR VIN– CORE INPUT R1 POWER­ 82.5� DOWN/ SWITCH DATA LATCH INTER DATA SHIFT REGISTER CLK SDATA GND GND GND GND GND DATEN DATEN CLK SDATA PD Figure 25. Basic Connection for Single-Ended Inverting Operation REV. A –9– AD8321 Varying the Gain and SPI Programming Between Burst On/Off Transients, Asynchronous Power- The gain of the AD8321 can be varied over a range of 53 dB from Down and DOCSIS approximately –27 dB to +26 dB, in increments of approximately A 42% reduction in consumed power may be achieved asynchro­ 0.7526 dB per LSB. Programming the gain of the AD8321 is nously by applying Logic 0 to PD Pin 6 activating the on-chip accomplished using conventional Serial Peripheral Interface or “reverse amplifier.” The supply current is then reduced to SPI protocol. Three digital lines, DATEN, CLK and SDATA, approximately 52 mA and the modem can no longer transmit in are used to stream eight bits of data into the serial shift register the upstream direction. The on-chip reverse amplifier is designed of the AD8321. Changing the state of the DATEN port from to reduce “between burst noise” and maintain a 75 W source Logic 1-to-0 starts the load sequence by activating the CLK impedance to the low pass port of the modem’s diplexer while line. No changes in output signal are realized during this transi­ minimizing power consumption. Changing the logic level applied tion. Subsequently, any data applied to SDATA is clocked into to the PD pin will result in a Burst On/Off Transient at the the serial shift register Most Significant Bit (MSB) first and on output of the AD8321. The transient results from switching the rising edge of each CLK pulse. The AD8321 may be pro­ between the forward transmit amplifier and the powered down grammed to deliver maximum gain (+26 dB) at decimal code (reverse) amplifier. Although the resulting transient meets the 71. As a result, only the last seven bits of a typical 8-bit SPI DOCSIS transient amplitude requirements at maximum gain, it word effect the gain resulting in the gain response depicted in is the lower gain range (i.e., 8 dBmV to 31 dBmV) where the Figure 22. Since the SPI codes from 0 through 71 appear digi­ AD8321 may exceed the 7 mV maximum. The diplexer may tally identical to codes 128 through 199 for all bits except the further reduce the glitch amplitude. An external RF switch, such MSB, the AD8321 repeats the gain vs. decimal code response as Alpha Industries AS128-73 GaAs 2 Watt High Linearity twice in the 256 available codes (see Operational Description for SPDT RF switch, may be used to further reduce the spurious gain equations and Figure 23 for Gain Response). The MSB of emissions, improve the isolation between the cable plant and the a typical SPI word (i.e., the first data bit presented to the SDATA upstream line driver and switch in a 75 W back termination line after the DATEN transition from Logic 1 to 0 and prior to required to maintain proper line termination to the LP port of the rising edge of the first clock pulse) is disregarded or ignored. the diplexer (see Figure 28). Data enters the serial shift register through the SDATA port Noise and DOCSIS on the rising edge of the next seven CLK pulses. Returning the One of the most difficult issues facing designers of DOCSIS DATEN line to Logic 1 latches the content of the shift register compliant modems is maintaining a quiet output from the PA into the attenuator core resulting in a well controlled change in during times when no information is being transmitted upstream. output signal level. The timing diagram for AD8321’s serial In addition, maintaining proper signal-to-noise ratios serves to interface is shown in Figure 24. ensure the quality of transmitted data. This is extremely critical Gain Dependence on Load Impedance when the output signal of the modem is set to the minimum The AD8321 has a dynamic output impedance of 75 W. This DOCSIS specified output level or 8 dBmV. The AD8321 output dynamic output impedance is trimmed to provide a maximum noise spectral density at minimum gain (or 8 dBmV) is 20 nV/÷Hz gain of +26 dB when loaded with 75 W. Operating the AD8321 measured at 10 MHz. Considering the “Spurious Emissions at load impedances other than 75 W will only change the gain of in 5 MHz to 42 MHz” of Table 4–8 in DOCSIS, the calculated the AD8321 while the specified gain range of 53 dB is unchanged. noise power in dBmV for 160 K is: SYM/SEC Varying the load impedance will result in 6 dB of additional gain when R approaches infinity. The relationship between Ê ˆ LOAD Ê ˆ 2 Ê ˆ R and gain is depicted in Figure 26 and is described by the Á ˜ LOAD Á ˜ 20log 20nV / Hz ¥ 160E + 3 + 60 or - 41 . 5 dBmV Ë ¯ Á Á ˜˜ following equation: Ë ¯ Ë ¯ Gain (dB) = [20 log ((2 ¥ R )/(R +75))]+(26–(0.7526 ¥ LOAD LOAD Comparing the computed noise power to the signal at 8 dBmV (71-Code))) yields –49.5 dBc or 3.5 dB higher than the required –53 dBc in DOCSIS Table 4–8. An attenuator designed to match the 35 AD8321 75 W source to the 75 W load may be required. Refer­ ring to the schematic of Figure 28 and the evaluation board 30 silkscreen of Figure 31, the matching attenuator is comprised of 25 the three resistors referred to as Rc, Rd and Re. Select the at­ tenuation level from Table I such that noise floor is reduced to 20 levels specified in DOCSIS. 15 Table I. 10 Rc (�) Rd (�) Re (�) Attenuation (dB) 1304 8.65 1304 –1 5 654.3 17.42 654.3 –2 0 432 26.1 432 –3 0 100 200 300 400 500 331.5 35.75 331.5 –4 R – � LOAD Figure 26. Maximum Gain vs. R LOAD REV. A –10– GAIN – dB AD8321 Distortion and DOCSIS Overshoot on PC Printer Ports Care must be taken when selecting attenuation levels specified The data lines on some PC parallel printer ports have excessive in Table I as the output signal from the AD8321 must compen­ overshoot. Overshoot presented to the CLK pin (TP7 on the sate for the losses resulting from any added attenuation as well evaluation board) may cause communications problems. The as the insertion losses associated with the diplexer. An increase evaluation board layout was designed to accommodate a series in input signal becomes apparent at the upper end of the gain resistor and shunt capacitor (R6 and C12) if required to filter or range and will be needed to achieve the 58 dBmV at the modem condition the CLK data. output. The insertion losses of the diplexer may vary, depend­ Between Burst Transient Reduction ing on the quality of the diplexer and whether the frequency of In order to reduce the amplitude of the “Burst On/Off Tran­ operation is in near proximity to the cut-off frequency of the sient” glitch at the output of the AD8321, when switching from low-pass filter. Figures 9 and 10 show the expected second forward transmit mode to reverse powered down mode, position and third harmonic distortion performance vs. fundamental the SWb switch in Figure 28 to position “a” before changing the frequency at various input power levels. These graphs indicate logic applied to PD Pin 6 of the AD8321 from Logic 1-to-0 the worst harmonic levels exhibited over the entire output range (and also 0-to-1). Use the “Enable Output Switch” feature in of the AD8321 (i.e., –27 dB to +26 dB). Figures 9 and 10 are the evaluation board control software (see Figure 31) to select useful when it is necessary to determine inband harmonic levels the appropriate position of the AS128-73 switch. A check in this (5 MHz to 42 MHz or 5 MHz to 65 MHz). Harmonics that box enables the switch to pass upstream data to the output of the are higher in frequency, as compared to the cutoff frequency of evaluation board. The AS128-73 produces a glitch of approxi­ the low-pass filter of the diplexer, will be further suppressed by mately 5 mV p-p regardless of the AD8321 gain setting. The the stop band attenuation level of the LP filter in the diplexer. AD8321-EVAL board comes with resistors and capacitors Designers must balance the need to improve noise performance installed on the logic lines controlling the RF switch (R8, R9, by adding attenuation with the resulting need for increased C16, C17). These values were selected to reduce the glitch signal amplitude while maintaining DOCSIS specified dis­ amplitude to DOCSIS acceptable levels and may be modified tortion performance. if required. The SPDT function of the AS128-73 RF switch Evaluation Board Features and Operation accommodates the need to maintain proper termination when The AD8321 evaluation board (p/n AD8321-EVAL) and com­ the diplexer is disconnected from the output of the AD8321. panion software program written in Microsoft Visual Basic are The AD8321-EVAL board accommodates the needed back available through Analog Devices, Inc. and can be used to termination (refer to the Cb and Rb of the evaluation circuit). control the AD8321 Variable Gain Upstream Power Amplifier Differential Inputs via the parallel port of a PC. This evaluation package provides a When evaluating the AD8321 in differential input mode, termi­ convenient way to program the gain/attenuation of the AD8321 nation resistor(s) should be selected and applied such that the without the addition of any external glue logic. AD8321-EVAL combined resistance of the termination resistor(s) and the input has been developed to facilitate the use of the AD8321 in an impedance of the AD8321 results in a match between the signal application targeted at DOCSIS compliance. A low cost Alpha source impedance and the input impedance of the AD8321. The Industries AS128-73 GaAs 2 Watt High Linearity SPDT RF evaluation board is designed to accommodate Mini-Circuits T1­ switch (referred to as SWb) is included on the evaluation board 6T-KK81 1:1 transformer for the purposes of converting a (see Figure 28) along with accommodations for a user specified single-ended (i.e., ground referenced) input signal to differen­ 75 W matching attenuator (See Table I for a table of resistor tial inputs. The following paragraphs identify three options for values of attenuators ranging from –1 dB to –4 dB). The providing differential input signals to the AD8321 evaluation AD8321 DATEN, CLK and SDATA digital lines are pro­ board. Option 1 uses a transformer to produce a truly differen­ grammed according to the gain setting and mode of operation tial input signal. The termination resistor(s) specified in Option ® selected using the Windows interface of the control software 1 and 2 may also be used without the transformer if a differen­ (see Figure 30). The serial interface of the AD8321 is ad­ tial signal source is available. Option 2 uses a transformer and- dressed through the parallel port of a PC using four or more produces ground referenced input signals that are separated in bits (plus ground). Two additional bits from the parallel port phase by 180∞. Option 3 relies on differential signals provided are used to control the RF switch(s). This software programs by the user and does not employ a transformer for single-to­ the AD8321 gain or attenuation, incorporates asynchronous differential conversion. control of the power-down feature (PD Pin 6) as well as asyn­ Differential Input Option 1: Install the Mini-Circuits T1-6T­ chronous control of the Alpha Industries RF switch(es) AS128­ KK81 1:1 transformer in the T1 location of the evaluation 73.* A standard printer cable is used to feed the necessary data board. Jumpers J1, J2 and J3 should be applied pointing in the to the AD8321-EVAL board. These features allow the designer direction of the transformer. A differential input termination to fully develop and evaluate the upstream signal path begin­ resistor of 82.5 W can be used in the R3 position. This value ning at the input to the PA. should be used when the single-ended input signal has a source impedance of 75 W. In this configuration, the input signal must be applied to the VIN+/DIFF IN port of the evaluation board. An open circuit is required in R1, R2 and J4 positions resulting in a 75 W differential input termination to the AD8321. If a 50 W single-ended input source is applied to the VIN+/DIFF IN port, the R3 value should be 53.6 W. Windows is a registered trademark of Microsoft Corporation. *Alpha Industries @ www.alphaind.com REV. A –11– AD8321 Differential Input Option 2: Install the Mini-Circuits T1-6T­ Controlling the Evaluation Board from a PC KK81 1:1 transformer in the T1 location of the evaluation The AD8321-EVAL package comes with the circuit described board. Jumpers J1, J2 and J3 should be applied pointing in the by Figure 28 and includes a –2 dB attenuator (reference Rc, Rd direction of the transformer. Apply an open circuit in the R3 and Re) and the control software allowing the user to program position while J4 is applied connecting the center-tap of the the gain/attenuation of the AD8321 via a standard printer cable secondary to ground. A 41 W resistor should be used between connected to the parallel port of a PC. each input and ground at R1 and R2. This option will also Install Software result in a 75 W differential input termination to the AD8321. To install the “CABDRIVE” software that controls the AD8321­ If a 50 W single-ended input source is applied to the VIN+/ EVAL evaluation circuit, close all Windows applications and DIFF IN port, the R1 and R2 values should be 26.7 W. select the “SETUP” file located on Disk 1 of the AD8321­ Differential Input Option 3: A differential input may be EVAL software. Follow the on screen instructions (see Figure applied to both VIN– and VIN+ inputs of the evaluation board. 29) and insert Disk 2 when prompted to do so. Enter the path In this example, no transformer is employed. Jumpers J1, J2 and of the directory into which the control software will be installed. J3 are installed in line with the input signals. Select the differen­ Select the button in the upper left corner to begin the installa­ tial input termination configuration of either Option 1 or Option 2. tion of “CABDRIVE” software into the specified directory. Apply Option 1 resistor value to R3 for a true differential input Running the Software or apply Option 2 values to R1 and R2 to produce ground refer­ To invoke the control software, select the “AD8321” icon from enced inputs that are separated in phase by 180∞. If the differen­ the directory containing the installed software. After invoking tial input signal source impedance is anything other than 75 W the control software, choose the appropriate printer port from or 50 W, calculate the appropriate value according to the equa­ the display portrayed in Figure 30. tions below: Controlling the Gain/Attenuation of AD8321 For Option 1 Configurations: The AD8321 control panel has four different functions. The Desired Input Impedance = R3�900 slide bar controls the gain/attenuation of the AD8321. Adjust the slider to the gain/attenuation displayed in units of dB. The For Option 2 and 3 (R1 = R2 = R): additional displays show the selection in units of Volts (output)/ Desired Input Impedance = 2 ¥ (R�450) Volts (input), and the corresponding control codes in decimal, binary and hexadecimal. (See Figure 31.) DIFF IN “POWER UP” and “POWER DOWN” R3 T1 AD8321 The buttons marked “Power Up” and “Power Down” select the mode of operation of the AD8321. The “Power Up” button OPTION 1 DIFFERENTIAL INPUT TERMINATION puts the AD8321 in forward transmit mode feeding the condi­ tioned signal to the VOUT port on the evaluation board. Con­ R2 versely, the “Power Down” button selects the reverse mode DIFF IN where the forward signal transmission is disabled and the low T1 AD8321 noise reverse amplifier actively maintains a 75 W back termina­ tion. These features may be selected asynchronously (at any R1 time). (See the section on Between Burst Transient Reduction for more specific details.) OPTION 2 DIFFERENTIAL INPUT TERMINATION Enable Output Switch R2 An Alpha Industries AS128-73 GaAs 2W Hi Linearity switch is installed on a standard AD8321-EVAL circuit and is controlled VIN+ by the check box on the control panel portrayed in Figure 31. AD8321 This feature is intended to remove the output of the AD8321 VIN– from the VOUT port prior to using the “Power Up” and R1 “Power Down” feature described above. This application circuit OPTION 3 DIFFERENTIAL INPUT TERMINATION may be used to reduce any transients created between bursts to DOCSIS compliant levels. (See the section on Between Burst Figure 27. Differential Input Termination Options Transient Reduction for more specific details.) REV. A –12– AD8321 TP1 C1 0.1�F J3 VIN– R1 82.5� TP4 VCC TP6 C10 SDATA P1–5 1 20 TP7 R6 CLK P1–6 2 19 C12 1000pF 3 TP8 18 DATEN C2 C11 P1–2 0.1�F 4 17 AD8321 C4 5 16 TP9 PD 6 15 P1–3 NOTE: C5 C7 BYPASS CAPACITORS C4, C5, C7, 7 14 C8, C9, C10 AND C11 ARE 0.1�F. C8 8 13 V CT C9 9 12 C14 C15 10 11 10�F 0.1�F TPd TP12 Vct Jb AS128-73 TPa Cd Cc SWb 0.1�F Rf TPc 0.1�F Rd TP5 10k� TPe V1 b TO Rc Re GND DIPLEXER Ce TP13 V CC 0.1�F Cb V2 0.1�F C10 C6 Rb 0.1�F 10�F 75� R8 1k� V1 P1–8 C16 1000pF R9 1k� V2 P1–7 C17 1000pF Figure 28. AD8321-EVAL Schematic of Single-Ended Inverting Input, Upstream PA Driver Solution Using AD8321, Matching Attenuator and Alpha Industries AS128-73 RF Switch REV. A –13– AD8321 EVALUATION BOARD FEATURES AND OPERATION Figure 29. Evaluation Board Software Installation Figure 30. Evaluation Board Control Software REV. A –14– AD8321 Figure 31. Screen Display of Windows-Based Control Software REV. A –15– AD8321 Figure 32. Evaluation Board Silkscreen (Component Side) REV. A –16– AD8321 Figure 33. Evaluation Board Layout (Component Side) Figure 34. Evaluation Board Layout (Solder Side) REV. A –17– AD8321 EVALUATION BOARD BILL OF MATERIALS AD8321 Evaluation Board Rev. B SINGLE- ENDED INVERTING INPUT March 17, 1999 Qty. Description Vendor Ref Desc. 2 10 mF 16 V. 1350 size tantalum chip capacitor ADS# 4-7-6 C6 & C14 14 0.1 mF 50 V. 1206 size ceramic chip capacitor ADS# 4-5-18 C1–C5, C7–C11, Cb–e 3 1,000 pF 50 V. 1206 size ceramic chip capacitor ADS# 4-5-20 C12, C16 & C17 1 82.5 W 1% 1/8 W. 1206 size chip resistor D -K # P 82.5 FCT-ND R1 3 0 W 5% 1/8 W. 1206 size chip resistor ADS# 3-18- 88 R2 & R6, Ca 2 1.00 kW 1% 1/8 W. 1206 size chip resistor ADS# 3-18-11 R8 & 9 1 75.0 W 1% 1/8 W. 1206 size chip resistor ADS# 3-18-145 Rb 2 649 W 1% 1/8 W. 1206 size chip resistor D -K # P 649 FCT-ND Rc & Re 1 10.0 kW 1% 1/8 W. 1206 size chip resistor ADS# 3-18-119 Rf 1 17.4 W 1% 1/8 W. 1206 size chip resistor D -K # P17.4 FCT-ND Rd 1 Alpha # AS 128-73 GaAs Hi Linearity switch Alpha # AS 128-73 SWb 2 Pink Test Point ADS# 12-18-63 TPc & TPd 1 Blue Test Point [Vct] ADS# 12-18-62 TP14 6 Grey Test Point [Bus lines] ADS# 12-18-64 TP6–TP9, TP12 & TP13 2 Yellow Test Point [INPUTS] ADS# 12-18-32 TP1 & TP2 3 Orange Test Point [OUTPUTS] ADS# 12-18-60 TPa, TPb & TPe 1 Red Test Point [DUT VCC] ADS# 12-18-43 TP4 2 Black Test Point [GND] ADS# 12-18-44 TP5 & TP15 2 2 pin .1 inch ctr. shunt Berg # 65474 - 001 ADS# 11-2-38 J3 & Jb 5 2 pin .1 inch ctr. male Header Berg # 69157 - 102 ADS# 11-2-37 J3, Ja, Jb, Jc, Jd 2 75 W right-angle BNC Telegartner # J01003A1949 Comp. Mktg. Services INPUTS, OUTPUT 1 Conn. 36 pin Centronics Right Angle ADS# 12-3-50 P1 4 5-way Metal Binding Post ADS# 12-7-7 DUT VCC, GND, Vct 1 AD8321 AR ADS# AD8321AR D.U.T. 1 AD8321 REV. B Evaluation PC board E.M.C. Evaluation PC board 4 #4 - 40 ¥ 1/4 inch ss panhead machine screw ADS# 30-1-1 4 #4 - 40 ¥ 3/4 inch long aluminum round stand-off ADS# 30-16-3 2 # 2 - 56 ¥ 3/8 inch ss panhead machine screw ADS# 30-1-17 (p1 hardware) 2 # 2 steel flat washer ADS# 30-6-6 (p1 hardware) 2 # 2 steel internal tooth lockwasher ADS# 30-5-2 (p1 hardware) 2 # 2 ss hex. machine nut ADS# 30-7-6 (p1 hardware) Optional Components J1, J2, J4, R3, Ra, SWa, T1, +VIN+ REV. A –18– AD8321 OUTLINE DIMENSIONS 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (R-20) Dimensions shown in millimeters and (inches) Revision History Location Page 6/05—Data Sheet Changed from REV. 0 to REV. A. Changes to ORDERING GUIDE....................................................................................................................................................4 Updated OUTLINE DIMENSIONS.............................................................................................................................................19 REV. A –19– –20– C01013–0–6/05(A)