ANALOG DEVICES AD8303

+3 V, Dual, Serial Input a Complete 12-Bit DAC AD8303 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Dual 12-Bit DAC V DD Pretrimmed Internal Voltage Reference R Single +3 V Operation OP E V DAC A AMP OUTA 0.5 mV/Bit with 2.0475 V Full Scale En D G CS A A I Low Power: 9.6 mW C CLK S T 3-Wire Serial SPI Compatible Interface A E R D R REF Power Shutdown I < 1 mA DD BE R SDI BUF PR AF E S (DATA) Compact SO-14, 1.75 mm Height Package N G E H DR I V I REF GE S APPLICATIONS F AN T T R REF P Portable Communications E C E D BUF E R D G Digitally Controlled Calibration A I C S Servo Controls LDA T B PC Peripherals E OP DAC B AMP V R OUTB B PR LDB AD8303 DGND MSB RS AGND SHDN GENERAL DESCRIPTION A double buffered serial data interface offers high speed, three- The AD8303 is a complete (includes internal reference) dual, wire, DSP and SPI microcontroller compatible inputs using 12-bit, voltage output digital-to-analog converter designed to LDA + LDB) data in (SDI), clock (CLK) and load strobe ( operate from a single +3 volt supply. Built using a CBCMOS CS) pin simplifies connection of multiple pins. A chip-select ( process, this monolithic DAC offers the user low cost and ease- DAC packages by enabling the clock input when active low. of-use in single-supply +3 volt systems. Operation is guaranteed RS input sets the output to zero scale or to 1/2 Additionally, an over the supply voltage range of +2.7 V to +5.5 V making this scale based on the level applied to the MSB pin. A power device ideal for battery operated applications. shutdown feature reduces power dissipation to less than 3 μW. The 2.0475 V full-scale voltage output is laser-trimmed to The AD8303 is specified over the extended industrial (–40°C to maintain accuracy over the operating temperature range of the +85°C) temperature range. AD8303s are available in plastic device. The binary input data format provides an easy-to-use DIP and low profile 1.75 mm height SO-14 surface mount one-half millivolt-per-bit software programmability. The voltage packages. For single-channel DAC applications, see the outputs are capable of sourcing 3 mA. AD8300 which is offered in the 8-lead DIP and SO-8 packages. 1.0 2 V = +5V V = +5V DD DD 0.8 T = –40°C, +25°C, +85°C A 1.5 0.6 –40°C 1 0.4 +25°C 0.5 0.2 0 0 –0.2 –0.5 –0.4 –1 +85°C –0.6 –1.5 –0.8 –1.0 –2 0 1024 2048 3072 4096 0 1024 2048 3072 4096 DIGITAL INPUT CODE – Decimal DIGITAL INPUT CODE – Decimal Figure 2. Linearity Error vs. Digital Code and Temperature Figure 1. Differential Nonlinearity Error vs. Code REV. 0 Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1996 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 DNL – LSB INL LINEARITY ERROR – LSB AD8303–SPECIFICATIONS (@ V = +2.7 V to +3.6 V, –408C ≤ T ≤ +858C, unless otherwise noted) +3 V OPERATION DD A 1 Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE 2 Resolution N 12 Bits 2 Relative Accuracy INL –2 ±1/2 +2 LSB 2 Differential Nonlinearity DNL Monotonic, T = +25°C –3/4 ±1/4 +3/4 LSB A 2 Differential Nonlinearity DNL Monotonic –1 ±1/2 +1 LSB Zero-Scale Error V Data = 000 1.25 +4.5 mV ZSE H 3 2 Full-Scale Voltage V Data = FFF 2.039 2.0475 2.056 Volts FS H 3, 4 Full-Scale Tempco TCV 16 ppm/°C FS ANALOG OUTPUTS Data = 800 , ΔV < 3 mV ±3mA Output Current I OUT H OUT Output Resistance to GND R Data = 000 30 Ω OUT H 4 3 Capacitive Load C No Oscillation 500 pF L REFERENCE OUTPUT Output Voltage V Load > 1 MΩ 1V REF LOGIC INPUTS Logic Input Low Voltage V 0.6 V IL Logic Input High Voltage V 2.1 V IH Input Leakage Current I 10 μA IL 4 Input Capacitance C 10 pF IL 4, 5 INTERFACE TIMING SPECIFICATIONS Clock Width High t 40 ns CH Clock Width Low t 40 ns CL Load Pulse Width t 40 ns LDW Data Setup t 15 ns DS Data Hold t 15 ns DH Reset Pulse Width t 40 ns RS Load Setup t 15 ns LD1 Load Hold t 40 ns LD2 Select t 40 ns CSS Deselect t 40 ns CSH 4 AC CHARACTERISTICS 6 Voltage Output Settling Time t To ±0.1% of Full Scale 4 μs S 6 Voltage Output Settling Time t To ±1 LSB of Final Value 14 μs S Shutdown Recovery Time t To ±0.1% of Full Scale 10 μs DSR Output Slew Rate SR Data = 000 to FFFH to 000 2.0 V/μs H H DAC Glitch Q 15 nV/s Digital Feedthrough Q 15 nV/s SUPPLY CHARACTERISTICS Power Supply Range V DNL < ±1 LSB 2.7 5.5 V DD RANGE Shutdown Current I SHDN = 0, No Load, V = 0 V, T = +25°C 0.02 1 μA DD_SD IL A 7 Supply Current I V = 3 V, V = 0 V, No Load 2 3.2 mA DD DD IL Power Dissipation P V = 3 V, V = 0 V, No Load 6 9.6 mW DISS DD IL Power Supply Sensitivity PSS ΔV = ± 5% 0.001 0.004 %/% DD NOTES 1 Typical readings represent the average value of room temperature operation. 2 1 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. 7 See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels. Specifications subject to change without notice. –2– REV. 0 SPECIFICATIONS AD8303 (@ V = +5 V 6 10%, –408C ≤ T ≤ +858C, unless otherwise noted) +5 V OPERATION DD A 1 Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE 2 Resolution N 12 Bits 2 Relative Accuracy INL –2 ±1/2 +2 LSB 2 Differential Nonlinearity DNL Monotonic, T = +25°C –3/4 ±1/4 +3/4 LSB A 2 Differential Nonlinearity DNL Monotonic –1 ±1/2 +1 LSB Zero-Scale Error V Data = 000 1.25 +4.5 mV ZSE H 3 Full-Scale Voltage V Data = FFF 2.039 2.0475 2.056 Volts FS H 3, 4 Full-Scale Tempco TCV 16 ppm/°C FS ANALOG OUTPUTS Data = 800 , ΔV < 3 mV ±3mA Output Current I OUT H OUT Output Resistance to GND R Data = 000 30 Ω OUT H 4 Capacitive Load C No Oscillation 500 pF L REFERENCE OUTPUT Output Voltage V Load > 1 MΩ 1V REF LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10 μA IL 4 Input Capacitance C 10 pF IL 4, 5 INTERFACE TIMING SPECIFICATIONS Clock Width High t 30 ns CH Clock Width Low t 30 ns CL Load Pulse Width t 30 ns LDW Data Setup t 15 ns DS Data Hold t 15 ns DH 30 ns Reset Pulse Width t RS Load Setup t 15 ns LD1 Load Hold t 30 ns LD2 Select t 30 ns CSS Deselect t 30 ns CSH 4 AC CHARACTERISTICS 6 Voltage Output Settling Time t To ±0.1% of Full Scale 4 μs S 6 5 Voltage Output Settling Time t To ±1 LSB of Final Value 12 μs S Shutdown Recovery Time t To ±0.1% of Full Scale 10 μs SDR Output Slew Rate SR Data = 000 to FFF to 000 2V/μs H H H DAC Glitch Q 15 nV s Digital Feedthrough Q 15 nV s SUPPLY CHARACTERISTICS DNL < ±1 LSB 2.7 3.0 5.5 V Power Supply Range V DD RANGE Shutdown Supply Current I SHDN = 0, No Load, V = 0 V, T = +25°C 0.02 1 μA DD_SD IL A 7 Positive Supply Current I V = 5 V, V = 0 V, No Load 2.1 3.4 mA DD DD IL Power Dissipation P V = 5 V, V = 0 V, No Load 10.5 17 mW DISS DD IL Power Supply Sensitivity PSS ΔV = ± 10% 0.001 0.004 %/% DD NOTES 1 Typical readings represent the average value of room temperature operation. 2 1 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. 7 See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels. Specifications subject to change without notice. REV. 0 –3– AD8303 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V DD Temperature Package Package Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V Model DNL Range Description Option V to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V OUT DD I Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA OUT AD8303AN ±0.75 –40°C to +85°C 14-Pin P-DIP N-14 Package Power Dissipation . . . . . . . . . . . . . . . (T –T )/θ J MAX A JA AD8303AR ±0.75 –40°C to +85°C 14-Lead SOIC R-14 Thermal Resistance θ JA The AD8303 contains 700 transistors. The die size measures 70 mil × 99 mil. 14-Pin Plastic DIP Package (N-14) . . . . . . . . . . . . 103°C/W 14-Lead SOIC Package (R-14) . . . . . . . . . . . . . . . . 158°C/W Maximum Junction Temperature (T ) . . . . . . . . . . . 150°C J MAX Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . .+300°C *Stress above those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK t t CSS CSH CS t LD2 LDA, B t LD1 SDI t t DS DH t CL CLK t CH t LDW LDA, B t RS RS t S FS ±1 LSB V OUT ERROR BAND ZS t S a. SHDN t SDR I DD b. Figure 3. Timing Diagrams CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8303 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. 0 AD8303 Table I. Control-Logic Truth Table CS CLK RS MSB SHDN LDA/B Serial Shift Register Function DAC Register Function H X H X H H No Effect Latched L L H X H H No Effect Latched L H H X H H No Effect Latched L ↑+ H X H H Shift-Register-Data Advanced One Bit Latched ↑+ L H X H H No Effect Latched HX H X H ↓– No Effect Updated with Current Shift Register Contents H X H X H L No Effect Transparent X X L H H X No Effect Loaded with 800 H XX ↑+ H H H No Effect Latched with 800 H X X L L H X No Effect Loaded with All Zeros XX ↑+ X H H No Effect Latched All Zeros X X X X L X No Effect No Effect NOTES 1 ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care. 2 Do not clock in serial data while LDA or LDB is LOW. PIN DESCRIPTIONS Pin No. Name Function 1 AGND Analog Ground. 2V DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference OUTA maintains a fixed full-scale voltage independent of time, temperature and power supply variations. 3V Reference Voltage Output Terminal. Very high output resistance must be buffered if used as a virtual REF ground. 4 DGND Digital Ground 5 CS Chip Select, Active Low Input. Disables shift register loading when high. Does not effect LDA or LDB operation. 6 CLK Clock Input, positive edge clocks data into shift register. 7 SDI Serial Data Input, input data loads directly into the shift register. 8 LDA Load DAC register strobes, active low. Transfers shift register data to DAC A register. Asynchronous active low input. See Control Logic Truth Table for operation. 9 RS Resets DAC register to zero condition or half-scale depending on MSB pin. Asynchronous active low input. 10 LDB Load DAC register strobes, active low. Transfers shift register data to DAC B register. Asynchronous active low input. See Control Logic Truth Table for operation. 11 MSB Digital Input: Logic High presets DAC registers to half-scale 800 (sets MSB bit to one) when the RS pin H is strobed; Logic Low clears all DAC registers to zero (000 ) when the RS pin is strobed. H 12 SHDN Active low shutdown control input. Does not affect register contents as long as power is present on V . DD 13 V Positive power supply input. Specified range of operation +2.7 V to +5.5 V DD 14 V DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference OUTB maintains a fixed full-scale voltage independent of time, temperature and power supply variations. PIN CONFIGURATION 14-Pin P-DIP (N-14) 14-Lead SOIC (R-14) AGND 1 14 V OUTB V 2 13 OUTA V DD V 3 12 SHDN REF AD8303 TOP VIEW DGND 4 11 MSB (Not to Scale) CS 5 10 LDB CLK 6 9 RS LDA SDI 7 8 REV. 0 –5– AD8303–Typical Performance Characteristics 7 120 POSITIVE T = +25°C A V = +5V 6 DD CURRENT T = +25°C A DATA = 000 H 80 LIMIT NBW = 635kHz 100 5 90 40 4 DATA = 800 H V = +5V DD 0 R TIED TO L 3 +1.024V V = +3V DD –40 2 10 0% NEGATIVE –80 1 CURRENT LIMIT 0 –120 TIME = 100µs/DIV 01 2 34 5 021 LOGIC VOLTAGE – Volts OUTPUT VOLTAGE – Volts Figure 5. Broadband Noise Figure 6. Supply Current vs. Logic Figure 4. I vs. V OUT OUT Input Voltage 75 V = +5V ± 10% DD 50mV 1V 5µs 60 100 100 90 90 T = +25°C A V V OUT OUT DATA = 800 H 45 V = +3V ± 10% 30 DD LD LD 10 10 0% 0% 15 5V 200ns 5V 0 CODE 800 TO 7FF H H 10 100 1k 10k 100k 1M FREQUENCY – Hz Figure 7. Power Supply Rejection Figure 8. Midscale Transition Figure 9. Large Signal Settling Time vs. Frequency Performance 120 2.5 TUE = ∑ (INL+ZS+FS) NO LOAD SS = 200 UNITS SS = 200 UNITS 10mV 100 2.0 V = +2.7V NORMALIZED TO +25°C DD 100 90 80 1.5 V OUT 60 1.0 V = +5.5V DD V = +2.7V DD 40 0.5 10 0% CLK 20 0 2V 1µs 0 –0.5 –5 –3 –1 1 3 5 7 9 11 13 15 –55 –35 –15 5 25 45 65 85 105 125 TOTAL UNADJUSTED ERROR – LSB TEMPERATURE – °C Figure 12. Full-Scale Voltage Drift Figure 11. Total Unadjusted Figure 10. Clock Feedthrough vs. vs. Temperature Error Histogram Time REV. 0 –6– POWER SUPPLY REJECTION – dB OUTPUT CURRENT – mA BROADBAND NOISE – 200µV/DIV FREQUENCY V DRIFT – mV OUT SUPPLY CURRENT – mA AD8303 2.0 10 2 NO LOAD SS = 200 UNITS V = +2.7V 1.5 DD V = +5V DD 1.5 NORMALIZED TO +25°C SS = 212 UNITS DATA = FFF H V = +2.7V DD 1.0 1 0.5 1 0.5 V = +4.5V DD FULL SCALE (DATA = FFFH) 0.0 0 –0.5 –0.5 ZERO SCALE (DATA = 000 ) H –1.0 0.1 –1 –55 –35 –15 5 25 45 65 85 105 125 1 10 100 1k 10k 100k 0 100 200 300 400 500 600 TEMPERATURE – °C HOURS OF OPERATION AT +150°C FREQUENCY – Hz Figure 13. Zero-Scale Voltage Drift Figure 14. Output Voltage Noise Figure 15. Long-Term Drift vs. Temperature Density vs. Frequency Accelerated by Burn-In 30 6 70 χ +2σ V = +5.5V, DD V = 2.4V, DATA = FFF 25 LOGIC H 60 V = +2.7V DD 5 SS = 200 UNITS χ T = –40 TO +85°C A 50 20 V = +3.6V, DD 4 V = 2.1V, DATA = FFF LOGIC H 40 15 χ –2σ 3 30 10 20 V = +5V DD 2 5 V = +3.0V OR +5.0V, DD SS = 212 UNITS 10 V = 0V, DATA = 000 LOGIC H 0 1 0 0 100 200 300 400 500 600 –60 –40 –20 0 20 40 60 80 100 120 140 –40 –32 –24 –16 –8 0 8 16 24 HOURS OF OPERATION AT +150°C TEMPERATURE – °C TEMPERATURE COEFFICIENT – ppm/ °C Figure 16. Shutdown Current vs. Figure 17. Supply Current vs. Figure 18. Full-Scale Output Time Accelerated by Burn-In Temperature Tempco Histogram 1000 500mV 500mV 100 100 90 90 V OUT V OUT 100 V = +5.5V DD 10 10 0% SHDN 0% SHDN 1µs 5V 1µs 5V 10 –55 –35 –15 5 25 45 65 95 105 125 TEMPERATURE – °C Figure 19. Shutdown Current vs. Figure 20. Shutdown Recovery Time Figure 21. Shutdown Time Temperature REV. 0 –7– I SHUTDOWN CURRENT – nA SHUTDOWN CURRENT – nA DD V DRIFT – mV OUT OUTPUT VOLTAGE NOISE DENSITY – µV/Hz I SUPPLY CURRENT – mA DD NOMINAL VOLTAGE CHANGE – mV FREQUENCY AD8303 THEORY OF OPERATION OUTPUT SECTION The AD8303 is a complete, ready-to-use, dual, 12-bit digital-to- The rail-to-rail output stage of this amplifier has been designed analog converter. Only one +2.7 V to +5.5 V power supply is to provide precision performance while operating near either necessary for operation. It contains two voltage-switched, 12-bit, power supply. Figure 23 shows an equivalent output schematic laser-trimmed digital-to-analog converters, a curvature- of the rail-to-rail amplifier with its N-channel pull-down FETs corrected bandgap reference, rail-to-rail output op amps, input that will pull an output load directly to GND. The output shift register, and two DAC registers. The serial data interface sourcing current is provided by a P-channel pull-up device that consists of a serial data input (SDI), clock (CLK), chip select can source current to GND terminated loads. (CS) and two DAC load strobe pins (LDA and LDB). The rail-to-rail output stage permits operation at supply For battery operation and similar low power applications, a voltages down to +2.7 V. The N-channel output pull-down shutdown feature (SHDN) is available to reduce power supply MOSFET shown in Figure 23 has a 35 Ω ON resistance which current to less than 1 μA. In addition an asynchronous reset pin sets the sink current capability near ground. In addition to (RS) will set both DAC outputs to either zero volts or to resistive load driving capability, the amplifier has also been midscale, depending on the logic value applied to the MSB pin. carefully designed and characterized for up to 500 pF capacitive This function is useful for power-on reset or system failure load driving capability. recovery to a known state. V DD P-CH D/A CONVERTER SECTION Each of the two DACs is a 12-bit device with an output that V OUT swings from GND potential to 0.4 V generated from the internal N-CH bandgap voltage (Figure 22). Each DAC uses a laser-trimmed segmented R-2R ladder that is switched by n-channel MOSFETs. The output voltage of the DAC has a constant AGND resistance independent of digital input code. The DAC output is internally connected to the rail-to-rail output op amp. Figure 23. Equivalent Analog Output Circuit V REF REFERENCE SECTION BANDGAP 1.0V REF The internal curvature-corrected bandgap voltage reference is 2kΩ 12-BIT DAC 0.4V laser trimmed for both initial accuracy and low temperature FS 1.0V 0.4V coefficient. Figure 18 provides a histogram of total output V OUT 10kΩ 2.047V performance of full-scale versus temperature, which is dominated FS 10kΩ by the reference performance. 2.5kΩ V Output REF The internal reference drives two resistor-divider networks. One Figure 22. AD8303 Equivalent Schematic of Analog Section divider provides a 0.4 V reference for the DAC. The second divider is trimmed to 1.0 V and is available at the V pin. The REF AMPLIFIER SECTION V output is useful for ratiometric applications, and also for REF The internal DAC’s output is buffered by a low power generating a “false ground” or bipolar offset. See Figures 30 consumption, precision amplifier. This low power amplifier and Figure 31 for typical applications. Since V has a high REF contains a differential PNP pair input stage that provides low output impedance, it must be buffered if it is required to deliver offset voltage and low noise, as well as the ability to amplify the current to an external load. zero-scale DAC output voltages, The rail-to-rail amplifier is configured with a gain of approximately five in order to set the 2.0475 volt full-scale output (0.5 mV/LSB). An equivalent circuit schematic for the amplifier section is shown in Figure 22. The op amp has a 4 μs typical settling time to 0.1% of full scale. There are slight differences in settling time for negative slewing signals versus positive. Also, negative transition settling time to within the last 6 LSBs of zero volts has an extended settling time. See the oscilloscope photos in the typical performances section of this data sheet. –8– REV. 0 AD8303 POWER SUPPLY Whether or not a separate power supply trace is available, The very low power consumption of the AD8303 is a direct however, generous supply bypassing will reduce supply-line result of a circuit design optimizing the use of a CBCMOS induced errors. Local supply bypassing consisting of a 10 μF process. By using the low power characteristics of CMOS for tantalum electrolytic in parallel with a 0.1 μF ceramic capacitor the logic, and the low noise, tight matching of the complementary is recommended in all applications (Figure 25). bipolar transistors, excellent analog accuracy is achieved. +2.7V TO +5.5V One advantage of the rail-to-rail output amplifiers used in the AD8303 is the wide range of usable supply voltage. The part is 13 7 V 0.1µF 10µF fully specified and tested for operation from +2.7 V to +5.5 V. SDI DD 6 2 CLK If reduced linearity and source current capability near full scale V OUTA 5 CS can be tolerated, operation of the AD8303 is possible down to 8 LDA AD8303 14 +2.7 V. V 10 OUTB LDB 9 RS 11 POWER SUPPLY BYPASSING AND GROUNDING MSB 12 SHDN Precision analog products, such as the AD8303, require a well AGND DGND 1 4 filtered power source. Since the AD8303 operates from a single +3 V to +5 V supply, it seems convenient to simply tap into the TO ANALOG GROUND digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range. In addition, fast logic gates can Figure 25. Recommended Supply Bypassing for the generate glitches hundred of millivolts in amplitude due to AD8303 wiring resistances and inductances. The power supply noise generated thereby means that special care must be taken to INPUT LOGIC LEVELS insure that the inherent precision of the DAC is maintained. All digital inputs are protected with a Zener-type ESD protection Good engineering judgment should be exercised when addressing structure (Figure 26) that allows logic input voltages to exceed the power supply grounding and bypassing of the AD8303. the V supply voltage. This feature can be useful if the user is DD driving one or more of the digital inputs with a 5 V CMOS logic The AD8303 should be powered directly from the system power input voltage level while operating the AD8303 on a +3 V power supply. This arrangement, shown in Figure 24, employs an LC supply. If this mode of interface is used, make sure that the V OL filter and separate power and ground connections to isolate the of the 5 V CMOS meets the V input requirement of the IL analog section from the logic switching transients. Analog and AD8303 operating at 3 V. See Figure 6 for a graph for digital digital ground pins of the AD8303 should be connected logic input threshold versus operating V supply voltage. DD together directly at the IC package. V DD FERRITE BEAD: 2 TURNS, FAIR-RITE LOGIC #2677006301 IN +5V TTL/CMOS GND LOGIC CIRCUITS 100µF 10-22µF 0.1µF ELECT. TANT. CER. +5V Figure 26. Equivalent Digital Input ESD Protection RETURN For power consumption-sensitive applications, it is important to note that the internal power consumption of the AD8303 is +5V strongly dependent on the actual logic input voltage levels POWER SUPPLY present in the SDI, CLK, CS, LDA, LDB, SHDN, RS and MSB pins. Since these inputs are standard CMOS logic structures, they contribute static power dissipation which Figure 24. Use Separate Traces to Reduce Power Supply depends on the actual driving logic V and V voltage levels. Noise OH OL Consequently, using CMOS logic versus TTL will provide minimal dissipation in the static state. REV. 0 –9– AD8303 MSB 12 DAC REGISTER A DAC A V OUTA RESET LOAD SDI D 12-BIT SHIFT REGISTER 12 CLK CLK Q11–Q0 en MSB CS 12 DAC REGISTER B DAC B V OUTB AD8303 RESET LOAD MSB RS LDA LDB SHDN Figure 27. AD8303 Digital Section Functional Block Diagram DIGITAL INTERFACE Separate Load pins (LDA and LDB) are provided to control the The AD8303 has a double-buffered serial data input. The flow of data from the shift register to the DAC registers. After serial-input register is separate from the two DAC registers, the new value is loaded in the serial-input register, it can be which allows preloading of a new data value into the serial asynchronously transferred to either DAC register by strobing register without disturbing the present DAC values. A the appropriate Load pin (LDA or LDB). The Load pins are functional block diagram of the digital section is shown in level sensitive, so they should be returned high before any new Figure 27, while Table I contains the truth table for the control data is loaded into the serial-input register. logic inputs. RESET (RS) AND MSB PINS Three pins control the serial data input. Data at the Serial Data The RS pin forces both of the DAC registers to a known state, Input (SDI) is clocked into the shift register on the rising edge based on the logic level on the MSB pin. If MSB is a logic zero, of CLK. Data is entered in MSB-first format. Twelve clock then forcing RS low will set the DAC latches to all zeros and the pulses are required to load the 12-bit DAC value. If additional DAC output voltage will be zero volts. If MSB is a logic one, then bits are clocked into the shift register, for example when a μC RS will force the DAC latches to one-half scale (800 ) and the H sends two 8-bit bytes, the MSBs are ignored (Figure 28). The DAC outputs will be 1.024 V. The half-scale reset is useful for CS) is low. If only CLK pin is only enabled when Chip Select ( systems where the DAC output is referenced to a “false CS can be one AD8303 is connected to a serial data bus, then ground” (see the Generating Bipolar Outputs with a Single tied (hardwired) to ground. Supply section of this data sheet for more information). BYTE 1 BYTE 2 The reset function is useful for setting the DAC outputs to zero MSB LSB MSB LSB at power-up or after a power supply interruption. Test systems B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 and motor controllers are two of many applications which X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 benefit from powering up to a known state. The reset pulse can D11–D0: 12-BIT DAC VALUE be generated by the microprocessor’s power-on RESET signal, X = DON'T CARE by an output from the microprocessor (Figure 33), or by an THE MSB OF BYTE 1 IS THE FIRST BIT THAT IS LOADED INTO THE DAC external resistor and capacitor (Figure 34). Figure 28. Typical AD8303-Microprocessor Serial Data RS and MSB have level-sensitive thresholds. The RS input Input Format overrides other logic inputs (specifically, LDA and LDB). However, LDA and LDB should be set high before RS goes high. If LDA or LDB are kept low, then the contents of the shift register will be transferred to the DAC register as soon as RS goes high. –10– REV. 0 AD8303 SHUTDOWN (SHDN) GENERATING “BIPOLAR” OUTPUTS WITH A SINGLE The shutdown feature is activated when SHDN is pulled low. SUPPLY While the AD8303 is in shutdown mode, the voltage reference, To maximize output signal swings in single supply operation, DACs, and output amplifiers are all turned off. Supply current many circuit designs employ a “false-ground” configuration. is less than 1 μA. The DAC output voltage goes to 0 V, pulled This method defines a voltage, usually at one half of full scale or to GND by the 12.5 kΩ feedback resistors (Figure 22). at one half of the power supply, as the “ground” reference. Signals are then measured differentially from the false ground, If power (i.e., V ) is maintained to the AD8303 during DD which produces a “quasi-bipolar” output swing. shutdown, the value stored in the DAC input latches will not change. When the SHDN pin is driven high, the DACs will The AD8303’s voltage reference output, combined with an op return to the same voltages as before shutdown. The CMOS amp, can provide a temperature compensated false-ground logic section of the AD8303 remains active while SHDN is low. reference, as shown in Figure 30. The op amp amplifies the Thus, new data can be loaded while the DACs are shut down AD8303’s 1.0 V reference by 1.024 to provide an analog and, when SHDN goes high, the DACs will assume the new common (false ground) at one-half scale (1.024 V). With this output voltage. The AD8303 recovers from shutdown very method, the DAC output is ±1.024 V (referenced to the false quickly. The voltage output settling time after shutdown is ground). The “Quasi-Bipolar” code table is given in Table III. typically only a few microseconds longer than the normal +3V settling time (Figure 20). 13 V +3V TO +5V DD 2 V V = ±1.024V OUTA OUT 13 (REFERENCED TO +3V 0.1µF 10µF AD8303 SIGNAL GROUND) V 7 3 DD SDI V 100Ω REF 6 SIGNAL GROUND CLK OP193 (FALSE GROUND, +1.024V) 5 AGND DGND CS AD8303 8 1 4 LDA 0V ≤ V ≤ 2.0475V OUT 2, 14 10 V V , V LDB OUTA OUTA OUTB 0.022µF 9 RS 2kΩ 500pF 14 11 V MSB OUTB R1 12 R2A SHDN 2.4kΩ 1µF 97.6kΩ AGND DGND R2B* 1 4 2kΩ *ZERO-SCALE TRIM Figure 29. Unipolar Output Operation Figure 30. A False-Ground Generator UNIPOLAR OUTPUT OPERATION Table III. Quasi-Bipolar Code Table This is the basic mode of operation for the AD8303. As shown in Figure 29, the AD8303 has been designed to drive loads as DAC Analog low as 2 kΩ in parallel with 500 pF. The code table for this Hexadecimal Decimal Output Common “Bipolar” operation is shown in Table II. Number Number In Voltage (False-Ground) Analog in DAC Register DAC Register (V) Voltage (V) Voltage (V) Table II. Unipolar Code Table FFF 4095 2.0475 1.024 +1.2035 801 2049 1.0245 1.024 0.0005 Hexadecimal Number Decimal Number Analog Output 800 2048 1.024 1.024 0 in DAC Register in DAC Register Voltage (V) 7FF 2047 1.0235 1.024 –0.0005 000 0 0 1.024 –1.024 FFF 4095 2.0475 801 2049 1.0245 Since the AD8303’s reference voltage output limits are typical, a 800 2048 1.024 trim potentiometer is included so that the “false-ground” output 7FF 2047 1.0235 can be adjusted to exactly 1.024 V. To maintain accuracy, 000 0 0 resistors R1 and R2A must be of the same type (preferably metal film) to insure temperature coefficient matching. The circuit includes compensation to allow for a 1 μF bypass capacitor at the false-ground output. The benefit of a large capacitor is that not only does the false ground present a very low dc resistance to the load, but its ac impedance is low as well. REV. 0 –11– AD8303 BIPOLAR OUTPUT OPERATION important to maintain accuracy. Resistor pairs R1-R2 and Although the AD8303 has been designed for single-supply R3-R4 should be selected to match within 0.01%. In addition, operation, the output can also be configured for bipolar these resistors must be of the same type (preferably metal film) operation. A typical circuit is shown in Figure 31. This circuit to insure temperature coefficient matching. Mismatching uses the AD8303’s internal voltage reference to generate a between R1 and R2 causes offset and gain errors while an R3 to bipolar offset. Since V must source current in this R4 mismatch yields gain errors. REF application, one half of an OP293 dual op amp is used as a buffer. The other op amp then amplifies the DAC output GENERATING A NEGATIVE SUPPLY VOLTAGE voltage to produce a bipolar output swing. The output voltage is Some applications may require a bipolar output configuration, coded in offset binary and is given by: as shown in Figure 31, but only have a single power supply rail available. This is very common in data acquisition systems using  R4   R2 R2 microprocessor-based systems. In these systems, +12 V, +15 V, V = 0.5 mV × Digital Code × × 1 + ±1.0V ×     O and/or +5 V only are available. Single supply rails are, of course,     R3 + R4 R1 R1 common in battery-powered systems. Shown in Figure 32 is a where 0.5 mV represents the pretrimmed value for one LSB of method of generating a negative supply using a single IC and the AD8303, Digital Code is the digital code sent to the DAC, two capacitors. The ADM8660 employs a charge pump and 1.0 V is the AD8303 reference voltage. technique to invert supply voltages as low as 1.5 V. A shutdown feature on the ADM8660 complements the shutdown of the +3V AD8303. Note, however, that the ADM8660 requires about 13 R2 OPTIONAL R1 500 μs to turn on after exiting the shutdown state. 20.48kΩ ZERO TRIM V 10kΩ DD 7 SDI 3 V 6 REF 1/2 +3V CLK 5 OP293 8 +3V 1/2 CS AD8303 8 R3 OP293 V+ –3V LDA 2 10kΩ 5 V = ±2.048V 2 10 OUT CAP+ OSC V OUTA LDB ADM8660 9 10µF 10µF –3V RS 4 R4 7 14 11 CAP– SHUTDOWN V 19.08kΩ OUTB MSB 12 OPTIONAL LV FC GND SHDN FULL-SCALE 61 3 TRIM AGND DGND 4 1 SHDN FROM AD8303 1/6 74HC04 Figure 31. Bipolar Output Operation Figure 32. Generating a Negative Supply Voltage For a ±2.048 V full scale using the circuit values shown, the transfer function becomes: MICROCOMPUTER INTERFACES V = 1 mV × Digital Code ± 2.048 V O The AD8303 serial data input provides an easy interface to a variety of single-chip microcomputers (μCs). Many μCs have a Note that the full-scale span has increased from 2.048 V to built-in serial data capability which can be used for communi- 4.096 V (±2.048 V). Therefore, although each AD8303 LSB cating with the DAC. In cases where no serial port is provided, represents 0.5 mV, each output LSB of the bipolar circuit has or it is being used for some other purpose (such as an RS-232 been scaled to 1 mV. The code table for this circuit is shown in communications interface), the AD8303 can easily be addressed Table IV. in software. Table IV. Bipolar Code Table Twelve data bits are required to load a value into the AD8303. If more than 12 bits are transmitted before the Chip Select Hexadecimal Number Decimal Number Analog Output input goes high, the extra (i.e., the most significant) bits are in DAC Register in DAC Register Voltage (V) ignored. This feature is valuable because most μCs only transmit data in 8-bit increments. Thus, the μC sends 16 bits to the DAC FFF 4095 2.047 instead of 12 bits. The AD8303 will only respond to the last 12 801 2049 0.001 bits clocked into the SDI input, however, so the serial data 800 2048 0 interface is not affected. 7FF 2047 –0.001 000 0 –2.048 As with the false-ground generator circuit, resistor matching is –12– REV. 0 AD8303 AD8303-MC68HC11 INTERFACE The 8051’s serial data transmission is straightforward. When The circuit illustrated in Figure 33 shows a serial interface data is written to the serial buffer register (SBUF, at Special between the AD8303 and the MC68HC11 8-bit micro- Function Register location 99H), the data is automatically processor. The MOSI output drives the AD8303’s serial data converted to serial format and clocked out via Port 3.0 and Port input, SDI, while SCK drives the clock (CLK). The DAC’s CS, 3.1 After 8 bits have been transmitted, the Transmit Interrupt LDA, LDB, MSB and RS inputs are driven by lines PD5 and flag (SCON.1) is set and the next 8 bits can be transmitted. PC0–PC3, respectively. The circuit of Figure 34 demonstrates “hardwiring” many of the AD8303 features which may not have to be changed within a (PD3) MOSI SDI given design. For example, the reset feature is controlled by a (PD4) SCK CLK resistor and capacitor. This produces a power-on reset pulse (PD5) SS CS without requiring a μC I/O pin. The MSB pin can be hardwired AD8303 PC0 LDA to V or ground, depending on whether a reset to 0 V or half DD PC1 LDB MC68HC11 PC2 MSB scale is required. If the AD8303 is the only device on the serial PC3 RS interface, CS can also be tied to ground. Finally, SHDN can be NOTE: ADDITIONAL PINS OMITTED FOR CLARITY tied to V if the shutdown feature will not be used. DD Software for the interface of Figure 34 is shown in Figure 35. Figure 33. AD8303-MC68HC11 Serial Interface This routine sends the 12-bit value placed in registers DAC_VAL0 and DAC_VAL1 to the DAC addressed by the two To load data into the AD8303, the 68HC11’s CPOL and LSBs of DAC_ADDR. CPHA bits are set high. This action configures the μC to transfer data on the rising edge of the serial clock. After CS is The subroutine begins by setting appropriate bits in the Serial set low, two bytes of data are sent to the AD8303 using the Control register to configure the serial port for Mode 0 format shown in Figure 28. Then LDA or LDB are strobed low, operation. The MSBs of the DAC value are obtained from transferring the serial-input register contents to the appropriate memory location DAC_VAL1, adjusted to compensate for the DAC. The RS and MSB inputs allow the DAC to be reset to 8051’s serial data format, and moved to the serial buffer either zero volts or half scale at any time. register. At this point, serial data transmission begins automatically. When all 8 bits have been sent, the Transmit AN 8051 μC INTERFACE Interrupt bit is set, and the subroutine then proceeds to send the A typical interface between the AD8303 and an 8051 μC is LSBs of the DAC value, stored at location DAC_VAL0. Next shown in Figure 34. This interface also uses the μC’s internal the LDA and LDB bits from DAC_ADDR are logically ANDed serial port. The serial port is programmed for Mode 0 with Port1. This action sets the appropriate AD8303 DAC operation, which functions as a simple 8-bit shift register. The select input low and transfers the DAC value from the serial- 8051’s Port 3.0 pin functions as the serial data output, while input register to the DAC register, causing the DAC output Port 3.1 serves as the serial clock. The LDA and LDB pins are voltage to change. Finally the LDA and LDB inputs are driven controlled by the 8051’s Port 1.0 and Port 1.1 lines, respectively. high to await the next DAC update. The 8051 sends data out of its shift register LSB first, while the 7 (P3.0) RxD SDI AD8303 requires data MSB first. The subroutine therefore 6 (P3.1) TxD CLK 8 includes a BYTESWAP subroutine to reformat the data. This P1.0 LDA 10 AD8303 routine transfers the MSB-first byte at location SHIFTREG to P1.1 LDB an LSB-first byte at location SENDBYTE. The routine rotates 80CL51 the MSB of the first byte into the carry with a Rotate Left Carry RS CS MSB SHDN instruction, then rotates the carry into the MSB of the second 10k 9 5 11 12 byte with a Rotate Right Carry instruction. After 8 loops, V DD + SENDBYTE contains the data in the proper format. The 1µF V DD BYTESWAP routine in Listing C is convenient because the DAC data can be calculated in normal LSB form. NOTE: ADDITIONAL PINS OMITTED FOR CLARITY Figure 34. AD8303-80CL51 Serial Interface REV. 0 –13– AD8303 ;AD8303.ASM ; ; This subroutine loads an AD8303 shift register with a 12-bit ; DAC value, and transfers the value to DAC A or DAC B. ; The DAC value is stored at location DAC-VAL1 (MSB) and DAC_VAL0 (LSB) ; The DAC address (A or B) is stored at DAC_ADDR, (b0=0 for A, b1=0 for B) ; ; Primary controls $MOD51 $TITLE(AD8303 Interface, Using the Serial Port in Mode 0) ; ; Variable declarations ; PORT1 DATA 90H ;SFR register for port 1 DAC_VAL0 DATA 40H ;LSBs of 12-bit DAC Value DAC_VAL1 DATA 41H ; MSBs of DAC Value DAC_ADDR DATA 42H ;DAC address, format is: ; 1,1,1,1,1,1,LDB,LDA ; Set bit low to select DAC LOOPCOUNT DATA 43H ;Count loops for byte swap SHIFTREG DATA 44H ;Shift reg. for byte swap SENDBYTE DATA 45H ; Destination reg. for SR ; ORG 100H ;arbitrary starting address DO_8303: CLR SCON.7 ;set serial CLR SCON.6 ; data mode 0 CLR SCON.5 ;Clr SM2 for mode 0 CLR SCON.1 ;Clr the transmit flag MOV SHIFTREG,DAC_VAL1 ;Get Most Significant Byte ACALL SEND_IT ; send to AD8303 MOV SHIFTREG,DAC_VAL0 ;Get Least Significant Byte ACALL SEND_IT ; send it to the AD8303 MOV A,PORT1 ;Get I/O port contents ANL A,DAC_ADDR ;Clr LDA/LDB, other bits unchanged MOV PORT1,A ;Send to I/O port ORL A,#00000011B ;Set LDA and LDB high MOV PORT1,A ;Send to I/O port RET ;Done ; ;Convert the byte to LSB-first format and send it to the AD8303 SEND_IT: MOV LOOPCOUNT,#8 ;Shift 8 bits BYTESWAP: MOV A,SHIFTREG ;Get source byte RLC A ;rotate MSB to carry MOV SHIFTREG,A ;Save new source byte MOV A,SENDBYTE ;get destination byte RRC A ;Move carry into MSB MOV SENDBYTE,A ;Save DJNZ LOOPCOUNT,BYTESWAP ;Done? MOV SBUF,SENDBYTE ;Send the byte SEND_WAIT: JNB SCON.1,SEND_WAIT ;Wait until 8 bits are send CLR SCON.1 ;Clear the serial flag RET ;Done END Figure 35. Software Listing for the AD8303-80CL51 Interface –14– REV. 0 AD8303 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Epoxy DIP (N-14) 0.795 (20.19) 0.725 (18.42) 14 8 0.280 (7.11) 0.240 (6.10) 17 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) 0.060 (1.52) 0.115 (2.93) PIN 1 0.015 (0.38) 0.210 (5.33) MAX 0.150 (3.81) 0.200 (5.05) MIN 0.125 (3.18) 0.015 (0.38) SEATING 0.022 (0.558) 0.100 0.070 (1.77) 0.008 (0.20) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC 14-Lead Narrow Body SOIC (R-14) 0.3444 (8.75) 0.3367 (8.55) 14 8 0.1574 (4.00) 0.2440 (6.20) 1 7 0.1497 (3.80) 0.2284 (5.80) 0.0688 (1.75) PIN 1 0.0196 (0.50) x 45° 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) 0° SEATING 0.0500 (1.27) 0.0099 (0.25) (1.27) 0.0138 (0.35) PLANE BSC 0.0160 (0.41) 0.0075 (0.19) REV. 0 –15– AD8303 –16– REV. 0 PRINTED IN U.S.A. C2098–18–1/96