ANALOG DEVICES AD8300

+3 Volt, Serial Input a Complete 12-Bit DAC AD8300 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete 12-Bit DAC No External Components 12-BIT REF V OUT Single +3 Volt Operation DAC 12 0.5 mV/Bit with 2.0475 V Full Scale V DD CLR DAC 6 ms Output Voltage Settling Time REGISTER LD Low Power: 3.6 mW 12 GND CS EN Compact SO-8 1.5 mm Height Package CLK SERIAL REGISTER APPLICATIONS AD8300 SDI Portable Communications Digitally Controlled Calibration Servo Controls PC Peripherals GENERAL DESCRIPTION A double buffered serial data interface offers high speed, three- The AD8300 is a complete 12-bit, voltage-output digital-to- wire, DSP and microcontroller compatible inputs using data in analog converter designed to operate from a single +3 volt sup- (SDI), clock (CLK) and load strobe (LD) pins. A chip select ply. Built using a CBCMOS process, this monolithic DAC (CS) pin simplifies connection of multiple DAC packages by offers the user low cost, and ease-of-use in single-supply +3 volt enabling the clock input when active low. Additionally, a CLR systems. Operation is guaranteed over the supply voltage range input sets the output to zero scale at power on or upon user of +2.7 V to +5.5 V making this device ideal for battery oper- demand. ated applications. The AD8300 is specified over the extended industrial (–40°C to The 2.0475 V full-scale voltage output is laser trimmed to +85°C) temperature range. AD8300s are available in plastic maintain accuracy over the operating temperature range of the DIP, and low profile 1.5 mm height SO-8 surface mount packages. device. The binary input data format provides an easy-to-use one-half-millivolt-per-bit software programmability. The voltage outputs are capable of sourcing 5 mA. 3.0 1.00 V = +2.7V DD 0.75 DVFS 1 LSB T = –408C, +258C, +1258C A 2.8 DATA = FFF H 0.50 T = +258C A 0.25 2.6 0.00 PROPER OPERATION 2.4 WHEN V SUPPLY DD –0.25 VOLTAGE ABOVE CURVE –0.50 2.2 = –408C = +258C –0.75 = +1258C 2.0 –1.00 0.01 0.1 1.0 10 0 1024 2048 3072 4096 OUTPUT LOAD CURRENT – mA DIGITAL INPUT CODE – Decimal Figure 1. Minimum Supply Voltage vs. Load Figure 2. Linearity Error vs. Digital Code and Temperature REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999 MINIMUM SUPPLY VOLTAGE – Volts INL LINEARITY ERROR – LSB AD8300–SPECIFICATIONS +3 V OPERATION (@ V = +5 V 6 10%, –408C £ T £ +858C, unless otherwise noted) DD A Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N [Note 1] 12 Bits Relative Accuracy INL –2–1/2 +2 LSB 2 Differential Nonlinearity DNL Monotonic –1–1/2 +1 LSB Zero-Scale Error V Data = 000 +1/2 +3 mV ZSE H 3 Full-Scale Voltage V Data = FFF 2.039 2.0475 2.056 Volts FS H Full-Scale Tempco TCV [Notes 3, 4] 16 ppm/°C FS ANALOG OUTPUT Output Current (Source) I Data = 800 , DV = 5 LSB 5 mA OUT H OUT Output Current (Sink) I Data = 800 , DV = 5 LSB 2 mA OUT H OUT Load Regulation L R = 200 W to ¥, Data = 800 1.5 5 LSB REG L H Output Resistance to GND R Data = 000 30WOUT H 4 Capacitive Load C No Oscillation 500 pF L LOGIC INPUTS 0.6 V Logic Input Low Voltage V IL Logic Input High Voltage V 2.1 V IH Input Leakage Current I 10mA IL Input Capacitance C 10 pF IL INTERFACE TIMING 4, 5 SPECIFICATIONS Clock Width High t 40 ns CH Clock Width Low t 40 ns CL Load Pulsewidth t 50 ns LDW Data Setup t 15 ns DS Data Hold t 15 ns DH Clear Pulsewidth t 40 ns CLRW Load Setup t 15 ns LD1 Load Hold t 40 ns LD2 Select t 40 ns CSS Deselect t 40 ns CSH 4 AC CHARACTERISTICS Voltage Output Settling Time t To –0.2% of Full Scale 7ms S 6 To –1 LSB of Final Value 14ms Output Slew Rate SR Data = 000 to FFF to 000 2.0 V/ms H H H DAC Glitch 15 nV/s Digital Feedthrough 15 nV/s SUPPLY CHARACTERISTICS Power Supply Range V DNL < –1 LSB 2.7 5.5 V DD RANGE Positive Supply Current I V = 3 V, V = 0 V, Data = 000 1.2 1.7 mA DD DD IL H V = 3.6 V, V = 2.3 V, Data = FFF 1.9 3.0 mA DD IH H Power Dissipation P V = 3 V, V = 0 V, Data = 000 3.6 5.1 mW DISS DD IL H Power Supply Sensitivity PSSDV = –5% 0.001 0.005 %/% DD NOTES 1 LSB = 0.5 mV for 0 V to +2.0475 V output range. 2 The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. –2– REV. A AD8300 +5 V OPERATION (@ V = +5 V 6 10%, –408C £ T £ +858C, unless otherwise noted) DD A Parameter Symbol Condition Min Typ Max Units STATIC PERFORMANCE Resolution N [Note 1] 12 Bits Relative Accuracy INL –2–1/2 +2 LSB 2 Differential Nonlinearity DNL Monotonic –1–1/2 +1 LSB Zero-Scale Error V Data = 000 +1/2 +3 mV ZSE H 3 Full-Scale Voltage V Data = FFF 2.039 2.0475 2.056 Volts FS H Full-Scale Tempco TCV [Notes 3, 4] 16 ppm/°C FS ANALOG OUTPUT Output Current (Source) I Data = 800 , DV = 5 LSB 5 mA OUT H OUT Output Current (Sink) I Data = 800 , DV = 5 LSB 2 mA OUT H OUT Load Regulation L R = 200W to ¥, Data = 800 1.5 5 LSB REG L H Output Resistance to GND R Data = 000 30WOUT H 4 Capacitive Load C No Oscillation 500 pF L LOGIC INPUTS Logic Input Low Voltage V 0.8 V IL Logic Input High Voltage V 2.4 V IH Input Leakage Current I 10mA IL Input Capacitance C 10 pF IL INTERFACE TIMING 4, 5 SPECIFICATIONS Clock Width High t 30 ns CH Clock Width Low t 30 ns CL Load Pulsewidth t 30 ns LDW Data Setup t 15 ns DS Data Hold t 15 ns DH Clear Pulsewidth t 30 ns CLWR Load Setup t 15 ns LD1 Load Hold t 30 ns LD2 Select t 30 ns CSS Deselect t 30 ns CSH 4 AC CHARACTERISTICS Voltage Output Settling Time t To –0.2% of Full Scale 6ms S 6 To –1 LSB of Final Value 13ms Output Slew Rate SR Data = 000 to FFF to 000 2.2 V/ms H H H DAC Glitch 15 nV/s Digital Feedthrough 15 nV/s SUPPLY CHARACTERISTICS Power Supply Range V DNL < –1 LSB 2.7 5.5 V DD RANGE Positive Supply Current I V = 5 V, V = 0 V, Data = 000 1.2 1.7 mA DD DD IL H V = 5.5 V, V = 2.3 V, Data = FFF 2.8 4.0 mA DD IH H Power Dissipation P V = 5 V, V = 0 V, Data = 000 6 5.1 mW DISS DD IL H Power Supply Sensitivity PSSDV = –10% 0.001 0.006 %/% DD NOTES 1 1 LSB = 0.5 mV for 0 V to +2.0475 V output range. 2 The first two codes (000 , 001 ) are excluded from the linearity error measurement. H H 3 Includes internal voltage reference error. 4 These parameters are guaranteed by design and not subject to production testing. 5 All input control signals are specified with t = t = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. R F 6 The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region. Specifications subject to change without notice. REV. A –3– AD8300 * PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS SO-8 Plastic DIP V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V DD Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V 1 8 1 8 V V DD OUT V to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V + 0.3 V OUT DD CS 2 7 GND AD8300 I Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA OUT 4 5 TOP VIEW CLK 3 6 CLR Package Power Dissipation . . . . . . . . . . . . . (T Max – T )/qJ A JA (Not to Scale) SDI 4 5 LD Thermal Resistance qJA 8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W PIN DESCRIPTIONS 8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W Maximum Junction Temperature (T Max) . . . . . . . . . . 150°C J Pin # Name Function Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C 1V Positive power supply input. Specified range Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C DD of operation +2.7 V to +5.5 V. Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C 2 CS Chip Select, active low input. Disables shift *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the register loading when high. Does not affect device at these or any other conditions above those indicated in the operational LD operation. sections of this specification is not implied. Exposure to absolute maximum rating 3 CLK Clock input, positive edge clocks data into conditions for extended periods may affect device reliability. shift register. 4 SDI Serial Data Input, input data loads directly into the shift register, MSB first. ORDERING GUIDE 5 LD Load DAC register strobes, active low. Transfers shift register data to DAC register. Package Package See Truth Table I for operation. Asynchro- Model INL Temp Description Options nous active low input. AD8300AN–2 XIND 8-Lead P-DIP N-8 6 CLR Resets DAC register to zero condition. AD8300AR–2 XIND 8-Lead SOIC SO-8 Asynchronous active low input. NOTES 7 GND Analog and Digital Ground. XIND = –40°C to +85°C. 8V DAC voltage output, 2.0475 V full scale OUT The AD8300 contains 630 transistors. The die size measures 72 mil · 65 mil. with 0.5 mV per bit. An internal tempera- ture stabilized reference maintains a fixed full-scale voltage independent of time, tem- perature and power supply variations. D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDI CLK t CSS t CSH CS t t LD1 LD2 LD SDI t t DS DH t CL CLK t CH t LDW LD t CLRW CLR t S t S FS V OUT ZS 61LSB ERROR BAND Figure 3. Timing Diagram CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. A Typical Performance Characteristics–AD8300 2.5 80 POSITIVE T = –40 TO +858C A V = +5V DD 60 CURRENT 2.0 LIMIT 40 V = +3V DD 20 1.5 DATA = 800 H 0 R TIED TO +1.024V L 1.0 –20 –40 V = +3V 0.5 DD NEGATIVE –60 CURRENT V = +5V DD LIMIT HORIZONTAL = 1ms/DIV 0 –80 01 23 45 6 02 1 V SUPPLY VOLTAGE – Volts DD OUTPUT VOLTAGE – Volts Figure 5. Logic Input Threshold Figure 6. Detail Settling Time Figure 4. I vs. V OUT OUT Voltage vs. V DD 50 45 V = +5V 610% DD 40 35 30 V = +3V 610% DD 25 20 15 T = +258C A 10 DATA = FFF H 5 HORIZONTAL = 20ms/DIV TIME = 100ms/DIV 0 10 100 1k 10k 100k 1M FREQUENCY – Hz Figure 9. Large Signal Settling Time Figure 8. Power Supply Rejection Figure 7. Broadband Noise vs. Frequency 3.5 3.0 2.5 V = +3V DD 2.0 1.5 V = +5V DD 1.0 T = +258C A 0.5 DATA = FFF H 0.5ms/DIV CODE 800 TO 7FF H H 0 01 2 34 5 LOGIC VOLTAGE – Volts Figure 12. Digital Feedthrough vs. Figure 10. Supply Current vs. Logic Figure 11. Midscale Transition Time Performance Input Voltage REV. A –5– SUPPLY CURRENT – mA BROADBAND NOISE – 200mV/DIV OUTPUT CURRENT – mA POWER SUPPLY REJECTION – dB LOGIC THRESHOLD VOLTAGE AD8300 1.5 3.0 60 V = +5.5V DD TUE = SINL+ZS+FS NO LOAD ss = 300 UNITS ss = 300 UNITS 1.0 50 V = +3V DD NORMALIZED TO +258C 2.6 V = +5.0V DD T = +258C A 0.5 40 2.2 V = +5V DD V = +4.5V DD 0 30 1.8 –0.5 V = +2.7, 3.0, 3.3V DD V = +2.7V 20 DD DATA = FFF H 1.4 V = +2.4V –1.0 IH 10 V = 0V IL –1.5 1.0 0 –60 –20 20 60 100 140 –55 –35 –15 5 25 45 65 85 105 125 –1 014 23 5 6 TEMPERATURE – 8C TEMPERATURE – 8C TOTAL UNADJUSTED ERROR – mV Figure 13. Total Unadjusted Figure 15. Supply Current vs. Figure 14. Zero-Scale Voltage Drift Error Histogram Temperature vs. Temperature 70 1.5 10 NO LOAD V = +3V 60 V = +3V DD DD 1.0 ss = 300 UNITS DATA = FFF DATA FFF H H NORMALIZED TO +258C T = –40 TO +858C 50 A 0.5 1 V = +5.5V DD 40 0 30 –0.5 0.1 20 V = +2.7V DD –1.0 10 –1.5 0 0.01 –50 –40 –30 –20 –1002 10030 40 1 10 100 1k 10k 100k –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE COEFFICIENT – ppm/8C FREQUENCY – Hz TEMPERATURE – 8C Figure 18. Full-Scale Output Figure 17. Output Voltage Noise Figure 16. Full-Scale Voltage Drift Tempco Histogram Density vs. Frequency vs. Temperature 2.4 V = +2.7V DD 2.0 ss = 135 UNITS 1.6 FULL SCALE (DATA = FFF ) H 1.2 0.8 0.4 ZERO SCALE (DATA = 000 ) H 0 0 100 200 300 400 500 600 HOURS OF OPERATION AT +1508C Figure 19. Long Term Drift Accelerated by Burn-In –6– REV. A V DRIFT – mV OUT FREQUENCY V DRIFT – mV NOISE DENSITY – mV/Hz OUT NOMINAL VOLTAGE CHANGE – mV I SUPPLY CURRENT – mA DD FREQUENCY AD8300 Table I. Control Logic Truth Table CS CLK CLR LD Serial Shift Register Function DAC Register Function H X H H No Effect Latched L L H H No Effect Latched L H H H No Effect Latched L›H H Shift-Register-Data Advanced One Bit Latched ›L H H No Effect Latched HX HflNo Effect Updated with Current Shift Register Contents H X H L No Effect Transparent H X L X No Effect Loaded with All Zeros HX›H No Effect Latched All Zeros NOTES 1.› = Positive Logic Transition; fl = Negative Logic Transition; X = Don’t Care. 2. Do not clock in serial data while LD is LOW. 3. Data loads MSB first. OPERATION OUTPUT SECTION The AD8300 is a complete ready to use 12-bit digital-to-analog The rail-to-rail output stage of this amplifier has been designed converter. Only one +3 V power supply is necessary for opera- to provide precision performance while operating near either tion. It contains a 12-bit laser-trimmed digital-to-analog power supply. Figure 21 shows an equivalent output schematic converter, a curvature-corrected bandgap reference, rail-to-rail of the rail-to-rail amplifier with its N-channel pull-down FETs output op amp, serial-input register, and DAC register. The that will pull an output load directly to GND. The output serial data interface consists of a serial-data-input (SDI) clock sourcing current is provided by a P-channel pull-up device that (CLK), and load strobe pins (LD) with an active low CS strobe. can source current to GND terminated loads. In addition an asynchronous CLR pin will set all DAC register V DD bits to zero causing the V to become zero volts. This func- OUT P-CH tion is useful for power on reset or system failure recovery to a known state. V OUT N-CH D/A CONVERTER SECTION The internal DAC is a 12-bit device with an output that swings from GND potential to 0.4 volt generated from the internal band- AGND gap voltage, see Figure 20. It uses a laser-trimmed segmented Figure 21. Equivalent Analog Output Circuit R-2R ladder which is switched by N-channel MOSFETs. The output voltage of the DAC has a constant resistance indepen- The rail-to-rail output stage achieves the minimum operating dent of digital input code. The DAC output is internally con- supply voltage capability shown in Figure 2. The N-channel nected to the rail-to-rail output op amp. output pull-down MOSFET shown in Figure 21 has a 35W on resistance which sets the sink current capability near ground. In AMPLIFIER SECTION addition to resistive load driving capability, the amplifier has The internal DAC’s output is buffered by a low power con- also been carefully designed and characterized for up to 500 pF sumption precision amplifier. This low power amplifier contains capacitive load driving capability. a differential PNP pair input stage that provides low offset volt- age and low noise, as well as the ability to amplify the zero-scale REFERENCE SECTION DAC output voltages. The rail-to-rail amplifier is configured The internal curvature-corrected bandgap voltage reference is with a gain of approximately five in order to set the 2.0475 volt laser trimmed for both initial accuracy and low temperature full-scale output (0.5 mV/LSB). See Figure 20 for an equivalent coefficient. Figure 18 provides a histogram of total output per- circuit schematic of the analog section. formance of full-scale vs. temperature which is dominated by the reference performance. 1.2V BANDGAP REF 0.4V POWER SUPPLY 12-BIT DAC FS V OUT The very low power consumption of the AD8300 is a direct 0.4V 2.047V result of a circuit design optimizing use of a CBCMOS process. FS By using the low power characteristics of the CMOS for the R2 R1 logic, and the low noise, tight matching of the complementary bipolar transistors, good analog accuracy is achieved. Figure 20. Equivalent AD8300 Schematic of Analog Portion For power-consumption sensitive applications it is important to The op amp has a 2ms typical settling time to 0.4% of full scale. note that the internal power consumption of the AD8300 is There are slight differences in settling time for negative slewing strongly dependent on the actual logic input voltage levels signals versus positive. Also negative transition settling time to present on the SDI, CLK, CS, LD, and CLR pins. Since these within the last 6 LSB of zero volts has an extended settling time. inputs are standard CMOS logic structures, they contribute See the oscilloscope photos in the typical performances section static power dissipation dependent on the actual driving logic of this data sheet. REV. A –7– AD8300 Table II. Unipolar Code Table V and V voltage levels. Consequently, for optimum dissipa- OH OL tion use of CMOS logic versus TTL provides minimal dissipa- Hexadecimal Decimal tion in the static state. A V = 0 V on the logic input pins INL Number in Number in Analog Output provides the lowest standby dissipation of 1.2 mA with a +3.3 V DAC Register DAC Register Voltage (V) power supply. FFF 4095 +2.0475 As with any analog system, it is recommended that the AD8300 801 2049 +1.0245 power supply be bypassed on the same PC card that contains 800 2048 +1.0240 the chip. Figure 8 shows the power supply rejection versus fre- 7FF 2047 +1.0235 quency performance. This should be taken into account when 000 0 +0.0000 using higher frequency switched-mode power supplies with ripple frequencies of 100 kHz and higher. One advantage of the rail-to-rail output amplifiers used in the AD8300 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from OUTLINE DIMENSIONS +2.7 V to +5.5 V. If reduced linearity and source current capa- Dimensions shown in inches and (mm). bility near full scale can be tolerated, operation of the AD8300 is possible down to +2.1 volts. The minimum operating supply 8-Lead SOIC (SO-8) voltage versus load current plot in Figure 2 provides information for operation below V = +2.7 V. DD 0.1968 (5.00) 0.1890 (4.80) TIMING AND CONTROL 85 The AD8300 has a separate serial-input register from the 12-bit 0.1574 (4.00) 0.2440 (6.20) 0.1497 (3.80) 0.2284 (5.80) DAC register that allows preloading of a new data value MSB 1 4 first into the serial register without disturbing the present DAC PIN 1 output voltage value. Data can only be loaded when the CS pin 0.0500 (1.27) 0.0196 (0.50) 3 458 is active low. After the new value is fully loaded in the serial- BSC 0.0099 (0.25) 0.0688 (1.75) input register, it can be asynchronously transferred to the DAC 0.0098 (0.25) 0.0532 (1.35) 0.0040 (0.10) register by strobing the LD pin. The DAC register uses a level 88 0.0192 (0.49) 08 0.0500 (1.27) 0.0098 (0.25) SEATING sensitive LD strobe that should be returned high before any new 0.0138 (0.35) 0.0160 (0.41) PLANE 0.0075 (0.19) data is loaded into the serial-input register. At any time the contents of the DAC resister can be reset to zero by strobing the CLR pin which causes the DAC output voltage to go to zero 8-Lead Plastic DIP (N-8) volts. All of the timing requirements are detailed in Figure 3 0.430 (10.92) along with Table I. Control Logic Truth Table. 0.348 (8.84) All digital inputs are protected with a Zener type ESD protection 8 5 0.280 (7.11) structure (Figure 22) that allows logic input voltages to exceed 0.240 (6.10) the V supply voltage. This feature can be useful if the user is DD 14 loading one or more of the digital inputs with a 5 V CMOS logic 0.325 (8.25) PIN 1 0.100 (2.54) 0.300 (7.62) input voltage level while operating the AD8300 on a +3.3 V 0.015 BSC power supply. If this mode of interface is used, make sure that (0.381) 0.210 0.195 (4.95) TYP (5.33) the V of the +5 V CMOS meets the V input requirement of OL IL 0.115 (2.93) MAX 0.130 the AD8300 operating at 3 V. See Figure 5 for the effect on 0.160 (4.06) (3.30) digital logic input threshold versus operating V supply voltage. MIN DD 0.115 (2.93) 0.015 (0.381) 0.022 (0.558) 0.070 (1.77) SEATING 158 0.008 (0.204) V DD PLANE 0.014 (0.356) 0.045 (1.15) 08 LOGIC IN GND Figure 22. Equivalent Digital Input ESD Protection Unipolar Output Operation This is the basic mode of operation for the AD8300. The AD8300 has been designed to drive loads as low as 400W in parallel with 500 pF. The code table for this operation is shown in Table II. APPLICATIONS INFORMATION See DAC8512 data sheet for additional application circuit ideas. –8– REV. A PRINTED IN U.S.A. C1968a–0–5/99