ANALOG DEVICES AD8273

Very Low Distortion, Dual-Channel, High Precision Difference Amplifier AD8273 FEATURES FUNCTIONAL BLOCK DIAGRAM +V S ±4000 V HBM ESD 11 Very low distortion 12kΩ 6kΩ 2 12 0.00025% THD + N (20 kHz) 0.0015% THD + N (100 kHz) 13 Drives 600 Ω loads 12kΩ 6kΩ Two gain settings 3 14 12kΩ 6kΩ Gain of ½ (−6 dB) 6 10 Gain of 2 (+6 dB) 0.05% maximum gain error 9 10 ppm/°C maximum gain drift 12kΩ 6kΩ 58 Excellent ac specifications 4 20 V/μs minimum slew rate –V S 800 ns to 0.01% settling time Figure 1. High accuracy dc performance 77 dB minimum CMRR 700 μV maximum offset voltage 14-lead SOIC package Supply current: 2.5 mA maximum per channel Supply range: ±2.5 V to ±18 V APPLICATIONS ADC drivers High performance audio Instrumentation amplifier building blocks Level translators Automatic test equipment Sine/cosine encoders GENERAL DESCRIPTION The AD8273 is a low distortion, dual-channel amplifier with Table 1. Difference Amplifiers by Category internal gain setting resistors. With no external components, it Low High Single-Supply Single-Supply can be configured as a high performance difference amplifier Distortion Voltage Unidirectional Bidirectional (G = ½ or 2), inverting amplifier (G = ½ or 2), or noninverting AD8270 AD628 AD8202 AD8205 amplifier (G = 1½ or 3). AD8273 AD629 AD8203 AD8206 The AD8273 operates on both single and dual supplies and only AD8274 AD8216 requires 2.5 mA maximum supply current for each amplifier. It AMP03 is specified over the industrial temperature range of −40°C to +85°C and is fully RoHS compliant. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06981-001 AD8273 TABLE OF CONTENTS Features .............................................................................................. 1  Pin Configuration and Function Descriptions..............................5  Applications....................................................................................... 1  Typical Performance Characteristics ..............................................6  Functional Block Diagram .............................................................. 1  Theory of Operation ...................................................................... 12  General Description ......................................................................... 1  Configurations............................................................................ 12  Revision History ............................................................................... 2  Power Supplies............................................................................ 12  Specifications..................................................................................... 3  Outline Dimensions....................................................................... 14  Absolute Maximum Ratings............................................................ 4  Ordering Guide .......................................................................... 14  Maximum Power Dissipation ..................................................... 4  ESD Caution.................................................................................. 4  REVISION HISTORY 8/10—Rev. A to Rev. B Changes to Data Sheet Title ............................................................ 1 Changes to THD + Noise (THD + N) Parameter, Gain Nonlinearity Parameter, and Offset vs. Power Supply Parameter, Table 2 ................................................................................................ 3 Changed −12A Pin to −INA Pin, +12A Pin to +INA Pin, +12B Pin to INB Pin, −12B Pin to −INB Pin, +6B Pin to REFB Pin, −6B Pin to SENSEB Pin, −6A Pin to SENSEA Pin, and +6A Pin to REFA Pin Throughout ................................................................ 5 Changes to Figure 3 and Table 4..................................................... 5 1/09—Rev. 0 to Rev. A Changes to Product Title, Features Section, and Applications Section................................................................................................ 1 Added Human Body Model (HBM) ESD Rating Parameter, Table 3 ................................................................................................ 4 Changes to Figure 6 to Figure 9...................................................... 6 Changes to Figure 10 to Figure 12.................................................. 7 Changes to Figure 18........................................................................ 8 Deleted Figure 31; Renumbered Sequentially ............................ 10 Added Figure 31 to Figure 33; Renumbered Sequentially ........ 10 Added Figure 34 to Figure 36........................................................ 11 1/08—Revision 0: Initial Version Rev. B | Page 2 of 16 AD8273 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = ½, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth 20 MHz Slew Rate 20 V/μs Settling Time to 0.1% 10 V step on output, CL = 100 pF 670 750 ns Settling Time to 0.01% 10 V step on output, CL = 100 pF 750 800 ns Channel Separation f = 1 kHz 130 dB 1 NOISE/DISTORTION THD + Noise (THD + N) f = 1 kHz, VOUT = 10 V p-p, 600 Ω load 0.00025 % 2 Noise Floor, RTO 20 kHz BW −106 dBu Output Voltage Noise (Referred to Output) f = 20 Hz to 20 kHz 3.5 μV rms f = 1 kHz 26 nV/√Hz GAIN Gain Error 0.05 % Gain Drift −40°C to +85°C 2 10 ppm/°C Gain Nonlinearity V = 10 V p-p, 600 Ω load 2 ppm OUT INPUT CHARACTERISTICS 3 Offset Referred to output 100 700 μV vs. Temperature −40°C to +85°C 3 μV/°C vs. Power Supply V = ±2.5 V to ±18 V 2 5 μV/V S Common-Mode Rejection Ratio V = ±40 V, R = 0 Ω, referred to input 77 86 dB CM S 4 Input Voltage Range −3VS + 4.5 +3VS − 4.5 V 5 Impedance Differential VCM = 0 V 36 kΩ 6 Common Mode 9 kΩ OUTPUT CHARACTERISTICS Output Swing −VS + 1.5 +VS − 1.5 V Short-Circuit Current Limit Sourcing 100 mA Sinking 60 mA Capacitive Load Drive G = ½ 200 pF G = 2 1200 pF POWER SUPPLY Supply Current (per Amplifier) 2.5 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 Includes amplifier voltage and current noise, as well as noise of internal resistors. 2 dBu = 20 log (V rms/0.7746). 3 Includes input bias and offset current errors. 4 May also be limited by absolute maximum input voltage or by the output swing. See the Absolute Maximum Ratings section and Figure 9 through Figure 12 for details. 5 Internal resistors are trimmed to be ratio matched but have ±20% absolute accuracy. 6 Common mode is calculated looking into both inputs. Common-mode impedance looking into only one input is 18 kΩ. Rev. B | Page 3 of 16 AD8273 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 3. The maximum safe power dissipation for the AD8273 is limited Parameter Rating by the associated rise in junction temperature (T ) on the die. At J Supply Voltage ±18 V approximately 150°C, which is the glass transition temperature, Output Short-Circuit Current Observe the plastic changes its properties. Even temporarily exceeding derating curve this temperature limit may change the stresses that the package Voltage at Any Input Pin 40 V exerts on the die, permanently shifting the parametric performance Differential Input Voltage 40 V of the amplifiers. Exceeding a temperature of 150°C for an Current into Any Input Pin 3 mA extended period can result in a loss of functionality. Human Body Model (HBM) ESD Rating ±4000 V Storage Temperature Range −65°C to +130°C The AD8273 has built-in, short-circuit protection that limits the Specified Temperature Range −40°C to +85°C output current to approximately 100 mA (see Figure 2 for more Thermal Resistance information). While the short-circuit condition itself does not θ 105°C/W JA damage the part, the heat generated by the condition can cause θ 36°C/W JC the part to exceed its maximum junction temperature, with Package Glass Transition Temperature (T) 150°C G corresponding negative effects on reliability. 2.0 Stresses above those listed under Absolute Maximum Ratings T MAX = 150°C J θ = 105°C/W JA may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any 1.6 other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute 1.2 maximum rating conditions for extended periods may affect device reliability. 0.8 0.4 0 –50 –25 0 25 50 75 100 125 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. B | Page 4 of 16 MAXIMUM POWER DISSIPATION (W) 06981-043 AD8273 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 14 REFA –INA 2 13 OUTA +INA 3 12 SENSEA AD8273 TOP VIEW –V 4 11 +V S S (Not to Scale) +INB 5 10 SENSEB –INB 6 9 OUTB NC 7 8 REFB NC = NO CONNECT Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 7 NC No Connect. 2 −INA The 12 kΩ resistor connects to the negative terminal of Op Amp A. 3 +INA The 12 kΩ resistor connects to the positive terminal of Op Amp A. 4 −V Negative Supply. S 5 +INB The 12 kΩ resistor connects to the positive terminal of Op Amp B. 6 −INB The 12 kΩ resistor connects to the negative terminal of Op Amp B. 8 REFB The 6 kΩ resistor connects to the positive terminal of Op Amp B. 9 OUTB Op Amp B Output. 10 SENSEB The 6 kΩ resistor connects to the negative terminal of Op Amp B. 11 +V Positive Supply. S 12 SENSEA The 6 kΩ resistor connects to the negative terminal of Op Amp A. 13 OUTA Op Amp A Output. 14 REFA The 6 kΩ resistor connects to the positive terminal of Op Amp A. Rev. B | Page 5 of 16 06981-020 30 20 10 0 –10 – 20 –30 AD8273 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15 V, TA = 25°C, G = ½, difference amplifier configuration, unless otherwise noted. 400 N: 1641 100 MEAN: –9.5 SD: 228.4 300 +2.9µV/°C 80 200 100 60 0 40 –100 –1.7µV/°C 20 –200 REPRESENTATIVE SAMPLES 0 –300 –500 –250 0 250 500 –50 –30 –10 10305070 90 110 130 V ±15V (µV/V) TEMPERATURE (°C) OSO Figure 4. Typical Distribution of System Offset Voltage, Figure 7. System Offset vs. Temperature, Normalized at 25°C, G = ½, Referred to Output Referred to Output 150 N: 1649 MEAN: –0.59 120 SD: 37.3 100 100 50 80 0 60 –50 40 –100 20 –150 REPRESENTATIVE SAMPLES 0 –200 –150 –100 –50 0 50 100 150 –45 –30 –15 0 15 30 45 60 75 90 105 120 CMRR ±15V (µV/V) TEMPERATURE (°C) Figure 5. Typical Distribution of CMRR, G = ½, Referred to Input Figure 8. Gain Error vs. Temperature, Normalized at 25°C 20 G = ½ 0V, +25V 15 10 +0.09µV/V/°C V = ±15V S 15 –13.5V, +11.5V +13.5V, +11.5V 10 5 –0.05µV/V/°C 0 –13.5V, –11.5V +13.5V, –11.5V –5 –10 –15 0V, –25V REPRESENTATIVE SAMPLES –20 –15 –10 –5 0 5 10 15 –50 –30 –10 10305070 90 110 130 OUTPUT VOLTAGE (V) TEMPERATURE (°C) Figure 6. CMRR vs. Temperature, Normalized at 25°C Figure 9. Input Common-Mode Voltage vs. Output Voltage, Gain = ½, ±15 V Supplies Rev. B | Page 6 of 16 CMRR (µV/V) HITS HITS 06981-036 06981-029 06981-028 GAIN ERROR (µV/V) SYSTEM OFFSET (μV) INPUT COMMON-MODE VOLTAGE (V) 06981-053 06981-030 06981-031 AD8273 20 140 G = ½ POSITIVE PSRR –3.5V, +15.8V 15 V = ±5V 120 S +3.5V, +8.8V 10 100 NEGATIVE PSRR V = ±2.5V S –1.0V, +6.2V 5 +1.0V, +4.2V 80 0 60 –1.0V, –4.0V –5 +1.0, –6.0V 40 –10 20 –15 –3.5V, –8.7V +3.5V, –15.5V 0 –20 –4 –3 –2 –1 01234 110 100 1k 10k 100k 1M OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 13. Power Supply Rejection vs. Frequency, G = ½, Referred to Output Figure 10. Input Common-Mode Voltage vs. Output Voltage, Gain = ½, ±5 V and ±2.5 V Supplies 25 32 0V, +20.85V G = 2 ±15V SUPPLY 20 28 V = ±15V S 15 24 10 –13.5V, +11.5V +13.5V, +11.5V 20 5 0 16 –5 12 +13.5V, –11.5V –10 –13.5V, –11.5V ±5V SUPPLY 8 –15 4 –20 0V, –20.85V –25 0 –15 –10 –5 0 5 10 15 100 1k 10k 100k 1M 10M OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 11. Input Common-Mode Voltage vs. Output Voltage, Figure 14. Maximum Output Voltage vs. Frequency Gain = 2, ±15 V Supplies 8 10 –3.5V, +6.9V G = 2 V = ±5V S G = 2 +3.5V, +5.2V 6 5 4 V = ±2.5V –1.0V, +2.7V S 0 +1.0V, +2.2V 2 G = ½ –5 0 –1.0V, –2.0V –2 +1.0, –2.6V –10 –4 –15 –3.5V, –5.2V –6 +3.5V, –6.9V –20 –8 –4 –3 –2 –1 01234 100 1k 10k 100k 1M 10M 100M OUTPUT VOLTAGE (V) FREQUENCY(Hz) Figure 12. Input Common-Mode Voltage vs. Output Voltage, Figure 15. Gain vs. Frequency Gain = 2, ±5 V and ±2.5 V Supplies Rev. B | Page 7 of 16 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 06981-045 06981-046 06981-044 POWER SUPPLY REJECTION (dB) GAIN (dB) MAXIMUM OUTPUT VOLTAGE (V p-p) 06981-006 06981-007 06981-021 AD8273 120 +V S –40°C +25°C +V – 3 GAIN = 2 S 100 GAIN = ½ +125°C +V – 6 S +85°C 80 –V + 6 S +125°C +85°C 60 –V + 3 +25°C S –40°C –V S 40 100 1k 10k 100k 1M 0 2040 6080 100 FREQUENCY (Hz) CURRENT (mA) Figure 19. Output Voltage vs. I Figure 16. Common-Mode Rejection vs. Frequency, Referred to Input OUT 120 I SHORT+ C = 100pF LOAD 100 80 60 40 20 0 –20 NO LOAD –40 600Ω 2kΩ I SHORT– –60 –80 –100 –120 –40 –20 0 20 40 60 80 100 120 1µs/DIV TEMPERATURE (°C) Figure 17. Short-Circuit Current vs. Temperature Figure 20. Small Signal Step Response, Gain = 2 +V S +85°C +125°C C = 100pF LOAD +V – 2 S +25°C –40°C +V – 4 S 0 NO LOAD –V + 4 +125°C S 600Ω 2kΩ –V + 2 S –40°C +25°C +85°C –V S 200 1k 10k 1µs/DIV R (Ω) LOAD Figure 18. Output Voltage Swing vs. R , V = ±15 V LOAD S Figure 21. Small Signal Step Response, Gain = ½ Rev. B | Page 8 of 16 OUTPUT VOLTAGE SWING (V) CURRENT (mA) COMMON-MODE REJECTION (dB) 06981-008 06981-022 06981-009 OUTPUT VOLTAGE (V) 50mV/DIV 50mV/DIV 06981-025 06981-024 06981-023 AD8273 100 90 80 2.5V 5V 70 15V 60 18V 50 40 30 20 10 0 0 20406080 100 120 140 160 180 200 1µs/DIV CAPACITANCE (pF) Figure 22. Small Signal Pulse Response with 500 pF Capacitor Load, Gain = 2 Figure 25. Small Signal Overshoot vs. Capacitive Load, G = ½, 600 Ω in Parallel with Capacitive Load 100 90 80 70 2.5V 15V 60 5V 50 18V 40 30 20 10 0 1µs/DIV 0 200 400 600 800 1000 1200 CAPACITANCE (pF) Figure 23. Small Signal Pulse Response for 100 pF Capacitive Load, Figure 26. Small Signal Overshoot vs. Capacitive Load, Gain = ½ G = 2, No Resistive Load 100 100 90 90 2.5V 80 80 5V 70 70 15V 2.5V 15V 60 5V 60 18V 50 50 40 40 18V 30 30 20 20 10 10 0 0 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) CAPACITANCE (pF) Figure 27. Small Signal Overshoot vs. Capacitive Load, Figure 24. Small Signal Overshoot vs. Capacitive Load, G = ½, No Resistive Load G = 2, 600 Ω in Parallel with Capacitive Load Rev. B | Page 9 of 16 OVERSHOOT (%) 50mV/DIV 50mV/DIV 06981-027 06981-026 06981-037 OVERSHOOT (%) OVERSHOOT (%) OVERSHOOT (%) 06981-040 06981-039 06981-038 AD8273 0.1 22kHz FILTER V = 10V p-p OUT R = 600Ω L 0.01 0.001 GAIN = 2 GAIN = ½ 0.0001 10 100 1k 10k 100k 1µs/DIV FREQUENCY (Hz) Figure 28. Large Signal Pulse Response, Gain = ½ Figure 31. THD + N vs. Frequency, Filter = 22 kHz 0.1 V = 10V p-p OUT 0.01 0.001 GAIN = 2 GAIN = ½ 0.0001 10 100 1k 10k 100k 1µs/DIV FREQUENCY (Hz) Figure 29. Large Signal Pulse Response, Gain = 2 Figure 32. THD + N vs. Frequency, Filter = 120 kHz 40 1 GAIN = ½ 35 f = 1kHz 30 0.1 25 +SR R = 2kΩ, 100Ω L 20 0.01 –SR 15 R = 600Ω L 10 0.001 5 0 0.0001 –40 –20 0 20 40 60 80 100 120 0 5 10 15 20 25 OUTPUT AMPLITUDE (dBu) TEMPERATURE (°C) Figure 30. Slew Rate vs. Temperature Figure 33. THD + N vs. Output Amplitude, G = ½ Rev. B | Page 10 of 16 SLEW RATE (V/µS) 2V/DIV 2V/DIV 06981-033 06981-032 06981-010 THDN + N (%) THD + N (%) THD + N (%) 06981-049 06981-048 06981-047 AD8273 10000 1 GAIN = 2 f = 1kHz 0.1 1000 0.01 R = 600Ω L R = 2kΩ L R = 100kΩ L GAIN = 2 100 0.001 GAIN = ½ 10 0.0001 0 5 10 15 20 25 1 10 100 1k 10k 100k OUTPUT AMPLITUDE (dBu) FREQUENCY (Hz) Figure 34. THD + N vs. Output Amplitude, G = 2 Figure 37. Voltage Noise Density vs. Frequency, Referred to Output 0.1 GAIN = ½ V = 10V p-p OUT G = 2 0.01 0.001 G = ½ THIRD HARMONIC ALL LOADS 0.0001 SECOND HARMONIC R = 600Ω L SECOND HARMONIC R = 100kΩ, 2kΩ L 0.00001 10 100 1k 10k 100k 1s/DIV FREQUENCY (Hz) Figure 38. 0.1 Hz to 10 Hz Voltage Noise, RTO Figure 35. Harmonic Distortion Products vs. Frequency, G = ½ 0.1 GAIN = 2 V = 10V p-p OUT 0.01 0.001 THIRD HARMONIC ALL LOADS 0.0001 SECOND HARMONIC R = 600Ω L SECOND HARMONIC R = 100kΩ, 2kΩ L 0.00001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 36. Harmonic Distortion Products vs. Frequency, G = 2 Rev. B | Page 11 of 16 AMPLITUDE (% OF FUNDAMENTAL) AMPLITUDE (% OF FUNDAMENTAL) THD + N (%) 06981-050 06981-052 06981-051 VOLTAGE NOISE DENSITY (nV/√Hz) 1µV/DIV 06981–035 06981-034 AD8273 THEORY OF OPERATION The AD8273 has two channels, each consisting of a high 6kΩ 12kΩ 12 2 –IN1 precision, low distortion op amp and four trimmed resistors. OUT1 Although such a circuit can be built discretely, placing the 13 resistors on the chip offers advantages to board designers that include better dc specifications, better ac specification, and 6kΩ 12kΩ 3 14 +IN1 lower production costs. 6kΩ 12kΩ The resistors on the AD8273 are laser trimmed and tightly 10 6 –IN2 matched. Specifications that depend on the resistor matching, OUT2 9 such as gain drift, common-mode rejection, and gain accuracy, are better than can be achieved with standard discrete resistors. 6kΩ 12kΩ 5 8 +IN2 The positive and negative input terminals of the AD8273 op amp are not pinned out intentionally. Keeping these nodes internal V = 2 (V − V ) OUT IN+ IN− means their capacitance is considerably lower than it would be Figure 40. Difference Amplifier, G = 2 in discrete designs. Lower capacitance at these nodes means better loop stability and improved common-mode rejection vs. 12kΩ 6kΩ 2 12 frequency. IN1 OUT1 The internal resistors of the AD8273 lower production costs. 13 6kΩ 14 One part rather than several is placed on the board, which 3 12kΩ improves both board build time and reliability. CONFIGURATIONS 12kΩ 6kΩ 610 IN2 The AD8273 can be configured in several different ways; see OUT2 Figure 39 to Figure 46. Because these configurations rely on the 9 6kΩ 8 internal, matched resistors, these configurations have excellent 12kΩ gain accuracy and gain drift. 5 POWER SUPPLIES V = −½ V OUT IN Use a stable dc voltage to power the AD8273. Noise on the Figure 41. Inverting Amplifier, G = ½ supply pins can adversely affect performance. Place a bypass capacitor of 0.1 μF between each supply pin and ground, as 6kΩ 12kΩ 12 2 IN1 close to each pin as possible. Also, use a tantalum capacitor of OUT1 10 μF between each supply and ground. It can be farther away 13 12kΩ 3 from the AD8273 and typically can be shared by other precision integrated circuits. 6kΩ 14 The AD8273 is specified at ±15 V, but it can be used with 6kΩ 12kΩ 10 6 unbalanced supplies as well, for example, −VS = 0 V, +VS = 20 V. IN2 The difference between the two supplies must be kept below 36 V. OUT2 9 12kΩ 5 12kΩ 6kΩ 2 12 –IN1 6kΩ 8 OUT1 13 V = −2 V OUT IN 3 12kΩ 6kΩ 14 Figure 42. Inverting Amplifier, G = 2 +IN1 12kΩ 6kΩ 6 10 –IN2 OUT2 9 5 12kΩ 6kΩ 8 +IN2 V = ½ (V − V ) OUT IN+ IN− Figure 39. Difference Amplifier, G = ½ Rev. B | Page 12 of 16 06981-012 06981-013 06981-017 06981-016 AD8273 12kΩ 6kΩ 12kΩ 6kΩ 2 12 212 OUT1 OUT1 13 13 14 6kΩ IN1 3 12kΩ 6kΩ 12kΩ 14 3 IN1 12kΩ 6kΩ 12kΩ 6kΩ 6 10 610 OUT2 OUT2 9 9 6kΩ 8 IN2 12kΩ 6kΩ 12kΩ 5 8 5 IN2 V = ½ V V = 1½ V OUT IN OUT IN Figure 43. Noninverting Amplifier, G = ½ Figure 45. Noninverting Amplifier, G = 1.5 12 6kΩ 12kΩ 2 6kΩ 12kΩ 12 2 OUT1 OUT1 13 13 3 12kΩ IN1 14 6kΩ 12kΩ 3 6kΩ 14 IN1 10 6kΩ 12kΩ 6kΩ 12kΩ 6 10 6 OUT2 OUT2 9 9 12kΩ 5 IN2 8 6kΩ 12kΩ 5 6kΩ 8 IN2 V = 3 V V = 2 V OUT IN OUT IN Figure 44. Noninverting Amplifier, G = 2 Figure 46. Noninverting Amplifier, G = 3 Rev. B | Page 13 of 16 06981-015 06981-019 06981-014 06981-018 AD8273 OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 14 8 4.00 (0.1575) 6.20 (0.2441) 1 3.80 (0.1496) 5.80 (0.2283) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 47. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8273ARZ −40°C to +85°C 14-Lead SOIC_N R-14 AD8273ARZ-R7 −40°C to +85°C 14-Lead SOIC_N, 7" Tape and Reel R-14 AD8273ARZ-RL −40°C to +85°C 14-Lead SOIC_N, 13" Tape and Reel R-14 1 Z = RoHS Compliant Part. Rev. B | Page 14 of 16 060606-A AD8273 NOTES Rev. B | Page 15 of 16 AD8273 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06981-0-8/10(B) Rev. B | Page 16 of 16