ANALOG DEVICES AD8264

Quad, 235 MHz, DC-Coupled VGA and Differential Output Amplifier AD8264 FEATURES FUNCTIONAL BLOCK DIAGRAM COMM VPOS VNEG Low noise Voltage noise: 2.3 nV/√Hz OPP1 VGA1 Current noise: 2 pA/√Hz + IPP1 VOL1 PrA ATTENUATOR 18dB 6dB Wide bandwidth –24dB TO 0dB 6dB IPN1 – VOH1 Small signal: 235 MHz (VGAx); 80 MHz (differential output GNH1 OFS1 amplifier) + CH1 GAIN CONTROL Large signal: 80 MHz (1 V p-p) – OPP2 VGA2 Gain range IPP2 + VOL2 PrA ATTENUATOR 0 to 24 dB (input to VGA output) 18dB 6dB –24dB TO 0dB 6dB IPN2 – 6 to 30 dB (input to differential output) VOH2 Gain scaling: 20 dB/V GNH2 + CH2 GAIN OFS2 CONTROL DC-coupled – OPP3 VGA3 Single-ended input and differential output IPP3 + Supplies: ±2.5 V to ±5 V VOL3 PrA ATTENUATOR 18dB 6dB –24dB TO 0dB 6dB Low power: 140 mW per channel @ ±3.3 V IPN3 – VOH3 GNH3 + CH3 GAIN OFS3 CONTROL – APPLICATIONS OPP4 VGA4 Multichannel data acquisition IPP4 + VOL4 Positron emission tomography ATTENUATOR PrA 18dB 6dB –24dB TO 0dB 6dB IPN4 – Gain trim VOH4 Industrial and medical ultrasound GNH4 + CH4 GAIN OFS4 Radar receivers CONTROL – GNLO VOCM Figure 1. GENERAL DESCRIPTION The gain of each channel is adjusted independently, and all The AD8264 is a 4-channel, linear-in-dB, general-purpose variable gain amplifier (VGA) with a preamplifier (preamp), channels are referenced to a single pin, GNLO. Combined with and a flexible differential output buffer. Intended for a broad a multi-output, digital-to-analog converter (DAC), each section range of applications, dc coupling combined with wide band- of the AD8264 can be used for active calibration or as a trim width makes this amplifier a very good pulse processor. amplifier. Each channel includes a single-ended input preamp/VGA The gain range of the VGA section is 24 dB. Operation from section to preserve the wide bandwidth and fast slew rate for low- a dual polarity power supply enables amplification of negative distortion pulse applications. A 6 dB differential output buffer voltage pulses that are generated by current-sinking pulses into with common-mode and offset adjustments enable direct coupling a grounded load, such as is typical of photodiodes or photo- to most modern high speed analog-to-digital converters (ADCs), multiplier tubes (PMT). Delay-free processing of wide-band using the converter reference output for perfect dc matching levels. video signals is also possible. The differential output amplifier permits convenient level shifting and interfacing to single- The −3 dB bandwidth of the preamp/VGA is dc to 235 MHz, supply ADCs using the VOCM and OFSx pins. and the bandwidth of the differential driver is 80 MHz. The floating gain control interface provides a precise linear-in-dB scale The AD8264 is available in a 40-lead, 6 mm × 6 mm LFCSP of 20 dB/V and is easy to interface to a variety of external circuits. with an operating temperature range of −40°C to +105°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. 07736-001 AD8264 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 28 Applications ....................................................................................... 1 Overview ..................................................................................... 28 Functional Block Diagram .............................................................. 1 Preamp ......................................................................................... 28 General Description ......................................................................... 1 VGA ............................................................................................. 28 Revision History ............................................................................... 2 Post Amplifier ............................................................................. 29 Specifications ..................................................................................... 3 Noise ............................................................................................ 29 Absolute Maximum Ratings ............................................................ 6 Applications Information .............................................................. 30 Thermal Resistance ...................................................................... 6 A Low Channel Count Application Concept Using a Discrete Reference ..................................................................................... 30 Maximum Power Dissipation ..................................................... 6 A DC Connected Concept Example ........................................ 31 ESD Caution .................................................................................. 6 Evaluation Board ............................................................................ 34 Pin Configuration and Function Descriptions ............................. 7 Connecting and Using the AD8264-EVALZ .......................... 34 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 37 Test Circuits ..................................................................................... 20 Ordering Guide .......................................................................... 37 REVISION HISTORY 1/11—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Connecting and Using the AD8264-EVALZ Section and Figure 117 ................................................................................. 34 Changes to Figure 118 .................................................................... 35 5/09—Revision 0: Initial Version Rev. A | Page 2 of 40 AD8264 SPECIFICATIONS V = ±2.5 V, T = 25°C, f = 10 MHz, C = 5 pF, R = 500 Ω per output (VGAx, VOHx, VOLx), V = (V − V ) = 0 V, S A L L GAIN GNHx GNLO V = GND, V = GND, gain range = 6 dB to 30 dB, unless otherwise specified. VOCM OFSx Table 1. Parameter Conditions Min Typ Max Unit GENERAL PERFORMANCE –3 dB Small Signal Bandwidth (VGAx) V = 10 mV p-p 235 MHz OUT –3 dB Large Signal Bandwidth (VGAx) V = 1 V p-p 150 MHz OUT 1 –3 dB Small Signal Bandwidth (Differential Output) V = 100 mV p-p 80 MHz OUT 1 –3 dB Large Signal Bandwidth (Differential Output) V = 2 V p-p 80 MHz OUT Slew Rate VGAx, V = 2 V p-p 380 V/µs OUT VGAx, V = 1 V p-p 290 V/µs OUT Differential output, V = 2 V p-p 470 V/µs OUT Differential output, V = 1 V p-p 220 V/µs OUT Input Bias Current Pins IPPx −8 −5 −3 µA Input Resistance Pins IPPx at dc; ΔV /ΔI 4.2 MΩ IN BIAS Input Capacitance Pins IPPx 2 pF Input Impedance Pins IPPx at 10 MHz 7.9 kΩ Input Voltage Noise 2.3 nV/√Hz Input Current Noise 2 pA/√Hz Noise Figure (Differential Output) V = 0.7 V, R = 50 Ω, unterminated 9 dB GAIN S Output-Referred Noise (Differential Output) V = 0.7 V (Gain = 30 dB) 72 nV/√Hz GAIN V = −0.7 V (Gain = 6 dB) 45 nV/√Hz GAIN Output Impedance VGAx, dc to 10 MHz 3.5 Ω Differential output, dc to 10 MHz <1 Ω Output Signal Range Preamp |V | − 1.3 V S VGAx, R ≥ 500 Ω |V | − 1.3 V L S Differential amplifier, R ≥ 500 Ω per side |V | − 0.5 V L S Output Offset Voltage Preamp offset −6 |<1| +6 mV VGAx offset, V = 0.7 V −18 |<5| +18 mV GAIN Differential output offset, V = 0.7 V −38 |<10| +38 mV GAIN DYNAMIC PERFORMANCE Harmonic Distortion VGAx = 1 V p-p, differential output = 2 V p-p (measured at VGAx) HD2 f = 1 MHz −73 dBc HD3 −68 dBc HD2 f = 10 MHz −71 dBc HD3 −61 dBc HD2 f = 35 MHz −60 dBc HD3 −53 dBc VGAx = 1 V p-p, differential output = 2 V p-p (measured at differential output) HD2 f = 1 MHz −78 dBc HD3 −66 dBc HD2 f = 10 MHz −71 dBc HD3 −43 dBc HD2 f = 35 MHz −56 dBc HD3 −20 dBc 2 Input 1 dB Compression Point V = −0.7 V, f = 10 MHz 7 dBm GAIN V = +0.7 V, f = 10 MHz −9.6 dBm GAIN Rev. A | Page 3 of 40 AD8264 Parameter Conditions Min Typ Max Unit Two-Tone Intermodulation Distortion (IMD3) VGAx = 1 V p-p, f = 10 MHz, f = 11 MHz −68 dBc 1 2 VGAx = 1 V p-p, f = 35 MHz, f = 36 MHz −51 dBc 1 2 V = 2 V p-p, f = 10 MHz, f = 11 MHz −49 dBc OUT 1 2 V = 2 V p-p, f = 35 MHz, f = 36 MHz −34 dBc OUT 1 2 Output Third-Order Intercept VGAx = 1 V p-p, f = 10 MHz 32 dBm 19 dBV RMS VGAx = 1 V p-p, f = 35 MHz 23 dBm 10 dBV RMS V = 2 V p-p, f = 10 MHz 30 dBm OUT 17 dBV RMS V = 2 V p-p, f = 35 MHz 21 dBm OUT 8 dBV RMS Overload Recovery V = 0.7 V, V stepped from 25 GAIN IN 0.1 V p-p to 1 V p-p ns Group Delay Variation 1 MHz < f < 100 MHz, full gain range ±1 ns ACCURACY 3 Absolute Gain Error −0.7 V < V < −0.6 V 0 0.2 to 2 3 dB GAIN −0.6 V < V < −0.5 V −1.25 ±0.35 +1.25 dB GAIN −0.5 V < V < +0.5 V −1 ±0.25 +1 dB GAIN 0.5 V < V < 0.6 V −1.25 ±0.35 +1.25 dB GAIN 0.6 V < V < 0.7 V −3 −0.2 to −2 0 dB GAIN 4 Gain Law Conformance ±0.2 −0.5 V < V < +0.5 V, ±2.5 V ≤ V ≤ ±5 V dB GAIN S −0.5 V < V < +0.5 V, −40°C ≤ T ≤ +105°C ±0.3 dB GAIN A Channel-to-Channel Matching Single IC, −0.5 V < V < +0.5 V, −0.5 ±0.1 to ±0.25 +0.5 GAIN −40°C ≤ T ≤ +105°C dB A Multiple ICs, −0.5 V < V < +0.5 V, ±0.25 GAIN −40°C ≤ T ≤ +105°C dB A GAIN CONTROL INTERFACE Gain Scaling Factor −0.5 V < V < +0.5 V 19.5 20.0 20.5 dB/V GAIN Over Temperature −40°C ≤ T ≤ +105°C 20 ± 0.5 dB/V A Gain Range 24 dB Gain Intercept to VGAx 11.5 11.9 12.2 dB Over Temperature −40°C ≤ T ≤ +105°C 11.9 ± 0.4 dB A Gain Intercept to Differential Output 17.5 17.9 18.2 dB Over Temperature −40°C ≤ T ≤ +105°C 17.9 ± 0.4 dB A GNHx Input Voltage Range GNLO = 0 V, no gain foldover −V +V V S S Input Resistance ΔV /ΔI , −0.7 V < V < +0.7 V 70 MΩ IN BIAS GAIN GNHx Input Bias Current −0.7 V < V < 0.7 V −0.9 −0.4 0 µA GAIN Over Temperature −0.7 V < V < 0.7 V, −40°C ≤ T ≤ +105°C −0.4 ± +0.2 µA GAIN A GNLO Input Bias Current −0.7 V < V < 0.7 V −1.2 µA GAIN Over Temperature −0.7 V < V < 0.7 V, −40°C ≤ T ≤ +105°C −1.2 ± +0.4 µA GAIN A Response Time 24 dB gain change 200 ns OUTPUT BUFFER VOCM Input Bias Current 0.3 1.5 2.5 nA Over Temperature −40°C ≤ T ≤ +105°C 1.5 ± 0.3 nA A VOCM Input Voltage Range OFSx = 0 V, VGAx = 0 V −1.4 +1.4 V Gain (VGAx to Differential Output) 5.75 6 6.25 dB Over Temperature −40°C ≤ T ≤ +105°C 6 ± 0.5 dB A Rev. A | Page 4 of 40 AD8264 Parameter Conditions Min Typ Max Unit POWER SUPPLY Supply Voltage ±2.5 ±5 V Power Consumption Quiescent Current V = ± 2.5 V 65 79 88 mA S V = ± 2.5 V, −40°C ≤ T ≤ +105°C 79 ± 25 mA S A V = ± 3.3 V 70 85 95 mA S V = ± 3.3 V, −40°C ≤ T ≤ +105°C 85 ± 30 mA S A V = ± 5 V 81 99 110 mA S 5 V = ± 5 V, −40°C ≤ T ≤ +85°C 99 ± 30 mA S A Power Dissipation V = ± 2.5 V 395 mW S V = ±3.3 V 560 mW S V = ±5 V 990 mW S PSRR From VPOS to differential output, V = 0.7 V −15 dB GAIN From VNEG to differential output, V = 0.7 V −15 dB GAIN 1 Differential Output = (VOHx − VOLx). 2 All dBm values are calculated with 50 Ω reference, unless otherwise noted. 3 Conformance to theoretical gain expression (see Equation 1 in the Theory of Operation section). 4 Conformance to best-fit dB linear curve. 5 For supplies greater than ±3.3 V, the operating temperature range is limited to −40°C ≤ T ≤ +85°C. A Rev. A | Page 5 of 40 AD8264 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. θ is specified for the worst-case conditions, that is, a device JA Parameter Rating soldered in a circuit board for surface-mount packages. The θ JA Voltage values in Table 3 assume a 4-layer JEDEC standard board with Supply Voltage (VPOS, VNEG) ±6 V zero airflow. Input Voltage (INPx) VPOS, VNEG Gain Voltage (GNHx, GNLO) VPOS, VNEG Table 3. Thermal Resistance Power Dissipation 2.5 W Package Type θ θ Unit JA JC Temperature 1 40-Lead LFCSP 31.0 2.3 °C/W Operating Temperature Range −40°C to +105°C 1 4-Layer JEDEC board (2S2P). Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C MAXIMUM POWER DISSIPATION Package Glass Transition Temperature (T ) 150°C G The maximum safe power dissipation for the AD8264 is limited Stresses above those listed under Absolute Maximum Ratings by the associated rise in junction temperature (T ) on the die. At J may cause permanent damage to the device. This is a stress approximately 150°C, which is the glass transition temperature, rating only; functional operation of the device at these or any the properties of the plastic change. Even temporarily exceeding other conditions above those indicated in the operational this temperature limit may change the stresses that the package section of this specification is not implied. Exposure to absolute exerts on the die, permanently shifting the parametric performance maximum rating conditions for extended periods may affect of the amplifiers. Exceeding a temperature of 150°C for an device reliability. extended period can cause changes in silicon devices, potentially resulting in a loss of functionality. ESD CAUTION Rev. A | Page 6 of 40 AD8264 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 40 39 38 37 36 35 34 33 32 31 IPN1 30 VOL1 1 OPP1 PIN1 29 VOH1 2 INDICATOR OPP2 3 28 VOH2 IPN2 4 27 VOL2 AD8264 IPP2 5 26 VGA2 TOP VIEW IPP3 6 25 VGA3 (Not to Scale) IPN3 7 24 VOL3 OPP3 8 VOH3 23 9 OPP4 VOH4 22 10 IPN4 21 VOL4 11 12 13 14 15 16 17 18 19 20 NOTES 1. EXPOSED PADDLE (PIN 0) NEEDS AN ELECTRICAL CONNECTION TO GROUND. FOR PROPER RF GROUNDING AND INCREASED RELIABILITY, THE PAD MUST BE CONNECTED TO THE GROUND PLANE. Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 0 (EP), 12, 39 COMM Ground. Exposed paddle (EP, Pin 0) needs an electrical connection to ground. For proper RF grounding and increased reliability, the pad must be connected to the ground plane. 1, 4, 7, 10 IPN1, IPN2, Negative Preamp Inputs for Channel 1 Through Channel 4. Normally, no external connection is needed. IPN3, IPN4 2, 3, 8, 9 OPP1, OPP2, Preamp Output for Channel 1 Through Channel 4. This pin is internally connected to the attenuator OPP3, OPP4 (VGA) input, and normally, no external connection is needed. 5, 6, 11, 40 IPP1, IPP2, Positive Preamp Input for Channel 1 Through Channel 4. High impedance. IPP3, IPP4 13, 14, 37, 38 GNH1, GNH2, Positive Gain Control Voltage Input for Channel 1 Through Channel 4. This pin is referenced to GNLO (Pin 36). GNH3, GNH4 15 VOCM This pin sets the differential output amplifier (VOHx and VOLx) common-mode voltage. 16, 35 VPOS Positive Supply (Internally Tied Together). 17, 34 VNEG Negative Supply (Internally Tied Together). 18, 19, 32, 33 OFS1, OFS2, Voltage sets the differential output offset for Channel 1 through Channel 4. This is the noninverting input OFS3, OFS4 to the differential amplifier, and it has the same bandwidth as the inverting input (VGAx). 20, 25, 26, 31 VGA4, VGA3 VGA Output for Channel 1 Through Channel 4. VGA2, VGA1 21, 24, 27, 30 VOL1, VOL2 Negative Differential Amplifier Output for Channel 1 Through Channel 4. VOL3, VOL4 22, 23, 28, 29 VOH1, VOH2, Positive Differential Amplifier Output for Channel 1 Through Channel 4. VOH3, VOH4 36 GNLO Negative Gain Control Input (Reference for GNHx Pins). Rev. A | Page 7 of 40 IPP4 IPP1 COMM COMM GNH4 GNH1 GNH3 GNH2 GNLO VOCM VPOS VPOS VNEG VNEG OFS4 OFS1 OFS3 OFS2 VGA1 VGA4 07736-003 AD8264 TYPICAL PERFORMANCE CHARACTERISTICS V = ±2.5 V, T = 25°C, f = 10 MHz, C = 5 pF, R = 500 Ω per output (VGAx, VOHx, VOLx), V = (V − V ) = 0 V, S A L L GAIN GNHx GNLO V = GND, V = GND, gain range = 6 dB to 30 dB, unless otherwise specified. VOCM OFSx 36 140 –40°C V = 0V MEAN: –0.1dB GAIN –40°C SD: 0.05dB +25°C 120 30 +25°C +85°C +85°C DIFFERENTIAL 100 24 +105°C OUTPUT +105°C 18 80 VGA 60 12 6 40 20 0 –6 0 –0.6 –0.4 –0.2 0 0.2 0.4 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 V (V) GAIN ERROR (dB) GAIN Figure 3. Gain vs. V vs. Temperature Figure 6. VGA Absolute Gain Error Histogram GAIN 2.0 MEAN: 20.1dB T = +105°C A SD: 0.09dB T = +25°C 180 A 1.5 T = –40°C A MAX 1.0 150 MIN 0.5 120 0 90 –0.5 60 –1.0 30 –1.5 0 –2.0 19.0 19.5 20.0 20.5 21.0 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 GAIN SCALING (dB/V) V (V) GAIN Figure 4. Gain Error vs. V vs. Temperature Figure 7. Gain Scale Factor Histogram (−0.4 V < V < +0.4 V) GAIN GAIN 2 MEAN: 11.9dB 1MHz SD: 0.08dB 10MHz 70MHz 1 80 100MHz 150MHz 0 60 –1 40 –2 20 –3 0 –4 11.7 11.8 11.9 12.0 12.1 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 GAIN INTERCEPT (dB) V (V) GAIN Figure 5. Gain Error vs. V at Various Frequencies to VGAx Figure 8. VGA Gain Intercept Histogram GAIN Rev. A | Page 8 of 40 GAIN ERROR (dB) GAIN ERROR (dB) GAIN (dB) 07736-004 07736-006 07736-005 HITS HITS HITS 07736-009 07736-008 07736-007 AD8264 700 30 CH 1 TO CH 2 V = 0.1V p-p V = 0V OUT GAIN CH 1 TO CH 3 CH 1 TO CH 4 600 20 500 10 400 0 300 –10 200 –20 100 –30 C = 0pF L C = 10pF L C = 22pF L 0 –40 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 100k 1M 10M 100M 500M GAIN ERROR MATCHING (dB) FREQUENCY (Hz) Figure 9. Channel-to-Channel Gain Match Histogram Figure 12. Frequency Response to Differential Output for Various Capacitive Loads 30 30 P = –28dBm IN V = 0.1V p-p OUT 24 20 18 10 12 0 6 –10 0 V = +0.7V GAIN V = +0.5V –20 GAIN –6 V = +0.2V GAIN V = 0V GAIN V = –0.2V GAIN –30 –12 C = 0pF L V = –0.5V GAIN C = 10pF L V = –0.7V GAIN C = 22pF L –18 –40 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 10. Frequency Response vs. Gain to VGAx for Figure 13. Frequency Response to Differential Output for Various Values of V Various Capacitive Loads with Series R = 10 Ω GAIN 40 20 P = –44dBm V = 0.1V p-p IN OUT 30 10 20 10 0 0 –10 –10 V = +0.7V GAIN –20 V = +0.5V GAIN V = +0.2V GAIN –20 V = 0V GAIN C = 0pF L –30 V = –0.2V GAIN C = 10pF L V = –0.5V GAIN C = 22pF L V = –0.7V GAIN C = 47pF L –40 –30 100k 1M 10M 100M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Frequency Response vs. Gain to Differential Output for Figure 14. Small Signal Frequency Response to VGAx for Various Values of V Various Capacitive Loads GAIN Rev. A | Page 9 of 40 HITS GAIN (dB) GAIN (dB) 07736-011 07736-010 07736-028 GAIN (dB) GAIN (dB) GAIN (dB) 07736-013 07736-014 07736-012 AD8264 20 30 V = 0.1V p-p P = –10dBm OUT IN V = +0.7V GAIN 24 10 18 V = 0V GAIN 12 0 6 V = –0.7V GAIN –10 0 –6 –20 C = 47pF L V = ±5V S C = 22pF –12 L V = ±3.3V S C = 9pF L V = ±2.5V C = 0pF S L –30 –18 100k 1M 10M 100M 500M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. Large Signal Frequency Response to VGAx for Figure 18. Small Signal Frequency Response vs. Gain to VGAx for Various Capacitive Loads Various Supply Voltages 20 40 P = –28dBm V = 0.1V p-p IN OUT V = +0.7V GAIN 30 10 V = 0V GAIN 20 10 V = –0.7V GAIN 0 0 –10 –10 –20 –20 C = 47pF L V = ±5V C = 22pF S L –30 C = 10pF V = ±3.3V S L C = 0pF V = ±2.5V S L –30 –40 100k 1M 10M 100M 500M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. Small Signal Frequency Response to VGAx for Figure 19. Small Signal Frequency Response vs. Gain to Differential Output Various Capacitive Loads with Series R = 10 Ω for Various Supply Voltages 20 36 P = –8dBm V = 0.1V p-p IN OUT DIFFERENTIAL V = 0.7V GAIN OUTPUT 30 10 VGA 24 0 18 12 –10 6 V = ±5V S –20 V = ±3.3V S C = 47pF V = ±2.5V L S 0 C = 22pF V = ±5V L S C = 10pF V = ±3.3V L S C = 0pF V = ±2.5V L S –30 –6 100k 1M 10M 100M 500M 100k 1M 10M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) Figure 17. Large Signal Frequency Response to VGAx for Figure 20. Large Signal Frequency Response to VGAx and Various Capacitive Loads with Series R = 10 Ω Differential Output for Various Supply Voltages Rev. A | Page 10 of 40 GAIN (dB) GAIN (dB) GAIN (dB) 07736-017 07736-016 07736-015 GAIN (dB) GAIN (dB) GAIN (dB) 07736-020 07736-018 07736-019 AD8264 5 1 P = –16dBm IN 4 0 3 V = 0V GAIN –1 V = –0.7V GAIN 2 V = +0.7V GAIN –2 V = ±2.5V, VOHx S V = ±3.3V, VOHx S 1 V = ±5V, VOHx S V = ±2.5V, VOLx S V = ±3.3V, VOLx S V = ±5V, VOLx S –3 0 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. Frequency Response from VOCM to VOHx and VOLx for Figure 24. Group Delay vs. Frequency to VGAx Various Supplies 8 9 V = 0.1V p-p OUT 7 3 V = –0.7V GAIN 6 –3 V = +0.7V 5 GAIN V = 0V GAIN –9 4 –15 3 V = ±5V S V = ±3.3V S V = ±2.5V S 2 –21 1M 10M 100M 100k 1M 10M 100M 500M FREQUENCY (Hz) Figure 22. Frequency Response from OFSx to Differential Output for Figure 25. Group Delay vs. Frequency to Differential Output Various Supply Voltages 12 15 P = –22dBm T = +105°C IN A T = +25°C A T = –40°C A 10 MAX 6 MIN 5 0 0 –6 –5 V = ±2.5V S V = ±3.3V S V = ±5V S –10 –12 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 100k 1M 10M 100M 1G FREQUENCY (Hz) V (V) GAIN Figure 23. Preamp Frequency Response to OPPx Figure 26. Differential Output Offset Voltage vs. V vs. Temperature GAIN Rev. A | Page 11 of 40 FREQUENCY (Hz) GAIN (dB) GAIN (dB) GAIN (dB) 07736-022 07736-023 07736-021 OFFSET VOLTAGE RTO (mV) DELAY (ns) DELAY (ns) 07736-026 07736-025 07736-024 AD8264 10 100 T = +105°C A T = +25°C A T = –40°C A MAX 5 MIN V = ±2.5V S 10 0 V = ±5V S 1 –5 –10 0.1 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.1 1 10 100 FREQUENCY (MHz) Figure 27. VGAx Output Offset Voltage vs. V vs. Temperature Figure 30. Output Resistance (VOHx, VOLx) vs. Frequency GAIN 3000 10 V = –0.4V GAIN V = 0V GAIN V = +0.4V GAIN 2500 2000 V = ±5V S 1500 V = ±2.5V S 1000 500 0 1 –30 –20 –10 0 10 20 30 0.1 1 10 100 OUTPUT OFFSET VOLTAGE (mV) FREQUENCY (MHz) Figure 28. Output Offset Histogram to VGAx Figure 31. Output Resistance (VGAx) vs. Frequency 800 100 V = –0.4V GAIN V = 0V GAIN 700 V = +0.4V GAIN 80 600 500 60 400 DIFFERENTIAL OUTPUT 40 300 200 20 100 VGAx 0 0 –30 –20 –10 0 10 20 30 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 OUTPUT OFFSET VOLTAGE (mV) V (V) GAIN Figure 29. Output Offset Histogram to Differential Output Figure 32. Output Referred Noise to VGAx and Differential Output vs. V GAIN Rev. A | Page 12 of 40 V (V) GAIN HITS HITS OFFSET VOLTAGE RTO (mV) 07736-095 07736-029 07736-027 OUTPUT RESISTANCE (Ω) OUTPUT RESISTANCE (Ω) OUTPUT NOISE (nV/√Hz) 07736-032 07736-031 07736-030 AD8264 100 35 30 DIFFERENTIAL OUTPUT (TERMINATED) 25 VGAx (TERMINATED) DIFFERENTIAL OUTPUT 10 20 VGAx (UNTERMINATED) 15 VGAx DIFFERENTIAL OUTPUT (UNTERMINATED) 10 1 5 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 V (V) V (V) GAIN GAIN Figure 33. Input Referred Noise from VGAx and Differential Output vs. V GAIN Figure 36. Noise Figure vs. V GAIN 100 –10 –20 –30 10 –40 –50 DIFFERENTIAL OUTPUT –60 VGAx 1 –70 1 100 1k 10k 100k 1M 10M 100M 0.1 1 10 100 FREQUENCY (Hz) FREQUENCY (MHz) Figure 34. Input Referred Noise vs. Frequency at Maximum Gain Figure 37. VOCM Common-Mode Rejection Ratio vs. Frequency 100 −30 HD2, V = ±2.5V S HD3, V = ±2.5V S HD2, V = ±5V S −40 HD3, V = ±5V S −50 10 −60 −70 DIFFERENTIAL OUTPUT −80 VGAx 1 −90 1 10 100 1k 10k 0 400 800 1200 1600 2000 R (Ω) R (Ω) SOURCE LOAD Figure 35. Input Referred Noise vs. R Figure 38. Harmonic Distortion to VGAx vs. R and Various Supplies SOURCE LOAD Rev. A | Page 13 of 40 INPUT REFERRED NOISE (nV/√Hz) INPUT REFERRED NOISE (nV/√Hz) INPUT REFERRED NOISE (nV/√Hz) 07736-035 07736-033 07736-034 HD (dBc) CMRR (dB) NOISE FIGURE (dB) 07736-037 07736-036 07736-038 AD8264 −30 –30 HD2, V = ±2.5V S HD3, V = ±2.5V S HD2, V = ±5V S −40 –40 HD3, V = ±5V S −50 –50 −60 –60 −70 –70 −80 –80 1MHz 10MHz 35MHz 100MHz −90 –90 0 10 20 30 40 50 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 C (pF) V (V) LOAD GAIN Figure 39. Harmonic Distortion to VGAx vs. C Figure 42. HD2 vs. V vs. Frequency to VGAx LOAD GAIN −30 −20 HD2, V = ±2.5V S HD3, V = ±2.5V S HD2, V = ±5V S −30 −40 HD3, V = ±5V S −40 −50 −50 −60 −60 −70 −70 −80 1MHz −80 10MHz 35MHz 100MHz −90 −90 0 400 800 1200 1600 2000 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 R (Ω) V (V) LOAD GAIN Figure 40. Harmonic Distortion to Differential Output vs. Figure 43. HD3 vs. V vs. Frequency to VGAx GAIN R and Various Supplies LOAD −30 −30 VGAx = 0.5Vp-p HD2, V = ±2.5V S VGAx = 1Vp-p HD3, V = ±2.5V S VGAx = 2Vp-p −40 −40 −50 −50 INPUT LIMITED −60 −60 −70 −70 −80 −80 −90 −90 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0 10 20 30 40 50 V (V) C (pF) GAIN LOAD Figure 44. HD2 vs. Amplitude to VGAx Figure 41. Harmonic Distortion to Differential Output vs. C LOAD Rev. A | Page 14 of 40 HD (dBc) HD (dBc) HD (dBc) 07736-041 07736-039 07736-040 HD2 (dBc) HD3 (dBc) HD2 (dBc) 07736-044 07736-043 07736-042 AD8264 −30 −30 VGAx = 0.5V p-p V = 0.5V p-p OUT VGAx = 1V p-p V = 1V p-p OUT VGAx = 2V p-p V = 2V p-p OUT −40 −40 INPUT LIMITED −50 −50 −60 −60 −70 −70 −80 −80 −90 −90 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 V (V) GAIN V (V) GAIN Figure 45. HD3 vs. Amplitude to VGAx Figure 48. HD2 vs. Amplitude to Differential Output −30 −30 1MHz 10MHz 35MHz −40 −40 −50 −50 −60 −60 −70 −70 −80 −80 V = 0.5V p-p OUT V = 1V p-p OUT V = 2V p-p OUT −90 −90 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 V (V) V (V) GAIN GAIN Figure 46. HD2 vs. V vs. Frequency to Differential Output Figure 49. HD3 vs. Amplitude to Differential Output GAIN 0 0 1MHz V = 1V p-p OUT 10MHz 35MHz −15 −20 −30 −40 −45 −60 −60 −80 −75 LOW TONE, f – 50kHz HIGH TONE, f + 50kHz −90 −100 1M 10M 100M –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 V (V) FREQUENCY (Hz) GAIN Figure 47. HD3 vs. V vs. Frequency to Differential Output Figure 50. IMD3 vs. Frequency to VGAx GAIN Rev. A | Page 15 of 40 HD3 (dBc) HD2 (dBc) HD3 (dBc) 07736-047 07736-046 07736-045 IMD3 (dBc) HD3 (dBc) HD2 (dBc) 07736-049 07736-048 07736-050 AD8264 20 50 f = 1MHz, OIP3L f = 35MHz, OIP3L f = 1MHz, OIP3H f = 35MHz, OIP3H f = 10MHz, OIP3L f = 100MHz, OIP3L 15 f = 10MHz, OIP3H f = 100MHz, OIP3H 40 10 30 5 0 20 VGAx (V = ±5V) S −5 DIFF OUT (V = ±5V) S 10 VGAx (V = ±3.3V) S −10 DIFF OUT (V = ±3.3V) S VGAx (V = ±2.5V) S DIFF OUT (V = ±2.5V) S 0 −15 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 V (V) V (V) GAIN GAIN Figure 54. Input P1dB vs. V Figure 51. OIP3 vs. V vs. Frequency to VGAx GAIN GAIN 0.10 0 V = 0.7V V = 1V p-p GAIN OUT −20 0.05 −40 0 −60 LOW TONE, f – 50kHz –0.05 −80 HIGH TONE, f + 50kHz –0.10 −100 1M 10M 100M –40 –20 0 20 40 60 80 100 TIME (ns) FREQUENCY (Hz) Figure 52. IMD3 vs. Frequency to Differential Output Figure 55. Small Signal Pulse Response to VGAx 50 0.15 V = 0.7V GAIN 0.10 40 0.05 30 0 20 –0.05 f = 1MHz, OIP3L f = 1MHz, OIP3H 10 f = 10MHz, OIP3L –0.10 f = 10MHz, OIP3H f = 35MHz, OIP3L f = 35MHz, OIP3H 0 –0.15 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 –40 –20 0 20 40 60 80 100 V (V) GAIN TIME (ns) Figure 53. OIP3 vs. Frequency to Differential Output Figure 56. Small Signal Pulse Response to Differential Output Rev. A | Page 16 of 40 IMD3 (dBc) OIP3 (dBm) OIP3 (dBm) 07736-051 07736-053 07736-052 VOLTAGE (V) VOLTAGE (V) INPUT-REFERRED P1dB (dBm) 07736-054 07736-056 07736-055 AD8264 1.5 1.5 V = 0.7V GAIN 1.0 1.0 0.5 0.5 0 0 1V p-p 1V p-p –0.5 –0.5 2V p-p 2V p-p –1.0 –1.0 –1.5 –1.5 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TIME (ns) TIME (ns) Figure 57. Large Signal Pulse Response to VGAx Figure 60. OFSx Large Signal Pulse Response 1.5 1.0 V = 0.7V V = 0.7V C = 0pF GAIN L GAIN C = 10pF L C = 22pF L 1.0 0.5 0.5 0 0 1V p-p –0.5 –0.5 2V p-p –1.0 –1.5 –1.0 –40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100 TIME (ns) TIME (ns) Figure 58. Large Signal Pulse Response to Differential Output Figure 61. Large Signal Pulse Response to VGAx for Various Capacitive Loads 1.5 2.0 2V p-p (V ) OL C = 0pF L 2V p-p (V ) OH C = 10pF L 1.5 1V p-p (V ) C = 22pF OL L 1.0 1V p-p (V ) OH 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 0 20 40 60 80 100 120 140 160 –40 –20 0 20 40 60 80 100 TIME (ns) TIME (ns) Figure 59. VOCM Large Signal Pulse Response Figure 62. Large Signal Pulse Response to Differential Output for Various Capacitive Loads Rev. A | Page 17 of 40 VOLTAGE (V) VOLTAGE (V) VOLTAGE (V) 07736-059 07736-058 07736-057 VOLTAGE (V) VOLTAGE (V) VOLTAGE (V) 07736-062 07736-061 07736-060 AD8264 –2.0 1.5 V = 0.7V GAIN C = 0pF L C = 10pF L –1.5 C = 22pF L 1.0 –1.0 0.5 –0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –2.0 –1.5 –40 –20 0 20 40 60 80 100 0 200 400 600 800 1000 1200 TIME (ns) TIME (ns) Figure 63. Large Signal Pulse Response to Differential Output for Figure 66. Preamp Overdrive Recovery Various Capacitive Loads with Series R = 10 Ω 1.5 1.5 1.0 1.0 V PULSE GAIN 0.5 0.5 GAIN RESPONSE 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 400 800 1200 1600 2000 0 200 400 600 800 1000 1200 TIME (ns) TIME (ns) Figure 64. VGAx Response to Change in V Figure 67. VGA Overdrive Recovery GAIN 1.5 0 VGAx (V = +0.7V) GAIN DIFF OUT (V = +0.7V) GAIN 1.0 –10 VGAx (V = −0.7V) GAIN DIFF OUT (V = −0.7V) GAIN 0.5 –20 GAIN RESPONSE 0 –30 –40 –0.5 V PULSE GAIN –50 –1.0 –1.5 –60 0 400 800 1200 1600 2000 100k 1M 10M 100M TIME (ns) FREQUENCY (Hz) Figure 65. Differential Output Response to Change in V Figure 68. Power Supply Rejection vs. Frequency (VPOS) GAIN Rev. A | Page 18 of 40 VOTLAGE (V) VOTLAGE (V) VOLTAGE (V) 07736-096 07736-065 07736-064 PSRR (dB) VOTLAGE (V) VOTLAGE (V) 07736-067 07736-066 07736-068 AD8264 5 135 VGAx (V = +0.7V) GAIN DIFF OUT (V = +0.7V) GAIN 125 –5 VGAx (V = −0.7V) GAIN DIFF OUT (V = −0.7V) ±5V GAIN 115 –15 105 –25 95 ±3.3V ±2.5V 85 –35 75 –45 65 –55 55 100k 1M 10M 100M –40 –15 10 35 60 85 110 FREQUENCY (Hz) TEMPERATURE (°C) Figure 69. Power Supply Rejection vs. Frequency (VNEG) Figure 70. Quiescent Supply Current vs. Temperature Rev. A | Page 19 of 40 PSRR (dB) 07736-069 SUPPLY CURRENT (mA) 07736-070 AD8264 TEST CIRCUITS V = ±2.5 V, T = 25°C, f = 10 MHz, C = 5 pF, R = 500 Ω per output (VGAx, VOHx, VOLx), V = (V − V ) = 0 V, S A L L GAIN GNHx GNLO V = GND, V = GND, gain range = 6 dB to 30 dB, unless otherwise specified. VOCM OFSx DC METER 500Ω AD8264 VGAx IPPx 500Ω + PrA VOLx 50Ω + 6dB DC IPNx – 6dB METER 500Ω – VOHx GNHx GNLO VOCM OFSx V GAIN OVEN Figure 71. Gain vs. V vs. Temperature (See Figure 3 and Figure 4) GAIN NETWORK ANALYZER OSCILLOSCOPE SIGNAL GENERATOR OUT CH1 CH2 CH1 CH2 50Ω 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL PROBE PROBE PROBE AD8264 AD8264 VGAx VGAx IPPx + 500Ω IPPx + PrA VOLx 50Ω + PrA VOLx 6dB 50Ω + 6dB IPNx – 6dB 500Ω IPNx – 6dB – VOHx – VOHx 500Ω GNHx GNLO VOCM OFSx GNHx GNLO VOCM OFSx V GAIN V GAIN Figure 72. Gain Error vs. V at Various Frequencies to VGAx (See Figure 5) Figure 74. Frequency Response vs. Gain to Differential Output for Various GAIN Values of V (See Figure 11) GAIN NETWORK ANALYZER NETWORK ANALYZER CH1 CH2 50Ω 50Ω DIFFERENTIAL CH1 CH2 PROBE 50Ω 50Ω AD8264 DIFFERENTIAL VGAx PROBE 500Ω IPPx + AD8264 PrA VOLx 50Ω + VGAx 6dB IPNx – 6dB IPPx + PrA VOLx – 50Ω + VOHx 6dB IPNx – 6dB 500Ω C L – VOHx GNHx GNLO VOCM OFSx 500Ω C L GNHx GNLO VOCM OFSx V GAIN Figure 73. Frequency Response vs. Gain to VGAx for Various Values of V , Figure 75. Frequency Response to Differential Output for GAIN V = GNHx – GNLO (See Figure 10) Various Capacitive Loads (See Figure 12) GAIN Rev. A | Page 20 of 40 07736-072 07736-100 07736-119 07736-102 07736-101 AD8264 NETWORK ANALYZER NETWORK ANALYZER CH1 CH2 50Ω 50Ω DIFFERENTIAL CH1 CH2 PROBE 50Ω 50Ω AD8264 DIFFERENTIAL VGAx PROBE IPPx + PrA AD8264 VOLx 50Ω + 6dB VGAx IPNx – 6dB IPPx + 10Ω PrA – VOLx VOHx 50Ω + 6dB 500Ω IPNx – 6dB C L – VOHx 10Ω GNHx OFSx V GNLO VOCM S 500Ω V V GNHx GNLO VOCM OFSx C L GAIN SUPPLY Figure 76. Frequency Response to Differential Output for Various Capacitive Figure 79. Frequency Response vs. Gain to VGAx for Loads with Series R = 10 Ω (See Figure 13) Various Supply Voltages (See Figure 18) NETWORK ANALYZER NETWORK ANALYZER CH1 CH2 CH1 CH2 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL PROBE DIFFERENTIAL PROBE AD8264 VGAx AD8264 500Ω C L VGAx IPPx + PrA VOLx 50Ω + IPPx 6dB + PrA – 6dB VOLx IPNx 50Ω + 6dB – 500Ω IPNx – 6dB VOHx – VOHx GNHx GNLO VOCM OFSx 500Ω GNHx GNLO VOCM OFSx V V S GAIN V GAIN V SUPPLY Figure 80. Frequency Response vs. Gain to Differential Output for Figure 77. Frequency Response to VGAx for Various Capacitive Loads Various Supply Voltages (See Figure 19) (See Figure 14) NETWORK ANALYZER NETWORK ANALYZER CH1 CH2 CH1 CH2 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL PROBE DIFFERENTIAL PROBE AD8264 10Ω VGAx AD8264 500Ω C L IPPx VGAx + PrA VOLx 50Ω + IPPx 6dB + PrA IPNx – 6dB VOLx + 6dB – 500Ω VOHx IPNx – 6dB – VOHx GNHx GNLO VOCM OFSx 500Ω GNHx GNLO VOCM OFSx V V S GAIN V SUPPLY 50Ω Figure 81. VOCM Frequency Response to Differential Output (See Figure 21) Figure 78. Frequency Response to VGAx for Various Capacitive Loads with Series R =10 Ω (See Figure 16) Rev. A | Page 21 of 40 07736-103 07736-077 07736-076 07736-078 07736-105 07736-104 AD8264 NETWORK ANALYZER CH1 CH2 SPECTRUM ANALYZER 50Ω 50Ω CH1 DIFFERENTIAL CH2 PROBE 50Ω 50Ω AD8264 VGAx IPPx + AD8264 AD8129 PrA VOLx + VGAx 10× 6dB IPNx – 6dB 500Ω IPPx + PrA VOLx – + VOHx 6dB IPNx – 6dB AD8129 500Ω – VOHx 10× GNHx GNLO VOCM OFSx V S GNHx OFSx GNLO VOCM V SUPPLY 50Ω V GAIN Figure 85. Output Referred Noise vs. V (See Figure 32) Figure 82. OFSx Frequency Response to Differential Output (See Figure 22) GAIN SPECTRUM ANALYZER 220Ω CH1 CH2 50Ω 50Ω 50Ω 500Ω AD8264 VGAx IPPx 500Ω + PrA VOLx + AD8264 AD8129 6dB DC 10× IPNx – 6dB VGAx METER 500Ω – VOHx IPPx + PrA VOLx + 6dB IPNx – 6dB GNHx GNLO VOCM OFSx AD8129 – VOHx 10× OVEN GNHx OFSx GNLO VOCM V GAIN Figure 86. Input Referred Noise vs. Frequency (See Figure 34) Figure 83. Output Offset Voltage vs. V vs. Temperature GAIN (See Figure 26 and Figure 27) NOISE METER NETWORK ANALYZER CH1 50Ω NOISE CH2 SOURCE 50Ω 50Ω AD8264 VGAx IPPx + AD8264 PrA VOLx 50Ω + 6dB VGAx IPNx – 6dB IPPx + – VOHx PrA VOLx 50Ω + 6dB IPNx – 6dB – GNHx GNLO VOCM OFSx VOHx V GAIN GNHx GNLO VOCM OFSx V S V SUPPLY Figure 87. Noise Figure vs. V (See Figure 36) Figure 84. Output Resistance vs. Frequency GAIN (See Figure 30 and Figure 31) Rev. A | Page 22 of 40 07736-110 07736-111 07736-106 07736-115 07736-113 07736-112 AD8264 SPECTRUM ANALYZER 220Ω CH1 CH2 50Ω 50Ω 50Ω 50Ω 0.1µF AD8264 AD8129 10× VGAx IPPx + PrA VOLx + R S 6dB IPNx – 6dB 50Ω 0.1µF AD8129 – VOHx 10× 50Ω 0.1µF GNHx GNLO VOCM OFSx 1kΩ 1kΩ Figure 88. Input Referred Noise vs. R (See Figure 35) SOURCE SPECTRUM ANALYZER NETWORK ANALYZER SIGNAL GENERATOR OUT CH1 CH1 CH2 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL LPF PROBE AD8264 10Ω AD8264 VGAx VGAx C IPPx + L PrA VOLx IPPx + 50Ω + 6dB PrA VOLx 50Ω + IPNx – 6dB 6dB 500Ω IPNx – 6dB – VOHx – VOHx 500Ω GNHx GNLO VOCM OFSx GNHx GNLO VOCM OFSx Figure 89. VOCM Common-Mode Rejection vs. Frequency (See Figure 37) Figure 91. Harmonic Distortion to VGAx vs. C (Figure 39) LOAD SPECTRUM ANALYZER SIGNAL GENERATOR OUT CH1 50Ω 50Ω SPECTRUM ANALYZER SIGNAL GENERATOR OUT CH1 50Ω 500Ω 50Ω LPF AD8264 450Ω VGAx LPF AD8264 IPPx + VGAx PrA VOLx 50Ω + 6dB IPPx + PrA IPNx – 6dB VOLx 50Ω + 6dB – IPNx – 6dB AD8130 VOHx 1× – VOHx R R GNHx GNLO VOCM OFSx V L L S GNHx GNLO VOCM OFSx V S V V SUPPLY SUPPLY Figure 90. Test Circuit Harmonic Distortion to VGAx vs. Figure 92. Harmonic Distortion to Differential Output vs. R and Various LOAD R and Various Supplies (See Figure 38) Supplies (See Figure 40) LOAD Rev. A | Page 23 of 40 07736-117 07736-116 07736-114 07736-118 07736-128 AD8264 SPECTRUM ANALYZER SIGNAL SPECTRUM ANALYZER GENERATOR SIGNAL OUT GENERATOR CH1 OUT 50Ω CH1 50Ω 50Ω 50Ω 350Ω LPF 450Ω AD8264 LPF AD8264 VGAx VGAx IPPx + PrA VOLx IPPx + 50Ω + 6dB PrA VOLx 50Ω + IPNx – 6dB AD8130 6dB 10Ω 1× IPNx – 6dB AD8130 – VOHx 1× – VOHx 10Ω V GNHx GNLO VOCM OFSx S C L C GNHx GNLO VOCM OFSx L V GAIN Figure 93. Harmonic Distortion to Differential Output vs. Figure 95. HD2 and HD3 to Differential Output (See Figure 46 through Figure 49) C (See Figure 41) LOAD SPECTRUM ANALYZER SPECTRUM ANALYZER SIGNAL GENERATOR OUT CH1 CH1 50Ω 50Ω 50Ω 450Ω OUT SIGNAL 450Ω GENERATOR AD8264 LPF 50Ω 50Ω VGAx AD8264 IPPx + VGAx PrA VOLx 50Ω + 6dB OUT SIGNAL IPPx IPNx – 6dB + GENERATOR PrA VOLx – 50Ω VOHx + 50Ω 6dB IPNx – 6dB – GNHx GNLO VOCM OFSx VOHx V GAIN GNHx GNLO VOCM OFSx V GAIN Figure 94. HD2 and HD3 to VGAx (See Figure 42 Through Figure 45) Figure 96. IMD3 and OIP3 to VGAx (See Figure 50 and Figure 51) SPECTRUM ANALYZER CH1 50Ω 450Ω OUT SIGNAL GENERATOR AD8264 50Ω 50Ω VGAx IPPx 10Ω + PrA VOLx 50Ω + 6dB OUT SIGNAL AD8130 IPNx – 6dB GENERATOR 10Ω 1× – VOHx 50Ω 500Ω 500Ω GNHx GNLO VOCM OFSx Figure 97. IMD3 and OIP3 to Differential Output (See Figure 52 and Figure 53) Rev. A | Page 24 of 40 07736-130 07736-129 07736-133 07736-131 07736-132 AD8264 NETWORK ANALYZER OSCILLOSCOPE CH2 CH1 CH3 CH1 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL PROBE 500Ω AD8264 VGAx IPPx + PrA VOLx 50Ω + 6dB AD8264 IPNx 500Ω – 6dB VGAx – VOHx IPPx + 500Ω PrA VOLx 50Ω + GNHx GNLO VOCM OFSx 6dB IPNx – 6dB 500Ω PULSE OUT GENERATOR – VOHx 50Ω 50Ω 500Ω GNHx GNLO VOCM OFSx V GAIN Figure 101. VOCM Pulse Response (See Figure 59) Figure 98. Input P1dB vs. V (See Figure 54) GAIN OSCILLOSCOPE OSCILLOSCOPE PULSE GENERATOR OUT CH1 CH2 CH1 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL PROBE DIFFERENTIAL DIFFERENTIAL AD8264 PROBE PROBE VGAx AD8264 IPPx + VGAx PrA VOLx 50Ω + 6dB 500Ω IPPx + IPNx – 6dB PrA VOLx 50Ω + – 6dB VOHx IPNx – 6dB – VOHx GNHx GNLO VOCM OFSx OUT PULSE GNHx GNLO VOCM OFSx GENERATOR 50Ω 50Ω Figure 99. Pulse Response to VGAx, V = 0.7 V (See Figure 55 and Figure 57) GAIN Figure 102. OFSx Pulse Response (See Figure 60) OSCILLOSCOPE OSCILLOSCOPE PULSE PULSE GENERATOR GENERATOR OUT OUT CH1 CH1 CH2 50Ω 50Ω 50Ω 50Ω 50Ω DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL PROBE PROBE PROBE AD8264 AD8264 VGAx VGAx IPPx C + L IPPx + PrA VOLx 50Ω + PrA VOLx 6dB 50Ω + 500Ω 6dB IPNx – 6dB IPNx – 6dB 500Ω – VOHx – VOHx 500Ω GNHx GNLO VOCM OFSx GNHx GNLO VOCM OFSx Figure 100. Pulse Response to Differential Outputs, V = 0.7 V Figure 103. Pulse Response to VGAx for Various Capacitive Loads, GAIN (See Figure 56 and Figure 58) V = 0.7 V (See Figure 61) GAIN Rev. A | Page 25 of 40 DIFFERENTIAL 07736-135 PROBE 07736-136 07736-134 07736-120 07736-122 07736-121 AD8264 OSCILLOSCOPE CH1 SIGNAL OSCILLOSCOPE GENERATOR OUT PULSE DIFFERENTIAL 50Ω GENERATOR PROBE OUT CH1 50Ω 50Ω 50Ω OPPx DIFFERENTIAL AD8264 PROBE VGAx AD8264 IPPx + VGAx PrA VOLx 50Ω + 6dB IPPx + PrA IPNx – 6dB VOLx 50Ω + 6dB C 500Ω – IPNx – 6dB L VOHx – VOHx C 500Ω L GNHx GNLO VOCM OFSx GNHx GNLO VOCM OFSx Figure 104. Pulse Response to Differential Output for Various Capacitive Figure 107. Preamp Overdrive Recovery (See Figure 66) Loads, V = 0.7 V (See Figure 62) GAIN OSCILLOSCOPE CH1 OSCILLOSCOPE SIGNAL GENERATOR PULSE OUT GENERATOR OUT 50Ω CH1 DIFFERENTIAL 50Ω 50Ω PROBE 50Ω DIFFERENTIAL PROBE AD8264 VGAx AD8264 VGAx IPPx + PrA VOLx 50Ω IPPx + 10Ω + 6dB PrA VOLx 50Ω C + IPNx 6dB L – 6dB 500Ω IPNx – 6dB – 10Ω VOHx – VOHx C 500Ω L GNHx GNLO VOCM OFSx GNHx GNLO VOCM OFSx Figure 105. Pulse Response to Differential Output for Various Capacitive Figure 108. VGA Overdrive Recovery, V = 0.7 V (See Figure 67) GAIN Loads with Series R = 10 Ω, V = 0.7 V (See Figure 63) GAIN OSCILLOSCOPE CH1 SIGNAL GENERATOR OUT CH2 50Ω 50Ω 50Ω DIFFERENTIAL PROBE AD8264 500Ω VGAx IPPx + PrA VOLx 50Ω + 6dB IPNx – 500Ω 6dB – VOHx 500Ω GNHx GNLO VOCM OFSx PULSE OUT GENERATOR 50Ω Figure 106. Gain Response to VGAx or Differential Output (See Figure 64 and Figure 65) Rev. A | Page 26 of 40 07736-125 07736-123 07736-124 07736-127 07736-126 AD8264 OSCILLOSCOPE CH2 CH1 CH3 50Ω 50Ω 50Ω DMM DMM (+1) (–1) DIFFERENTIAL PROBE VPOS VNEG AD8264 AD8264 VGAx VGAx 500Ω IPPx + IPPx + PrA VOLx 50Ω + PrA 6dB VOLx 50Ω + IPNx – 6dB 500Ω 6dB IPNx – 6dB – VOHx – VOHx 500Ω V GNHx GNLO VOCM OFSx S V GAIN V GNHx GNLO VOCM OFSx SUPPLY Figure 110. Quiescent Supply Current (See Figure 70) Figure 109. PSRR (See Figure 68 and Figure 69) Rev. A | Page 27 of 40 07736-108 07736-109 AD8264 THEORY OF OPERATION OVERVIEW VGA The AD8264 is a dc-coupled quad channel VGA with a fixed The VGA has a voltage feedback architecture and uses analog gain-of-2 (6 dB) preamplifier and a single-ended-to-differential control to vary the gain. Its low gain range helps to maintain output amplifier with level shift capability that can be used as an low offset and is intended for gain trim applications. The offset ADC driver. Figure 111 shows a representative block diagram of of the preamp and the VGA are trimmed; therefore, the maximum a single channel; all four channels are identical. The supply can input referred offset is <0.5 mV over temperature (see Figure 26). operate from ±2.5 V to ±5 V. The primary application is as a Keeping the gain of each stage relatively low also allows the pulse processor for medical positron emission tomography bandwidth to stay high. (PET) imaging; however, the part is useful for any dc-coupled The gain of the VGA is adjusted using the fully differential application that can benefit from variable gain. control inputs, GNHx and GNLO. The GNLO pin is internally The signal chain consists of three fundamental stages: the connected to all four channels and must be biased externally. preamplifier, the variable gain amplifier, and the differential Under typical conditions, the GNLO pin is grounded. The gain output buffer amplifier. The preamplifier has an internally fixed high control pins (GNHx) are independent for each channel. gain-of-2 (6 dB). The VGA comprises an attenuator that The gain slope is nominally 20 dB/V. With GNLO connected to provides 0 dB to 24 dB of attenuation, followed by a fixed gain ground, each GNHx input can have a voltage applied from VNEG 18 dB (8×) amplifier. The single-ended VGA output is connected to VPOS without gain foldover. directly to the noninverting input of the differential output To make use of the full gain range of the VGA, the nominal gain (post) amplifier, which has a differential fixed gain-of-2 (6 dB). control voltage needed at GNHx is ±0.65 V relative to the voltage The gain range from the preamp input to the VGA output is applied to GNLO. At the lowest supply voltage of ±2.5 V, the pin 0 dB to 24 dB. The aggregate gain range from preamp input to GNLO should always be grounded. With increasing supply, the the differential postamplifier output is 6 dB to 30 dB. common-mode range of the gain control interface increases. This means that GNLO can be anywhere within ±1.2 V at The ideal gain equation for the gain from the single-ended ±3.3 V supplies and ±2.8 V at ±5 V supplies. input to the output is V = V − V (1) GAIN GNHx GNLO Table 5. Gain Control Input Range Supply Voltage (V) GNLO Voltage Range (V) V Range (V) dB GAIN Gain= 20 ×V +ICPT (2) GAIN ±5 ±2.8 ±0.65 V ±3.3 ±1.2 ±0.65 The ideal value for ICPT, or the intercept, is defined at V = 0 V. GAIN ±2.5 0 ±0.65 The ICPT for the VGA output and differential amplifier outputs equals 12.1 dB and 18.1 dB, respectively. The actual intercept For example, at ±3.3 V supplies, the outputs of a single-supply varies with any additional gain or loss along the signal path. unipolar DAC, such as the 10-bit, 4-channel AD5314, can be The measured values are both approximately 0.2 dB low. used to drive the GNHx pins directly, in conjunction with using PREAMP the ADR318 1.8 V reference to bias the GNLO pin at V /2 = 0.9. REF The preamplifier is a current feedback amplifier, designed to Because the GNLO pin sources only about 1.2 µA for the four channels (~300 nA per channel, the same as for the GNHx pins), a drive the internal 100 Ω gain setting resistors and the resistive simple resistive divider is generally adequate to set the voltage at attenuator, which together result in a nominal load to the the GNLO input. preamplifier of about 113 Ω. Normally, the negative preamp input, IPNx, is not connected externally. The positive input IPPx is the high impedance input of the current feedback amp. Note that, at the largest supply voltage of ±5 V, the input signal can become so large that the preamplifier output cannot deliver the required current to drive the 113 Ω load and, therefore, limits at 6 V p-p. This means that the input limits at 3 V p-p. The short-circuit input referred noise at maximum VGA gain is about 2.3 nV/√Hz, and this accounts for all of the amplifiers and gain setting resistors. When measuring the input referred noise from the VGA output, the number is slightly lower at 2.1 nV/√Hz because the noise of the postamplifier is not included in the noise calculation. Rev. A | Page 28 of 40 AD8264 COMPOSITE GAIN IS +6dB TO +30dB PREAMP OUTPUT SINGLE-ENDED HS (NOT USED) VGA OUTPUT OPPx VGAx 3 NONINVERTING FIXED GAIN VGA DIFFERENTIAL OUTPUT PREAMP AMPLIFIER INPUT AMPLIFIER AMPLIFIER 6dB (2×) 6dB (2×) 18dB (8×) IPPx 1kΩ 2kΩ 1 + ATTENUATOR IPNx 100Ω –24dB TO 0dB – 747Ω VOLx DIFFERENTIAL INVERTING AMPLIFIER 2 VGA OUTPUT INPUT (NOT USED) 100Ω 107Ω VOHx GAIN INTERPOLATOR INTERFACE VPOS 2kΩ POWER BIAS SUPPLIES VNEG 1kΩ COMM GNHx GNLO VOCM OFSx DIFFERENTIAL GAIN OUTPUT COMMON-MODE OFFSET CONTROL INPUTS VOLTAGE ADJUSTMENT ADJUST 1.2V p-p MAX @ ±2.5V DIFFERENTIAL OUTPUT NEVER LIMITS 2.6V p-p MAX @ ±2.5V 1 2 3 2V p-p MAX @ ±3.5V TO ±3.3V BECAUSE VGA LIMITS FIRST. 4V p-p MAX @ ±3.5V TO ±3.3V 3V p-p MAX@ ±5V (PREAMP DIFFERENTIAL OUTPUT SWING = 2x VGA OUT 7.5V p-p MAX @ ±5V DRIVE LIMITED) 5.2V p-p MAX @ ±2.5V 34nV/√Hz 2.3nV/√Hz 8V p-p MAX @ ±3.5V TO ±3.3V 15V p-p MAX @ ±5V 73nV/√Hz Figure 111. Single-Channel Block Diagram If dc offset is not desired, then the OFSx pins should be connected POST AMPLIFIER to ground. However, the OFSx pins can also be used as separate From the preamp input to the VGA output (VGAx), the gain inputs if the user wants this function. is noninverting. As can be seen in Figure 111, the VGAx pins drive the positive input of the differential amplifier. The gain NOISE is inverting from the input of the preamp to the output pin at At maximum gain, the preamplifier is the primary contributor VOLx, and the gain is noninverting to the output VOHx. of noise and results in a differential output referred noise of Other than the input from VGAx, each differential amplifier roughly 73 nV/√Hz. The noise at the VGAx outputs is 34 nV/√Hz, has two additional inputs: VOCM and OFSx. A common and because of the gain-of-2, the VGA output noise is amplified VOCM pin is shared among all four postamplifiers, while by 6 dB to 68 nV/√Hz. The differential amplifier, including the separate OFSx pins are provided for each channel. gain setting resistors, contributes another 26 nV/√Hz, and the VOCM Pin rms sum results in a total noise of 73 nV/√Hz. At the lowest gain, the noise at the VGA output is approximately 19 nV/√Hz, and The VOCM pin sets the common-mode voltage of the differential when multiplied by two, it results in 38 nV/√Hz at the differential output and must be biased by an external voltage. When driving output; again, rms summing this with the 26 nV/√Hz of the a dc-coupled ADC, the voltage typically comes from the ADC differential amplifier causes the total output referred noise to reference, as shown in the Applications Information section. be approximately 46 nV/√Hz. If dc level shift is not necessary, the VOCM pin is connected to ground. The input referred noise to the preamplifier at maximum gain is 2.3 nV/√Hz and increases with decreasing gain. Note that all OFSx Pins noise numbers include the necessary gain setting resistors. The OFSx pins are the inverting inputs of the differential post amplifiers and can be used to prebias a differential dc offset at the output. This is very useful when the input is a unipolar pulse because the user can set up the gain and the offset in such a way as to optimally map a unipolar pulse into the full-scale input of an ADC, while dc coupling throughout. Rev. A | Page 29 of 40 07736-081 AD8264 APPLICATIONS INFORMATION Figure 112 also includes the DAC output equation, which A LOW CHANNEL COUNT APPLICATION CONCEPT indicates that the output can vary between 0 V and VREF = 1.25 V. USING A DISCRETE REFERENCE The output of the AD8264 is ideal to drive an ADC like the 1.8 V The AD8264 is particularly well suited for use in the analog quad-channel AD9228. If eight channels are needed, two AD8264s front end of medical PET imaging systems. Figure 112 shows with the octal AD9222 ADC achieve the same thing. The same how the AD8264 may be used with the AD5314 (a 4-channel, resistive divider can be used for two AD8264s because the bias 10-bit DAC) and the AD9222/AD9228 (an octal or quad, 12-bit current flowing is now ~2 µA, but this still only introduces an ADC, respectively). The DAC sets the gain of the AD8264. Note error of 1 mV with ideally matched resistors. With 20 dB/V gain that the full gain span of 24 dB is achieved with this setup because scaling, this is a gain error of only 0.02 dB, which is much the gain control input range of the AD8264 is very close to 1.25 V. smaller than the fundamental gain error of the AD8264 The GNLO pin must offset by 1.25/2 = 625 mV because the (typically ~0.2 dB). gain control input is bipolar around the voltage applied at GNLO. This is done with two 1 kΩ, 1% resistors. The approximately 1 µA The single-ended-to-differential amplifier of the AD8264 of bias current flowing from the GNLO pin does not contribute amplifies the VGA output signal by 6 dB and can provide the a significant error because the basic gain error of the AD8264 is required dc bias of the AD9222/AD9228, as shown in Figure 112. the limiting factor. The ADC is connected with the default internal reference because the SENSE pin is grounded. With this connection, the AD9222/ The ADR127 1.25 V precision reference with an input of 3.3 V AD9228 VREF pin is an output that provides 1 V; this is then can supply −2 mA to +5 mA from −40°C to +125°C, which is connected to the VOCM input of the AD8264, which sets the sufficient to drive both the resistive divider and the REFIN pin output common-mode voltage of the VOHx and VOLx pins to of the AD5314. The AD5314 is based on the string DAC concept, 1 V. This voltage is very close to the recommended optimal value of which means that the REFIN pin looks like a resistor that is VDD/2 = 0.9 V. With this configuration, the ADC inputs are set nominally 45 kΩ; this results in a current draw of 1.25V/45 kΩ = to a full-scale (FS) of 2 V p-p. 28 µA. Even at the lowest specified resistance of 37 kΩ, this is still only a current of 34 µA. Therefore, the total current draw from Note that the ADC VREF should not drive many loads; therefore, the ADR127 is the 625 µA of the resistive divider plus ~30 µA, for multiple AD8264s, the VREF should be buffered. which equals ~655 µA, well below the 5 mA maximum current. ADR127 NC 1 NC 6 +3.3V NC 2 GND 5 1.25V V × D REFIN V 4 V = 3 V OUT IN OUT N 2 0.1µF 1µF V RANGE = 0V TO 1.25V +3.3V OUT EACH 10µF REFIN V 1kΩ DD V A OUT 1% 625mV V B DAC OUT AD5314 1kΩ V C OUT 0.1µF 1% V D OUT GND +3.3V ~250nA EACH VPOS GNLO R S GNH1 IPPx GNH2 GNH3 R TERM AD8264 GNH4 VGA OUTPUTS TO OTHER VGAx SIGNAL PROCESSING +1.8V VNEG VOCM OFSx VOHx VOLx FS = 2V p-p R FILT VDD V – x ADC IN –3.3V AD9222/ C GND 10µF 0.1µF FILT AD9228 V + x IN VREF SENSE R FILT OUTPUT COMMON-MODE VOLTAGE = 1V VOHx = 1V, VOLx = 1V; VOFS = 0V SENSE GROUNDED: VREF = 1V Figure 112. Application Concept of the AD8264 with the AD5314 10-Bit DAC and the AD9222/AD9228 12-Bit ADC Rev. A | Page 30 of 40 ~1µA 625µA 07736-082 AD8264 Figure 113 shows how the AD8264 is connected in a PET A DC CONNECTED CONCEPT EXAMPLE application. The PMT generates a negative-going current pulse The dc connected concept example in Figure 113 is an application that results in a voltage pulse at the preamplifier input and a with the 40-channel AD5381, 3 V, 12-bit DAC. The main difference differential output pulse on VOLx and VOHx. between this example and Figure 112 is that, for the same ADR127 1.25 V reference, the full-scale output of the DAC is from To fully appreciate the advantages of the AD8264, note the 0 V to 2 × VREFIN = 2.5 V. Two options for gain control common-mode and polarity conversion afforded. The AD9228, include the following: as with most modern ADCs, is a low voltage, single-polarity device. Recall that the PMT is a high voltage device that yields a • Use the same circuit as in Figure 112 but use only half the negative pulse. To map the pulse to the input range of the ADC, DAC output voltage from 0 V to 1.25 V. This is the simplest the pulse must be inverted, shifted, and amplified to the full solution, requiring the fewest extra components. Note that input range of the ADC. This is done by using the gain control, the overall gain resolution increases by one bit to 11 bits signal offset, and common-mode features of the AD8264. over the 10-bit AD5314. The full-scale input of the converter is 0 V to 2 V, with a common- • Ground GNLO and scale the DAC output so that the mode of 1 V. Match the VOCM voltage of the AD8264 to the GNHx inputs vary from −0.652 V to +0.625 V. Figure 113 ADC common mode (VREF = 1 V), and the two devices can be shows a possible circuit implementation using a divider connected directly using an appropriate level of the antialiasing between the DAC output and a −1.25 V reference. filter. The PMT signal is 0 V to −0.1 V. With a gain of 20× (26 dB), GNLO cannot simply be increased to 1.25 V because, for a the AD8264 output signal range is 2 V p-p. Prebias the signal given supply voltage, GNLO has a limited voltage range to negative by −0.5 V using the AD8264 OFSx inputs, which sets achieve the full gain span (see Table 5). VOHx = 1.5 V and VOLx = 0.5 V for VOCM = 1 V. The output However, a third possibility is to use another voltage that is is perfectly matched to the input of the ADC. between 1.2 V and 625 mV on GNLO, such as 1 V. In this case, Note that, by connecting VOLx to the positive ADC input and the DAC must vary from 0.375 V to 1.625 V to achieve the fully VOHx to the negative ADC input, the negative input pulse is specified gain range. inverted automatically. The VGAx output is still a negative Note the gain limits when the differential gain control exceeds pulse, amplified by 20 dB for this example. ±0.625 V, either to 6 dB or to 30 dB. If the differential gain control input voltage is exceeded, no gain foldover occurs. ADR127 1 NC NC 6 +3.3V GND NC 2 5 VREF = 1.25V 2 × V × D REFIN V = V V 4 OUT 3 IN OUT N 2 0.1µF 1µF VOLTAGE FROM DAC AD5381 = 0 TO 2.5V V RANGE = 0V TO 1.25V +3.3V OUT EACH V 0 V 39 OUT OUT 10µF VARIES FROM REFIN V VOUT0 DD 12.5 TO 32.5µA VOUT1 DAC VOUT2 49.9kΩ 49.9kΩ AD5381 VOUT4 ~250nA GNH4 1% 1% TO 9 OTHER –625mV GNH1 AD8264s TO GND VOUT39 49.9kΩ 49.9kΩ +625mV 0.1µF 0.1µF EXAMPLE 1% 1% +3.3V 0V VREF = 1.25V ~250nA EACH 49.9kΩ 49.9kΩ SCALE VPOS GNLO 1% 1% –0.1V GNH1 SCALE CIRCUIT SCALE CIRCUIT CIRCUIT IPPx SCALE CIRCUIT GNH2 –1.25V GNH3 SCALE CIRCUIT 10µF 0.1µF +3.3V 100Ω AD8264 GNH4 SCALE CIRCUIT PMT VGA OUTPUTS TO OTHER VGAx SIGNAL PROCESSING +1.8V AD8663 VNEG VOCM OFSx VOHx VOLx FS = 2V p-p –3.3V R FILT VDD V + x ADC –3.3V IN AD9222/ C GND FILT AD9228 V – x IN VREF SENSE VOFS = –0.5V R FILT 10µF 0.1µF OUTPUT COMMON-MODE VOLTAGE = 1V SENSE GROUNDED: VREF = 1V VOHx = 1.5V, VOLx = 0.5V; VOFx = –0.5V Figure 113. Concept Application of AD8264 with 40-Channel AD5381 12-Bit, 3 V DAC and AD9222/AD9228 12-Bit ADC Rev. A | Page 31 of 40 07736-083 AD8264 TO V RANGE = 0V TO 1.25V OUT SWITCHING +3.3V –3.3V +3.3V +3.3V EACH POWER SUPPLY VPOS VPOS VNEG DVDD AVDDx VOUT0 GNH1 –INx VOUT1 GNH2 VOHx VOUT3 GNH3 DAC VOLx USB 2.0 TO PC VOUT4 PARALLEL GNH4 VGA +INx AD5381 ADI VISUAL INTERFACE TO 9 OUTPUTS TO ADC EVAL BOARD ANALOG AD8264 VGA OTHER TO PC OTHER AD9228 SIGNAL ANALYSIS CONTROL VOUT39 AD8264s EVAL BOARD PROCESSING EVAL KIT SOFTWARE IPPx +1.0V +2.5V VGAx DGND AGNDx VREF OFSx VOCM GNLO REFIN (ON BOARD) 1.0 0.8 0V 0.6 0.4 –0.1V GNLO = 625mV OFSx = −0.5V VOCM = 1.0V 0.2 0 INx PULSE –0.2 –0.4 GENERATOR –0.6 –0.8 –1.0 0 50 100 150 200 250 300 SAMPLES Figure 114. Evaluation Setup for DC-Coupled Analog Front-End Pulse Processing Application Using the AD8264 Figure 115. AD5381 Evaluation Software A convenient method of verifying and customizing the signal and program such DAC parameters as input codes, offset level, chains shown in Figure 112 or Figure 113 is by ordering the and output range based on a 2.5 V or 1.25 V reference. For corresponding evaluation boards available on www.analog.com. example, as shown in Figure 114, the reference can be set to 1.25 V, The AD8264-EVALZ is a platform through which the user can with a 0 V to 1.25 V output range to drive the GNHx inputs. quickly become familiar with the features and performance The ADC evaluation kit includes the AD9228-65EBZ board and capabilities of the AD8264. See the Evaluation Board section for HSC-ADC-FIFO5 board to decode the ADC output. It also more information. leverages the capabilities of VisualAnalog®, powerful simulation The EVAL-AD5381EB (40-channel DAC) includes a parallel PC and data analysis software that enables the user to run FFTs and interface and software evaluation program to control the DAC. to do real-time capture of the output levels. The AD5381evaluation software allows the user to configure Rev. A | Page 32 of 40 INPUT EXAMPLES VOLTAGE (V) 07736-085 07736-084 AD8264 TO V RANGE = 0V TO 1.25V OUT +3.3V –3.3V SWITCHING +3.3V +3.3V EACH POWER SUPPLY VPOS VPOS VNEG DVDD AVDDx V GNH1 –INx OUT0 V GNH2 VOHx OUT1 V GNH3 OUT3 DAC VOLx USB 2.0 TO PC V PARALLEL OUT4 GNH4 VGA +INx AD5381 ADI VISUAL INTERFACE TO 9 OUTPUTS TO ADC EVAL BOARD ANALOG AD8264 VGA OTHER TO PC OTHER AD9228 SIGNAL ANALYSIS CONTROL V AD8264S EVAL BOARD OUT39 PROCESSING EVAL KIT SOFTWARE IPPx +2.5V +1.0V VGAx DGND AGNDx VREF OFSx VOCM GNLO REFIN (ON BOARD) 0 –15 –30 GNLO = 625mV VOCM = 1.0V –45 –60 INx –75 + –90 3 2 4 AC –105 SOURCE –120 –135 –150 1.5M 3.0M 4.5M 6.0M 7.5M 9.0M 10.5M Figure 116. Evaluation Setup for AC Signal Processing Application Using the AD8264 Rev. A | Page 33 of 40 INPUT EXAMPLES 07736-086 AD8264 EVALUATION BOARD Analog Devices, Inc. provides evaluation boards to customers as CONNECTING AND USING THE AD8264-EVALZ a support service so that the circuit designer can become The AD8264 operates with bipolar power supplies from ±2.5 V dc familiar with the device in the most efficient way possible. The to ±5 V dc. Make sure the current capacity is ≥400 mA. Connect a AD8264 evaluation board provides a fast, easy, and convenient ground reference from the supplies to any of the black test loops, means to assess the performance of the AD8264 before going the positive supply to the red test loop (+V), and the negative through the hassle and expense of design and layout of a custom supply to the blue test loop (−V). board. The board is shipped fully assembled and tested, and it Notice that the board is shipped with jumpers installed on provides basic functionality as shipped. Standard connectors the 2-pin headers marked GN1_2, GN3_4, OFS_12, OFS_34, enable the user to attach standard lab test equipment without GNLO, and VOCM. If these jumpers are missing, the offset and having to wait for the rest of the design to be completed. Figure 117 common-mode functions float high, substantially increasing shows a digital image of the top view, and Figure 118 shows the the quiescent current of the board. schematic diagram of the AD8264 evaluation board. Apply input signals to any of the preamps at the SMA connectors, The printed circuit board (PCB) artwork for all conductor and silk- IN1 through IN4. These connectors are terminated with 50 Ω to screen layers is shown in Figure 119 to Figure 124. A description of accommodate typical signal generator analyzer voltage source a typical test setup can be found in the Applications Information impedances. The gain of the AD8264 preamps is fixed at 6 dB (2×) section. The PCB artwork can be used as a guide for circuit and can be monitored at the SMA connectors, OP1_2 and OP3_4, layout and placement of parts. This is particularly useful for if desired. Note that there are output selector switches for each pair multiple function circuits with many pins, requiring multiple of preamps and 453 Ω resistors in series with the preamp outputs. passive components. Figure 117. Digital Image of the AD8264-EVALZ (Top View) Rev. A | Page 34 of 40 07736-087 AD8264 GN1_2 +V –V OFS12 +V –V GND1 GND2 GND3 GND4 GND5 GND6 + C34 C33 10µF + 10µF L1 L2 R10 R9 FB FB DNI DNI R32 DNI VPOS GN1_2 OFS_12 GNLO IN_1 C20 C19 R51 0.1µF 0.1µF IN1 0Ω C24 0.1µF R11 VGA_1 R1 49.9Ω VGA1 453Ω R47 R48 R49 R86 R24 0Ω 0Ω 0Ω 0Ω DNI 40 39 38 37 36 35 34 33 32 31 OPP_1 OP12 R7 R55 453Ω 1 30 0Ω OP1_2 OPP12 IPN1 VOL1 R31 R56 VOUT_1 DNI 2 29 0Ω OPP1 VOH1 R58 OPP_2 3 28 0Ω IN_2 OPP2 VOH2 PIN 0 R73 R23 R22 R57 R45 EXPOSED PADDLE VOUT_2 0Ω DNI DNI 4 27 0Ω 49.9Ω IN2 IPN2 VOL2 R69 VGA2 453Ω 26 5 IPP2 VGA2 IN_3 R46 R78 PIN 0: EXPOSED PADDLE R67 49.9Ω 0Ω VGA3 25 453Ω 6 IN3 IPP3 VGA3 R25 R66 VGA3 DNI 0Ω 7 24 IPN3 VOL3 R20 R65 OPP_3 VOUT_3 DNI 23 0Ω 8 OPP3 VOH3 R63 OPP_4 OP34 R6 9 22 0Ω OPP4 453Ω VOH4 OP3_4 R19 R64 VOUT_4 DNI 0Ω 10 21 IPN4 VOL4 R29 OPP34 DNI 11 12 13 14 15 16 17 18 19 20 IN_4 VGA_4 R80 R70 R71 R8 R79 R17 R72 VGA4 0Ω 0Ω 0Ω 453Ω 0Ω 49.9Ω 0Ω C23 IN4 0.1µF C22 C21 0.1µF 0.1µF R16 GN34 DNI OFS34 R17 GN3_4 L3 L4 OFS_34 DNI FB FB R28 VOCM DNI +V –V VO_CM Figure 118. AD8264-EVALZ Schematic The SMA connectors, VGA1 through VGA4, enable signal quiescent gain control voltage at the GNHx pins from floating monitoring at these nodes, with 453 Ω resistors for protecting high. The low sides of the gain controls for each channel are the device. These resistors can be shorted at the discretion of internally connected in the AD8264, and a 2-pin header with the user if wide bandwidth is desired. The differential outputs jumper is provided to connect this pin (GNLO) to ground as well. are provided with 0.1” spacing 2-pin headers, which fit the low A similar arrangement of 2-pin headers is provided for the output capacitance Tektronix differential scope probe P6045 model. offset voltage. As shipped, the offset pins are connected to ground, Note that the gain control input of the AD8264 is differential. preventing the pins from floating high. Each channel has its own gain control pin (GNHx); however, For connecting to an ADC, remove the jumpers at the OF1_2 pairs of pins are connected together on the evaluation board and OF3_4 headers and connect the appropriate offset voltage and connected to a test loop. The 2-pin headers are provided for at the test loops, OF12 and OF34. If the VOCM pin is buffered, jumpers to connect the gain pins to ground, preventing the it can be connected to the reference of the ADC. Rev. A | Page 35 of 40 VGA2 IPP4 IPP1 COMM COMM GNH4 GNH1 GNH3 GNH2 VOCM GNLO VPOS VPOS VNEG VNEG OFS4 OFS1 OFS3 OFS2 VGA4 VGA1 07736-088 AD8264 Figure 122. Secondary Side Copper Figure 119. Component Side Assembly Figure 120. Component Side Copper Figure 123. Ground Plane Figure 121. Component Side Silk Screen Figure 124. Power Plane Rev. A | Page 36 of 40 07736-090 07736-091 07736-089 07736-093 07736-092 07736-094 AD8264 OUTLINE DIMENSIONS 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 1 30 PIN 1 0.50 INDICATOR TOP 4.25 BSC 5.75 EXPOSED VIEW 4.10 SQ BSC SQ PAD (BOT TOM VIEW) 3.95 0.50 21 10 0.40 20 11 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.02 NOM 1.00 THE PIN CONFIGURATION AND 0.30 0.85 FUNCTION DESCRIPTIONS COPLANARITY 0.20 REF SECTION OF THIS DATA SHEET. 0.80 0.23 SEATING 0.08 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 125. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8264ACPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1 H1V AD8264ACPZ-R7 −40°C to +85°C 40-Lead LFCSP_VQ, 7” Tape and Reel CP-40-1 H1V AD8264ACPZ-RL −40°C to +85°C 40-Lead LFCSP_VQ, 13” Tape and Reel CP-40-1 H1V AD8264-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 37 of 40 072108-A AD8264 NOTES Rev. A | Page 38 of 40 AD8264 NOTES Rev. A | Page 39 of 40 AD8264 NOTES ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07736-0-1/11(A) Rev. A | Page 40 of 40