ANALOG DEVICES AD8260

High Current Driver Amplifier and Digital VGA/Preamplifier with 3 dB Steps AD8260 FEATURES FUNCTIONAL BLOCK DIAGRAM VOCM INPP INRP INRN INPN TXFB VNEG VNEG High current driver 32 31 30 29 28 27 26 25 Differential input—direct drive from DAC 1.5kΩ 1kΩ 1kΩ 1.5kΩ Preset gain: 1.5× −3 dB bandwidth: 195 MHz VMDO 1 24 TXOP + – Large output drive: >±300 mA GM ×1 VGA/preamplifier TXEN 2 23 TXOP HIGH CURRENT DRIVER Low noise VMDI 3 AD8260 22 VPOS Voltage noise: 2.4 nV/√Hz VMID Current noise: 5 pA/√Hz VNCM 4 21 VPOS BIAS −3 dB bandwidth: 230 MHz VPSB 5 20 Gain range: 30 dB in 3 dB steps VPSR −6 dB to +24 dB (for preamplifier gain of 6 dB) VGA/PREAMPLIFIER 19 VMDO 6 ENBL Single-ended preamplifier input and differential VGA ATTENUATOR output VGAP 7 18 PRAI Supplies: 3.3 V to 10 V (with VMID enabled) GM STAGES ±3.3 V to ±5 V (with VMID disabled) 8 17 VGAN FDBK LOGIC Power: 93 mW with 3.3 V supplies Power-down for VGA, driver amplifier, and system 9 10 11 12 13 14 15 16 VNGR VPSR GNS3 GNS2 GNS1 GNS0 PRAO VNGR APPLICATIONS Figure 1. Functional Block Diagram Digital AGC systems Tx/Rx signal processing Power line transceivers GENERAL DESCRIPTION The AD8260 includes a high current driver, usable as a dynamic range, it is essential that the part be ac-coupled when transmitter, and a low noise digitally programmable variable operating on a single supply. gain amplifier (DGA), useable as a receiver. The AD8260 preamplifier (PrA) is configured with external The receiver section consists of a single-ended input preampli- resistors for gains greater than 6 dB and can be inverting or fier, and linear-in-dB, differential-output DGA. The receiver has noninverting. The DGA is characterized with a noninverting a small signal –3 dB bandwidth of 230 MHz; the driver small preamplifier gain of 2×. The attenuator has a range of 30 dB and signal bandwidth is 195 MHz. The driver delivers ±300 mA, the output amplifier has a gain of 8× (18.06 dB). The lowest noninverting gain range is −6 dB to +24 dB and shifts up with well suited for driving low impedance loads, even when connected to a 3.3 V supply. increased preamplifier gain. The gain is controlled via a parallel port (Pin GNS0 to Pin GNS3) with 10 gain steps of 3 dB per The AD8260 DGA is ideal for trim applications and has a gain code. The preamplifier and DGA are disabled for any code that span of 30 dB, in 3 dB steps. Excellent bandwidth uniformity is is not assigned a gain step. maintained across the entire frequency range. The low output- referred noise of the DGA is advantageous in driving high The AD8260 can operate with single or dual supplies from 3.3 V speed ADCs. The differential output facilitates the interface to to ±5 V. An internal buffer normally provides a split supply modern low voltage high speed ADCs. reference for single-supply operation; an external reference can also be used when the VMID buffer is shut down. Single-supply and dual-supply operation makes the part versatile and enables gain control of negative-going pulses, such as those The operating temperature range is −40°C to +105°C. The generated by photodiodes or photo-multiplier tubes, as well as AD8260 is available in a 5 mm × 5 mm, 32-lead LFCSP. processing band-pass signals on a single supply. For maximum Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved. 07192-001 AD8260 TABLE OF CONTENTS Features .............................................................................................. 1 VMID Buffer ............................................................................... 22 Applications ....................................................................................... 1 Preamplifier ................................................................................. 22 Functional Block Diagram .............................................................. 1 Preamplifier Noise ...................................................................... 22 General Description ......................................................................... 1 DGA ............................................................................................. 23 Revision History ............................................................................... 2 Gain Control ............................................................................... 23 Specifications ..................................................................................... 3 Output Stage ................................................................................ 23 Absolute Maximum Ratings ............................................................ 6 Attenuator.................................................................................... 23 ESD Caution .................................................................................. 6 Single-Supply Operation and AC Coupling ........................... 24 Pin Configuration and Function Descriptions ............................. 7 Power-Up/Power-Down Sequence .......................................... 24 Typical Performance Characteristics ............................................. 8 Logic Interfaces ........................................................................... 24 Test Circuits ..................................................................................... 16 Applications Information .............................................................. 25 Theory of Operation ...................................................................... 20 Evaluation Board ............................................................................ 26 Overview ...................................................................................... 20 Connecting the Evaluation Board ............................................ 27 High Current Driver Amplifier ................................................ 21 Outline Dimensions ....................................................................... 32 Precautions to Be Observed During Half-Duplex Ordering Guide .......................................................................... 32 Operation ..................................................................................... 22 REVISION HISTORY 2/11—Rev. 0 to Rev. A Added EPAD Notation..................................................................... 7 Changes to Figure 70 ...................................................................... 29 5/08—Revision 0: Initial Version Rev. A | Page 2 of 32 AD8260 SPECIFICATIONS V (supply voltage) = 3.3 V, T = 25°C, preamplifier gain = 2× (R = R = 100 Ω), V = V /2, f = 10 MHz, C = 5 pF, R = 500 Ω, S A FB1 FB2 VMDO S L LOAD DGA differential output. All dBm values are referenced to 50 Ω, gain code 1011, unless otherwise specified. Table 1. Parameter Conditions Min Typ Max Unit DRIVER AMPLIFIER—GENERAL PARAMETERS –3 dB Small Signal Bandwidth V = 10 mV p-p, R = 500 Ω 195 MHz OUT LOAD V = 10 mV p-p, R = 50 Ω 120 MHz OUT LOAD V = 10 mV p-p, R = 10 Ω 85 MHz OUT LOAD –3 dB Large Signal Bandwidth V = 1 V p-p 195 MHz OUT V = 2 V p-p 190 MHz OUT V = 2 V p-p, R = 50 Ω 180 MHz OUT LOAD Slew Rate V = 1 V p-p 730 V/µs OUT V = 2 V p-p 725 V/µs OUT V = 2 V p-p, R = 50 Ω 620 V/µs OUT LOAD Gain Nominal gain with internal gain setting resistors 3.0 3.52 dB Input Voltage Noise f = 10 MHz 9.5 nV/√Hz Noise Figure R = 100 Ω (differential, 2 × 50 Ω that convert 17.6 dB S differential DAC output currents to differential voltage) Output-Referred Noise Gain = 3.52 dB (1.5×), includes internal gain setting 14.3 nV/√Hz resistors Output Impedance DC to 10 MHz, V = ±3.3 V ≤1.7 Ω S Output Current R = 1 Ω, V = ±0.5 V ±310 mA LOAD IN Output Signal Range R ≥ 500 Ω V ± 1.5 V LOAD MDO V = +5 V V ± 2.3 V S MDO ±4.7 V V = ±5 V S Input Signal Range Differential input signal 2 V p-p Output Offset Voltage Gain = 3.52 dB (1.5×), max and min limits are 3σ −20 ±5 +20 mV DRIVER AMPLIFIER—DYNAMIC PERFORMANCE Harmonic Distortion V = 1 V p-p OUT HD2 f = 1 MHz −84 dBc HD3 −85 dBc HD2 f = 10 MHz −83 dBc HD3 −70 dBc Harmonic Distortion V = 2 V p-p OUT HD2 f = 1 MHz −78 dBc HD3 −76 dBc HD2 f = 10 MHz −70 dBc HD3 −58 dBc Input 1 dB Compression Point 13 dBm Multitone Power Ratio (MTPR, In-Band) R = 50 Ω, V = 1.4 V p-p max, 10 tones, 2 MHz to −49 dBc LOAD OUT 22 MHz with missing tone at 12 MHz (spacing 2 MHz) R = 50 Ω, V = 1.4 V p-p max, 16 tones, 2 MHz to −43 dBc LOAD OUT 38 MHz with missing tones at 10 MHz, 20 MHz, 30 MHz, and 40 MHz (spacing 2 MHz) Two-Tone Intermodulation Distortion (IMD3) V = 1 V p-p, f = 10 MHz, f = 11 MHz −90 dBc OUT 1 2 V = 2 V p-p, f = 10 MHz, f = 11 MHz −71 dBc OUT 1 2 V = 1 V p-p, f = 45 MHz, f = 46 MHz −60 dBc OUT 1 2 V = 2 V p-p, f = 45 MHz, f = 46 MHz −48 dBc OUT 1 2 Output Third-Order Intercept V = 1 V p-p, f = 10 MHz 43 dBm OUT V = 2 V p-p, f = 10 MHz 40 dBm OUT V = 1 V p-p, f = 45 MHz 28 dBm OUT V = 2 V p-p, f = 45 MHz 28 dBm OUT Two-Tone Intermodulation Distortion (IMD3), V = 1 V p-p, f = 10 MHz, f = 11 MHz −69 dBc OUT 1 2 R = 50 Ω LOAD V = 2 V p-p, f = 10 MHz, f = 11 MHz −72 dBc OUT 1 2 V = 1 V p-p, f = 45 MHz, f = 46 MHz −51 dBc OUT 1 2 V = 2 V p-p, f = 45 MHz, f = 46 MHz −48 dBc OUT 1 2 Rev. A | Page 3 of 32 AD8260 Parameter Conditions Min Typ Max Unit Output Third-Order Intercept, R = 50 Ω V = 1 V p-p, f = 10 MHz 33 dBm LOAD OUT V = 2 V p-p, f = 10 MHz 40 dBm OUT V = 1 V p-p, f = 45 MHz 23 dBm OUT V = 2 V p-p, f = 45 MHz 28 dBm OUT PREAMPLFIER AND VGA—GENERAL PARAMETERS −3 dB Small Signal Bandwidth V = 10 mV p-p, gain code = 0110 230 MHz OUT −3 dB Large Signal Bandwidth V = 1 V p-p, gain code = 0110 165 MHz OUT V = 2 V p-p, gain code = 0110 135 MHz OUT Slew Rate V = 1 V p-p, gain code = 0110 330 V/µs OUT V = 1.6 V p-p, gain code = 0110 335 V/µs OUT Input Voltage Noise f = 10 MHz (shorted input) 2.4 nV/√Hz f = 10 MHz (input open) 6.2 nV/√Hz Noise Figure Max gain (gain code = 1011), R = 50 Ω, unterminated 10.2 dB S Max gain (gain code = 1011), R = 50 Ω, 15.5 dB S shunt terminated with 50 Ω Output-Referred Noise Max gain (gain code = 1011), gain = 24 dB (input short) 38 nV/√Hz Max gain (gain code = 1011), gain = 24 dB (input open) 98.1 nV/√Hz Min gain (gain code = 0001), gain = −6 dB 25 nV/√Hz Output Impedance DC to 10 MHz ≤3 Ω Output Signal Range (per Pin) R ≥ 500 Ω V ± 0.7 V LOAD MDO V = +5 V V ± 1.4 V S MDO V = ±5 V ±3.6 V S Input Signal Range Preamplifier input V ± 0.3 V MDO Output Offset Voltage Max gain (gain code = 1011), gain = 24 dB, 3 σ limits −50 ±20 +50 mV PREAMPLIFIER AND VGA—DYNAMIC PERFORMANCE Harmonic Distortion Gain code = 0110, gain = 9 dB, V = 1 V p-p OUT HD2 f = 1 MHz −90 dBc HD3 −87 dBc HD2 f = 10 MHz −75 dBc HD3 −58 dBc Harmonic Distortion Gain code = 1011, gain = 24 dB, V = 2 V p-p OUT HD2 f = 1 MHz −94 dBc HD3 −90 dBc HD2 f = 10 MHz −61 dBc HD3 −84 dBc Input 1 dB Compression Point Min gain (gain code = 0001), gain = −6 dB 1.9 dBm (preamplifier limited) Max gain (gain code = 1011), gain = 24 dB −9.2 dBm (VGA limited) MTPR (In-Band) V = 1.4 V p-p-max, 10 tones, 2 MHz to 22 MHz with −68 dBc OUT missing tone at 12 MHz (spacing 2 MHz), gain code = 1011, gain = 24 dB V = 1.4 V p-p-max, 16 tones, 2 MHz to 38 MHz with −61 dBc OUT missing tones at 10 MHz, 20 MHz, 30 MHz, and 40 MHz (spacing 2 MHz) Two-Tone Intermodulation Distortion (IMD3) Gain code = 1011, gain = 24 dB V = 1 V p-p, f = 10 MHz, f = 11 MHz −92 dBc OUT 1 2 V = 2 V p-p, f = 10 MHz, f = 11 MHz −77 dBc OUT 1 2 V = 1 V p-p, f = 45 MHz, f = 46 MHz −50 dBc OUT 1 2 V = 2 V p-p, f = 45 MHz, f = 46 MHz −36 dBc OUT 1 2 Output Third-Order Intercept Gain code = 1011, gain = 24 dB V = 1 V p-p, f = 10 MHz 44 dBm OUT V = 2 V p-p, f = 10 MHz 43 dBm OUT V = 1 V p-p, f = 45 MHz 27 dBm OUT V = 2 V p-p, f = 45 MHz 22 dBm OUT Overload Recovery Max gain (gain code = 1011), gain = 24 dB, 50 ns V = 50 mV p-p to 500 mV p-p IN Group Delay Variation 1 MHz < f < 50 MHz, full gain range 2 ns Rev. A | Page 4 of 32 AD8260 Parameter Conditions Min Typ Max Unit ACCURACY Absolute Gain Error All gain codes, limits are 3σ −0.5 ±0.15 +0.5 dB Gain Law Conformance (DNL) Differential gain error code-to-code −0.3 ±0.15 +0.3 dB GAIN CONTROL Gain Step per Code 3.0 dB Gain Range Default = −6dB to +24 dB 30 dB Response Time 30 dB gain change (gain code stepped from 0001 to 1011) 50 ns LOGIC INTERFACES High Level Input Voltage 1.4 V V S Low Level Input Voltage 0 0.8 V Logic Input Bias Current Logic high, V = 3.3 V 0.2 μA LOGIC Logic low 18 nA POWER SUPPLY Supply Voltage Single supply 3.3 10 V Dual supply ±3.3 ±5 V Quiescent Current Full chip enabled (TXEN = 1, ENBL = 1, gain code = 0001) 28.3 mA TXEN = 0, ENBL = 1, gain code = 0001, driver off, DGA on 19.1 mA TXEN = 1, ENBL = 1, gain code = 0000, driver on, DGA off 10.8 mA Chip disabled (TXEN = 0, ENBL = 0, gain code = 0000) 35 µA V = ±5 V, no signal 34.2 mA S PSRR Max gain (gain code = 1011), gain = 24 dB, 1 MHz −30 dB Driver amplifier, 1 MHz −48 dB Power Dissipation No signal 93 mW No signal, V − V = 10 V 342 mW POS NEG ENABLE TIMES Chip Enable Time Bias only, TXEN = 0, gain code = 0000, ENBL = 0 to 1 0.4 µs All at once, TXEN = 0 to 1, gain code = 0000 to 0001, 0.3 µs ENBL = 0 to 1 Preamplifier and DGA Enable Time ENBL = 1, TXEN = 0, gain code = 0000 to 0001 0.3 µs Driver Enable Time ENBL = 1, gain code = 0001, TXEN stepped from 0 to 1 0.2 µs DISABLE TIMES Chip Disable Time TXEN = 1 to 0, gain code = 0001 to 0000, 20 µs ENBL = 1 to 0, I = 100 μA SUPPLY All at once, TXEN = 1 to 0, gain code = 0001 to 0000, 50 µs ENBL = 1 to 0, I = 35 µA SUPPLY Preamplifier and DGA Disable Time ENBL = 1, TXEN = 0, gain code = 0001 to 0000 0.4 µs Driver Disable Time ENBL = 1, gain code = 0000, TXEN = 1 to 0 2.2 µs Rev. A | Page 5 of 32 AD8260 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Voltage rating only; functional operation of the device at these or any Supply Voltage (VPOS, VNEG) ±6 V other conditions above those indicated in the operational Input Voltage (INxx, PRAI, VPOS, VNEG FDBK, VMDI, VOCM) section of this specification is not implied. Exposure to absolute Logic Voltages VPOS, ground maximum rating conditions for extended periods may affect Temperature device reliability. Operating Temperature Range –40°C to +105°C Storage Temperature Range –65°C to +150°C ESD CAUTION Lead Temperature (Soldering, 60 sec) 300°C 1 Thermal Data Maximum Junction Temperature 125°C θ 47.3°C/W JA θ 6.9°C/W JC θ 28.6°C/W JB Ψ 0.6°C/W JT Ψ 27.4°C/W JB 1 Thermal data at zero airflow with exposed pad soldered to four-layer JEDEC board with vias per JESD51-5. Rev. A | Page 6 of 32 AD8260 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 24 TXOP VMDO 1 PIN 1 23 TXOP TXEN 2 INDICATOR 22 VPOS VMDI 3 VNCM 4 AD8260 21 VPOS TOP VIEW VPSB 5 20 VPSR (Not to Scale) ENBL 6 19 VMDO VGAP 7 18 PRAI VGAN 8 17 FDBK 9 10 11 12 13 14 15 16 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. THE GROUND PLANE PATTERN SHOULD INCLUDE A PATTERN OF VIAS TO INNER LAYERS. Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 1, 19 VMDO VMID Buffer Output. Requires robust ac decoupling with a capacitance of 0.1 µF capacitor or greater. 2 TXEN Driver Enable. Logic threshold = 1.1 V with ±0.2 V hysteresis. 3 VMDI VMID Input Voltage. Normally decoupled with a 0.1 µF capacitor. When pulled to VNCM, the VMID buffer shuts down. This can be useful when using the part with dual supplies or when an external midpoint generator is used. 4 VNCM Negative Supply for Bias Cell, VMID Cell, and Logic Inputs. (Ground this pin in applications.) 5 VPSB Positive Supply for Bias Cell and VMID Cell. 6 ENBL Enable. Logic threshold = 1.1 V. When low, the AD8260 is disabled and the supply current is 35 µA when TXEN and all GNSx pins are also low. 7 VGAP Positive VGA Output (Needs to Be Ac-Coupled for Single Supply). 8 VGAN Negative VGA Output (Needs to Be Ac-Coupled for Single Supply). 1 9, 16 VNGR Negative Supply for Preamplifier and DGA (Set to −VPOS for Dual Supply; GND for Single Supply). 1 10, 20 VPSR Positive Supply for Preamplifier, DGA, and GNSx Logic Decoder. 11 GNS3 MSB for Gain Control. Logic threshold = 1.1 V. 12 GNS2 Gain Control Bit. Logic threshold = 1.1 V. 13 GNS1 Gain Control Bit. Logic threshold = 1.1 V. 14 GNS0 LSB for Gain Control. Logic threshold = 1.1 V. 15 PRAO Preamplifier Output. 17 FDBK Negative Input of Preamplifier. 18 PRAI Positive Input of Preamplifier. 1 21, 22 VPOS Positive Supply for Driver Amplifier. 1 23, 24 TXOP Driver Output. 1 25, 26 VNEG Negative Supply for Driver Amplifier (Set to −VPOS for Dual Supply; GND for Single Supply). 27 TXFB Feedback for Driver Amplifier. 28 INPN Negative Driver Amplifier Input. 29 INRN Negative Gain Resistor Input for Driver Amplifier. 30 INRP Positive Gain Resistor Input for Driver Amplifier. 31 INPP Positive Driver Amplifier Input. 32 VOCM Output Common Mode Pin. Normally connected to Pin VMDO. EPAD Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane. The ground plane pattern should include a pattern of vias to inner layers. 1 Pins with the same name are connected internally. Rev. A | Page 7 of 32 VNGR VOCM VPSR INPP GNS3 INRP GNS2 INRN GNS1 INPN GNS0 TXFB PRAO VNEG VNGR VNEG 07192-002 AD8260 TYPICAL PERFORMANCE CHARACTERISTICS V (supply voltage) = 3.3 V, T = 25°C, C = 5 pF, f = 10 MHz, preamplifier gain = 2×, R and R of the preamplifier = 100 Ω, S A L FB1 FB2 R of the driver amplifier = 500 Ω, T and R enabled, unless otherwise specified. LOAD X X 5 20 V = 200mV p-p OUT T = +25°C T = –40°C RTO 4 15 3 T = +105°C RTI 10 2 5 1 0 0 100k 1M 10M 100M 200M 100k 1M 10M 50M FREQUENCY (Hz) FREQUENCY (Hz) Figure 3. Small-Signal Frequency Response at Three Temperatures of the Figure 6. Input-Referred and Output-Referred Noise of the High Current High Current Driver—See Figure 51 Driver—See Figure 52 5 100 V = 200mV p-p OUT V = +3.3V S 4 10 3 V = +5V S V = ±5V S 2 1 1 0 0.1 100k 1M 10M 100M 200M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 4. Small-Signal Frequency Response of the High Current Driver for Figure 7. Output Impedance of the High Current Driver Three Supply Voltages—See Figure 51 See Figure 53 5 –20 V = 1V p-p; R = 50Ω LOAD LOAD V = 1V p-p; R = 500Ω LOAD LOAD –30 V = 2V p-p; R = 50Ω LOAD LOAD V = 2V p-p; R = 500Ω 4 LOAD LOAD –40 –50 3 2V p-p –60 HD2 HD3 2 –70 –80 1V p-p 1 –90 0 –100 10 100 1k 100k 1M 10M 100M 200M LOAD RESISTANCE (Ω) FREQUENCY (Hz) Figure 5. Large-Signal Frequency Response of the High Current Driver for Two Figure 8. Harmonic Distortion (HD2, HD3) vs. Load Resistance for the High Values of Output Voltage and Two Values of Load Resistance—See Figure 51 Current Driver—See Figure 54 Rev. A | Page 8 of 32 GAIN (dB) GAIN (dB) GAIN (dB) 07192-005 07192-004 07192-003 HARMONIC DISTORTION (dBc) OUTPUT IMPEDANCE (Ω) NOISE (nV/√Hz) 07192-008 07192-007 07192-006 AD8260 0 –20 f = 10MHz –30 HD2, V = 1V p-p OUT –20 HD3, V = 1V p-p OUT –40 HD2, V = 2V p-p OUT R = 50Ω, V = 1V p-p LOAD OUT HD3, V = 2V p-p OUT R = 50Ω, V = 2V p-p LOAD OUT –50 –40 R = 500Ω, V = 1V p-p LOAD OUT R = 500Ω, V = 2V p-p LOAD OUT –60 –60 –70 –80 –80 –90 –100 –100 0 10 20 30 40 50 60 70 80 90 100 2M 10M 100M LOAD CAPACITANCE (pF) FREQUENCY (Hz) Figure 9. Harmonic Distortion (HD2, HD3) vs. Load Capacitance at Two Figure 12. IMD3 vs. Frequency for Two Values of Output Voltage and Two Values of Output Voltage for the High Current Driver—See Figure 54 Values of Load Resistance for the High Current Driver—See Figure 55 50 0 f = 10MHz –20 40 –40 30 –60 R = 50Ω, V = 1V p-p LOAD OUT HD3 R = 50Ω, V = 2V p-p HD2 LOAD OUT 20 R = 500Ω, V = 1V p-p LOAD OUT –80 R = 500Ω, V = 2V p-p LOAD OUT 10 –100 –120 0 0 0.5 1.0 1.5 2.0 2.5 3.0 2M 10M 100M OUTPUT VOLTAGE (V p-p) FREQUENCY (Hz) Figure 13. Third-Order Intercept (OIP3) vs. Frequency for the High Current Driver Figure 10. Harmonic Distortion (HD2, HD3) vs. Output Voltage for the High See Figure 55 Current Driver—See Figure 54 –20 20 R = 50Ω LOAD R = 500Ω –30 LOAD –40 15 HD2 –50 2V p-p HD3 10 –60 –70 –80 5 1V p-p –90 0 –100 1M 10M 100M 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Harmonic Distortion (HD2, HD3) vs. Frequency of the High Current Figure 14. Input-Referred 1 dB Compression (IP1dB) vs. Frequency for Two Driver at Two Values of Output Voltage—See Figure 54 Values of Load Resistance for the High Current Driver Rev. A | Page 9 of 32 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 07192-010 07192-009 07192-011 OIP3 (dBm) IP1dB (dBm) IMD3 (dBc) 07192-014 07192-013 07192-012 AD8260 0.20 0 C = 5pF LOAD 0.15 C = 10pF LOAD –10 C = 47pF LOAD 0.10 –20 –30 0.05 –40 0 –50 –0.05 –60 –0.10 –70 –0.15 R = 50Ω LOAD NONINVERTING –80 –0.20 –90 –30 –20 –10 0 10 20 30 40 50 60 70 80 0 2 4 6 8 10 12 14 16 18 20 22 24 TIME (ns) FREQUENCY (MHz) Figure 15. Missing Tone Power Ratio for the High Current Driver Figure 18. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, C , and 50 Ω Load—See Figure 56 LOAD 0.20 2.0 C = 5pF LOAD C = 5pF LOAD NONINVERTING NONINVERTING 0.15 1.5 0.10 1.0 0.5 0 .05 0 0 –0.5 –0.05 –1.0 –0.10 R = 10Ω R = 10Ω LOAD LOAD R = 50Ω R = 50Ω LOAD LOAD –1.5 R = 100Ω –0.15 R = 100Ω LOAD LOAD R = 500Ω LOAD R = 500Ω LOAD –0.20 –2.0 –30 –20 –10 0 10 20 30 40 50 60 70 80 30 20 10 0 10 20 30 40 50 60 70 80 TIME (ns) TIME (ns) Figure 16. Small-Signal Pulse Response of the High Current Driver for Various Figure 19. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Resistance, R —See Figure 56 Values of Load Resistance, R —See Figure 56 LOAD LOAD 0.20 2.0 C = 5pF C = 5pF LOAD LOAD 0.15 C = 10pF LOAD 1.5 C = 10pF LOAD C = 47pF C = 47pF LOAD LOAD 0.10 1.0 0.05 0.5 0 0 –0.05 –0.5 –0.10 –1.0 R = 500Ω LOAD NONINVERTING –0.15 R = 500Ω –1.5 LOAD NONINVERTING –0.20 –2.0 –30 –20 –10 0 10 20 30 40 50 60 70 80 –30 –20 –10 0 10 20 30 40 50 60 70 80 TIME (ns) TIME (ns) Figure 17. Small-Signal Pulse Response of the High Current Driver for Various Figure 20. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, C , and R = 500 Ω—See Figure 56 LOAD LOAD Values of Load Capacitance, C , and R = 500 Ω—See Figure 56 LOAD LOAD Rev. A | Page 10 of 32 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT (dBm) 07192-015 07192-017 07192-016 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07192-020 07192-019 07192-018 AD8260 2.0 1.00 R = 50Ω LOAD C = 5pF NONINVERTING LOAD 1.5 C = 10pF 0.75 LOAD C = 47pF LOAD AVERAGE OF 3 SAMPLES 1.0 f = 1MHz, 10MHz, AND 40MHz 0.50 0.5 0.25 0 0 –0.5 –0.25 –1.0 –0.50 –1.5 –0.75 –2.0 –1.00 –30 –20 –10 0 10 20 30 40 50 60 70 80 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 TIME (ns) GAIN SELECT CODE Figure 21. Large-Signal Pulse Response of the High Current Driver for Various Figure 24. Absolute Gain Error vs. Gain Select Code for Three Samples for the Values of Load Capacitance, C , and 50 Ω Load—See Figure 56 VGA/Preamplifier at Three Frequencies Normalized to 1 MHz and Code 0110 LOAD See Figure 57 27 1.00 24 0.75 21 AVERAGE OF 3 SAMPLES T = +105°C f = 1MHz, 10MHz, AND 40MHz T = +25°C 18 0.50 T = –40°C 15 0.25 12 9 0 6 –0.25 3 0 –0.50 –3 AVERAGE OF 3 SAMPLES AT –0.75 EACH TEMPERATURE –6 –9 –1.00 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE GAIN SELECT CODE Figure 22. Gain vs. Gain Select Code for Three Samples for the Figure 25. Gain Error vs. Gain Select Code at Three Temperatures for the VGA/Preamplifier at Three Frequencies—See Figure 57 VGA/Preamplifier—See Figure 57 4.00 50 40 3.75 T = +105°C 30 T = +25°C 3.50 T = –40°C AVERAGE OF 3 SAMPLES 20 f = 1MHz, 10MHz, AND 40MHz 3.25 10 3.00 0 –10 2.75 –20 2.50 –30 AVERAGE OF 3 SAMPLES AT 2.25 –40 EACH TEMPERATURE 2.00 –50 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE GAIN SELECT CODE Figure 23. Gain Step vs. Gain Select Code for Three Samples for the Figure 26. Output Offset Voltage vs. Gain Select Code at Three Temperatures VGA/Preamplifier at Three Frequencies—See Figure 57 for the VGA/Preamplifier—See Figure 58 Rev. A | Page 11 of 32 OUTPUT VOLTAGE (V) GAIN STEP (dB) GAIN (dB) 07192-022 07192-023 07192-021 GAIN ERROR (dB) ABSOLUTE GAIN ERROR (dB) OFFSET VOLTAGE (mV) 07192-026 07192-025 07192-024 AD8260 27 10 1011 24 1010 21 1001 8 18 1000 15 0111 12 6 0110 9 0101 6 0100 4 3 0011 0 0010 –3 2 0001 –6 –9 –12 0 100k 1M 10M 100M 200M 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 27. Frequency Response for a Supply Voltage (V ) of 3.3 V for all Codes Figure 30. Group Delay vs. Frequency for the VGA/Preamplifier S of the VGA/Preamplifier—See Figure 59 See Figure 59 27 100 1011 24 1010 21 1001 18 1000 15 10 0111 12 0110 9 0101 VGAN 6 0100 VGAP 3 0011 1 0 0010 –3 0001 –6 –9 V = 5V S –12 0.1 100k 1M 10M 100M 200M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 28. Frequency Response for a Supply Voltage (V ) of 5 V for All Codes Figure 31. Output Resistance vs. Frequency for the VGA/Preamplifier S for the VGA/Preamplifier—See Figure 59 See Figure 60 27 50 1011 24 1010 21 1001 18 40 1000 15 0111 12 0110 9 30 0101 6 0100 3 0011 0 0010 20 –3 0001 –6 –9 V = ±5V S –12 10 100k 1M 10M 100M 200M 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE FREQUENCY (Hz) Figure 29. Frequency Response for a Dual Supply (V ) = ±5 V for All Codes for Figure 32. Output-Referred Noise vs. Gain Select Code for the S the VGA/Preamplifier—See Figure 59 VGA/Preamplifier—See Figure 61 Rev. A | Page 12 of 32 DIFFERENTIAL GAIN (dB) DIFFERENTIAL GAIN (dB) DIFFERENTIAL GAIN (dB) 07192-029 07192-028 07192-027 OUTPUT RESISTANCE (Ω) GROUP DELAY (ns) OUTPUT-REFERRED NOISE (nV/√Hz) 07192-032 07192-030 07192-031 AD8260 100 30 V = 1V p-p OUT GAIN CODE = 0110 GAIN CODE = 1011 40 50 60 70 HD2 HD3 80 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 100k 1M 10M 50M FREQUENCY (Hz) LOAD RESISTANCE (Ω) Figure 33. Output-Referred Noise vs. Frequency for the VGA/Preamplifier at Figure 36. Harmonic Distortion (HD2, HD3) vs. Load Resistance for the Maximum Gain—See Figure 61 VGA/Preamplifier—See Figure 62 100 –30 V = 1V p-p OUT GAIN CODE = 0110 –40 –50 10 –60 HD2 HD3 –70 1 –80 50 0 10 20 30 40 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 LOAD CAPACITANCE (pF) GAIN SELECT CODE Figure 34. Input-Referred Noise vs. Gain Select Code for the VGA/Preamplifier Figure 37. Harmonic Distortion (HD2, HD3) vs. Load Capacitance for the See Figure 61 VGA/Preamplifier—See Figure 62 10 0 HD2, f = 1MHz C GAIN CODE = 1011 HD3, f = 1MHz C –20 HD2, f = 10MHz C V = 1V p-p HD3, f = 10MHz OUT C –40 MEASUREMENT OF –60 DISTORTION IS LIMITED BY THE MAXIMUM DYNAMIC –80 INPUT RANGE OF THE PREAMPLIFIER –100 –120 1 0101 0110 0111 1000 1001 1010 1011 100k 1M 10M 50M FREQUENCY (Hz) GAIN SELECT CODE Figure 35. Short-Circuit Input Noise vs. Frequency for the VGA/Preamplifier Figure 38. Harmonic Distortion (HD2, HD3) vs. Gain Select Code at 1 MHz See Figure 61 and 10 MHz for the VGA/Preamplifier—See Figure 62 Rev. A | Page 13 of 32 SHORT-CIRCUIT INPUT-REFERRED NOISE OUTPUT-REFERRED NOISE (nV/√Hz) (nV/√Hz) INPUT-REFERRED NOISE (nV/√Hz) 07192-034 07192-033 07192-035 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 07192-038 07192-037 07192-036 AD8260 0 10 GAIN CODE = 1011 IP1dB LIMITED AT LOW GAIN BY THE V = 1V p-p OUT 5 DYNAMIC RANGE OF THE PREAMPLIFIER –20 0 –40 HD2 –5 HD3 –60 –10 –15 –80 –20 1MHz –100 10MHz –25 –120 –30 1M 10M 100M 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 FREQUENCY (Hz) GAIN SELECT CODE Figure 39. Harmonic Distortion (HD2, HD3) vs. Frequency for the Figure 42. Input 1 dB Compression (IP1dB) vs. Gain Select Code at 1 MHz and VGA/Preamplifier—See Figure 62 10 MHz for the VGA/Preamplifier 0 T INPUT –20 2mV/DIV 1 0V V = 1V p-p OUT TONES 1MHz APART –40 EACH TONE 0.5V p-p GAIN CODE = 1011 –60 LOWER UPPER –80 OUTPUT 50mV/DIV M 0V –100 –120 M10.0ns A CH4 180µV 1M 10M 100M CH1 2.00VΩ FREQUENCY (Hz) MATH 5.00mV 10.0ns T 27.2000ns Figure 40. Third-Order Intermodulation Distortion (IMD3) vs. Frequency for Figure 43. Small-Signal Pulse Response for the VGA/Preamplifier the VGA/Preamplifier 60 T INPUT 50 20mV/DIV 3 0V 40 30 20 OUTPUT 500mV/DIV M 0V LOWER UPPER 10 GAIN CODE = 1011 TONES 1MHz APART 0 M10.0ns A CH4 200µV 1M 10M 100M CH3 20.0mVΩ FREQUENCY (Hz) MATH 50.0mV 10.0ns T 27.2000ns Figure 41. OIP3 vs. Frequency for the VGA/Preamplifier Figure 44. Large-Signal Pulse Response for the VGA/Preamplifier Rev. A | Page 14 of 32 OIP3 (dBm) IMD3 (dBc) HARMONIC DISTORTION (dBc) 07192-039 07192-041 07192-040 INPUT IP1dB (dBm) 07192-044 07192-043 07192-042 AD8260 1.5 –10 +SUPPLY VGA/PREAMPLIFIER +SUPPLY HIGH CURRENT DRIVER 1.0 –20 –SUPPLY VGA PREAMPLIFIER V = +3V, +5V, AND ±5V –SUPPLY HIGH CURRENT DRIVER S 0.5 –30 0 –40 –50 –0.5 V = ±3.3V S GAIN CODE = 1011 –60 –1.0 –70 –1.5 –3 –2 –1 0 1 2 3 4 5 6 7 8 100k 1M 5M FREQUENCY (Hz) TIME (ns) Figure 48. PSRR vs. Frequency for Dual Supplies for the High Current Driver Figure 45. Large-Signal Pulse Response for Various Values of Supply Voltage and the VGA/Preamplifier for the VGA/Preamplifier 40 T 35 30 M CH1 AMPL 3.28V 25 1 CH2 AMPL 20 1.20mV 15 MATH AMPL 117mV 10 4 FULLY ENABLED 5 VGA/PREAMPLIFIER ENABLED HIGH CURRENT DRIVER ENABLED 0 CH1 1.00VΩ CH2 20.0mVΩ M200ns A CH1 760mV –55 –35 –15 5 25 45 65 85 105 125 CH2 20.0mVΩ TEMPERATURE (°C) T 595.200ns MATH 100mV 200nV Figure 46. Gain Response for the VGA/Preamplifier, Yellow: Gain Code Select, Figure 49. Quiescent Supply Current vs. Temperature for Three Operating States Red: VGA Differential Output, Blue/Green: VGAP and VGAN 2 80 70 1 60 50 0 40 30 –1 20 10 –2 0 –200 –100 0 100 200 300 400 500 600 700 800 –55 –35 –15 5 25 45 65 85 105 125 TIME (ns) TEMPERATURE (°C) Figure 47. Overdrive Recovery of the VGA/Preamplifier—Gain Code = 1011 Figure 50. Standby Quiescent Supply Current vs. Temperature Rev. A | Page 15 of 32 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07192-045 07192-047 07192-046 STANDBY QUIESCENT SUPPLY CURRENT (µA) QUIESCENT SUPPLY CURRENT (mA) PSRR (dB) 07192-050 07192-049 07192-048 AD8260 TEST CIRCUITS NETWORK ANALYZER OUT 50Ω 50Ω IN AD8260—HIGH CURRENT DRIVER 0.1µF INRN TXFB 50Ω – 0.1µF TXOP 453Ω INRP 5pF + 0.1µF VOCM VMDO Figure 51. Test Circuit for Frequency Response of the High Current Driver SPECTRUM AD8260—HIGH CURRENT DRIVER ANALYZER INRN TXFB 0.1µF – – 0.1µF TXOP IN INRP + 50Ω + 0.1µF VOCM VMDO Figure 52. Test Circuit for Input-Referred and Output-Referred Noise of the High Current Driver +3.3V AD8260—HIGH CURRENT DRIVER NETWORK ANALYZER INRN TXFB WITH S-PARAMETER MODE 0.1µF – TXOP IN INRP + 0.1µF VOCM 50Ω –3.3V Figure 53. Test Circuit for Output Impedance of the High Current Driver LP SPECTRUM AD8260—HIGH CURRENT DRIVER FILTER ANALYZER 0.1µF 1:1 INRN TXFB SIGNAL 50Ω GENERATOR R – LOAD 0.1µF TXOP IN 50Ω 50Ω INRP 50Ω + C LOAD 0.1µF VOCM VMDO Figure 54. Test Circuit for Harmonic Distortion of the High Current Driver Rev. A | Page 16 of 32 07192-152 07192-151 07192-153 07192-154 + – AD8260 SIGNAL GENERATORS AD8260—HIGH CURRENT DRIVER SPECTRUM 50Ω ANALYZER 0.1µF 1kΩ 1:1 INRN TXFB 1kΩ – 0.1µF 453Ω TXOP IN INRP 50Ω + 50Ω 0.1µF VOCM VMDO Figure 55. Test Circuit for IMD3 and OIP3 of the High Current Driver AD8260—HIGH CURRENT DRIVER 0.1µF OSCILLOSCOPE INRN TXFB 50Ω R – LOAD 0.1µF TXOP IN 0.1µF INRP + 50Ω C LOAD VOCM 12.5Ω 50Ω VMDO Figure 56. Test Circuit for Pulse Response of the High Current Driver OSCILLOSCOPE AD8260—VGA/PREAMPLIFIER SIGNAL 0.1µF 453Ω 0.1µF GENERATOR + PREAMP 50Ω 50Ω – 453Ω 0.1µF IN 50Ω 100Ω 100Ω VMDO Figure 57. Test Circuit for Gain Step Size and Error of the VGA/Preamplifier AD8260—VGA/PREAMPLIFIER DMM 0.1µF + PREAMP – 100Ω 100Ω VMDO Figure 58. Test Circuit for Output-Referred Offset Voltage of the VGA/Preamplifier Rev. A | Page 17 of 32 07192-158 07192-156 07192-157 07192-155 AD8260 NETWORK ANALYZER 50Ω IN AD8260—VGA/PREAMPLIFIER 0.1µF 453Ω 0.1µF + PREAMP 50Ω – 453Ω 0.1µF 100Ω 100Ω VMDO Figure 59. Test Circuit for Frequency Response and Group Delay of the VGA/Preamplifier NETWORK ANALYZER WITH S-PARAMETER CAPABILITY 50Ω IN +3.3V AD8260—VGA/ PREAMPLIFIER 0.1µF + PREAMP – 100Ω –3.3V 100Ω Figure 60. Test Circuit for Output Resistance of the VGA/Preamplifier SPECTRUM AD8260—VGA/PREAMPLIFIER ANALYZER 0.1µF AD8129 0.1µF + 0.1µF 1kΩ PREAMP VGA ×10 0.1µF VMDO – 50Ω 1kΩ 100Ω 100Ω VMDO Figure 61. Test Circuit for Input-Referred and Output-Referred Noise Measurements of the VGA/Preamplifier Rev. A | Page 18 of 32 07192-160 07192-159 07192-051 AD8260 SPECTRUM ANALYZER AD8260—VGA/PREAMPLIFIER LP FILTER 0.1µF 475Ω 0.1µF 50Ω 1:1 + IN 50Ω 50Ω PREAMP 0.1µF 475Ω – SIGNAL GENERATOR 100Ω 100Ω VMDO Figure 62. Test Circuit for Harmonic Distortion Measurements of the VGA/Preamplifier AD8260—VGA/PREAMPLIFIER OSCILLOSCOPE 0.1µF + PREAMP 50Ω – 50Ω IN 50Ω 100Ω 100Ω VMDO Figure 63. Test Circuit for IP1dB, Pulse Response, Overdrive Recovery, and Gain Response of the VGA/Preamplifier Rev. A | Page 19 of 32 07192-163 07192-052 AD8260 THEORY OF OPERATION 4-bit parallel interface. Figure 64 shows the circuit block OVERVIEW diagram and basic application connections, and illustrates the The AD8260 is a self-contained transceiver intended for analog envisioned external DAC, ADC, and power-line bus interface communications using a power line as the media. Operating on connections. The diagram shows the connections for single 3.3 V supplies as low as 3.3 V, it includes a high current driver usable supply operation; if a dual supply is available, the VMID as a transmitter and a low noise digitally programmable variable generator can be shut down and Pin VMDI, Pin VMDO, and gain amplifier (DGA), usable as a receiver (see Figure 64). An Pin VOCM need to be grounded. Note that Pin VNCM uncommitted current-feedback high frequency op amp acts as a functions as the negative supply for the bias and VMID cells, preamplifier and interface to the DGA and is user configured plus the logic interfaces, and should always be tied to ground. for gains greater than 6 dB. Combined, the VGA and preamplifier For optimal dynamic range, it is important that the inputs and are usable at high signal levels from dc to 100 MHz, with a outputs to both the driver amplifier and the preamplifier and small-signal −3 dB bandwidth of 230 MHz. To implement a the DGA output amplifier be ac-coupled in a single-supply high current-output VGA, the VGA output can be connected application. In Figure 64, the DAC and ADC are presumed to to the driver-amplifier differential input. operate on a 1.8 V or 3.3 V supply with a corresponding limited The small-signal −3 dB bandwidth of the driver amplifier is output and input swing. The DAC outputs are currents that 195 MHz and the large-signal bandwidth is >115 MHz, even point down and generate a voltage in the 50 Ω resistors that are when driving a 50 Ω load. connected to ground. The maximum voltage with a peak DAC The device is fabricated on the Analog Devices, Inc., high speed output current of 15 mA is 0.75 V; if a DAC with a 20 mA peak (eXtra Fast Complementary Bipolar) XFCB process. The pream- current is used, then the maximum voltage is 1 V per side for a plifier and DGA feature low dc offset voltage, and a nominal differential input signal of 2 V p-p. gain range of −6 dB to +24 dB, a 30 dB gain span, and a differential The driver amplifier supports a 3 V p-p output swing on a output for ADC driving. The power consumption is 93 mW 3.3 V supply. Because of its gain of 1.5, the maximum input with a single 3.3 V supply. The supply current is typically about swing is 2 V p-p. The corresponding maximum output swing for 28 mA when all circuits in the device are active. During normal the DGA is 2.4 V p-p differential; the input to the preamplifier usage, either the driver amplifier is on or the preamplifier and can be a maximum of 0.6 V p-p. DGA are on and, therefore, the supply current in general is less than 28 mA. The gain of the AD8260 VGA is programmed via a Rev. A | Page 20 of 32 AD8260 1V MAX WITH 1.8V OR 3.3V 200mA pk 20mA DAC 50Ω OPTIONAL USER SELECTED C REDUCES HF PEAKING FB 50Ω 0.1µF 0.1µF WITH CAPACITIVE LOADING C FB VOCM INPP 32 31 30 29 28 27 26 25 1.5kΩ 1kΩ 1kΩ 1.5kΩ OPTIONAL CLAMP DIODES AND SNUBBING RESISTORS VMDO TXOP 1 24 + – 0.1µF GM ×1 TXEN TXOP 0.1µF 2 23 0V, 1.8V/3.3V VMDI VPOS 0.1µF AD8260 22 3 0.1µF VMID VNCM VPOS 4 21 POWERLINE BIAS CABLE, ETC. VPSB VPSR 3.3V 5 20 3.3V 0V, 1.8V/3.3V ENBL VMDO 1.8V OR 3.3V 6 19 LOW-PASS ATTENUATOR 0.1µF AA FILTER 0.1µF VGAP PRAI 7 18 INP ADC RFB1 GM STAGES FS INPUT 0.1µF 100Ω VGAN FDBK 2V p-p 8 17 INN LOGIC RFB2 100Ω 9 10 11 12 13 14 15 16 3.3V Figure 64. Block Diagram and Basic Application Connections For optimum distortion, the input drive must be controlled HIGH CURRENT DRIVER AMPLIFIER such that the output swing is well within saturation levels The high current driver amplifier can deliver very large output established by the supply rail. The output swing can be reduced currents suitable for driving complex impedances, such as a by using load resistors with values less than 50 Ω or by reducing power line, a 50 Ω line, or a coaxial cable. The input of the the amplifier gain by connecting external resistors in parallel amplifier is fully differential and intended to be driven by a with the internal 1 kΩ and 1.5 kΩ resistors between Pin 27, differential current-output DAC, as shown in Figure 64. The Pin 28, and Pin 29, and between Pin 30, Pin 31, and Pin 32. differential input signal is amplified by 1.5× and produces a Coincidently, noise is reduced because the gain setting resistors 2.25 V p-p single-ended output signal from a 1.5 V p-p input are the primary noise sources of the high current driver amplifier. signal. A DAC with 15 mA maximum output current into a The output-referred noise is 14 nV/√Hz, of which 11 nV/√Hz is 50 Ω load provides 1.5 V p-p of input voltage and results in due to the gain setting resistors. Matching of the gain setting 2.25 V p-p at the output. A DAC whose output is 20 mA produces resistors is important for good common-mode rejection and the an output swing of 3 V p-p (neglecting a small gain error when accuracy of the differential gain. If external resistors are used, driving the parallel combination of the 50 Ω load-resistor and the their accuracy should be at least ±1%. How low the resistor internal 1 kΩ gain resistor of the AD8260). values can be is primarily determined by the quality of the ac For a 3.3 V supply rail, the maximum limit of the output voltage ground at Pin VOCM; as the gain setting resistors decrease in is 3 V p-p and distorts severely if exceeded. The recommended value, the dynamic current increases, and the quality of the output for optimum distortion is 2 V p-p for a 3.3 V supply. decoupling capacitors needs to increase correspondingly. Correspondingly, larger output swings are accommodated for higher supply voltages such as +5 V or ±5 V. Rev. A | Page 21 of 32 VNGR VPSR GNS3 INRP GNS2 INRN GNS1 INPN GNS0 TXFB PRAO VNEG VNGR VNEG 07192-053 AD8260 determine the −3 dB bandwidth of the amplifier. Smaller PRECAUTIONS TO BE OBSERVED DURING HALF- resistor values may compromise preamplifier stability. DUPLEX OPERATION Because the AD8260 is internally dc-coupled, larger preamplifier During receive, when the high current driver-amplifier is gains increase its offset voltage. The circuit contains an internal disabled, its gain setting resistors provide a signal path from bias resistor and some offset compensation; however, if a lower input to output. To prevent inadvertent DAC signals from being value of offset voltage is required, it can be compensated by transmitted while receiving via the preamplifier and DGA, the connecting a resistor between the FDBK pin and the supply DAC in Figure 64 must have no output signal. voltage. If the offset is negative, the resistor value connects to During transmit, the preamplifier and VGA should be disabled the negative supply; otherwise, it connects to the positive supply. through any of the nongain-setting codes (see Table 4). For larger gains, the overall noise is reduced if a low value of VMID BUFFER R is selected. For values of R = 20 Ω and R = 301 Ω, the FB1 FB1 FB2 The VMID buffer is a dc bias source that generates the voltage preamplifier gain is 16× (24.1 dB) and the input-referred noise on Pin 1 and Pin 19, VMDO. Node VMDO cannot accommodate is about 1.5 nV/√Hz. For this value of gain, the overall gain range large dynamic currents and requires excellent ac decoupling to increases by 18 dB so that the absolute gain range is 12 dB to 42 dB. ground. A high quality 0.1μF capacitor located as close as PREAMPLIFIER NOISE possible to Pin 1 and Pin 19 (see Figure 64) is normally sufficient The total input-referred voltage and current noise of the positive to decouple the high values of current from Node VMDO. input of the preamplifier is about 2.4 nV/√Hz and 5 pA/√Hz, When operating with dual power supplies, the buffer is disabled respectively. The DGA output referred noise is about 25 nV/√Hz by connecting Pin VMDI, Pin VOCM, and Pin VMDO to ground. at low gains and 39 nV/√Hz at the highest gain. The 25 nV/√Hz Because the logic decoder in the DGA (GNSx inputs) requires divided by the DGA fixed gain of 8× results in 3.12 nV/√Hz 3.3 V of headroom, the positive supply rails must be 3.3 V or referred to the DGA input. Note that this value includes the greater whether single-ended or dual. If a dual supply is used, noise of the DGA gain setting resistors as well. If this voltage is the negative rails are the same magnitude (opposite polarity) divided by the preamplifier gain of 2×, the DGA noise referred as the positive, that is, −3.3 V when VPOS, VPSB, and VPSR all the way to the preamplifier input is about 1.56 nV/√Hz. From are +3.3 V. this, it can be determined that the preamplifier, including the PREAMPLIFIER 100 Ω gain setting resistors, contributes about 1.8 nV/√Hz. The The AD8260 includes an uncommitted current feedback op two 100 Ω resistors each contribute 1.29 nV/√Hz at the output amp to buffer the resistive attenuator of the DGA. External of the preamplifier and 0.9 nV/√Hz referred to the input. With resistors are used to adjust the gain. The preamplifier is the gain resistor noise subtracted, the preamplifier noise alone characterized with a noninverting gain of 6 dB (2×) and both is about 1.6 nV/√Hz. gain resistor values of 100 Ω. The preamplifier gain can be Equation 1 shows the calculation that determines the output- increased using different gain ratios of R and R , trading off FB1 FB2 referred noise at maximum gain (24 dB or 16×). bandwidth and offset voltage. The sum of the values of R and FB1 R should be ≥200 Ω to maintain low distortion. R should FB2 FB2 be ≥100 Ω because it and an internal compensation capacitor R 2 2 2 2 2 2 FB2 e = (e ×A) + (e ×A ) + (i ×R ) + (e × ×A ) + (e ×A ) + (e ×A ) (1) n−out t t n,RFB1 n,RFB2 n,RS n,PrA n,PrA S VGA VGA n,VGA VGA R FB1 where: A is the total gain from preamplifier input to the VGA output. t e , is the noise of the source resistance. n RS e is the input-referred voltage noise of the preamplifier. n,PrA i is the current noise of the preamplifier at the PRAI pin. n,PrA R is the source resistance. S A is the VGA gain. VGA e is the voltage noise of R . n,RFB1 FB1 e is the voltage noise of R . n,RFB2 FB2 e is the input-referred voltage noise of DGA (low gain output-referred noise divided by a fixed gain of 8×). n,VGA Rev. A | Page 22 of 32 AD8260 Assuming R = 0, R = R = 100 Ω, A = 16, and A = 8, the S FB1 FB2 t VGA Table 4. Gain Control Logic Table noise simplifies to D3 D2 D1 D0 Function Comments 2 2 2 0 0 0 0 Disable PrA and DGA powered down e = (1.6×16) + 2 (1.29×8) + (3.12×8) = n−out (2) 0 0 0 1 −6 The numbers in the function 39 nV / Hz column are composite gain 0 0 1 0 −3 values in dB for the correspond- 0 0 1 1 0 Taking this result and dividing by 16 gives the total input-referred ing code, when the preamplifier 0 1 0 0 3 gain is 6 dB. For other values of noise with a short-circuited input as 2.4 nV/√Hz. When the 0 1 0 1 6 preamplifier gain, the gain is preamplifier is used in the inverting configuration with the 0 1 1 0 9 amended accordingly; for same R = R = 100 Ω as in the previous example, then e example, if the preamplifier FB1 FB2 n-out 0 1 1 1 12 gain is 12 dB, the gain values does not change; however, because the gain decreases by 6 dB, 1 0 0 0 15 increase by 6 dB. When using the input-referred noise increases by a factor of 2 to about 1 0 0 1 18 the DGA single ended, the 4.8 nV/√Hz. The reason for this is that the noise gain to the DGA 1 0 1 0 21 composite gain decreases output of all the noise generators stays the same, but the preamp by 6 dB. 1 0 1 1 24 inverting gain is ( −1×) compared to the (+2×) in the noninverting 1 1 0 0 Disable PrA and DGA powered down configuration. This doubles the input-referred noise. 1 1 0 1 Disable PrA and DGA powered down 1 1 1 0 Disable PrA and DGA powered down DGA 1 1 1 1 Disable PrA and DGA powered down Referring to Figure 64, the signal path consists of a 30 dB OUTPUT STAGE programmable attenuator followed by a fixed gain amplifier of The gain of the voltage feedback output stage is fixed at 18 dB and 18 dB for a total DGA gain range of −12 dB to +18 dB. With the inaccessible to the user. Otherwise, it is similar to the preamplifier preamplifier configured for a gain of 6 dB, the composite gain in speed and bandwidth. The overall −3 dB bandwidth of the range is −6 dB to +24 dB from single-ended preamplifier input preamplifier and DGA combination is 230 MHz. to differential DGA output. The DGA plus preamplifier with 6 dB of gain implements the ATTENUATOR following gain law: The input resistance of the VGA attenuator is nominally 265 Ω. Assuming that the default preamplifier feedback network of R dB FB1   Gain(dB)= 3.01 ×Code +ICPT(dB)   and R is 200 Ω, the effective preamplifier load is about 114 Ω. FB2 Code   The attenuator is composed of ten 3.01 dB sections for a total where: attenuation span of −30.10 dB. Following the attenuator is a ICPT is the nominal intercept, −9 dB. fixed gain amplifier with 18 dB (8×) gain. Because of this relatively Code values are decimal from 1 to 11. low gain, the output offset is less than 20 mV over the operating The ICPT increases as the gain of the preamplifier is increased. temperature range; the offset is largest at maximum gain because For example, if the gain of the preamplifier is increased by 6 dB, the preamplifier offset is amplified. The VMDO pin defines the then ICPT increases to −3 dB. common-mode reference for the input and output. The voltage at VMID is half the supply voltage for single-supply operation GAIN CONTROL and 0 V when dual supplies are used. To change the gain, the desired four bits are programmed on Pin GNS0 to Pin GNS3, where GNS0 is the LSB (D0) and GNS3 is the MSB (D3). The states of Decimal 0 and Decimal 12 through Decimal 15 disable the preamplifier (PrA) and DGA (see Table 4). Rev. A | Page 23 of 32 AD8260 active first to listen to any signals, and the driver needs to SINGLE-SUPPLY OPERATION AND AC COUPLING be off. Therefore, the gain code should be set to 0001 (−6 dB When operating the AD8260 from a single supply, there are two of gain) first and then the gain adjusted as needed. Note bias options for VMDO. that any code besides 1 to 11 (binary) disables the receive • Use an external low impedance midpoint reference at section (see Table 4). During receive, it is also important Pin VMDO and pull VMDI to VNCM to shut down the that the DAC that provides the signal for the high current VMID buffer. driver be disabled to avoid interfering with the received signal. • Use the internal VMID buffer as shown in Figure 64. 3. After receive, presumably data needs to be transmitted via the high current driver amplifier. At this point, the DAC In both cases, decoupling capacitors are needed on Pin VMDO should still be off. Pull Pin TXEN high and allow the high to absorb the dynamic currents. current driver to settle. Enable the DAC. Although the During single-supply operation, the preamplifier input is normally preamplifier and DGA can remain enabled during the ac-coupled. An internal bias resistor (nominally 1 k Ω) connected previous sequence, there may be significant preamplifier between PRAI and VMDO provides bias to the preamplifier overdrive, and it is best that the receiver be disabled while input pin. A 50 Ω resistor connected between Pin PRAI and transmitting. Pin VMDO, in parallel with the internal 1 kΩ, serves as a termina- 4. Pull Pin ENBL low to disable the chip. To achieve the tion resistor and at the same time reduces the offset; the result specified sleep current of 35 μA, all logic pins must be is a composite value of about 48 Ω. The VGA input is biased pulled low as well. through the attenuator network and the voltage at Pin VMDO. LOGIC INTERFACES When active, the VMID buffer provides the needed bias currents. When the buffer is disabled, an external voltage is required at All logic pins use the same interfaces and, therefore, have the Pin VMDO to provide the bias currents. For example, for a single same behavior and thresholds. The interface contains a Schmitt 5 V application, a reference such as the ADR43 and a stable op trigger type input with a threshold at about 1.1 V and a hystere- amp provide an adequate 2.5 V VMDO source. sis of ±0.2 V. POWER-UP/POWER-DOWN SEQUENCE Therefore, the logic low is between ground and 0.8 V, and logic high is from 1.4 V to VPOS. Because the threshold is so low, the For glitch-free power-up operation, the following power-up and logic interfaces can be driven directly from 1.8 V or 3.3 V CMOS. power-down sequence is recommended: The input bias current is nominally 0.2 μA when the applied 1. Enable the bias by pulling the ENBL pin high. Maintain voltage is 3.3 V and 18 nA when grounded. GNS0 to GNS3 and TXEN at ground. 2. It is assumed that after the part wakes up from sleep mode, the receive section (preamplifier and DGA) needs to be Rev. A | Page 24 of 32 AD8260 APPLICATIONS INFORMATION CONTROLLER The AD8260 is ideally suited for compact applications requiring MICROPROCESSOR + high frequency and large current drive of complex modulation MODULATOR products. Because the driver is capable of providing up to 300 mA (using a 3.3 V supply rail) to very low impedance loads, undefined DAC ADC network impedances are of little consequence. Such applications can include, but are not limited to, local power line wiring AD8260 found in homes or in automobiles, or low impedance complex filters used in communications. Pulse response performance with loading effects are illustrated by various curves in the COUPLING Typical Performance Characteristics section. Figure 65 is an application block diagram showing AD8260 LOCAL POWER WIRING devices configured as transceivers in a small local network. COUPLING COUPLING In this figure, consider a small security system consisting of a master controller and four satellite cameras. For example, the master can be a processor-controlled switch that routes data to and from local satellite cameras. The cameras video signals are AD8260 AD8260 modulated for transmission over an existing power system such SATELLITE CAMERAS as the wiring found in homes or small businesses. Using the DAC ADC DAC ADC existing power network in this way eliminates the need to install additional cabling, thereby saving cost. Portability is also MICROPROCESSOR + MICROPROCESSOR + MODULATOR MODULATOR achieved because the system can be moved to other locations should the need arise, simply by unplugging a satellite and CAMERA moving it elsewhere. The AD8260 transceivers perform the CAMERA same function at the master and slave locations; a high frequency Figure 65. AD8260 Transceiver Application current-output DAC converts digital-to-analog data for the Figure 66 shows the AD8260 as a low distortion, high power high current driver for transmission over a low impedance load. driver. The VGA and high current driver are combined by The input of the VGA/preamplifier connects to the same load, simply connecting the differential output of the VGA directly to functioning as the receiver. In such a system, multiple AD8260 the input of the driver. devices are connected to form a network, much like a LAN, AD8260 except using the power-line wiring in a home or automobile in VGA/ HIGH CURRENT COMPLEX LOW lieu of a CAT-5 cable, for example. PREAMPLIFIER DRIVER Z FILTER ≥10Ω DAC Figure 66. AD8260 Used as a VGA Driving a Low Impedance Load Rev. A | Page 25 of 32 07192-066 07192-065 AD8260 EVALUATION BOARD Analog Devices provides evaluation boards to customers as a PCB artwork for all conductor and silkscreen layers is shown in support service so that the circuit designer can become familiar Figure 71 through Figure 76. A description of a typical test setup is with the device in the most efficient way possible. The AD8260 explained in the Connecting the Evaluation Board section. The evaluation board provides a fast, easy, and convenient means to artwork can be used as a guide in circuit layout and parts assess the performance of the AD8260 before going through the placement. This is particularly useful for multiple function inconvenience and expense of design and layout of a custom circuits with many pins, requiring multiple passive components. board. The board is shipped fully assembled and tested and The board is shipped with the device fully enabled. Moving the provides basic functionality as shipped. Connectors enable the ENABLE jumper to its upper position on the board disables the user to connect standard types of lab test equipment without device. When the TX_EN jumper is in its upper position, the having to wait for the rest of the design to be completed. Figure 67 high current driver is disabled. shows a digital image of the top view and Figure 70 shows the schematic. Figure 67. Top View of the AD8260-EVALZ Rev. A | Page 26 of 32 07192-067 AD8260 DEFAULT GAIN SETTING CONNECTING THE EVALUATION BOARD COMPONENTS ARE SHOWN IN BLACK, OPTIONAL COMPONENTS Figure 69 shows an evaluation board with typical test connec- ARE SHOWN IN GRAY. tions. The various pieces of test equipment are representative, VMDO 1 and equivalent equipment may be substituted. VOCM 1.5kΩ 32 The AD8260 includes two amplifier channels: a high current INPP 31 driver and a digitally controlled VGA that is independently enabled. The slide switch labeled ENABLE functions as the chip 1kΩ INRP TXOP 30 + enable, the GNSx switches permit the preamplifier/VGA to 24 operate, and the TX_EN switch enables the high current driver. TXOP 23 – These independent enable functions permit the device to 1kΩ 1.5kΩ INRN TXFB operate in a send or listen mode when used as a transceiver. 29 27 The high current driver features differential inputs and is INPN 28 optimally driven by a differential signal source. The input signal is monitored at the 2-pin header labeled INP, using a differential probe such as the Tektronix P6247 (not shown). Two 49.9 Ω resistors are provided (R12 and R13), either for terminating C COMP coaxial cables from a signal generator or to be used as load Figure 68. Gain-Setting Resistors of the High Current Driver resistors for a DAC with a current source output. An optional external load resistor is connected at the SMA connector TXOP The VGA/preamplifier is completely independent of the high and the output signal monitored at the 2-pin header labeled current driver and features a single-ended input at the SMA TXOP_1. connector PRAI. The input signal is monitored at the header As shipped, the gain of the high current driver is 1.5×, its default VPRE_IN. The output is monitored at the 2-pin header value. The internal differential network with resistor values of VGA_OUT. 1 kΩ and 1.5 kΩ establishes this value. Other values of gain are The gain bits, GNS0 through GNS3, must be set before the realized by connecting external resistors to the device at Pin 23, VGA/preamplifier can operate. Table 4 lists the binary gain Pin 24, Pin 27, Pin 28, and Pin 31, as shown in Figure 68, which codes. The board is shipped with both enables (ENBL and shows the internal structure for the default gain and how the TXEN) engaged and the gain-code switches adjusted for gain can be modified. maximum DGA gain (1011). Resistor R5 and Resistor R6 establish the preamplifier gain and are 100 Ω as shipped for a noninverting preamplifier gain of 2×. Rev. A | Page 27 of 32 07192-068 AD8260 PULSE GENERATOR WITH DIFFERENTIAL OUTPUT + 5 V HIGH - 5 V CURRENT DRIVER INPUTS VGA OUTPUT HIGH (TO SCOPE) CURRENT DRIVER R OUTPUT LOAD SINGLE- ENDED VGA INPUT POWER SUPPLY FUNCTION GENERATOR FOR VGA INPUT Figure 69. Typical Evaluation Board Connections Rev. A | Page 28 of 32 07192-057 AD8260 +VS GND –VS INRP INRN + R12 R13 C8 C9 C3 C4 49.9Ω 49.9Ω 0.1µF 0.1µF 10µF 10µF + +VS –VS C19 C18 GND1 GND2 GND3 GND4 GND5 GND6 0.1µF 0.1µF INR INP L7 120nH R18 FB DNI –VS R17 R15 C1 C2 DNI DNI 0.1µF 0.1µF R14 DNI C17 R7 R9 0.1µF TXOP 0Ω 0Ω R16 DNI R21 0Ω TXOP_1 C14 VMDO 0.1µF 32 31 30 29 28 27 26 25 VOCM VNEG VPSB TXEN 1 24 L6 VMDO TXOP 120nH EN 2 +VS 23 FB TXEN TXOP TX_EN VMDI 3 DIS C6 C5 22 VMDI VPOS L5 0.1µF 0.1µF C13 120nH L1 4 21 0.1µF FB VPSB 120nH VNCM U1 VPOS FB 5 C7 VPS AD8260 20 VPSB VPSR 0.1µF C15 ENBL 0.1µF 6 19 C11 VMDO EN ENBL VPRE_IN PRAI 0.1µF ENABLE 7 18 VGAP PRAI DIS R10 8 17 C21 C23 FDBK VGAN R6 R1 49.9Ω 0.1µF VGAP 0.1µF 100Ω 453Ω VNGR VNGR C12 9 10 11 12 13 14 15 16 R5 R11 VPRE_OUT C10 0.1µF VGA _ OUT 100Ω R2 453Ω 0.1µF 453Ω PRAO R19 0Ω VGAN GNS0 H L2 C20 L R20 120nH 0.1µF R4 R3 0Ω GNS1 FB DNI DNI –VS C16 L3 L4 0.1µF GNS2 120nH 120nH FB FB +VS GNS3 –VS C22 0.1µF Figure 70. AD8260 Evaluation Board—Schematic Diagram Rev. A | Page 29 of 32 INPP VPSR INRP GNS3 INRN GNS2 INPN GNS1 TXFB GNS0 VNEG PRAO 07192-070 AD8260 Figure 71. AD8260-EVALZ Component Side Assembly Figure 73. AD8260-EVALZ Secondary Side Copper Figure 72. AD8260-EVALZ Component Side Copper Figure 74. AD8260-EVALZ Power Plane Rev. A | Page 30 of 32 07192-060 07192-071 07192-062 07192-061 AD8260 Figure 75. AD8260-EVALZ Ground Plane Figure 76. Component Side Silkscreen Rev. A | Page 31 of 32 07192-063 07192-064 AD8260 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 0.50 PIN 1 TOP 2.85 INDICATOR BSC EXPOSED 4.75 VIEW 2.70 SQ PAD BSC SQ (BOTTOM VIEW) 2.55 0.50 17 0.40 8 16 9 0.30 0.20 MIN 3.50 REF 0.80 MAX 1.00 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.85 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 THE PIN CONFIGURATION AND 0.02 NOM FUNCTION DESCRIPTIONS 0.30 SEATING SECTION OF THIS DATA SHEET. COPLANARITY 0.20 REF PLANE 0.25 0.08 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 77. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Package Description Package Option AD8260ACPZ-R7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 AD8260ACPZ-RL −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 AD8260ACPZ-WP −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 AD8260-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07192-0-2/11(A) Rev. A | Page 32 of 32 032807-A