ANALOG DEVICES AD8253

10 MHz, 20 V/μs, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier AD8253 FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR A1 A0 Small package: 10-lead MSOP 2 6 5 4 Programmable gains: 1, 10, 100, 1000 LOGIC Digital or pin-programmable gain setting –IN 1 Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 7 OUT Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.2 μV/°C (maximum), G = 1000 Excellent ac performance +IN 10 Fast settling time: 780 ns to 0.001% (maximum) AD8253 High slew rate: 20 V/μs (minimum) 8 3 9 Low distortion: −110 dB THD at 1 kHz,10 V swing +V –V REF S S High CMRR over frequency: 100 dB to 20 kHz (minimum) Figure 1. Low noise: 10 nV/√Hz, G = 1000 (maximum) 80 Low power: 4 mA 70 APPLICATIONS G = 1000 60 Data acquisition 50 Biomedical analysis G = 100 40 Test and measurement 30 GENERAL DESCRIPTION G = 10 20 The AD8253 is an instrumentation amplifier with digitally 10 programmable gains that has gigaohm (GΩ) input impedance, G = 1 0 low output noise, and low distortion, making it suitable for interfacing with sensors and driving high sample rate analog-to- –10 digital converters (ADCs). –20 1k 10k 100k 1M 10M 100M It has a high bandwidth of 10 MHz, low THD of −110 dB, and FREQUENCY (Hz) fast settling time of 780 ns (maximum) to 0.001%. Offset drift and Figure 2. Gain vs. Frequency gain drift are guaranteed to 1.2 μV/°C and 10 ppm/°C, respectively, Table 1. Instrumentation Amplifiers by Category for G = 1000. In addition to its wide input common voltage range, General Zero Mil Low High Speed it boasts a high common-mode rejection of 100 dB at G = 1000 Purpose Drift Grade Power PGA from dc to 20 kHz. The combination of precision dc performance 1 1 1 AD8220 AD8231 AD620 AD627 AD8250 coupled with high speed capabilities makes the AD8253 an 1 1 AD8221 AD8553 AD621 AD623 AD8251 excellent candidate for data acquisition. Furthermore, this 1 1 AD8222 AD8555 AD524 AD8223 AD8253 monolithic solution simplifies design and manufacturing and 1 1 AD8224 AD8556 AD526 boosts performance of instrumentation by maintaining a tight 1 AD8228 AD8557 AD624 match of internal resistors and amplifiers. 1 Rail-to-rail output. The AD8253 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see Figure 1 The AD8253 is available in a 10-lead MSOP package and is for the functional block diagram). A 2-bit word sent via a bus specified over the −40°C to +85°C temperature range, making it WR can be latched using the input. An alternative is to use an excellent solution for applications where size and packing density are important considerations. transparent gain mode, where the state of logic levels at the gain port determines the gain. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 06983-001 006983-023 AD8253 TABLE OF CONTENTS Features .............................................................................................. 1  Power Supply Regulation and Bypassing ................................ 18  Applications ....................................................................................... 1  Input Bias Current Return Path ............................................... 18  General Description ......................................................................... 1  Input Protection ......................................................................... 18  Functional Block Diagram .............................................................. 1  Reference Terminal .................................................................... 19  Revision History ............................................................................... 2  Common-Mode Input Voltage Range ..................................... 19  Specif ica t ions ..................................................................................... 3  Layout .......................................................................................... 19  Timing Diagram ........................................................................... 5  RF Interference ........................................................................... 19  Absolute Maximum Ratings ............................................................ 6  Driving an Analog-to-Digital Converter ................................ 20  Maximum Power Dissipation ..................................................... 6  Applications Information .............................................................. 21  ESD Caution .................................................................................. 6  Differential Output .................................................................... 21  Pin Configuration and Function Descriptions ............................. 7  Setting Gains with a Microcontroller ...................................... 21  Typical Performance Characteristics ............................................. 8  Data Acquisition ......................................................................... 22  Theory of Operation ...................................................................... 16  Outline Dimensions ....................................................................... 23  Gain Selection ............................................................................. 16  Ordering Guide .......................................................................... 23  REVISION HISTORY 8/08—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 23 7/08—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8253 SPECIFICATIONS +VS = +15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 100 dB G = 10 96 120 dB G = 100 100 120 dB G = 1000 100 120 dB 1 CMRR to 20 kHz +IN = −IN = −10 V to +10 V G = 1 80 dB G = 10 96 dB G = 100 100 dB G = 1000 100 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 45 nV/√Hz G = 10 12 nV/√Hz G = 100 11 nV/√Hz G = 1000 10 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 10 1 μV p-p G = 100 0.5 μV p-p G = 1000 0.5 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 10, 100, 1000 ±150 + 900/G μV Over Temperature T = −40°C to +85°C ±210 + 900/G μV Average TC T = −40°C to +85°C ±1.2 + 5/G μV/°C Offset Referred to the Input vs. Supply (PSR) V = ±5 V to ±15 V ±5 + 25/G μV/V S INPUT CURRENT Input Bias Current 5 50 nA 2 Over Temperature T = −40°C to +85°C 40 60 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 40 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small-Signal −3 dB Bandwidth G = 1 10 MHz G = 10 4 MHz G = 100 550 kHz G = 1000 60 kHz Settling Time 0.01% ΔOUT = 10 V step G = 1 700 ns G = 10 680 ns G = 100 1.5 μs G = 1000 14 μs Rev. A | Page 3 of 24 AD8253 Parameter Conditions Min Typ Max Unit Settling Time 0.001% ΔOUT = 10 V step G = 1 780 ns G = 10 880 ns G =100 1.8 μs G = 1000 1.8 μs Slew Rate G = 1 20 V/μs G = 10 20 V/μs G = 100 12 V/μs G = 1000 2 V/μs Total Harmonic Distortion + Noise f = 1 kHz, R = 10 kΩ, ±10 V, −110 dB L G = 1, 10 Hz to 22 kHz band- pass filter GAIN Gain Range G = 1, 10, 100, 1000 1 1000 V/V Gain Error OUT = ±10 V G = 1 0.03 % G = 10, 100, 1000 0.04 % Gain Nonlinearity OUT = −10 V to +10 V G = 1 R = 10 kΩ, 2 kΩ, 600 Ω 5 ppm L G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 3 ppm G = 100 RL = 10 kΩ, 2 kΩ, 600 Ω 18 ppm G = 1000 RL = 10 kΩ, 2 kΩ, 600 Ω 110 ppm Gain vs. Temperature All gains 3 10 ppm/°C INPUT Input Impedance Differential 4||1.25 GΩ||pF Common Mode 1||5 GΩ||pF Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1 +VS − 1.5 V 3 Over Temperature T = −40°C to +85°C −V + 1.2 +V − 1.7 V S S OUTPUT Output Swing −13.7 +13.6 V 4 Over Temperature T = −40°C to +85°C −13.7 +13.6 V Short-Circuit Current 37 mA REFERENCE INPUT R 20 kΩ IN I +IN, −IN, REF = 0 1 μA IN Voltage Range −V +V V S S Gain to Output 1 ± 0.0001 V/V DIGITAL LOGIC Digital Ground Voltage, DGND Referred to GND −V + 4.25 0 +V − 2.7 V S S Digital Input Voltage Low Referred to GND DGND 1.2 V Digital Input Voltage High Referred to GND 1.5 +VS V Digital Input Current 1 μA 5 Gain Switching Time 325 ns t See Figure 3 timing diagram 15 ns SU tHD 30 ns 20 ns t WR -LOW 15 ns t WR -HIGH Rev. A | Page 4 of 24 AD8253 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range ±5 ±15 V Quiescent Current, +IS 4.6 5.3 mA Quiescent Current, −I 4.5 5.3 mA S Over Temperature T = −40°C to +85°C 6 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 See Figure 20 for CMRR vs. frequency for more information on typical performance over frequency. 2 Input bias current over temperature: minimum at hot and maximum at cold. 3 See Figure 30 for input voltage limit vs. supply voltage and temperature. 4 See Figure 32, Figure 33, and Figure 34 for output voltage swing vs. supply voltage and temperature for various loads. 5 Add time for the output to slew and settle to calculate the total time for a gain change. TIMING DIAGRAM t t WR-HIGH WR-LOW WR t t SU HD A0, A1 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. A | Page 5 of 24 06983-003 AD8253 ABSOLUTE MAXIMUM RATINGS power is the voltage between the supply pins (VS) times the Table 3. quiescent current (IS). Assuming the load (RL) is referenced to Parameter Rating midsupply, the total drive power is VS/2 × IOUT, some of which is Supply Voltage ±17 V dissipated in the package and some of which is dissipated in the Power Dissipation See Figure 4 load (V × I ). OUT OUT 1 Output Short-Circuit Current Indefinite The difference between the total drive power and the load Common-Mode Input Voltage ±VS power is the drive power dissipated in the package. Differential Input Voltage ±VS Digital Logic Inputs ±V S P = Quiescent Power + (Total Drive Power − Load Power) D Storage Temperature Range –65°C to +125°C 2 2 ⎛ ⎞ V V V Operating Temperature Range –40°C to +85°C S OUT OUT ⎜ ⎟ P =() V × I + × – D S S ⎜ ⎟ Lead Temperature (Soldering 10 sec) 300°C 2 R R ⎝ L ⎠ L Junction Temperature 140°C In single-supply operation with RL referenced to −VS, the worst θ (4-Layer JEDEC Standard Board) 112°C/W JA case is VOUT = VS/2. Package Glass Transition Temperature 140°C Airflow increases heat dissipation, effectively reducing θJA. In 1 Assumes the load is referenced to midsupply. addition, more metal directly in contact with the package leads 2 Temperature for specified performance is −40°C to +85°C. For performance from metal traces through holes, ground, and power planes to +125°C, see the Typical Performance Characteristics section. reduces the θ . JA Figure 4 shows the maximum safe power dissipation in the Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress package vs. the ambient temperature on a 4-layer JEDEC rating only; functional operation of the device at these or any standard board. 2.00 other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute 1.75 maximum rating conditions for extended periods may affect 1.50 device reliability. 1.25 MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8253 package is 1.00 limited by the associated rise in junction temperature (TJ) on 0.75 the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140°C, which is the 0.50 glass transition temperature, the plastic changes its properties. 0.25 Even temporarily exceeding this temperature limit can change 0 the stresses that the package exerts on the die, permanently –40 –20 0 20 40 60 80 100 120 shifting the parametric performance of the AD8253. Exceeding AMBIENT TEMPERATURE (°C) a junction temperature of 140°C for an extended period can Figure 4. Maximum Power Dissipation vs. Ambient Temperature result in changes in silicon devices, potentially causing failure. ESD CAUTION The still-air thermal properties of the package and PCB (θ ), JA the ambient temperature (T ), and the total power dissipated in A the package (P ) determine the junction temperature of the die. D The junction temperature is calculated as T = T +(P × θ ) J A D JA The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent Rev. A | Page 6 of 24 MAXIMUM POWER DISSIPATION (W) 06983-004 AD8253 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 10 +IN DGND 2 9 REF AD8253 –V 3 8 +V S TOP VIEW S (Not to Scale) A0 4 7 OUT 5 6 A1 WR Figure 5. 10-Lead MSOP (RM-10) Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −V Negative Supply Terminal. S 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6 WR Write Enable. 7 OUT Output Terminal. 8 +VS Positive Supply Terminal. 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input. Rev. A | Page 7 of 24 06983-005 AD8253 TYPICAL PERFORMANCE CHARACTERISTICS TA @ 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 210 240 180 210 150 180 150 120 120 90 90 60 60 30 30 0 0 –60 –40 –20 0 20 –60 –40 –20 0 20 40 60 CMRR (µV/V) INPUT OFFSET CURRENT (nA) Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current 90 180 80 150 70 60 120 50 90 G = 1 G = 100 40 60 30 G = 10 20 30 10 G = 1000 0 0 –200 –100 0 100 200 1 10 100 1k 10k 100k INPUT OFFSET VOLTAGE, V , RTI (µV) OSI FREQUENCY (Hz) Figure 10. Voltage Spectral Density Noise vs. Frequency Figure 7. Typical Distribution of Offset Voltage, VOSI 300 250 200 150 100 50 2µV/DIV 1s/DIV 0 –90 –60 –30 0 30 60 90 INPUT BIAS CURRENT (nA) Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Figure 8. Typical Distribution of Input Bias Current Rev. A | Page 8 of 24 NUMBER OF UNITS NUMBER OF UNITS NUMBER OF UNITS 06983-007 06983-008 06983-006 NOISE (nV/√Hz) NUMBER OF UNITS 06983-011 06983-009 06983-010 AD8253 20 18 16 14 12 10 8 6 4 2 500nV/DIV 1s/DIV 0 0.01 0.1 1 10 WARM-UP TIME (Minutes) Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1000 Figure 15. Change in Input Offset Voltage vs. Warm-Up Time, G = 1000 140 18 16 120 14 G = 1000 G = 100 100 12 80 10 G = 1 8 60 G = 10 6 40 4 20 2 0 0 10 100 1k 10k 100k 1M 11 10 100 1k 10k00k FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Current Noise Spectral Density vs. Frequency Figure 16. Positive PSRR vs. Frequency, RTI 140 G = 100 120 G = 1000 100 80 G = 10 60 40 G = 1 20 140pA/DIV 1s/DIV 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 14. 0.1 Hz to 10 Hz Current Noise Figure 17. Negative PSRR vs. Frequency, RTI Rev. A | Page 9 of 24 NOISE (pA/√Hz) 06983-014 06983-012 06983-013 PSRR (dB) PSRR (dB) CHANGE IN INPUT OFFSET VOLTAGE (µV) 06983-015 06983-017 06983-016 AD8253 20 12.0 120 10 10.5 100 I + B 0 9.0 G = 1000 I – B 80 –10 7.5 G = 100 –20 6.0 60 G = 10 –30 4.5 I 40 OS –40 3.0 20 G = 1 –50 1.5 –60 0 0 10 100 1k 10k 100k 1M –15 –10 –5 0 5 10 15 COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 18. Input Bias Current and Offset Current vs. Common-Mode Voltage Figure 21. CMRR vs. Frequency, 1 kΩ Source Imbalance 30 15 25 10 20 5 15 10 0 I – B 5 I + –5 B 0 –10 I OS –5 –10 –15 –50 –30 –10 1030507090 110 130 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Input Bias Current and Offset Current vs. Temperature Figure 22. CMRR vs. Temperature, G = 1 120 80 G = 1000 70 G = 100 100 G = 1000 60 50 80 G = 100 40 G = 1 60 30 G = 10 G = 10 20 40 10 G = 1 0 20 –10 0 –20 10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. CMRR vs. Frequency Figure 23. Gain vs. Frequency Rev. A | Page 10 of 24 INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT AND CMRR (dB) OFFSET CURRENT (nA) 06983-020 06983-019 INPUT OFFSET CURRENT (nA) 06983-018 GAIN (dB) CMRR (µV/V) CMRR (dB) 06983-022 06983-021 006983-023 AD8253 40 400 30 300 20 200 10 100 0 0 –10 –100 –20 –200 –30 –300 –40 –400 –10 –8 –6 –4 –2 02468 10 –10 –8 –6 –4 –2 02468 10 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity, G = 1, R = 10 kΩ, 2 kΩ, 600 Ω Figure 27. Gain Nonlinearity, G = 1000, R = 10 kΩ, 2 kΩ, 600 Ω L L 40 16 0V, +13.9V 30 12 V , ±15V S 20 8 –14.1V, +7.3V +13.8V, +7.3V 0V, +3.8V 4 10 –4V, +1.9V +3.8V, +1.9V 0 0 V = ±5V S –4V, –1.9V +3.8V, –1.9V –10 –4 0V, –4.2V –14.1V, –7.3V +13.8V, –7.3V –20 –8 –30 –12 0V, –14.2V –40 –16 –10 –8 –6 –4 –2 02468 10 –16 –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 25. Gain Nonlinearity, G = 10, R = 10 kΩ, 2 kΩ, 600 Ω L Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 1 80 16 0V, +13.7V 60 12 V ±15V S 40 8 –14.4V, +6V 0V, +3.8V +14.1V, +6V 4 20 –4.3V, +2V +4.3V, +2V 0 0 V = ±5V S –4.3V, –2V +4.3V, –2V –20 –4 –14.4V, –6V 0V, –4.2V +14.1V, –6V –40 –8 –60 –12 0V, –14.1V –80 –16 –10 –8 –6 –4 –2 02468 10 –16 –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 1000 Figure 26. Gain Nonlinearity, G = 100, R = 10 kΩ, 2 kΩ, 600 Ω L Rev. A | Page 11 of 24 NONLINEARITY (10ppm/DIV) NONLINEARITY (10ppm/DIV) NONLINEARITY (10ppm/DIV) 06983-026 06983-025 06983-024 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) NONLINEARITY (10 ppm/DIV) 06983-027 06983-029 06983-028 +25°C +25°C +25°C +25°C +25°C +25°C AD8253 +V +V S S +125°C +85°C –0.2 +125°C –0.4 –1 –0.6 –0.8 –2 +25°C –1.0 –40°C +85°C –40°C –40°C +85°C +1.0 +2 +25°C –40°C +0.8 +0.6 +1 +0.4 +125°C +125°C +0.2 +85°C –V –V S S 416 416 6 8 10 12 14 6 8 10 12 14 SUPPLY VOLTAGE (±V ) SUPPLY VOLTAGE (±V ) S S Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ Figure 33. Output Voltage Swing vs. Supply Voltage, G =1000, RL = 10 kΩ 25 15 FAULT FAULT CONDITION CONDITION 20 +85°C (OVER-DRIVEN (OVER-DRIVEN 10 INPUT) INPUT) 15 G=1000 G=1000 +Vs –40°C 10 5 5 +125°C +IN +IN 0 0 –IN –IN –5 +85°C –5 –10 +125°C –Vs –15 –10 –20 –40°C –25 –15 100 1k 10k LOAD RESISTANCE (Ω) DIFFERENTIAL INPUT VOLTAGE (V) Figure 31. Fault Current Draw vs. Input Voltage, G = 1000, R = 10 kΩ Figure 34. Output Voltage Swing vs. Load Resistance L +V +V S S –40°C –0.2 –0.4 +25°C –0.4 +85°C +125°C –0.8 –0.6 +125°C –0.8 –1.2 –1.0 –1.6 –1.2 +85°C –40°C –2.0 +2.0 +85°C –40°C +1.2 +1.6 +1.0 +0.8 +1.2 +0.6 +0.8 +0.4 +125°C +0.4 +0.2 –V –V S S 41 6 8 10 12 146 41 6 8 10 12 146 SUPPLY VOLTAGE (±V ) OUTPUT CURRENT (mA) S Figure 35. Output Voltage Swing vs. Output Current Figure 32. Output Voltage Swing vs. Supply Voltage, G = 1000, RL = 2 kΩ Rev. A | Page 12 of 24 OUTPUT VOLTAGE SWING (V) INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES CURRENT (mA) REFERRED TO SUPPLY VOLTAGES –10 –1 –100m –10m –1m –100µ –10µ/ 10µ 100µ 1m 10m 100m 1 10 06983-031 06983-030 06983-032 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 06983-034 06983-035 06983-033 AD8253 5V/DIV NO 47pF 100pF LOAD 1392ns TO 0.01% 1712ns TO 0.001% 0.002%/DIV 20mV/DIV 2µs/DIV 2µs/DIV TIME (µs) Figure 36. Small-Signal Pulse Response for Various Capacitive Loads, G = 1 Figure 39. Large-Signal Pulse Response and Settling Time, G = 100, R = 10 kΩ L 5V/DIV 5V/DIV 664ns TO 0.01% 12.88µs TO 0.01% 744ns TO 0.001% 16.64µs TO 0.001% 0.002%/DIV 0.002%/DIV 2µs/DIV 10µs/DIV TIME (µs) TIME (µs) Figure 37. Large-Signal Pulse Response and Settling Time, G = 1, RL = 10 kΩ Figure 40. Large-Signal Pulse Response and Settling Time, G = 1000, RL = 10 kΩ 5V/DIV 656ns TO 0.01% 840ns TO 0.001% 0.002%/DIV 2µs/DIV 20mV/DIV 2µs/DIV TIME (µs) Figure 41. Small-Signal Response, Figure 38. Large-Signal Pulse Response and Settling Time, G = 1, RL = 2 kΩ, CL = 100 G = 10, R = 10 kΩ L Rev. A | Page 13 of 24 06983-038 06983-037 06983-036 06983-041 06983-039 06983-040 AD8253 1400 1200 1000 SETTLED TO 0.001% 800 600 SETTLED TO 0.01% 400 200 20mV/DIV 2µs/DIV 0 22 4 6 8 10 12 14 16 180 STEP SIZE (V) Figure 42. Small-Signal Response, Figure 45. Settling Time vs. Step Size, G = 1, R = 10 kΩ L G = 10, R = 2 kΩ, C = 100 pF L L 1400 1200 1000 SETTLED TO 0.001% 800 SETTLED TO 0.01% 600 400 200 20mV/DIV 20µs/DIV 0 22 4 6 8 1012 1416180 STEP SIZE (V) Figure 43. Small-Signal Response, Figure 46. Settling Time vs. Step Size, G = 10, RL = 10 kΩ G = 100, RL = 2 kΩ, CL = 100 pF 2000 SETTLED TO 0.001% 1800 1600 1400 SETTLED TO 0.01% 1200 1000 800 600 400 200 20mV/DIV 20µs/DIV 0 220 4 6 8 10 12 14 16 18 STEP SIZE (V) Figure 44. Small-Signal Response, G = 1000, R = 2 kΩ, C = 100 pF L L Figure 47. Settling Time vs. Step Size, G = 100, RL = 10 kΩ Rev. A | Page 14 of 24 06983-044 06983-043 06983-042 TIME (ns) TIME (ns) TIME (ns) 06983-047 06983-046 06983-045 AD8253 0 20 –10 18 SETTLED TO 0.001% –20 16 –30 14 –40 G = 1000 12 –50 SETTLED TO 0.01% 10 –60 G = 100 –70 8 G = 10 –80 6 –90 G = 1 4 –100 2 –110 0 –120 10 1M 22 4 6 8 10121416180 100 1k 10k 100k STEP SIZE (V) FREQUENCY (Hz) Figure 48. Settling Time vs. Step Size, G = 1000, R = 10 kΩ Figure 50. Total Harmonic Distortion vs. Frequency, L 10 Hz to 500 kHz Band-Pass Filter, 2 kΩ Load 0 –10 –20 –30 –40 –50 G = 1000 –60 –70 G = 100 –80 G = 10 –90 –100 G = 1 –110 –120 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 49. Total Harmonic Distortion vs. Frequency, 10 Hz to 22 kHz Band-Pass Filter, 2 kΩ Load Rev. A | Page 15 of 24 THD + N (dB) TIME (µs) 06983-048 06983-049 THD + N (dB) 06983-050 AD8253 THEORY OF OPERATION +V +V S S A0 A1 2.2kΩ +V S –V –V S S 1.2kΩ –IN 10kΩ 10kΩ A1 –V S +V S DIGITAL GAIN A3 OUT CONTROL –V S +V S +V S 10kΩ 10kΩ A2 REF 1.2kΩ +IN –V S +V +V S S –V S 2.2kΩ WR DGND –V –V S S Figure 51. Simplified Schematic The AD8253 is a monolithic instrumentation amplifier based Transparent Gain Mode on the classic 3-op-amp topology, as shown in Figure 51. It is The easiest way to set the gain is to program it directly via a fabricated on the Analog Devices, Inc., proprietary iCMOS® logic high or logic low voltage applied to A0 and A1. Figure 52 process that provides precision linear performance and a robust shows an example of this gain setting method, referred to through- digital interface. A parallel interface allows users to digitally out the data sheet as transparent gain mode. Tie WR to the program gains of 1, 10, 100, and 1000. Gain control is achieved negative supply to engage transparent gain mode. In this mode, by switching resistors in an internal precision resistor array (as any change in voltage applied to A0 and A1 from logic low to shown in Figure 51). logic high, or vice versa, immediately results in a gain change. All internal amplifiers employ distortion cancellation circuitry Table 5 is the truth table for transparent gain mode, and Figure 52 and achieve high linearity and ultralow THD. Laser-trimmed shows the AD8253 configured in transparent gain mode. resistors allow for a maximum gain error of less than 0.03% for +15V G = 1 and a minimum CMRR of 100 dB for G = 1000. A pinout 10μF0.1µF optimized for high CMRR over frequency enables the AD8253 WR –15V to offer a guaranteed minimum CMRR over frequency of 80 dB A1 +5V A0 at 20 kHz (G = 1). The balanced input reduces the parasitics +IN +5V G = 1000 that in the past had adversely affected CMRR performance. AD8253 GAIN SELECTION REF This section describes how to configure the AD8253 for basic –IN operation. Logic low and logic high voltage limits are listed in DGND DGND the Specifications section. Typically, logic low is 0 V and logic 10μF0.1µF high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table (Table 2) for the permissible –15V voltage range of DGND. The gain of the AD8253 can be set NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V . S using two methods: transparent gain mode and latched gain THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE mode. Regardless of the mode, pull-up or pull-down resistors SET TO LOGIC HIGH, RESULTING IN A GAIN OF 1000. should be used to provide a well-defined voltage at the A0 and Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 1000 A1 pins. Rev. A | Page 16 of 24 06983-061 06983-051 AD8253 Table 5. Truth Table Logic Levels for Transparent Gain Mode Table 6. Truth Table Logic Levels for Latched Gain Mode WR A1 A0 Gain WR A1 A0 Gain −VS Low Low 1 High to Low Low Low Change to 1 −VS Low High 10 High to Low Low High Change to 10 −V High Low 100 S High to Low High Low Change to 100 −V High High 1000 S High to Low High High Change to 1000 1 1 Low to Low X X No change 1 1 Latched Gain Mode Low to High X X No change 1 1 High to High X X No change Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation 1 X = don’t care. amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8253 can be set using WR as a latch, On power-up, the AD8253 defaults to a gain of 1 when in allowing other devices to share A0 and A1. Figure 53 shows a latched gain mode. In contrast, if the AD8253 is configured in schematic using this method, known as latched gain mode. The transparent gain mode, it starts at the gain indicated by the WR AD8253 is in this mode when is held at logic high or logic voltage levels on A0 and A1 on power-up. low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 Timing for Latched Gain Mode WR are read on the downward edge of the signal as it transitions In latched gain mode, logic levels at A0 and A1 must be held for from logic high to logic low. This latches in the logic levels on a minimum setup time, t , before the downward edge of WR SU A0 and A1, resulting in a gain change. See the truth table listing latches in the gain. Similarly, they must be held for a minimum in Table 6 for more on these gain changes. hold time, t , after the downward edge of WR to ensure that HD +15V WR +5V the gain is latched in correctly. After tHD, A0 and A1 may change WR 0V 10μF0.1µF logic levels, but the gain does not change until the next downward +5V A1 A1 0V WR WR edge of . The minimum duration that can be held high A0 +5V A0 WR 0V is t WR-HIGH, and t WR-LOW is the minimum duration that can +IN + G = PREVIOUS G = 1000 be held low. Digital timing specifications are listed in Table 2. STATE AD8253 The time required for a gain change is dominated by the settling REF time of the amplifier. A timing diagram is shown in Figure 54. – –IN When sharing a data bus with other devices, logic levels applied DGND DGND to those devices can potentially feed through to the output of 10μF0.1µF the AD8253. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the –15V PCB also reduces coupling between the digital and analog NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS portions of the board. FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000. Figure 53. Latched Gain Mode, G = 1000 t t WR-HIGH WR-LOW WR t t SU HD A0, A1 Figure 54. Timing Diagram for Latched Gain Mode Rev. A | Page 17 of 24 06983-052 06983-053 AD8253 INCORRECT CORRECT POWER SUPPLY REGULATION AND BYPASSING +V +V S S The AD8253 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect per- formance. As in all linear circuits, bypass capacitors must be AD8253 AD8253 used to decouple the amplifier. REF REF Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum capacitor can be used farther away from the part (see Figure 55) –V –V S S and, in most cases, it can be shared by other precision integrated TRANSFORMER TRANSFORMER circuits. +V +V S S +V S 10µF 0.1µF WR A1 AD8253 AD8253 A0 +IN REF REF V OUT 10MΩ AD8253 LOAD –V –V S S REF –IN THERMOCOUPLE THERMOCOUPLE DGND +V +V S S 10µF 0.1µF C C –V DGND S 1 R f = HIGH-PASS Figure 55. Supply Decoupling, REF, and Output Referred to Ground AD8253 2πRC AD8253 C C REF REF INPUT BIAS CURRENT RETURN PATH R The AD8253 input bias current must have a return path to its –V –V local analog ground. When the source, such as a thermocouple, S S CAPACITIVELY COUPLED CAPACITIVELY COUPLED cannot provide a return current path, one should be created Figure 56. Creating an IBIAS Path (see Figure 56). INPUT PROTECTION All terminals of the AD8253 are protected against ESD. An external resistor should be used in series with each of the inputs to limit current for voltages greater than 0.5 V beyond either supply rail. In such a case, the AD8253 safely handles a continuous 6 mA current at room temperature. For applications where the AD8253 encounters extreme overload voltages, external series resistors and low leakage diode clamps such as BAV199Ls, FJH1100s, or SP720s should be used. Rev. A | Page 18 of 24 06983-054 06983-055 AD8253 Coupling Noise REFERENCE TERMINAL To prevent coupling noise onto the AD8253, follow these The reference terminal, REF, is at one end of a 10 kΩ resistor guidelines: (see Figure 51). The instrumentation amplifier output is referenced to the voltage on the REF terminal; this is useful • Do not run digital lines under the device. when the output signal needs to be offset to voltages other than • Run the analog ground plane under the AD8253. its local analog ground. For example, a voltage source can be • Shield fast-switching signals with digital ground to avoid tied to the REF pin to level shift the output so that the AD8253 radiating noise to other sections of the board, and never can interface with a single-supply ADC. The allowable reference run them near analog signal paths. voltage range is a function of the gain, common-mode input, • Avoid crossover of digital and analog signals. and supply voltages. The REF pin should not exceed either +VS • Connect digital and analog ground at one point only or −VS by more than 0.5 V. (typically under the ADC). For best performance, especially in cases where the output is • Power supply lines should use large traces to ensure a low not measured with respect to the REF terminal, source imped- impedance path. Decoupling is necessary; follow the ance to the REF terminal should be kept low because parasitic guidelines listed in the Power Supply Regulation and resistance can adversely affect CMRR and gain accuracy. Bypassing section. INCORRECT CORRECT Common-Mode Rejection The AD8253 has high CMRR over frequency, giving it greater immunity to disturbances, such as line noise and its associated AD8253 AD8253 harmonics, in contrast to typical in amps whose CMRR falls off V REF around 200 Hz. They often need common-mode filters at the V REF inputs to compensate for this shortcoming. The AD8253 is able + to reject CMRR over a greater frequency range, reducing the OP1177 – need for input common-mode filtering. Careful board layout maximizes system performance. To maintain Figure 57. Driving the Reference Pin high CMRR over frequency, lay out the input traces symmetrically. Ensure that the traces maintain resistive and capacitive balance; COMMON-MODE INPUT VOLTAGE RANGE this holds for additional PCB metal layers under the input pins The 3-op-amp architecture of the AD8253 applies gain and then and traces. Source resistance and capacitance should be placed removes the common-mode voltage. Therefore, internal nodes as close to the inputs as possible. Should a trace cross the inputs in the AD8253 experience a combination of both the gained (from another layer), it should be routed perpendicular to the signal and the common-mode signal. This combined signal can input traces. be limited by the voltage supplies even when the individual RF INTERFERENCE input and output signals are not. Figure 28 and Figure 29 show the allowable common-mode input voltage ranges for various RF rectification is often a problem when amplifiers are used in output voltages, supply voltages, and gains. applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals LAYOUT can be filtered with a low-pass RC network placed at the input Grounding of the instrumentation amplifier, as shown in Figure 58. The In mixed-signal circuits, low level analog signals need to be filter limits the input signal bandwidth according to the following isolated from the noisy digital environment. Designing with the relationship: AD8253 is no exception. Its supply voltages are referenced to an 1 analog ground. Its digital circuit is referenced to a digital ground. FilterFreq = DIFF 2 π R(2C + C ) Although it is convenient to tie both grounds to a single ground D C plane, the current traveling through the ground wires and PC 1 FilterFreq = board can cause an error. Therefore, use separate analog and CM 2 π RC C digital ground planes. Only at one point, star ground, should analog and digital ground meet. where C ≥ 10 C . D C The output voltage of the AD8253 develops with respect to the potential on the reference terminal. Take care to tie REF to the appropriate local analog ground or to connect it to a voltage that is referenced to the local analog ground. Rev. A | Page 19 of 24 06983-056 AD8253 +15V In this example, a 1 nF capacitor and a 49.9 Ω resistor create an antialiasing filter for the AD7612. The 1 nF capacitor also serves 0.1µF 10µF to store and deliver necessary charge to the switched capacitor C C input of the ADC. The 49.9 Ω series resistor reduces the burden R +IN of the 1 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7612. V OUT C D AD8253 Selecting too small a resistor improves the correlation between R REF the voltage at the output of the AD8253 and the voltage at the –IN input of the AD7612 but may destabilize the AD8253. A trade- C C off must be made between selecting a resistor small enough to 0.1µF 10µF maintain accuracy and large enough to maintain stability. +15V –15V Figure 58. RFI Suppression 10μF0.1µF WR +12V –12V Values of R and CC should be chosen to minimize RFI. A1 A0 Mismatch between the R × CC at the positive input and the +IN 0.1μF 0.1μF R × CC at negative input degrades the CMRR of the AD8253. 49.9Ω By using a value of CD that is 10 times larger than the value of AD8253 AD7612 1nF C , the effect of the mismatch is reduced and performance is REF C –IN +5V improved. ADR435 DGND DGND DRIVING AN ANALOG-TO-DIGITAL CONVERTER 10μF0.1µF An instrumentation amplifier is often used in front of an analog- to-digital converter to provide CMRR. Usually, instrumentation –15V amplifiers require a buffer to drive an ADC. However, the low Figure 59. Driving an ADC output noise, low distortion, and low settle time of the AD8253 make it an excellent ADC driver. Rev. A | Page 20 of 24 06983-057 06983-058 AD8253 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER +15V In certain applications, it is necessary to create a differential signal. High resolution analog-to-digital converters often require a 10μF0.1µF differential input. In other cases, transmission over a long distance WR MICRO- A1 can require differential signals for better immunity to interference. CONTROLLER A0 +IN + Figure 61 shows how to configure the AD8253 to output a differential signal. An op amp, the AD8675, is used in an AD8253 inverting topology to create a differential voltage. VREF sets the REF – output midpoint according to the equation shown in the figure. –IN Errors from the op amp are common to both outputs and are DGND DGND thus common mode. Likewise, errors from using mismatched 10μF0.1µF resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input –15V ADCs or instrumentation amplifiers. Figure 60. Programming Gain Using a Microcontroller When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC. +15V 0.1μF AMPLITUDE WR +5V A1 A0 +IN AMPLITUDE –5V + V A = V + V OUT IN REF 2 +2.5V AD8253 0V V IN G = 1 –2.5V TIME REF – 4.99kΩ 0.1μF DGND – + V REF 0V –15V –15V +15V AD8675 4.99kΩ 56pF AMPLITUDE 0.1µF 0.1µF +15V –15V +2.5V 10μF 10μF 0V 0V DGND –2.5V V B = –V + V OUT IN REF TIME 2 Figure 61. Differential Output with Level Shift Rev. A | Page 21 of 24 06983-060 06983-059 13 AD8253 0 DATA ACQUISITION –10 –20 The AD8253 makes an excellent instrumentation amplifier –30 for use in data acquisition systems. Its wide bandwidth, low –40 –50 distortion, low settling time, and low noise enable it to –60 condition signals in front of a variety of 16-bit ADCs. –70 –80 Figure 63 shows the AD825x as part of a total data acquisition –90 system. The quick slew rate of the AD8253 allows it to condition –100 –110 rapidly changing signals from the multiplexed inputs. An FPGA –120 controls the AD7612, AD8253, and ADG1209. In addition, –130 –140 mechanical switches and jumpers allow users to pin strap the –150 gains when in transparent gain mode. –160 –170 This system achieved −116 dB of THD at 1 kHz and a signal-to-050 5 1015202530354045 FREQUENCY (kHz) noise ratio of 91 dB during testing, as shown in Figure 62. Figure 62. FFT of the AD825x in a Total Data Acquisition System Using the AD8253 1 kHz Signal JMP JMP –V S +12V –12V +12V + + +5V 0.1µF 2kΩ 10µF 10µF 14 GND V 2 DD DGND 806Ω EN DGND JMP 4 +CH1 S1A 806Ω +5V DGND +CH2 5 S2A 2kΩ 806Ω 2 ALTERA +CH3 6 S3A 6 DGND EPF6010ATC144-3 806Ω 0Ω 0Ω C 5 +CH4 7 S4A C WR DGND +IN DA 8 10 + 4 A1 ADG1209 VOUT 806Ω A0 +IN AD8253 7 AD7612 –CH4 C 10 S4B D REF 0Ω 0Ω 0Ω 49.9Ω –IN 1nF 806Ω 9 9 1 –V DB – S –CH3 11 S3B +V S 3 806Ω ADR435 15 GND –CH2 12 S2B 8 806Ω A0 –CH1 S1B 1 A1 C4 C3 0.1µF V 16 SS 0.1µF 3 +12V –12V JMP 0.1µF +5V –12V 2kΩ DGND JMP +5V R8 2kΩ DGND Figure 63. Schematic of ADG1209, AD8253, and AD7612 Used with the AD825x in a Total Data Acquisition System Rev. A | Page 22 of 24 C C AMPLITUDE (dB) 06983-067 06983-062 AD8253 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.33 SEATING 0.23 0° 0.05 0.17 PLANE 0.40 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 64. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD8253ARMZ –40°C to +85°C 10-Lead MSOP RM-10 Y0K 1 AD8253ARMZ-RL –40°C to +85°C 10-Lead MSOP RM-10 Y0K 1 AD8253ARMZ-R7 –40°C to +85°C 10-Lead MSOP RM-10 Y0K 1 AD8253-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 23 of 24 AD8253 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06983-0-8/08(A) Rev. A | Page 24 of 24