ANALOG DEVICES AD8251

10 MHz, 20 V/μs, G = 1, 2, 4, 8 iCMOS Programmable Gain Instrumentation Amplifier AD8251 FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR A1 A0 Small package: 10-lead MSOP 2 6 5 4 Programmable gains: 1, 2, 4, 8 LOGIC –IN 1 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance 7 High CMRR: 98 dB (minimum), G = 8 OUT Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.8 μV/°C (maximum), G = 8 Excellent ac performance +IN 10 Fast settling time: 785 ns to 0.001% (maximum) AD8251 High slew rate: 20 V/μs (minimum) 8 3 9 Low distortion: −110 dB THD at 1 kHz, 10 V swing +V –V REF S S High CMRR over frequency: 80 dB to 50 kHz (minimum) Figure 1. Low noise: 18 nV/√Hz, G = 8 (maximum) 25 Low power: 4.1 mA 20 APPLICATIONS G = 8 Data acquisition 15 G = 4 Biomedical analysis Test and measurement 10 G = 2 GENERAL DESCRIPTION 5 The AD8251 is an instrumentation amplifier with digitally G = 1 0 programmable gains that has GΩ input impedance, low output noise, and low distortion, making it suitable for interfacing with –5 sensors and driving high sample rate analog-to-digital converters (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 dB, –10 1k 10k 100k 1M 10M 100M and fast settling time of 785 ns (maximum) to 0.001%. Offset FREQUENCY (Hz) drift and gain drift are guaranteed to 1.8 μV/°C and 10 ppm/°C, Figure 2. Gain vs. Frequency respectively, for G = 8. In addition to its wide input common Table 1. Instrumentation Amplifiers by Category voltage range, it boasts a high common-mode rejection of 80 dB General Mil Low High Speed at G = 1 from dc to 50 kHz. The combination of precision dc Purpose Zero Drift Grade Power PGA performance coupled with high speed capabilities makes the 1 1 1 AD8220 AD8231 AD620 AD627 AD8250 AD8251 an excellent candidate for data acquisition. Furthermore, 1 1 AD8221 AD8553 AD621 AD623 AD8251 this monolithic solution simplifies design and manufacturing 1 1 AD8222 AD8555 AD524 AD8223 AD8253 and boosts performance of instrumentation by maintaining a 1 1 AD8224 AD8556 AD526 tight match of internal resistors and amplifiers. 1 AD8228 AD8557 AD624 The AD8251 user interface consists of a parallel port that allows 1 Rail-to-rail output. users to set the gain in one of two ways (see Figure 1). A 2-bit word The AD8251 is available in a 10-lead MSOP package and is sent via a bus can be latched using the WR input. An alternative is specified over the −40°C to +85°C temperature range, making it to use the transparent gain mode where the state of the logic an excellent solution for applications where size and packing levels at the gain port determines the gain. density are important considerations. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 06287-001 06287-002 AD8251 TABLE OF CONTENTS Features .............................................................................................. 1 Power Supply Regulation and Bypassing ................................ 18 Applications....................................................................................... 1 Input Bias Current Return Path ............................................... 18 General Description ......................................................................... 1 Input Protection ......................................................................... 18 Functional Block Diagram .............................................................. 1 Reference Terminal .................................................................... 19 Revision History ............................................................................... 2 Common-Mode Input Voltage Range ..................................... 19 Specifications..................................................................................... 3 Layout .......................................................................................... 19 Timing Diagram ........................................................................... 5 RF Interference ........................................................................... 20 Absolute Maximum Ratings............................................................ 6 Driving an ADC ......................................................................... 20 Maximum Power Dissipation ..................................................... 6 Applications..................................................................................... 21 ESD Caution.................................................................................. 6 Differential Output .................................................................... 21 Pin Configuration and Function Descriptions............................. 7 Setting Gains with a Microcontroller ...................................... 21 Typical Performance Characteristics ............................................. 8 Data Acquisition......................................................................... 22 Theory of Operation ...................................................................... 16 Outline Dimensions....................................................................... 23 Gain Selection ............................................................................. 16 Ordering Guide .......................................................................... 23 REVISION HISTORY 11/10—Rev. A to Rev. B Changes to Table 2.............................................................................3 Changes to Voltage Offset, Offset RTI V , Average TC Changes to Table 3.............................................................................6 OS Parameter in Table 2......................................................................... 3 Inserted Figure 17; Renumbered Sequentially ..............................9 Updated Outline Dimensions ....................................................... 23 Inserted Figure 29........................................................................... 11 Changes to Timing for Latched Gain Mode Section ................. 17 5/08—Rev. 0 to Rev. A Changes to Table 1............................................................................ 1 5/07—Revision 0: Initial Version Rev. B | Page 2 of 24 AD8251 SPECIFICATIONS +VS = 15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 98 dB G = 2 86 104 dB G = 4 92 110 dB G = 8 98 110 dB CMRR to 50 kHz +IN = −IN = −10 V to +10 V G = 1 80 dB G = 2 84 dB G = 4 86 dB G = 8 86 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 4 22 nV/√Hz G = 8 18 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 4 1.8 μV p-p G = 8 1.2 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 2, 4, 8 ±(70 + 200/G) ±(200 + 600/G) μV Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average TC T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C Offset Referred to the Input vs. Supply (PSR) V = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V S INPUT CURRENT Input Bias Current 5 30 nA Over Temperature T = −40°C to +85°C 40 nA Average TC T = −40°C to +85°C 400 pA/°C Input Offset Current 5 30 nA Over Temperature T = −40°C to +85°C 30 nA Average TC T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 10 MHz G = 2 10 MHz G = 4 8 MHz G = 8 2.5 MHz Settling Time 0.01% ΔOUT = 10 V step G = 1 615 ns G = 2 460 ns G = 4 460 ns G = 8 625 ns Rev. B | Page 3 of 24 AD8251 Parameter Conditions Min Typ Max Unit Settling Time 0.001% ΔOUT = 10 V step G = 1 785 ns G = 2 700 ns G = 4 700 ns G = 8 770 ns Slew Rate G = 1 20 V/μs G = 2 30 V/μs G = 4 30 V/μs G = 8 30 V/μs Total Harmonic Distortion + Noise f = 1 kHz, R = 10 kΩ, ±10 V, −110 dB L G = 1, 10 Hz to 22 kHz band- pass filter GAIN Gain Range G = 1, 2, 4, 8 1 8 V/V Gain Error OUT = ±10 V G = 1 0.03 % G = 2, 4, 8 0.04 % Gain Nonlinearity OUT = −10 V to +10 V G = 1 R = 10 kΩ, 2 kΩ, 600 Ω 9 ppm L G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm G = 4 RL = 10 kΩ, 2 kΩ, 600 Ω 12 ppm G = 8 RL = 10 kΩ, 2 kΩ, 600 Ω 15 ppm Gain vs. Temperature All gains 3 10 ppm/°C INPUT Input Impedance Differential 5.3||0.5 GΩ||pF Common Mode 1.25||2 GΩ||pF Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V Over Temperature T = −40°C to +85°C −V + 1.6 +V − 1.7 V S S OUTPUT Output Swing −13.5 +13.5 V Over Temperature T = −40°C to +85°C −13.5 +13.5 V Short-Circuit Current 37 mA REFERENCE INPUT R 20 kΩ IN I +IN, −IN, REF = 0 1 μA IN Voltage Range −V +V V S S Gain to Output 1 ± 0.0001 V/V DIGITAL LOGIC Digital Ground Voltage, DGND Referred to GND −V + 4.25 0 +V − 2.7 V S S Digital Input Voltage Low Referred to GND DGND 2.1 V Digital Input Voltage High Referred to GND 2.8 +VS V Digital Input Current 1 μA 1 Gain Switching Time 325 ns t See Figure 3 timing diagram 20 ns SU tHD See Figure 3 timing diagram 10 ns See Figure 3 timing diagram 20 ns t WR -LOW See Figure 3 timing diagram 40 ns t WR -HIGH Rev. B | Page 4 of 24 AD8251 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −I 3.7 4.5 mA S Over Temperature T = −40°C to +85°C 4.5 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 Add time for the output to slew and settle to calculate the total time for a gain change. TIMING DIAGRAM t t WR-HIGH WR-LOW WR t t SU HD A0, A1 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. B | Page 5 of 24 06287-003 AD8251 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (PD) is the sum of the Table 3. quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage ±17 V power is the voltage between the supply pins (VS) times the Power Dissipation See Figure 4 quiescent current (I ). Assuming the load (R ) is referenced to S L 1 Output Short-Circuit Current Indefinite midsupply, the total drive power is V /2 × I , some of which is S OUT Common-Mode Input Voltage +VS + 13 V to −VS − 13 V dissipated in the package and some in the load (V × I ). OUT OUT 2 Differential Input Voltage +VS + 13 V, −VS − 13 V The difference between the total drive power and the load Digital Logic Inputs ±V S power is the drive power dissipated in the package. Storage Temperature Range −65°C to +125°C 3 Operating Temperature Range −40°C to +85°C PD = Quiescent Power + (Total Drive Power − Load Power) Lead Temperature (Soldering, 10 sec) 300°C 2 ⎛ ⎞ V V V S OUT OUT Junction Temperature 140°C ⎜ ⎟ P =() V× I + × – D S S ⎜ ⎟ 2 R R θ (Four-Layer JEDEC Standard Board) 112°C/W ⎝ L ⎠ L JA Package Glass Transition Temperature 140°C In single-supply operation with RL referenced to −VS, the worst case is VOUT = VS/2. 1 Assumes the load is referenced to midsupply. 2 Current must be kept to less than 6 mA. Airflow increases heat dissipation, effectively reducing θ . In JA 3 Temperature for specified performance is −40°C to +85°C. For performance addition, more metal directly in contact with the package leads to +125°C, see the Typical Performance Characteristics section. from metal traces, through holes, ground, and power planes Stresses above those listed under Absolute Maximum Ratings reduces the θ . JA may cause permanent damage to the device. This is a stress Figure 4 shows the maximum safe power dissipation in the rating only; functional operation of the device at these or any package vs. the ambient temperature on a four-layer JEDEC other conditions above those indicated in the operational section of standard board. this specification is not implied. Exposure to absolute maximum 2.00 rating conditions for extended periods may affect device reliability. 1.75 MAXIMUM POWER DISSIPATION 1.50 The maximum safe power dissipation in the AD8251 package is limited by the associated rise in junction temperature (T ) on J 1.25 the die. The plastic encapsulating the die locally reaches the 1.00 junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. 0.75 Even temporarily exceeding this temperature limit can change 0.50 the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8251. Exceeding 0.25 a junction temperature of 140°C for an extended period can 0 result in changes in silicon devices, potentially causing failure. –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) The still air thermal properties of the package and PCB (θ ), JA Figure 4. Maximum Power Dissipation vs. Ambient Temperature the ambient temperature (T ), and the total power dissipated in A the package (PD) determine the junction temperature of the die. ESD CAUTION The junction temperature is calculated as T = T +(P × θ ) J A D JA Rev. B | Page 6 of 24 MAXIMUM POWER DISSIPATION (W) 06287-004 AD8251 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 10 +IN DGND 2 9 REF AD8251 –V 3 8 +V S TOP VIEW S (Not to Scale) A0 4 7 OUT 5 6 A1 WR Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −V Negative Supply Terminal. S 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6 WR Write Enable. 7 OUT Output Terminal. 8 +V Positive Supply Terminal. S 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input. Rev. B | Page 7 of 24 06287-005 AD8251 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 2700 800 2400 700 2100 600 1800 500 1500 400 1200 300 900 200 600 100 300 0 0 –30 –20 –10 0 10 20 30 –120 –90 –60 –30 0 30 60 90 120 INPUT OFFSET CURRENT (nA) CMRR (µV/V) Figure 9. Typical Distribution of Input Offset Current Figure 6. Typical Distribution of CMRR, G = 1 90 500 80 70 400 60 50 300 G = 1 40 200 30 G = 2 G = 4 20 100 G = 8 10 0 0 –200 –100 0 100 200 1 10 100 1k 10k 100k INPUT OFFSET VOLTAGE, V , RTI (µV) OSI FREQUENCY (Hz) Figure 7. Typical Distribution of Offset Voltage, V Figure 10. Voltage Spectral Density Noise vs. Frequency OSI 800 600 400 200 2µV/DIV 1s/DIV 0 –30 –20 –10 0 10 20 30 INPUT BIAS CURRENT (nA) Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. B | Page 8 of 24 NUMBER OF UNITS NUMBER OF UNITS NUMBER OF UNITS 06287-008 06287-007 06287-006 NOISE (nV/√Hz) NUMBER OF UNITS 06287-011 06287-010 06287-009 AD8251 150 130 G = 4 110 G = 2 90 G = 1 70 G = 8 50 30 1.25µV/DIV 1s/DIV 10 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 8 Figure 15. Positive PSRR vs. Frequency, RTI 150 18 16 130 14 110 G= 4 12 G=8 90 10 8 70 G=1 6 50 4 G= 2 30 2 0 10 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Current Noise Spectral Density vs. Frequency Figure 16. Negative PSRR vs. Frequency, RTI 10 9 8 7 6 5 4 3 2 1 140pA/DIV 1s/DIV 0 0.01 0.1 1 10 WARM-UP TIME (minutes) Figure 14. 0.1 Hz to 10 Hz Current Noise Figure 17. Change in Offset Voltage, RTI vs. Warmup Time Rev. B | Page 9 of 24 NOISE (pA/√Hz) 06287-014 06287-012 06287-013 CHANGE IN OFFSET VOLTAGE, RTI (µV) PSRR (dB) PSRR (dB) 06287-117 06287-017 06287-016 AD8251 20 15 15 10 I + B 10 5 5 0 I – B 0 –5 I OS –5 –10 –10 –15 –60 –40 –20 0 20 40 60 80 100 120 140 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (ºC) TEMPERATURE (°C) Figure 18. Input Bias Current and Offset Current vs. Temperature Figure 21. ΔCMRR vs. Temperature, G = 1 140 25 V = ±15V S G = 4 G = 8 V = 200mV p-p IN 20 R = 2kΩ G = 8 L 120 15 G = 4 100 G = 2 10 G = 2 5 80 G = 1 G = 1 0 60 –5 40 –10 10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. CMRR vs. Frequency Figure 22. Gain vs. Frequency 140 40 30 120 20 G = 8 10 100 G = 4 0 G = 2 80 G = 1 –10 –20 60 –30 40 –40 10 100 1k 10k 100k 1M –10 –8 –6 –4 –2 02468 10 OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, RL = 10 kΩ, 2 kΩ, 600 Ω Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance Rev. B | Page 10 of 24 CMRR (dB) CMRR (dB) INPUT BIAS CURRENT AND OFFSET CURRENT (nA) 06287-021 06287-020 06287-019 GAIN (dB) ∆CMRR (µV/V) GAIN NONLINEARITY (10ppm/DIV) 06287-024 06287-023 06287-022 AD8251 16 40 0V, +13.5V 30 12 –14.2V, +7.1V +14V, +7V 0V, ±15V 20 8 0V, +3.85V –4V, +2.2V +4V, +2V 10 4 0 V = ±5V 0 S –10 –4V, –2V +4V, –2V –4 0V, –3.9V –20 –8 –30 –12 –14.2V, –7.1V +14V, –7V 0V, –13.5V –40 –16 –10 –8 –6 –4 –2 02468 10 –16 16 –12 –8 –4 0 4 8 12 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity vs. Output Voltage, G = 2, RL = 10 kΩ, 2 kΩ, 600 Ω Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1 40 16 –13V, +13.5V 0V, +13.5V +13V, +13V 30 12 V ±15V S 20 8 –4V, +4V 0V, +4V +4V, +3.9V 10 4 0 V = ±5V 0 S –10 –4 –4V, –3.9V 0V, –3.9V +4V, –4V –20 –8 –30 –12 –13V, –13.1V 0V, –13.5V +13V, –13.5V –40 –16 –10 –8 –6 –4 –2 02468 10 –16 16 –12 –8 –4 0 4 8 12 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 8 Figure 25. Gain Nonlinearity vs. Output Voltage, G = 4, RL = 10 kΩ, 2 kΩ, 600 Ω 40 35 I + B I – 30 B 30 I OS 20 25 10 20 0 15 –10 10 –20 5 –30 –40 0 –10 –8 –6 –4 –2 02468 10 –15 –10 –501 5 015 OUTPUT VOLTAGE (V) COMMON-MODE VOLTAGE (V) Figure 26. Gain Nonlinearity vs. Output Voltage, G = 8, RL = 10 kΩ, 2 kΩ, 600 Ω Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage Rev. B | Page 11 of 24 GAIN NONLINEARITY (10ppm/DIV) GAIN NONLINEARITY (10ppm/DIV) GAIN NONLINEARITY (10ppm/DIV) 06287-027 06287-026 06287-025 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) INPUT BIAS CURRENT AND OFFSET CURRENT (nA) 06287-129 06287-029 06287-028 +85°C 5°C +8 +25°C +25°C AD8251 +V +V S S +85°C +125°C –0.2 +125°C +85°C –0.4 –1 –0.6 +25°C –40°C –0.8 –2 –1.0 –40°C –40°C 1.0 +2 –40°C 0.8 +25°C 0.6 +1 +85°C 0.4 +125°C 0.2 +125°C +85°C –V –V S S 416 416 6 8 10 12 14 6 8 10 12 14 SUPPLY VOLTAGE (±V ) SUPPLY VOLTAGE (±V ) S S Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF = 0 V, RL = 10 kΩ Figure 33. Output Voltage Swing vs. Supply Voltage, G = 8, RL = 10 kΩ 15 15 +25°C +V S 10 +85°C 10 –40°C +125°C FAULT CONDITION FAULT CONDITION (OVER DRIVEN INPUT) (OVER DRIVEN INPUT) 5 G = 8 G = 8 5 +IN 0 0 –IN –5 –5 +125°C –40°C –10 –10 +85°C –V S +25°C –15 –15 –16 –12 –8 –4 0 4 8 12 16 100 1k 10k DIFFERENTIAL INPUT VOLTAGE (V) LOAD RESISTANCE (Ω) Figure 31. Fault Current Draw vs. Input Voltage, G = 8, R = 10 kΩ Figure 34. Output Voltage Swing vs. Load Resistance L +V +V S S –0.2 +85°C –0.4 +125°C –0.4 +125°C –0.8 –0.6 –0.8 –1.2 +25°C –1.0 –40°C –1.6 –40°C +25°C –2.0 +25°C –40°C 2.0 –40°C 1.6 1.0 +25°C 1.2 0.8 0.6 0.8 +125°C 0.4 +125°C 0.4 +85°C 0.2 –V –V S S 41 6 8 10 12 146 41 6 8 10 12 146 SUPPLY VOLTAGE (±V ) OUTPUT CURRENT (mA) S Figure 32. Output Voltage Swing vs. Supply Voltage, G = 8, RL = 2 kΩ Figure 35. Output Voltage Swing vs. Output Current Rev. B | Page 12 of 24 OUTPUT VOLTAGE SWING (V) INPUT VOLTAGE (V) CURRENT (mA) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 06287-031 06287-030 06287-032 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 06287-034 06287-035 06287-033 AD8251 100pF NO 47pF LOAD 5V/DIV 376ns TO 0.01% 640ns TO 0.001% 0.002%/DIV 20mV/DIV 2µs/DIV 2µs/DIV Figure 39. Large Signal Pulse Response and Settling Time, Figure 36. Small Signal Pulse Response for Various Capacitive Loads G = 4, RL = 10 kΩ 5V/DIV 5V/DIV 364ns TO 0.01% 585ns TO 0.01% 522ns TO 0.001% 723ns TO 0.001% 0.002%/DIV 0.002%/DIV 2µs/DIV 2µs/DIV Figure 40. Large Signal Pulse Response and Settling Time, Figure 37. Large Signal Pulse Response and Settling Time, G = 8, R = 10 kΩ G = 1, R = 10 kΩ L L 5V/DIV 400ns TO 0.01% 600ns TO 0.001% 0.002%/DIV 2µs/DIV 25mV/DIV 2µs/DIV Figure 41. Small Signal Response, Figure 38. Large Signal Pulse Response and Settling Time, G = 1, R = 2 kΩ, C = 100 pF L L G = 2, RL = 10 kΩ Rev. B | Page 13 of 24 06287-038 06287-037 06287-036 06287-041 06287-040 06287-039 AD8251 1200 1000 SETTLED TO 0.001% 800 600 SETTLED TO 0.01% 400 200 25mV/DIV 2µs/DIV 0 22 4 6 8 10121416180 STEP SIZE (V) Figure 42. Small Signal Response, Figure 45. Settling Time vs. Step Size, G = 1, R = 10 kΩ L G = 2, RL = 2 kΩ, CL = 100 pF 1200 1000 800 SETTLED TO 0.001% 600 400 SETTLED TO 0.01% 200 25mV/DIV 2µs/DIV 0 22 4 6 8 101214 16180 STEP SIZE (V) Figure 46. Settling Time vs. Step Size, G = 2, R = 10 kΩ Figure 43. Small Signal Response, L G = 4, RL = 2 kΩ, CL = 100 pF 1200 1000 800 SETTLED TO 0.001% 600 400 SETTLED TO 0.01% 200 25mV/DIV 2µs/DIV 0 22 4 6 8 101214 16180 STEP SIZE (V) Figure 44. Small Signal Response, Figure 47. Settling Time vs. Step Size, G = 4, R = 10 kΩ L G = 8, R = 2 kΩ, C = 100 pF L L Rev. B | Page 14 of 24 06287-044 06287-042 06287-043 TIME (ns) TIME (ns) TIME (ns) 06287-047 06287-046 06287-045 AD8251 –50 1200 –55 –60 1000 –65 –70 800 –75 –80 G = 8 SETTLED TO 0.001% –85 G = 4 G = 2 600 –90 –95 400 –100 SETTLED TO 0.01% –105 200 –110 G = 1 –115 0 –120 10 100 1k 10k 100k 1M 22 4 6 8 101214 16180 STEP SIZE (V) FREQUENCY (Hz) Figure 48. Settling Time vs. Step Size, G = 8, R = 10 kΩ Figure 50. Total Harmonic Distortion + Noise vs. Frequency, L 10 Hz to 500 kHz Band-Pass Filter, R = 2 kΩ L –50 –55 –60 –65 –70 –75 –80 –85 G = 8 –90 G = 4 –95 –100 –105 –110 G = 2 –115 G = 1 –120 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 49. Total Harmonic Distortion + Noise vs. Frequency, 10 Hz to 22 kHz Band-Pass Filter, R = 2 kΩ L Rev. B | Page 15 of 24 THD + N (dB) TIME (ns) 06287-048 06287-049 THD + N (dB) 06287-050 AD8251 THEORY OF OPERATION +V +V S S A0 A1 2.2kΩ +V S –V –V S S 2.2kΩ –IN 10kΩ 10kΩ A1 –V S +V S DIGITAL GAIN A3 OUT CONTROL –V S +V S +V S 10kΩ 10kΩ A2 REF +IN 2.2kΩ –V S +V +V S S –V S 2.2kΩ WR DGND –V –V S S Figure 51. Simplified Schematic The AD8251 is a monolithic instrumentation amplifier based Transparent Gain Mode on the classic 3-op-amp topology, as shown in Figure 51. It is The easiest way to set the gain is to program it directly via a fabricated on the Analog Devices, Inc., proprietary iCMOS® logic high or logic low voltage applied to A0 and A1. Figure 52 process that provides precision, linear performance, and a shows an example of this gain setting method, referred to through- robust digital interface. A parallel interface allows users to out the data sheet as transparent gain mode. Tie WR to the negative digitally program gains of 1, 2, 4, and 8. Gain control is achieved supply to engage transparent gain mode. In this mode, any change by switching resistors in an internal, precision resistor array (as in voltage applied to A0 and A1 from logic low to logic high, or shown in Figure 51). Although the AD8251 has a voltage feedback vice versa, immediately results in a gain change. Table 5 is the topology, the gain bandwidth product increases for gains of 1, 2, truth table for transparent gain mode, and Figure 52 shows the and 4 because each gain has its own frequency compensation. AD8251 configured in transparent gain mode. This results in maximum bandwidth at higher gains. +15V All internal amplifiers employ distortion cancellation circuitry 10μF0.1µF and achieve high linearity and ultralow THD. Laser trimmed WR –15V resistors allow for a maximum gain error of less than 0.03% A1 +5V A0 for G = 1 and minimum CMRR of 98 dB for G = 8. A pinout +IN +5V G = 8 optimized for high CMRR over frequency enables the AD8251 to offer a guaranteed minimum CMRR over frequency of 80 dB AD8251 at 50 kHz (G = 1). The balanced input reduces the parasitics REF that, in the past, adversely affected CMRR performance. –IN DGND DGND GAIN SELECTION 10μF0.1µF Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high –15V is 5 V; both voltages are measured with respect to DGND. See NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V . S Table 2 for the permissible voltage range of DGND. The gain of THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE the AD8251 can be set using two methods. SET TO LOGIC HIGH, RESULTING IN A GAIN OF 8. Figure 52. Transparent Gain Mode, A0 and A1 = High, G = 8 Rev. B | Page 16 of 24 06287-061 06287-051 AD8251 Table 5. Truth Table Logic Levels for Transparent Gain Mode Table 6. Truth Table Logic Levels for Latched Gain Mode WR A1 A0 Gain WR A1 A0 Gain −VS Low Low 1 High to low Low Low Change to 1 −VS Low High 2 High to low Low High Change to 2 −V High Low 4 S High to low High Low Change to 4 −V High High 8 S High to low High High Change to 8 1 1 Low to low X X No change 1 1 Latched Gain Mode Low to high X X No change 1 1 High to high X X No change Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation 1 X = don’t care. amplifiers on the same PCB. In such cases, devices can share a On power-up, the AD8251 defaults to a gain of 1 when in latched data bus. The gain of the AD8251 can be set using WR as a latch, gain mode. In contrast, if the AD8251 is configured in transparent allowing other devices to share A0 and A1. Figure 53 shows a gain mode, it starts at the gain indicated by the voltage levels on schematic using this method, known as latched gain mode. The A0 and A1 at power-up. WR AD8251 is in this mode when is held at logic high or logic Timing for Latched Gain Mode low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 In latched gain mode, logic levels at A0 and A1 must be held for WR are read on the downward edge of the signal as it transitions a minimum setup time, t , before the downward edge of WR SU from logic high to logic low. This latches in the logic levels on latches in the gain. Similarly, they must be held for a minimum A0 and A1, resulting in a gain change. See the truth table in WR hold time of tHD after the downward edge of to ensure that Table 6 for more information on these gain changes. the gain is latched in correctly. After t , A0 and A1 can change +15V HD WR +5V logic levels, but the gain does not change (until the next WR 0V 10μF0.1µF downward edge of WR). The minimum duration that WR can +5V A1 A1 0V be held high is t , and the minimum duration that WR WR-HIGH A0 +5V A0 0V +IN can be held low is t WR-LOW. Digital timing specifications are + G = PREVIOUS G = 8 listed in Table 2. The time required for a gain change is STATE AD8251 dominated by the settling time of the amplifier. A timing REF diagram is shown in Figure 54. – –IN When sharing a data bus with other devices, logic levels applied DGND DGND to those devices can potentially feed through to the output of 10μF0.1µF the AD8251. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the –15V PCB also reduces coupling between the digital and analog portions NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS of the board. Pull-up or pull-down resistors should be used to FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A provide a well-defined voltage at the A0 and A1 pins. GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8. Figure 53. Latched Gain Mode, G = 8 t t WR-HIGH WR-LOW WR t t SU HD A0, A1 Figure 54. Timing Diagram for Latched Gain Mode Rev. B | Page 17 of 24 06287-052 06287-053 AD8251 INCORRECT CORRECT POWER SUPPLY REGULATION AND BYPASSING +V +V S S The AD8251 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect per- formance. As in all linear circuits, bypass capacitors must be AD8251 AD8251 used to decouple the amplifier. REF REF Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum capacitor can be used farther away from the part (see Figure 55) –V –V S S and, in most cases, it can be shared by other precision integrated TRANSFORMER TRANSFORMER circuits. +V +V S S +V S 0.1µF 10µF WR A1 AD8251 AD8251 A0 +IN REF REF OUT 10MΩ AD8251 LOAD –V –V S S REF –IN THERMOCOUPLE THERMOCOUPLE DGND +V +V S S 0.1µF 10µF C C –V DGND S 1 R f = HIGH-PASS Figure 55. Supply Decoupling, REF, and Output Referred to Ground AD8251 2πRC AD8251 C C REF REF INPUT BIAS CURRENT RETURN PATH R The AD8251 input bias current must have a return path to its –V –V local analog ground. When the source, such as a thermocouple, S S CAPACITIVELY COUPLED CAPACITIVELY COUPLED cannot provide a return current path, one should be created Figure 56. Creating an IBIAS Return Path (see Figure 56). INPUT PROTECTION All terminals of the AD8251 are protected against ESD. Note that 2.2 kΩ series resistors precede the ESD diodes as shown in Figure 51. The resistors limit current into the diodes and allow for dc overload conditions 13 V above the positive supply and 13 V below the negative supply. An external resistor should be used in series with each input to limit current for voltages greater than 13 V beyond either supply rail. In either scenario, the AD8251 safely handles a continuous 6 mA current at room temperature. For applications where the AD8251 encounters extreme overload voltages, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used. Rev. B | Page 18 of 24 06287-054 06287-055 AD8251 The output voltage of the AD8251 develops with respect to the REFERENCE TERMINAL potential on the reference terminal. Take care to tie REF to the The reference terminal, REF, is at one end of a 10 kΩ resistor appropriate local analog ground or to connect it to a voltage that (see Figure 51). The instrumentation amplifier output is referenced is referenced to the local analog ground. to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog Coupling Noise ground. For example, a voltage source can be tied to the REF To prevent coupling noise onto the AD8251, follow these pin to level shift the output so that the AD8251 can interface guidelines: with a single-supply ADC. The allowable reference voltage • Do not run digital lines under the device. range is a function of the gain, common-mode input, and supply voltages. The REF pin should not exceed either +VS • Run the analog ground plane under the AD8251. or −VS by more than 0.5 V. • Shield fast switching signals with digital ground to avoid For best performance, especially in cases where the output is radiating noise to other sections of the board, and never not measured with respect to the REF terminal, source imped- run them near analog signal paths. ance to the REF terminal should be kept low because parasitic • Avoid crossover of digital and analog signals. resistance can adversely affect CMRR and gain accuracy. • Connect digital and analog ground at one point only INCORRECT CORRECT (typically under the ADC). • Use large traces on the power supply lines to ensure a low AD8251 AD8251 impedance path. Decoupling is necessary; follow the V REF guidelines listed in the Power Supply Regulation and V REF Bypassing section. + Common-Mode Rejection OP1177 The AD8251 has high CMRR over frequency, giving it greater – immunity to disturbances, such as line noise and its associated harmonics, in contrast to typical instrumentation amplifiers Figure 57. Driving the Reference Pin whose CMRR falls off around 200 Hz. The typical instrumentation COMMON-MODE INPUT VOLTAGE RANGE amplifiers often need common-mode filters at their inputs to The 3-op-amp architecture of the AD8251 applies gain and then compensate for this shortcoming. The AD8251 is able to reject removes the common-mode voltage. Therefore, internal nodes CMRR over a greater frequency range, reducing the need for in the AD8251 experience a combination of both the gained input common-mode filtering. signal and the common-mode signal. This combined signal Careful board layout maximizes system performance. To can be limited by the voltage supplies even when the individual maintain high CMRR over frequency, lay out the input traces input and output signals are not. Figure 27 and Figure 28 show symmetrically. Ensure that the traces maintain resistive and the allowable common-mode input voltage ranges for various capacitive balance; this holds for additional PCB metal layers output voltages, supply voltages, and gains. under the input pins and traces. Source resistance and capaci- tance should be placed as close to the inputs as possible. Should LAYOUT a trace cross the inputs (from another layer), it should be routed Grounding perpendicular to the input traces. In mixed-signal circuits, low level analog signals need to be isolated from the noisy digital environment. Designing with the AD8251 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PCB can cause errors. Therefore, use separate analog and digital ground planes. Analog and digital ground should meet at one point only: star ground. Rev. B | Page 19 of 24 06287-056 AD8251 RF INTERFERENCE DRIVING AN ADC RF rectification is often a problem when amplifiers are used in An instrumentation amplifier is often used in front of an ADC applications where there are strong RF signals. The disturbance to provide CMRR. Usually, instrumentation amplifiers require a can appear as a small dc offset voltage. High frequency signals buffer to drive an ADC. However, the low output noise, low can be filtered with a low-pass RC network placed at the input distortion, and low settle time of the AD8251 make it an of the instrumentation amplifier, as shown in Figure 58. The excellent ADC driver. filter limits the input signal bandwidth according to the following In Figure 59, a 1 nF capacitor and a 49.9 Ω resistor create an relationship: antialiasing filter for the AD7612. The 1 nF capacitor stores and 1 delivers the necessary charge to the switched capacitor input of FilterFreq = DIFF the ADC. The 49.9 Ω series resistor reduces the burden of the 2 π R(2C + C ) D C 1 nF load from the amplifier and isolates it from the kickback 1 current injected from the switched capacitor input of the AD7612. FilterFreq = CM 2 π RC Selecting too small a resistor improves the correlation between C the voltage at the output of the AD8251 and the voltage at the where CD ≥ 10 CC. input of the AD7612 but may destabilize the AD8251. A trade- +15V off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. 0.1µF 10µF +15V C C R +IN 10μF0.1µF WR +12V –12V V A1 OUT C D AD8251 A0 +IN 0.1μF 0.1μF R REF –IN 49.9Ω AD8251 AD7612 C C 1nF REF 0.1µF 10µF +5V –IN ADR435 DGND DGND –15V 10μF0.1µF Figure 58. RFI Suppression Values of R and C should be chosen to minimize RFI. A C –15V mismatch between the R × C at the positive input and the C Figure 59. Driving an ADC R × CC at negative input degrades the CMRR of the AD8251. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved. Rev. B | Page 20 of 24 06287-057 06287-058 AD8251 APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER +15V In certain applications, it is necessary to create a differential signal. High resolution ADCs often require a differential input. 10μF0.1µF In other cases, transmission over a long distance can require WR MICRO- A1 differential signals for better immunity to interference. CONTROLLER A0 +IN + Figure 61 shows how to configure the AD8251 to output a differential signal. An op amp, the AD817, is used in an AD8251 inverting topology to create a differential voltage. VREF sets the REF – output midpoint according to the equation shown in the figure. –IN Errors from the op amp are common to both outputs and are DGND DGND thus common mode. Likewise, errors from using mismatched 10μF0.1µF resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input –15V ADCs or instrumentation amplifiers. Figure 60. Programming Gain Using a Microcontroller When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC. +12V 0.1μF AMPLITUDE WR +5V A1 A0 +IN AMPLITUDE –5V + V A = V + V OUT IN REF 2 +2.5V AD8251 0V V IN G = 1 –2.5V TIME REF – 4.99kΩ 0.1μF DGND – + V REF 0V –12V –12V +12V AD817 4.99kΩ 10pF AMPLITUDE 0.1µF 0.1µF +12V –12V +2.5V 10μF 10μF 0V 0V DGND –2.5V V B = –V + V OUT IN REF TIME 2 Figure 61. Differential Output with Level Shift Rev. B | Page 21 of 24 06287-060 06287-059 13 AD8251 –70 DATA ACQUISITION –80 The AD8251 makes an excellent instrumentation amplifier –90 for use in data acquisition systems. Its wide bandwidth, low –100 distortion, low settling time, and low noise enable it to –110 condition signals in front of a variety of 16-bit ADCs. –120 Figure 63 shows a schematic of the AD825x data acquisition –130 demonstration board. The quick slew rate of the AD8251 allows –140 it to condition rapidly changing signals from the multiplexed –150 inputs. An FPGA controls the AD7612, AD8251, and ADG1209. –160 In addition, mechanical switches and jumpers allow users to pin –170 strap the gains when in transparent gain mode. –180 This system achieved −106 dB of THD at 1 kHz and a signal-to-050 5 10 15 202530354045 FREQUENCY (kHz) noise ratio of 91 dB during testing, as shown in Figure 62. Figure 62. FFT of the AD825x DAQ Demo Board Using the AD8251 1 kHz Signal JMP JMP –V S +12V –12V +12V + + +5V 0.1µF 2kΩ 10µF 10µF 14 GND V 2 DD DGND 806Ω EN DGND JMP 4 +CH1 S1A 806Ω +5V DGND +CH2 5 S2A 2kΩ 806Ω 2 ALTERA +CH3 6 S3A 6 DGND EPF6010ATC144-3 806Ω 0Ω 0Ω C 5 +CH4 7 S4A C WR DGND +IN DA 8 10 + 4 A1 ADG1209 OUT 806Ω A0 +IN AD8251 7 AD7612 –CH4 C 10 S4B D REF 0Ω 0Ω 0Ω 49.9Ω –IN 1nF 806Ω 9 DB 9 1 –V – S –CH3 11 S3B +V S 3 806Ω ADR435 15 GND –CH2 12 S2B 8 806Ω A0 –CH1 S1B 1 A1 C4 C3 0.1µF V 16 SS 0.1µF 3 +12V –12V JMP 0.1µF +5V –12V 2kΩ DGND JMP +5V R8 2kΩ DGND Figure 63. Schematic of ADG1209, AD8251, and AD7612 in the AD825x DAQ Demo Board Rev. B | Page 22 of 24 C C AMPLITUDE (dB) 06287-067 06287-062 AD8251 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA Figure 64. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8251ARMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H0T AD8251ARMZ-RL −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H0T AD8251ARMZ-R7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H0T AD8251-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 23 of 24 091709-A AD8251 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06287-0-11/10(B) Rev. B | Page 24 of 24