ANALOG DEVICES AD8250

10 MHz, 20 V/μs, G = 1, 2, 5, 10 iCMOS Programmable Gain Instrumentation Amplifier AD8250 FEATURES FUNCTIONAL BLOCK DIAGRAM DGND WR A1 A0 Small package: 10-lead MSOP 2 6 5 4 Programmable gains: 1, 2, 5, 10 LOGIC Digital or pin-programmable gain setting –IN 1 Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR 98 dB (minimum), G = 10 7 OUT Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.7 μV/°C (maximum), G = 10 Excellent ac performance +IN 10 Fast settling time: 615 ns to 0.001% (maximum) AD8250 High slew rate: 20 V/μs (minimum) 8 3 Low distortion: −110 dB THD at 1 kHz 9 +V –V REF S S High CMRR over frequency: 80 dB to 50 kHz (minimum) Figure 1. Low noise: 18 nV/√Hz, G = 10 (maximum) Low power: 4.1 mA 25 G = 10 APPLICATIONS 20 Data acquisition G = 5 15 Biomedical analysis Test and measurement 10 G = 2 5 GENERAL DESCRIPTION G = 1 0 The AD8250 is an instrumentation amplifier with digitally programmable gains that has GΩ input impedance, low output –5 noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters –10 1k 10k 100k 1M 10M 100M (ADCs). It has a high bandwidth of 10 MHz, low THD of −110 FREQUENCY (Hz) dB and fast settling time of 615 ns (maximum) to 0.001%. Offset Figure 2. Gain vs. Frequency drift and gain drift are guaranteed to 1.7 μV/°C and 10 ppm/°C, respectively, for G = 10. In addition to its wide input common Table 1. Instrumentation Amplifiers by Category voltage range, it boasts a high common-mode rejection of 80 dB General Mil Low High Speed at G = 1 from dc to 50 kHz. The combination of precision dc Purpose Zero Drift Grade Power PGA performance coupled with high speed capabilities makes the 1 1 1 AD8220 AD8231 AD620 AD627 AD8250 AD8250 an excellent candidate for data acquisition. Furthermore, 1 1 AD8221 AD8553 AD621 AD623 AD8251 1 1 this monolithic solution simplifies design and manufacturing AD8222 AD8555 AD524 AD8223 AD8253 1 1 and boosts performance of instrumentation by maintaining a AD8224 AD8556 AD526 1 AD8228 AD8557 AD624 tight match of internal resistors and amplifiers. 1 Rail-to-rail output. The AD8250 user interface consists of a parallel port that allows users to set the gain in one of two ways (see Figure 1). A 2-bit word The AD8250 is available in a 10-lead MSOP package and is sent via a bus can be latched using the WR input. An alternative is specified over the −40°C to +85°C temperature range, making to use the transparent gain mode where the state of the logic levels it an excellent solution for applications where size and packing at the gain port determines the gain. density are important considerations. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 06288-001 06288-023 AD8250 TABLE OF CONTENTS Features .............................................................................................. 1 Input Bias Current Return Path ............................................... 17 Applications....................................................................................... 1 Input Protection ......................................................................... 17 General Description ......................................................................... 1 Reference Terminal .................................................................... 18 Functional Block Diagram .............................................................. 1 Common-Mode Input Voltage Range ..................................... 18 Revision History ............................................................................... 2 Layout .......................................................................................... 18 Specifications..................................................................................... 3 RF Interference ........................................................................... 19 Timing Diagram ........................................................................... 5 Driving an ADC ......................................................................... 19 Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 20 Maximum Power Dissipation ..................................................... 6 Differential Output .................................................................... 20 ESD Caution.................................................................................. 6 Setting Gains with a Microcontroller ...................................... 20 Pin Configuration and Function Descriptions............................. 7 Data Acquisition......................................................................... 21 Typical Performance Characteristics ............................................. 8 Outline Dimensions....................................................................... 22 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 22 Gain Selection ............................................................................. 15 Power Supply Regulation and Bypassing ................................ 17 REVISION HISTORY 11/10—Rev. A to Rev. B Changes to Figure 24 to Figure 26................................................ 11 Changes to Voltage Offset, Offset RTI V , Average Added Figure 29 ............................................................................. 11 OS Temperature Coefficient Parameter in Table 2............................. 3 Changes to Figure 31...................................................................... 12 Updated Outline Dimensions ....................................................... 22 Deleted Figure 43 to Figure 46; Renumbered Sequentially ...... 14 Inserted Figure 45 and Figure 46.................................................. 14 5/08—Rev. 0 to Rev. A Changes to Timing for Latched Gain Mode Section ................. 16 Changes to Table 1............................................................................ 1 Changes to Layout Section and Coupling Noise Section.......... 18 Changes to Table 2............................................................................ 3 Changes to Figure 59...................................................................... 21 Changes to Table 3............................................................................ 6 Added Figure 17; Renumbered Sequentially ................................ 9 1/07—Revision 0: Initial Version Changes to Figure 23...................................................................... 10 Rev. B | Page 2 of 24 AD8250 SPECIFICATIONS +VS = 15 V, −VS = −15 V, VREF = 0 V @ TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 kΩ Source Imbalance +IN = −IN = −10 V to +10 V G = 1 80 98 dB G = 2 86 104 dB G = 5 94 110 dB G = 10 98 110 dB CMRR to 50 kHz +IN = −IN = −10 V to +10 V G = 1 80 dB G = 2 86 dB G = 5 90 dB G = 10 90 dB NOISE Voltage Noise, 1 kHz, RTI G = 1 40 nV/√Hz G = 2 27 nV/√Hz G = 5 21 nV/√Hz G = 10 18 nV/√Hz 0.1 Hz to 10 Hz, RTI G = 1 2.5 μV p-p G = 2 2.5 μV p-p G = 5 1.5 μV p-p G = 10 1.0 μV p-p Current Noise, 1 kHz 5 pA/√Hz Current Noise, 0.1 Hz to 10 Hz 60 pA p-p VOLTAGE OFFSET Offset RTI VOS G = 1, 2, 5, 10 ±(70 + 200/G) ±(200 + 600/G) μV Over Temperature T = −40°C to +85°C ±(90 + 300/G) ±(260 + 900/G) μV Average Temperature Coefficient T = −40°C to +85°C ±(0.6 + 1.5/G) ±(1.2 + 5/G) μV/°C Offset Referred to the Input vs. Supply (PSR) V = ±5 V to ±15 V ±(2 + 7/G) ±(6 + 20/G) μV/V S INPUT CURRENT Input Bias Current 5 30 nA Over Temperature T = −40°C to +85°C 40 nA Average Temperature Coefficient T = −40°C to +85°C 400 pA/°C Input Offset Current 5 30 nA Over Temperature T = −40°C to +85°C 30 nA Average Temperature Coefficient T = −40°C to +85°C 160 pA/°C DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 10 MHz G = 2 10 MHz G = 5 10 MHz G = 10 3 MHz Settling Time 0.01% ΔOUT = 10 V step G = 1 585 ns G = 2 605 ns G = 5 605 ns G = 10 648 ns Rev. B | Page 3 of 24 AD8250 Parameter Conditions Min Typ Max Unit Settling Time 0.001% ΔOUT = 10 V step G = 1 615 ns G = 2 635 ns G = 5 635 ns G = 10 685 ns Slew Rate G = 1 20 V/μs G = 2 25 V/μs G = 5 25 V/μs G = 10 25 V/μs Total Harmonic Distortion f = 1 kHz, R = 10 kΩ, ±10 V, −110 dB L G = 1, 10 Hz to 22 kHz band-pass filter GAIN Gain Range G = 1, 2, 5, 10 1 10 V/V Gain Error OUT = ±10 V G = 1 0.03 % G = 2, 5, 10 0.04 % Gain Nonlinearity OUT = −10 V to +10 V G = 1 R = 10 kΩ, 2 kΩ, 600 Ω 6 ppm L G = 2 RL = 10 kΩ, 2 kΩ, 600 Ω 8 ppm G = 5 RL = 10 kΩ, 2 kΩ, 600 Ω 8 ppm G = 10 RL = 10 kΩ, 2 kΩ, 600 Ω 10 ppm Gain vs. Temperature All gains 10 ppm/°C INPUT Input Impedance Differential 5.3||0.5 GΩ||pF Common Mode 1.25||2 GΩ||pF Input Operating Voltage Range VS = ±5 V to ±15 V −VS + 1.5 +VS − 1.5 V Over Temperature T = −40°C to +85°C −V + 1.6 +V − 1.7 V S S OUTPUT Output Swing −13.5 +13.5 V Over Temperature T = −40°C to +85°C −13.5 +13.5 V Short-Circuit Current 37 mA REFERENCE INPUT R 20 kΩ IN I +IN, −IN, REF = 0 1 μA IN Voltage Range −V +V V S S Gain to Output 1 ± 0.0001 V/V DIGITAL LOGIC Digital Ground Voltage, DGND Referred to GND −V + 4.25 0 +V − 2.7 V S S Digital Input Voltage Low Referred to GND DGND 2.1 V Digital Input Voltage High Referred to GND 2.8 +VS V Digital Input Current 1 μA 1 Gain Switching Time 325 ns t See Figure 3 timing diagram 20 ns SU tHD See Figure 3 timing diagram 10 ns See Figure 3 timing diagram 20 ns t WR -LOW See Figure 3 timing diagram 40 ns t WR -HIGH Rev. B | Page 4 of 24 AD8250 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range ±5 ±15 V Quiescent Current, +IS 4.1 4.5 mA Quiescent Current, −I 3.7 4.5 mA S Over Temperature T = −40°C to +85°C 4.5 mA TEMPERATURE RANGE Specified Performance −40 +85 °C 1 Add time for the output to slew and settle to calculate the total time for a gain change. TIMING DIAGRAM t t WR-HIGH WR-LOW WR t t SU HD A0, A1 Figure 3. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section) Rev. B | Page 5 of 24 06288-057 AD8250 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (PD) is the sum of the Table 3. quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage ±17 V power is the voltage between the supply pins (VS) times the Power Dissipation See Figure 4 quiescent current (I ). Assuming that the load (R ) is referenced S L 1 Output Short-Circuit Current Indefinite to midsupply, the total drive power is V /2 × I , some of which S OUT Common-Mode Input Voltage +VS + 13 V, −VS − 13 V is dissipated in the package and some in the load (V × I ). OUT OUT 2 Differential Input Voltage +VS + 13 V, −VS − 13 V Digital Logic Inputs ±VS The difference between the total drive power and the load Storage Temperature Range −65°C to +125°C power is the drive power dissipated in the package. 3 Operating Temperature Range −40°C to +85°C PD = Quiescent Power + (Total Drive Power − Load Power) Lead Temperature (Soldering, 10 sec) 300°C 2 Junction Temperature 140°C ⎛ ⎞ V V V S OUT OUT ⎜ ⎟ P =() V× I + × – D S S ⎜ ⎟ θ (Four-Layer JEDEC Standard Board) 112°C/W JA 2 R R ⎝ L ⎠ L Package Glass Transition Temperature 140°C In single-supply operation with RL referenced to −VS, the worst 1 Assumes that the load is referenced to midsupply. 2 case is VOUT = VS/2. Current must be kept to less than 6 mA. 3 Temperature for specified performance is −40°C to +85°C. For performance to 125°C, see the Typical Performance Characteristics section. Airflow increases heat dissipation, effectively reducing θ . In JA addition, more metal directly in contact with the package leads Stresses above those listed under Absolute Maximum Ratings from metal traces, through holes, ground, and power planes may cause permanent damage to the device. This is a stress reduces the θ . JA rating only; functional operation of the device at these or any Figure 4 shows the maximum safe power dissipation in the other conditions above those indicated in the operational section of package vs. the ambient temperature on a four-layer JEDEC this specification is not implied. Exposure to absolute maximum standard board. rating conditions for extended periods may affect device reliability. 2.00 MAXIMUM POWER DISSIPATION 1.75 The maximum safe power dissipation in the AD8250 package is limited by the associated rise in junction temperature (TJ) on 1.50 the die. The plastic encapsulating the die locally reaches the 1.25 junction temperature. At approximately 140°C, which is the glass transition temperature, the plastic changes its properties. 1.00 Even temporarily exceeding this temperature limit can change 0.75 the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8250. Exceeding 0.50 a junction temperature of 140°C for an extended period can 0.25 result in changes in silicon devices, potentially causing failure. 0 –40 –20 0 20 40 60 80 100 120 The still-air thermal properties of the package and PCB (θJA), AMBIENT TEMPERATURE (°C) the ambient temperature (TA), and the total power dissipated in Figure 4. Maximum Power Dissipation vs. Ambient Temperature the package (P ) determine the junction temperature of the die. D The junction temperature is calculated as ESD CAUTION T = T + (P × θ ) J A D JA Rev. B | Page 6 of 24 MAXIMUM POWER DISSIPATION (W) 06288-004 AD8250 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 10 +IN DGND 2 9 REF AD8250 –V 3 8 +V S TOP VIEW S (Not to Scale) A0 4 7 OUT 5 6 A1 WR Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Inverting Input Terminal. True differential input. 2 DGND Digital Ground. 3 −V Negative Supply Terminal. S 4 A0 Gain Setting Pin (LSB). 5 A1 Gain Setting Pin (MSB). 6 WR Write Enable. 7 OUT Output Terminal. 8 +V Positive Supply Terminal. S 9 REF Reference Voltage Terminal. 10 +IN Noninverting Input Terminal. True differential input. Rev. B | Page 7 of 24 06288-005 AD8250 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 1400 500 1200 400 1000 300 800 600 200 400 100 200 0 0 –120 –90 –60 –30 0 30 60 90 120 –30 –20 –10 0 10 20 30 INPUT OFFSET CURRENT (nA) CMRR (µV/V) Figure 9. Typical Distribution of Input Offset Current Figure 6. Typical Distribution of CMRR, G = 1 90 350 80 300 70 250 60 200 50 G = 1 40 150 G = 2 30 100 G = 5 20 G = 10 50 10 0 0 1 10 100 1k 10k 100k –200 –150 –100 –50 0 50 100 150 200 FREQUENCY (Hz) OFFSET VOLTAGE RTI (µV) Figure 7. Typical Distribution of Offset Voltage, V Figure 10. Voltage Spectral Density Noise vs. Frequency OSI 600 500 400 300 200 100 2µV/DIV 1s/DIV 0 –30 –20 –10 0 10 20 30 INPUT BIAS CURRENT (nA) Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. B | Page 8 of 24 NUMBER OF UNITS NUMBER OF UNITS NUMBER OF UNITS 06288-007 06288-006 06288-008 NOISE RTI (nV/ Hz) NUMBER OF UNITS 06288-011 06288-009 06288-010 AD8250 150 G = 10 G = 5 130 110 G = 2 G = 1 90 70 50 30 1µV/DIV 1s/DIV 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 10 Figure 15. Positive PSRR vs. Frequency, RTI 18 150 16 130 14 G = 10 110 12 G = 5 90 10 G = 2 8 70 G = 1 6 50 4 30 2 10 0 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Current Noise Spectral Density vs. Frequency Figure 16. Negative PSRR vs. Frequency, RTI 10 9 8 7 6 5 4 3 2 1 140pA/DIV 1s/DIV 0 10 0.01 0.1 1 WARMUP TIME (Minutes) Figure 14. 0.1 Hz to 10 Hz Current Noise Figure 17. Change in Offset Voltage, RTI vs. Warmup Time Rev. B | Page 9 of 24 CURRENT NOISE (pA/ Hz) 06288-014 06288-012 06288-013 PSRR (dB) PSRR (dB) CHANGE IN OFFSET VOLTAGE, RTI (µV) 06288-117 06288-017 06288-016 AD8250 10 15 8 10 6 4 I – B 5 2 0 0 I + –2 B –5 –4 I OS –6 –10 –8 –10 –15 –50 –30 –10 10 30 50 70 90 110 130 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 21. CMRR vs. Temperature, G = 1 Figure 18. Input Bias Current and Offset Current vs. Temperature 140 25 G = 10 G = 10 G = 5 20 120 G = 5 15 100 G = 1 G = 2 10 G = 2 80 5 G = 1 60 0 40 –5 –10 20 1 10 100 1k 10k 100k 1M 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. CMRR vs. Frequency Figure 22. Gain vs. Frequency 140 40 f = 1kHz G = 10 G = 5 30 120 20 100 10 G = 2 G = 1 80 0 –10 60 –20 40 –30 20 –40 –10 –8 –6 –4 –2 0 2468 10 1 10 100 1k 10k 100k 1M OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 23. Gain Nonlinearity vs. Output Voltage, G = 1, R = 10 kΩ, 2 kΩ, 600 Ω L Figure 20. CMRR vs. Frequency, 1 kΩ Source Imbalance Rev. B | Page 10 of 24 CMRR (dB) CMRR (dB) INPUT BIAS CURRENT AND OFFSET CURRENT (nA) 06288-019 06288-021 06288-020 GAIN (dB) ∆CMRR (µV/V) GAIN NONLINEARITY (10ppm/DIV) 06288-024 06288-049 06288-023 AD8250 40 16 0V, +13.8V f = 1kHz 30 12 V = ±15V S –13.8V, +6.9V +13.8V, +6.9V 20 8 0V, +3.7V 4 10 –3.8V, +1.9V +3.9V, +1.9V V = ±5V 0 0 S –3.8V, –1.9V +3.8V, –2.1V –4 –10 0V, –4.0V –8 –20 –13.8V, –6.9V +13.8V, –6.9V –12 –30 0V, –14V –40 –16 –10 –8 –6 –4 –2 0 2468 10 –16 –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 24. Gain Nonlinearity vs. Output Voltage, G = 2, RL = 10 kΩ, 2 kΩ, 600 Ω Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1 40 16 0V, +13.8V –14.1V, +13.6V +13.6V, +13.1V f = 1kHz 12 V = ±15V 30 S 8 20 +0V, +3.5V 4 10 –4.2V, +2.2V +4.3V, +2.1V 0 0 V = ±5V S –4.2V, –2.0V +4.3V, –2.1V –10 –4 0V, –4.1V –20 –8 –12 –30 –14.1V, –13.6V +13.6V, –13.1V 0V, –14V –16 –40 –10 –8 –6 –4 –2 0 2 4 6 8 10 –16 –12 –8 –4 0 4 8 12 16 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 25. Gain Nonlinearity vs. Output Voltage, G = 5, R = 10 kΩ, 2 kΩ, 600 Ω Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 10 L 40 35 f = 1kHz I + 30 B 30 I – B I 25 OS 20 20 10 15 0 10 5 –10 0 –20 –5 –30 –10 –40 –15 –10 –8 –6 –4 –2 0 2 4 6 8 10 –15 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) COMMON-MODE VOLTAGE (V) Figure 26. Gain Nonlinearity vs. Output Voltage, G = 10, R = 10 kΩ, 2 kΩ, 600 Ω L Figure 29. Input Bias Current and Offset Current vs. Common-Mode Voltage Rev. B | Page 11 of 24 GAIN NONLINEARITY (10ppm/DIV) GAIN NONLINEARITY (10ppm/DIV) GAIN NONLINEARITY (10ppm/DIV) 06288-027 06288-026 06288-025 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT BIAS CURRENT AND OFFSET CURRENT (nA) 06288-129 06288-029 06288-028 AD8250 +V +V S S –0.2 +125°C –0.4 –1 –0.6 +85°C +125°C +25°C –40°C –0.8 –2 –1.0 +25°C +85°C –40°C +25°C –40°C +1.0 +2 +0.8 +85°C –40°C +25°C +0.6 +1 +0.4 +125°C +85°C +0.2 +125°C –V –V S S 4 6 8 10 12 14 16 4 6 8 10 12 14 16 SUPPLY VOLTAGE (±V ) SUPPLY VOLTAGE (±V ) S S Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, V = 0 V, R = 10 kΩ Figure 33. Output Voltage Swing vs. Supply Voltage, G = 10, R = 10 kΩ REF L L 15 15 +25°C +V S 10 10 –40°C FAULT CONDITION FAULT CONDITION (OVER DRIVEN INPUT) (OVER DRIVEN INPUT) G = 10 G = 10 5 5 +IN +85°C +125°C 0 0 –IN +85°C –5 –5 +125°C –10 –10 –40°C –V S +25°C –15 –15 –16 –12 –8 –4 0 4 8 12 16 100 1k 10k DIFFERENTIAL INPUT VOLTAGE (V) LOAD RESISTANCE (Ω) Figure 31. Fault Current Draw vs. Input Voltage, G = 10, RL = 10 kΩ Figure 34. Output Voltage Swing vs. Load Resistance +V +V S S –0.2 +85°C +125°C –0.4 –0.4 +125°C –0.8 –0.6 –0.8 –1.2 –1.0 +25°C –40°C –1.6 +25°C +85°C –40°C –2.0 +2.0 +25°C –40°C +85°C +1.6 +1.0 +25°C –40°C +0.8 +1.2 +0.6 +0.8 +125°C +0.4 +125°C +0.4 +0.2 +85°C –V S –V S 02 4 6 8 10 12 14 16 4 6 8 10 12 14 16 SUPPLY VOLTAGE (±V ) OUTPUT CURRENT (mA) S Figure 32. Output Voltage Swing vs. Supply Voltage, G = 10, RL = 2 kΩ Figure 35. Output Voltage Swing vs. Output Current Rev. B | Page 12 of 24 OUTPUT VOLTAGE SWING INPUT VOLTAGE CURRENT (mA) REFERRED TO SUPPLY VOLTAGE (V) REFERRED TO SUPPLY VOLTAGE (V) 06288-031 06288-030 06288-032 OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGE (V) REFERRED TO SUPPLY VOLTAGE (V) 06288-035 06288-034 06288-033 AD8250 100pF NO 47pF LOAD 5V/DIV 605ns TO 0.01% 635ns TO 0.001% 0.002%/DIV 20mV/DIV 2µs/DIV 2µs/DIV TIME (µs) TIME (µs) Figure 36. Small Signal Pulse Response for Various Capacitive Loads Figure 39. Large Signal Pulse Response and Settling Time G = 5, RL = 10 kΩ 5V/DIV 5V/DIV 585ns TO 0.01% 648ns TO 0.01% 615ns TO 0.001% 685ns TO 0.001% 0.002%/DIV 0.002%/DIV 2µs/DIV 2µs/DIV TIME (µs) TIME (µs) Figure 37. Large Signal Pulse Response and Settling Time, Figure 40. Large Signal Pulse Response and Settling Time G = 1, R = 10 kΩ G = 10, R = 10 kΩ L L 5V/DIV 605ns TO 0.01% 635ns TO 0.001% 0.002%/DIV 20mV/DIV 2µs/DIV 2µs/DIV TIME (µs) TIME (µs) Figure 38. Large Signal Pulse Response and Settling Time Figure 41. Small Signal Response G = 2, RL = 10 kΩ G = 1, RL = 2 kΩ, CL = 100 pF Rev. B | Page 13 of 24 V (V) OUT 06288-038 06288-037 06288-036 V (V) OUT 06288-040 06288-039 06288-042 AD8250 –50 G = 1 –55 G = 2 –60 G = 5 G = 10 –65 –70 –75 –80 –85 –90 –95 –100 –105 –110 20mV/DIV 2µs/DIV –115 –120 TIME (µs) 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 42. Small Signal Response Figure 45. Total Harmonic Distortion + Noise vs. Frequency, G = 2, R = 2 kΩ, C = 100 pF 10 Hz to 22 kHz Band-Pass Filter, R = 2 kΩ L L L –50 G = 1 G = 2 G = 5 –60 G = 10 –70 –80 –90 –100 20mV/DIV 2µs/DIV –110 TIME (µs) 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 43. Small Signal Response Figure 46. Total Harmonic Distortion + Noise vs. Frequency, G = 5, R = 2 kΩ, C = 100 pF 10 Hz to 500 kHz Band-Pass Filter, R = 2 kΩ L L L 20mV/DIV 2µs/DIV TIME (µs) Figure 44. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF Rev. B | Page 14 of 24 V (V) V (V) V (V) OUT OUT OUT 06288-045 06288-044 06288-043 THD + N (dB) THD + N (dB) 06288-150 06288-149 AD8250 THEORY OF OPERATION +V +V S S A0 A1 2.2kΩ +V S –V –V S S 2.2kΩ –IN 10kΩ 10kΩ A1 –V S +V S DIGITAL GAIN A3 OUT CONTROL –V S +V S +V S 10kΩ 10kΩ A2 REF +IN 2.2kΩ –V S +V +V S S –V S 2.2kΩ WR DGND –V –V S S Figure 47. Simplified Schematic Transparent Gain Mode The AD8250 is a monolithic instrumentation amplifier based on the classic, 3-op-amp topology as shown in Figure 47. It is The easiest way to set the gain is to program it directly via a fabricated on the Analog Devices, Inc., proprietary iCMOS® logic high or logic low voltage applied to A0 and A1. Figure 48 process that provides precision, linear performance, and a shows an example of this gain setting method, referred to through- robust digital interface. A parallel interface allows users to out the data sheet as transparent gain mode. Tie WR to the negative digitally program gains of 1, 2, 5, and 10. Gain control is achieved supply to engage transparent gain mode. In this mode, any change by switching resistors in an internal, precision resistor array (as in voltage applied to A0 and A1 from logic low to logic high, or shown in Figure 47). Although the AD8250 has a voltage feedback vice versa, immediately results in a gain change. Table 5 is the topology, the gain bandwidth product increases for gains of 1, 2, truth table for transparent gain mode, and Figure 48 shows the and 5 because each gain has its own frequency compensation. AD8250 configured in transparent gain mode. This results in maximum bandwidth at higher gains. +15V All internal amplifiers employ distortion cancellation circuitry 10μF0.1µF and achieve high linearity and ultralow THD. Laser trimmed WR –15V A1 resistors allow for a maximum gain error of less than 0.03% +5V A0 for G = 1 and minimum CMRR of 98 dB for G = 10. A pinout +IN +5V G = 10 optimized for high CMRR over frequency enables the AD8250 AD8250 to offer a guaranteed minimum CMRR over frequency of 80 dB REF at 50 kHz (G = 1). The balanced input reduces the parasitics –IN that, in the past, adversely affected CMRR performance. DGND DGND GAIN SELECTION 10μF0.1µF Logic low and logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high –15V NOTE: is 5 V; both voltages are measured with respect to DGND. See 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −V . S THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE Table 2 for the permissible voltage range of DGND. The gain of THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10. the AD8250 can be set using two methods. Figure 48. Transparent Gain Mode, A0 and A1 = High, G = 10 Rev. B | Page 15 of 24 06288-054 06288-055 AD8250 Table 5. Truth Table Logic Levels for Transparent Gain Mode Table 6. Truth Table Logic Levels for Latched Gain Mode WR A1 A0 Gain WR A1 A0 Gain −VS Low Low 1 High to low Low Low Change to 1 −VS Low High 2 High to low Low High Change to 2 −V High Low 5 High to low High Low Change to 5 S −V High High 10 High to low High High Change to 10 S 1 1 Low to low X X No change Latched Gain Mode 1 1 Low to high X X No change Some applications have multiple programmable devices such as 1 1 High to high X X No change multiplexers or other programmable gain instrumentation 1 X = don’t care. amplifiers on the same PCB. In such cases, devices can share a On power-up, the AD8250 defaults to a gain of 1 when in latched data bus. The gain of the AD8250 can be set using WR as a latch, gain mode. In contrast, if the AD8250 is configured in transparent allowing other devices to share A0 and A1. Figure 49 shows a gain mode, it starts at the gain indicated by the voltage levels on schematic using this method, known as latched gain mode. The A0 and A1 at power-up. WR AD8250 is in this mode when is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 Timing for Latched Gain Mode WR and A1 are read on the downward edge of the signal as it In latched gain mode, logic levels at A0 and A1 have to be held transitions from logic high to logic low. This latches in the logic for a minimum setup time, tSU, before the downward edge of levels on A0 and A1, resulting in a gain change. See the truth WR latches in the gain. Similarly, they must be held for a table in Table 6 for more information on these gain changes. WR minimum hold time of tHD after the downward edge of to +15V ensure that the gain is latched in correctly. After t , A0 and A1 HD WR +5V can change logic levels, but the gain does not change (until the WR 0V 10μF0.1µF A1 +5V next downward edge of WR). The minimum duration that WR A1 0V can be held high is t WR-HIGH, and the minimum duration that A0 +5V A0 0V +IN WR can be held low is t . Digital timing specifications are WR-LOW + G = PREVIOUS G = 10 STATE listed in Table 2. The time required for a gain change is dominated AD8250 by the settling time of the amplifier. A timing diagram is shown REF – in Figure 50. –IN When sharing a data bus with other devices, logic levels applied DGND DGND 10μF0.1µF to those devices can potentially feed through to the output of the AD8250. Feedthrough can be minimized by decreasing the –15V edge rate of the logic signals. Furthermore, careful layout of the NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS PCB also reduces coupling between the digital and analog portions FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A of the board. Pull-up or pull-down resistors should be used to GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10. provide a well-defined voltage at the A0 and A1 pins. Figure 49. Latched Gain Mode, G = 10 t t WR-HIGH WR-LOW WR t t SU HD A0, A1 Figure 50. Timing Diagram for Latched Gain Mode Rev. B | Page 16 of 24 06288-056 06288-057 AD8250 INCORRECT CORRECT POWER SUPPLY REGULATION AND BYPASSING +V +V S S The AD8250 has high PSRR. However, for optimal performance, a stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect per- AD8250 AD8250 formance. As in all linear circuits, bypass capacitors must be REF REF used to decouple the amplifier. Place a 0.1 μF capacitor close to each supply pin. A 10 μF tantalum –V –V S S capacitor can be used farther away from the part (see Figure 51) TRANSFORMER TRANSFORMER and, in most cases, it can be shared by other precision integrated circuits. +V +V S S +V S 0.1µF 10µF AD8250 AD8250 WR A1 REF REF A0 +IN 10MΩ OUT AD8250 –V –V S S LOAD THERMOCOUPLE THERMOCOUPLE REF –IN +V +V S S DGND C C 0.1µF 10µF 1 R –V DGND S f = HIGH-PASS AD8250 2πRC AD8250 C C Figure 51. Supply Decoupling, REF, and Output Referred to Ground REF REF R INPUT BIAS CURRENT RETURN PATH –V –V The AD8250 input bias current must have a return path to its S S CAPACITIVELY COUPLED CAPACITIVELY COUPLED local analog ground. When the source, such as a thermocouple, Figure 52. Creating an IBIAS Return Path cannot provide a return current path, one should be created (see Figure 52). INPUT PROTECTION All terminals of the AD8250 are protected against ESD. Note that 2.2 kΩ series resistors precede the ESD diodes as shown in Figure 47. The resistors limit current into the diodes and allow for dc overload conditions 13 V above the positive supply and 13 V below the negative supply. An external resistor should be used in series with each input to limit current for voltages greater than 13 V beyond either supply rail. In either scenario, the AD8250 safely handles a continuous 6 mA current at room temperature. For applications where the AD8250 encounters extreme overload voltages, external series resistors and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s, should be used. Rev. B | Page 17 of 24 06288-058 06288-059 AD8250 REFERENCE TERMINAL The output voltage of the AD8250 develops with respect to the potential on the reference terminal. Take care to tie REF to the The reference terminal, REF, is at one end of a 10 kΩ resistor appropriate local analog ground or to connect it to a voltage that (see Figure 47). The instrumentation amplifier output is referenced is referenced to the local analog ground. to the voltage on the REF terminal; this is useful when the output signal needs to be offset to voltages other than its local analog Coupling Noise ground. For example, a voltage source can be tied to the REF To prevent coupling noise onto the AD8250, do the following pin to level shift the output so that the AD8250 can interface guidelines: with a single-supply ADC. The allowable reference voltage range is a function of the gain, common-mode input, and • Do not run digital lines under the device. supply voltages. The REF pin should not exceed either +VS or −VS by more than 0.5 V. • Run the analog ground plane under the AD8250. For best performance, especially in cases where the output is • Shield fast switching signals with digital ground to avoid not measured with respect to the REF terminal, source imped- radiating noise to other sections of the board, and never ance to the REF terminal should be kept low because parasitic run them near analog signal paths. resistance can adversely affect CMRR and gain accuracy. • Avoid crossover of digital and analog signals. INCORRECT CORRECT • Connect digital and analog ground at one point only (typically under the ADC). AD8250 AD8250 • Use the large traces on power supply lines to ensure a low V REF impedance path. Decoupling is necessary; follow the V REF guidelines listed in the Power Supply Regulation and + Bypassing section. OP1177 – Common-Mode Rejection The AD8250 has high CMRR over frequency, giving it greater Figure 53. Driving the Reference Pin immunity to disturbances, such as line noise and its associated COMMON-MODE INPUT VOLTAGE RANGE harmonics, in contrast to typical instrumentation amplifiers whose CMRR falls off around 200 Hz. Typical instrumentation The 3-op-amp architecture of the AD8250 applies gain and then amplifiers often need common-mode filters at their inputs to removes the common-mode voltage. Therefore, internal nodes compensate for this shortcoming. The AD8250 is able to reject in the AD8250 experience a combination of both the gained CMRR over a greater frequency range, reducing the need for signal and the common-mode signal. This combined signal can be input common-mode filtering. limited by the voltage supplies even when the individual input and output signals are not. Figure 27 and Figure 28 show the allowable Careful board layout maximizes system performance. To common-mode input voltage ranges for various output voltages, maintain high CMRR over frequency, lay out the input traces supply voltages, and gains. symmetrically. Ensure that the traces maintain resistive and capacitive balance; this holds for additional PCB metal layers LAYOUT under the input pins and traces. Source resistance and capaci- Grounding tance should be placed as close to the inputs as possible. Should a In mixed-signal circuits, low level analog signals need to be trace cross the inputs (from another layer), route it perpendicular isolated from the noisy digital environment. Designing with the to the input traces. AD8250 is no exception. Its supply voltages are referenced to an analog ground. Its digital circuit is referenced to a digital ground. Although it is convenient to tie both grounds to a single ground plane, the current traveling through the ground wires and PCB can cause errors. Therefore, use separate analog and digital ground planes. Analog and digital ground should meet at only one point: star ground. Rev. B | Page 18 of 24 06288-060 AD8250 DRIVING AN ADC RF INTERFERENCE An instrumentation amplifier is often used in front of an ADC RF rectification is often a problem when amplifiers are used in to provide CMRR. Usually, instrumentation amplifiers require a applications where there are strong RF signals. The disturbance buffer to drive an ADC. However, the low output noise, low can appear as a small dc offset voltage. High frequency signals distortion, and low settle time of the AD8250 make it an excellent can be filtered with a low-pass RC network placed at the input ADC driver. of the instrumentation amplifier, as shown in Figure 54. The filter limits the input signal bandwidth according to the following In this example, a 1 nF capacitor and a 49.9 Ω resistor create an relationship: antialiasing filter for the AD7612. The 1 nF capacitor stores and 1 delivers the necessary charge to the switched capacitor input of FilterFreq = DIFF 2π R(2C + C ) the ADC. The 49.9 Ω series resistor reduces the burden of the D C 1 nF load from the amplifier and isolates it from the kickback 1 FilterFreq = current injected from the switched capacitor input of the AD7612. CM 2π RC C Selecting too small a resistor improves the correlation between the voltage at the output of the AD8250 and the voltage at the where CD ≥ 10 CC. input of the AD7612 but may destabilize the AD8250. A trade- +15V off must be made between selecting a resistor small enough to maintain accuracy and large enough to maintain stability. 0.1µF 10µF +15V C C R +IN 10μF0.1µF WR +12V –12V OUT A1 C D AD8250 A0 +IN 0.1μF 0.1μF R REF –IN 49.9Ω AD8250 AD7612 C C 1nF REF 0.1µF 10µF +5V –IN ADR435 DGND DGND –15V 10μF0.1µF Figure 54. RFI Suppression Values of R and C should be chosen to minimize RFI. A C –15V mismatch between the R × C at the positive input and the C Figure 55. Driving an ADC R × CC at the negative input degrades the CMRR of the AD8250. By using a value of CD that is 10 times larger than the value of CC, the effect of the mismatch is reduced and performance is improved. Rev. B | Page 19 of 24 06288-061 06288-062 AD8250 APPLICATIONS DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER +15V In certain applications, it is necessary to create a differential signal. High resolution ADCs often require a differential input. 10μF0.1µF In other cases, transmission over a long distance can require WR MICRO- A1 differential signals for better immunity to interference. CONTROLLER A0 +IN + Figure 57 shows how to configure the AD8250 to output a AD8250 differential signal. An op amp, the AD817, is used in an inverting REF topology to create a differential voltage. VREF sets the output – –IN midpoint according to the equation shown in the figure. Errors from the op amp are common to both outputs and are thus DGND DGND 10μF0.1µF common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected –15V in differential signal processing by differential input ADCs or Figure 56. Programming Gain Using a Microcontroller instrumentation amplifiers. When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC. +12V 0.1μF AMPLITUDE WR +5V A1 A0 +IN AMPLITUDE –5V + V A = V + V OUT IN REF 2 +2.5V AD8250 0V V IN G = 1 –2.5V TIME REF – 4.99kΩ 0.1μF DGND – + V REF 0V –12V –12V +12V AD817 4.99kΩ 10pF AMPLITUDE 0.1µF 0.1µF +12V –12V +2.5V 10μF 10μF 0V 0V DGND –2.5V V B = –V + V OUT IN REF TIME 2 Figure 57. Differential Output with Level Shift Rev. B | Page 20 of 24 06288-064 06288-063 13 AD8250 0 DATA ACQUISITION –10 –20 The AD8250 makes an excellent instrumentation amplifier for –30 use in data acquisition systems. Its wide bandwidth, low distortion, –40 low settling time, and low noise enable it to condition signals in –50 front of a variety of 16-bit ADCs. –60 –70 Figure 59 shows a schematic of the AD825x data acquisition –80 demonstration board. The quick slew rate of the AD8250 allows –90 –100 it to condition rapidly changing signals from the multiplexed –110 inputs. An FPGA controls the AD7612, AD8250, and ADG1209. –120 In addition, mechanical switches and jumpers allow users to pin –130 strap the gains when in transparent gain mode. –140 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) This system achieved −111 dB of THD at 1 kHz and a signal-to- Figure 58. FFT of the AD825x DAQ Demo Board Using the AD8250, noise ratio of 91 dB during testing, as shown in Figure 58. 1 kHz Signal JMP JMP –V S +12V –12V +12V + + +5V 0.1µF 10µF 10µF 2kΩ 14 GND 2 V DD DGND 806Ω EN DGND JMP 4 S1A +CH1 806Ω +5V DGND +CH2 5 S2A 2kΩ 806Ω 2 ALTERA +CH3 6 S3A DGND 6 EPF6010ATC144-3 806Ω +CH4 0Ω 0Ω C 5 7 S4A C WR DGND +IN DA 8 10 + 4 A1 ADG1209 +IN 806Ω A0 OUT 7 AD8250 AD7612 –CH4 10 C S4B D REF 0Ω 0Ω 0Ω 49.9Ω –IN 1nF 806Ω 9 9 1 –V DB – 11 S –CH3 S3B +V S 3 806Ω ADR435 GND 15 –CH2 12 S2B 8 A0 806Ω –CH1 S1B A1 1 C4 C3 0.1µF V 16 SS 0.1µF 3 +12V –12V JMP 0.1µF +5V –12V 2kΩ DGND JMP +5V R8 2kΩ DGND Figure 59. Schematic of ADG1209, AD8250, and AD7612 in the AD825x DAQ Demo Board Rev. B | Page 21 of 24 C C AMPLITUDE (dB) 06288-065 06288-066 AD8250 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.30 0.05 0.13 0° 0.40 0.15 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 60. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8250ARMZ –40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H00 AD8250ARMZ-RL –40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H00 AD8250ARMZ-R7 –40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 H00 AD8250-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 22 of 24 091709-A AD8250 NOTES Rev. B | Page 23 of 24 AD8250 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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