ANALOG DEVICES AD825

Low Cost, General-Purpose High Speed JFET Amplifier AD825 FEATURES CONNECTION DIAGRAMS High speed NC 1 8 NC 41 MHz, −3 dB bandwidth AD825 –IN 2 7 +V S TOP VIEW 125 V/µs slew rate +IN 3 6 OUTPUT (Not to Scale) –V 4 5 NC 80 ns settling time S Input bias current of 20 pA and noise current of 10 fA/√Hz NC = NO CONNECT Input voltage noise of 12 nV/√Hz Figure 1. 8-Lead Plastic SOIC (R) Package Fully specified power supplies: ±5 V to ±15 V Low distortion: −76 dB at 1 MHz High output drive capability NC 1 16 NC Drives unlimited capacitance load NC 2 15 NC NC 3 14 NC 50 mA min output current AD825 –INPUT 4 13 +V S No phase reversal when input is at rail TOP VIEW +INPUT 5 12 OUTPUT (Not to Scale) Available in 8-lead SOIC –V 6 11 NC S NC 7 10 NC APPLICATIONS NC 8 9 NC CCDs NC = NO CONNECT Low distortion filters Mixed gain stages Figure 2. 16-Lead Plastic SOIC (R-16) Package Audio amplifiers Photo detector interfaces ADC input buffers DAC output buffers GENERAL DESCRIPTION The AD825 is a superbly optimized operational amplifier for 10V 200ns high speed, low cost, and dc parameters, making it ideally suited for a broad range of signal conditioning and data acquisition applications. The ac performance, gain, bandwidth, slew rate, and drive capability are all very stable over temperature. The AD825 also maintains stable gain under varying load conditions. The unique input stage has ultralow input bias current and input current noise. Signals that go to either rail on this high performance input do not cause phase reversals at the output. These features make the AD825 a good choice as a buffer for 10V MUX outputs, creating minimal offset and gain errors. Figure 3. Performance with Rail-to-Rail Input Signals The AD825 is fully specified for operation with dual ±5 V and ±15 V supplies. This power supply flexibility, and the low supply current of 6.5 mA with excellent ac characteristics under all supply conditions, makes the AD825 well-suited for many demanding applications. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 00876-E-001 00876-E-002 00876-E-003 AD825 TABLE OF CONTENTS Specifications..................................................................................... 3 REVISION HISTORY Absolute Maximum Ratings............................................................ 5 10/04—Data Sheet Changed from Rev. E to Rev. F Changes to Figure 1......................................................................... 1 Pin Configurations ........................................................................... 5 Changes to Figure 4......................................................................... 5 Changes to Figure 21....................................................................... 8 ESD Caution.................................................................................. 5 3/04—Data Sheet Changed from Rev. D to Rev. E Typical Performance Characteristics ............................................. 6 Changes to Specifications............................................................... 3 Driving Capacitive Loads .............................................................. 10 Addition of 16-Lead SOIC Pin Configuration ............................ 5 Changes to Figure 27....................................................................... 9 Theory of Operation ...................................................................... 10 Updated Outline Dimensions...................................................... 12 Updated Ordering Guide.............................................................. 12 Input Consideration................................................................... 10 2/01—Data Sheet Changed from Rev. C to Rev. D Grounding and Bypassing......................................................... 10 Addition of 16-lead SOIC package (R-16) Second-Order Low-Pass Filter.................................................. 11 Connection Diagram ...................................................................... 4 Addition to Absolute Maximum Ratings ..................................... 4 Outline Dimensions ....................................................................... 12 Addition to Ordering Guide (R-16).............................................. 4 Addition of 16-lead SOIC package (R-16) Ordering Guide........................................................................... 12 Outline Dimensions ...................................................................... 11 Rev. F | Page 2 of 12 AD825 SPECIFICATIONS All limits are determined to be at least four standard deviations away from mean value. At TA = 25°C, VS = ±15 V, unless otherwise noted. Table 1. AD825A Parameter Conditions VS Min Typ Max Unit DYNAMIC PERFORMANCE Unity Gain Bandwidth ±15 V 23 26 MHz Bandwidth for 0.1 dB Flatness Gain = +1 ±15 V 18 21 MHz −3 dB Bandwidth Gain = +1 ±15 V 44 46 MHz Slew Rate R = 1 kΩ, G = +1 ±15 V 125 140 V/µs LOAD Settling Time to 0.1% 0 V to 10 V Step, A = −1 ±15 V 150 180 ns V to 0.1% 0 V to 10 V Step, AV = −1 ±15 V 180 220 ns Total Harmonic Distortion FC = 1 MHz, G = −1 ±15 V −77 dB Differential Gain Error NTSC ±15 V 1.3 % (R = 150 Ω) Gain = +2 LOAD Differential Phase Error NTSC ±15 V 2.1 Degrees (RLOAD = 150 Ω) Gain = +2 INPUT OFFSET VOLTAGE ±15 V 1 2 mV T to T 5 mV MIN MAX Offset Drift 10 µV/°C INPUT BIAS CURRENT ±15 V 15 40 pA T 5 pA MIN TMAX 700 pA INPUT OFFSET CURRENT ±15 V 20 30 pA T 5 pA MIN TMAX 440 pA OPEN-LOOP GAIN V = ±10 V ±15 V OUT RLOAD = 1 kΩ 70 76 dB VOUT = ±7.5 V ±15 V RLOAD = 1 kΩ 70 76 dB V = ±7.5 V ±15 V OUT R = 150 kΩ (50 mA Output) 68 74 dB LOAD COMMON-MODE REJECTION VCM = ±10 ±15 V 71 80 dB INPUT VOLTAGE NOISE f = 10 kHz ±15 V 12 Hz nV/√ INPUT CURRENT NOISE f = 10 kHz ±15 V 10 Hz fA/√ INPUT COMMON-MODE VOLTAGE RANGE ±15 V ±13.5 V OUTPUT VOLTAGE SWING RLOAD = 1 kΩ ±15 V 13 ±13.3 V RLOAD = 500 Ω ±15 V 12.9 ±13.2 V Output Current ±15 V 50 mA Short-Circuit Current ±15 V 100 mA 11 INPUT RESISTANCE 5 ×10 Ω INPUT CAPACITANCE 6 pF OUTPUT RESISTANCE Open Loop 8 Ω POWER SUPPLY Quiescent Current ±15 V 6.5 7.2 mA T to T ±15 V 7.5 mA MIN MAX Rev. F | Page 3 of 12 AD825 All limits are determined to be at least four standard deviations away from mean value. At T = 25°C, V = ±5 V unless otherwise noted. A S Table 2. AD825A Parameter Conditions VS Min Typ Max Unit DYNAMIC PERFORMANCE Unity Gain Bandwidth ±5 V 18 21 MHz Bandwidth for 0.1 dB Flatness Gain = +1 ±5 V 8 10 MHz −3 dB Bandwidth Gain = +1 ±5 V 34 37 MHz Slew Rate RLOAD = 1 kΩ, G = −1 ±5 V 115 130 V/µs Settling Time to 0.1% −2.5 V to +2.5 V ±5 V 75 90 ns to 0.01% −2.5 V to +2.5 V ±5 V 90 110 ns Total Harmonic Distortion F = 1 MHz, G = −1 ±5 V −76 dB C Differential Gain Error NTSC ±5 V 1.2 % (RLOAD = 150 Ω) Gain = +2 Differential Phase Error NTSC ±5 V 1.4 Degrees (R = 150 Ω) Gain = +2 LOAD INPUT OFFSET VOLTAGE ±5 V 1 2 mV TMIN to TMAX 5 mV Offset Drift 10 µV/°C INPUT BIAS CURRENT ±5 V 10 30 pA T 5 pA MIN T 600 pA MAX INPUT OFFSET CURRENT ±5 V 15 25 pA T 5 pA MIN Offset Current Drift T 280 pA MAX OPEN-LOOP GAIN VOUT = ±2.5 ±5 V R = 500 Ω 64 66 dB LOAD R = 150 Ω 64 66 dB LOAD COMMON-MODE REJECTION VCM = ±2 V ±5 V 69 80 dB INPUT VOLTAGE NOISE f = 10 kHz ±5 V 12 Hz nV/√ INPUT CURRENT NOISE f = 10 kHz ±5 V 10 Hz fA/√ INPUT COMMON-MODE VOLTAGE RANGE ±5 V ± 3.5 V OUTPUT VOLTAGE SWING RLOAD = 500 Ω +3.2 ±3.4 V RLOAD = 150 Ω ±5 V +3.1 ±3.2 V Output Current ±5 V 50 mA Short-Circuit Current 80 mA 11 INPUT RESISTANCE 5 ×10 Ω INPUT CAPACITANCE 6 pF OUTPUT RESISTANCE Open Loop 8 Ω POWER SUPPLY Quiescent Current ±5 V 6.2 6.8 mA T to T ±5 V 7.5 mA MIN MAX POWER SUPPLY REJECTION VS = ±5 V to ±15 V 76 88 dB Rev. F | Page 4 of 12 AD825 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS Table 3. NC 1 8 NC Parameter Rating AD825 –IN 2 7 +V S TOP VIEW Supply Voltage ±18 V +IN 3 6 OUTPUT (Not to Scale) 1 –V 4 5 NC Internal Power Dissipation S Small Outline (R) See Figure 6 NC = NO CONNECT Input Voltage (Common Mode) ±VS Figure 4. 8-Lead SOIC Differential Input Voltage ±VS Output Short-Circuit Duration See Figure 6 Storage Temperature Range (R, R-16) −65°C to +125°C NC 1 16 NC Operating Temperature Range −40°C to +85°C NC 2 15 NC Lead Temperature Range 300°C NC 3 14 NC (Soldering 10 sec) –INPUT 4 AD825 13 +V S TOP VIEW Stresses above those listed under Absolute Maximum Ratings +INPUT 5 12 OUTPUT (Not to Scale) –V 6 11 NC S may cause permanent damage to the device. This is a stress NC 7 10 NC rating only; functional operation of the device at these or any NC 8 9 NC other conditions above those indicated in the operational NC = NO CONNECT section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect Figure 5. 16-Lead SOIC device reliability. 2.5 T = 150°C J 1 Specification is for device in free air: 2.0 16-LEAD SOIC PACKAGE 8-lead SOIC package: θJA = 155°C/W 16-lead SOIC package: θ = 85°C/W JA 1.5 1.0 8-LEAD SOIC PACKAGE 0.5 0 –50–40–30–20–10 0 102030 40 50 607080 90 AMBIENT TEMPERATURE (°C) Figure 6. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 5 of 12 MAXIMUM POWER DISSIPATION (W) 00876-E-001 00876-E-002 00876-E-004 AD825 TYPICAL PERFORMANCE CHARACTERISTICS 20 100 15 10 10 5 R = 150Ω R = 1kΩ L L 1 0 –5 0.1 –10 –15 0.01 –20 01 2 4 6 8 10 12 14 168 100 1k 10k 100k 1M 10M SUPPLY VOLTAGE (V) FREQUENCY (Hz) Figure 10. Closed-Loop Output Impedance vs. Frequency Figure 7. Output Voltage Swing vs. Supply Voltage 80 15 35 BANDWIDTH 30 10 V = ±15V S 25 60 5 20 V = ±5V 0 S PHASE MARGIN 15 40 –5 10 V = ±15V S –10 5 20 0 –15 60 0 100 200 300 400 500 600 700 800 900 1000 –60 –40 –20 0 20 40 80 100 120 140 LOAD RESISTANCE (Ω) TEMPERATURE (°C) Figure 8. Output Voltage Swing vs. Load Resistance Figure 11. Unity Gain Bandwidth and Phase Margin vs. Temperature 7.0 80 180 V = ±15V S 70 135 –40° +25° V = ±5V 6.5 60 90 S +85° 45 50 0 6.0 40 30 5.5 20 10 0 5.0 02 2 4 6 8 10 12 14 16 180 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) SUPPLY VOLTAGE (±V) Figure 9. Quiescent Supply Current vs. Supply Voltage Figure 12. Open-Loop Gain and Phase Margin vs. Frequency for Various Temperatures Rev. F | Page 6 of 12 OUTPUT SWING (V) OUTPUT SWING (V) SUPPLY CURRENT (mA) 00876-E-007 00876-E-005 00876-E-006 UNITY GAIN BANDWIDTH (MHz) OPEN-LOOP GAIN (dB) OUTPUT IMPEDANCE (Ω) OPEN-LOOP PHASE (Degrees) PHASE MARGIN (°C) 00876-E-008 00876-E-010 00876-E-009 AD825 80 30 R = 1kΩ L 75 20 V = ±15V S R = 150Ω L 70 V = ±5V S 10 65 60 0 10 1k 10k 10k 100k 1M 10M FREQUENCY (Hz) LOAD RESISTANCE (Ω) Figure 13. Open-Loop Gain vs. Load Resistance Figure 16. Large Signal Frequency Response; G = +2 200 10 180 0 160 –10 –PSRR 140 –20 0.01% 120 –30 0.01% +PSRR 100 –40 0.1% 0.1% 80 –50 60 –60 40 –70 20 –80 0 –90 10 8 6 4 2 0 –2 –4 –6 –8 –10 10k 100k 1M 10M FREQUENCY (Hz) OUTPUT SWING (0 to ±V) Figure 17. Output Swing and Error vs. Settling Time Figure 14. Power Supply Rejection vs. Frequency 130 –50 120 –55 110 –60 100 V = ±15V SECOND S 90 –65 V = ±5V S 80 THIRD –70 70 60 –75 50 –80 40 30 –85 10 100 1k 10k 100k 1M 10M 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. Common-Mode Rejection vs. Frequency Figure 18. Harmonic Distortion vs. Frequency Rev. F | Page 7 of 12 CMR (dB) OPEN-LOOP GAIN (dB) PSR (dB) 00876-E-012 00876-E-013 00876-E-011 DISTORTION (dB) SETTLING TIME (ns) OUTPUT VOLTAGE (V p-p) 00876-E-014 00876-E-015 00876-E-016 AD825 +V 10µF 160 S ±15V 140 0.01µF 7 ±5V 2 TEKTRONIX TEKTRONIX 120 HP PULSE (LS) 6 AD825 P6204 FET 7A24 V IN V OR OUT PROBE PREAMP 3 4 100 FUNCTION (SS) GENERATOR 0.01µF 50Ω R L 80 –V 10µF S 60 Figure 22. Noninverting Amplifier Connection 40 20 0 60 –60 –40 –20 0 20 40 80 100 120 140 TEMPERATURE (°C) Figure 19. Slew Rate vs. Temperature 2 5V 100ns 1 0 –1 –2 –3 V –4 OUT V IN V 0.1dB FLATNESS –5 S ±5V 10MHz –6 ±15V 21MHz –7 5V –8 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 20. Closed-Loop Gain vs. Frequency, Gain = +1 Figure 23. Noninverting Large Signal Pulse Response, RL = 1 kΩ 2 200mV 50ns 1 0 –1 –2 1kΩ 1kΩ –3 V IN –4 V OUT –5 V 0.1dB FLATNESS S –6 ±5V 7.7MHz –7 ±15V 9.8MHz 200mV –8 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 24. Noninverting Small Signal Pulse Response, R = 1 kΩ Figure 21. Closed-Loop Gain vs. Frequency, Gain = −1 L Rev. F | Page 8 of 12 SLEW RATE (V/µs) GAIN (dB) GAIN (dB) 00876-E-018 00876-E-019 00876-E-017 00876-E-022 00876-E-021 00876-E-020 AD825 5V 100ns 100ns 5V 5V 5V Figure 25. Noninverting Large Signal Pulse Response, R = 150 Ω Figure 28. Inverting Large Signal Pulse Response, R = 1 kΩ L L 200mV 50ns 200mV 50ns 200mV 200mV Figure 26. Noninverting Small Signal Pulse Response, RL = 150 Ω Figure 29. Inverting Small Signal Pulse Response, R = 1 kΩ L 1kΩ +V 10µF S 0.01µF 7 V IN HP PULSE 2 TEKTRONIX TEKTRONIX GENERATOR R IN 6 AD825 P6204 FET 7A24 1kΩ V OUT PROBE PREAMP 3 4 0.01µF 50Ω R L –V 10µF S Figure 27. Inverting Amplifier Connection Rev. F | Page 9 of 12 00876-E-024 00876-E-023 00876-E-025 00876-E-027 00876-E-026 AD825 DRIVING CAPACITIVE LOADS VPOS The internal compensation of the AD825, together with its high output current drive, permits excellent large signal performance while driving extremely high capacitive loads. NEG 1kΩ POS +V 10µF S 0.01µF C F VOUT 7 V IN HP PULSE 2 TEKTRONIX TEKTRONIX GENERATOR R IN 6 AD825 P6204 FET 7A24 1kΩ V OUT PROBE PREAMP 3 4 0.01µF C 50Ω L –V 10µF S VNEG Figure 30. Inverting Amplifier Driving a Capacitive Load Figure 32. Simplified Schematic 5V 500ns The capacitor, C , in the output stage, enables the AD825 to INPUT F drive heavy capacitive loads. For light loads, the gain of the output buffer is close to unity, CF is bootstrapped, and not much happens. As the capacitive load is increased, the gain of the output buffer is decreased and the bandwidth of the amplifier is reduced through a portion of C adding to the dominant pole. F As the capacitive load is further increased, the amplifier’s bandwidth continues to drop, maintaining the stability of the AD825. OUTPUT 5V INPUT CONSIDERATION The AD825 with its unique input stage ensures no phase Figure 31. Inverting Amplifier Pulse Response reversal for signals as large as or even larger than the supply While Driving a 400 pF Capacitive Load voltages. Also, layout considerations of the input transistors ensure functionality even with a large differential signal. THEORY OF OPERATION The AD825 is a low cost, wideband, high performance FET The need for a low noise input stage calls for a larger FET input operational amplifier. With its unique input stage design, transistor. One should consider the additional capacitance that the AD825 ensures no phase reversal, even for inputs that is added to ensure stability. When filters are designed with the exceed the power supply voltages, and its output stage is AD825, one needs to consider the input capacitance (5 pF to designed to drive heavy capacitive or resistive loads with small 6 pF) of the AD825 as part of the passive network. changes relative to no load conditions. GROUNDING AND BYPASSING The AD825 (Figure 32) consists of common-drain, common- The AD825 is a low input bias current FET amplifier. Its high base FET input stage driving a cascoded, common-base frequency response makes it useful in applications, such as matched NPN gain stage. The output buffer stage uses emitter photodiode interfaces, filters, and audio circuits. When followers in a Class AB amplifier that can deliver large current designing high frequency circuits, some special precautions are to the load while maintaining low levels of distortion. in order. Circuits must be built with short interconnects, and resistances should have low inductive paths to ground. Power supply leads should be bypassed to common as close as possible to the amplifier pins. Ceramic capacitors of 0.1 µF are recommended. Rev. F | Page 10 of 12 00876-E-029 00876-E-028 00876-E-030 AD825 +5V SECOND-ORDER LOW-PASS FILTER C1 C3 24pF 0.1µF A second-order Butterworth low-pass filter can be implemented R1 R2 9.31kΩ 9.31kΩ using the AD825 as shown in Figure 33. The extremely low bias V IN C2 AD825 V currents of the AD825 allow the use of large resistor values and, OUT 6pF consequently, small capacitor values without concern for developing large offset errors. Low current noise is another factor in permitting the use of large resistors without having to C4 0.1µF worry about the resultant voltage noise. –5V With the values shown, the corner frequency will be 1 MHz. Figure 33. Second-Order Butterworth Low-Pass Filter The equations for component selection are shown below. Note that the noninverting input (and the inverting input) has an 0 input capacitance of 6 pF. As a result, the calculated value of C1 –10 (12 pF) is reduced to 6 pF. –20 1.414 C1= –30 2π f R1 CUTOFF –40 0.707 –50 () C2 farads = 2π f R1 CUTOFF –60 –70 ( ) R1=R2=User Selected Typically 10 kΩto 100 kΩ –80 A plot of the filter frequency response is shown in Figure 34; 10k 100k 1M 10M 100M better than 40 dB of high frequency rejection is provided. FREQUENCY (Hz) Figure 34. Frequency Response of Second-Order Butterworth Filter Rev. F | Page 11 of 12 HIGH FREQUENCY REJECTION (dB) 00876-E-031 00876-E-032 AD825 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 5.00 (0.1968) 16 9 4.80 (0.1890) 7.60 (0.2992) 7.40 (0.2913) 85 6.20 (0.2440) 4.00 (0.1574) 10.65 (0.4193) 1 8 5.80 (0.2284) 3.80 (0.1497) 10.00 (0.3937) 1 4 1.27 (0.0500) 0.50 (0.0196) 1.27 (0.0500) 0.75 (0.0295) × 45° 2.65 (0.1043) BSC 1.75 (0.0688) BSC × 45° 0.25 (0.0099) 0.25 (0.0098) 2.35 (0.0925) 1.35 (0.0532) 0.25 (0.0098) 0.30 (0.0118) 0.10 (0.0040) 0.10 (0.0039) 8° 0.51 (0.0201) 8° 0° 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.51 (0.0201) SEATING 0.31 (0.0122) COPLANARITY 0° 1.27 (0.0500) SEATING 0.33 (0.0130) 0.10 0.40 (0.0157) PLANE 0.10 0.17 (0.0067) 0.31 (0.0122) PLANE 0.40 (0.0157) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-012AA COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 35. 8-Lead Standard Small Outline Package [SOIC] Figure 36. 16-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Wide Body (R-16) Dimensions shown in millimeters (inches) Dimensions shown in millimeters (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option AD825AR −40°C to +85°C 8-Lead SOIC R-8 AD825AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD825AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD825AR-16 −40°C to +85°C 16-Lead SOIC R-16 AD825AR-16-REEL −40°C to +85°C 16-Lead SOIC, 13" Tape and Reel R-16 AD825AR-16-REEL7 −40°C to +85°C 16-Lead SOIC, 7" Tape and Reel R-16 1 AD825ARZ-16 −40°C to +85°C 16-Lead SOIC R-16 1 AD825ARZ-16-REEL −40°C to +85°C 16-Lead SOIC, 13" Tape and Reel R-16 1 AD825ARZ-16-REEL7 −40°C to +85°C 16-Lead SOIC, 7" Tape and Reel R-16 AD825ACHIPS Die 1 Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00876–0–10/04(F) Rev. F | Page 12 of 12