ANALOG DEVICES AD824

Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp AD824 PIN CONFIGURATIONS FEATURES Single Supply Operation: 3 V to 30 V 14-Lead Epoxy SOIC 16-Lead Epoxy SOIC Very Low Input Bias Current: 2 pA (R Suffix) (R Suffix) Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 500 �A/Amp OUT D OUT A 1 16 OUT A 1 14 OUT D Wide Bandwidth: 2 MHz –IN A –IN D 2 15 –IN A 2 13 –IN D Slew Rate: 2 V/�s +IN A 3 14 +IN D +IN A 3 12 +IN D No Phase Reversal AD824 V+ 4 13 V– AD824 V+ 4 11 V– TOP VIEW +IN B 5 APPLICATIONS 12 +IN C (Not to Scale) +IN B 5 10 +IN C Photo Diode Preamplifier –IN B 6 11 –IN C –IN B 6 –IN C 9 Battery Powered Instrumentation OUT B 7 10 OUT C 7 OUT C OUT B 8 Power Supply Control and Protection 8 9 NC NC Medical Instrumentation NC = NO CONNECT Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier GENERAL DESCRIPTION The FET input combined with laser trimming provides an input The AD824 is a quad, FET input, single supply amplifier, fea- that has extremely low bias currents with guaranteed offsets turing rail-to-rail outputs. The combination of FET inputs and below 1 mV. This enables high accuracy designs even with rail-to-rail outputs makes the AD824 useful in a wide variety of high source impedances. Precision is combined with low low voltage applications where low input current is a primary noise, making the AD824 ideal for use in battery powered consideration. medical equipment. The AD824 is guaranteed to operate from a 3 V single supply Applications for the AD824 include portable medical equipment, up to ±15 V dual supplies. AD824AR-3V Parametric Perfor- photo diode preamplifiers and high impedance transducer mance at 3 V is fully guaranteed. amplifiers. Fabricated on ADI’s complementary bipolar process, the AD824 The ability of the output to swing rail-to-rail enables designers has a unique input stage that allows the input voltage to safely to build multistage filters in single supply systems and maintain extend beyond the negative supply and to the positive supply high signal-to-noise ratios. without any phase inversion or latchup. The output voltage The AD824 is specified over the extended industrial (–40∞C to swings to within 15 mV of the supplies. Capacitive loads to +85∞C) temperature range and is available in narrow 14-lead 350 pF can be handled without oscillation. and 16-lead SOIC packages. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. 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AD824–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, V = 0 V, V = 0.2 V, T = 25�C unless otherwise noted) S CM OUT A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage AD824A V 0.1 1.0 mV OS T to T 1.5 mV MIN MAX Input Bias Current I 212 pA B T to T 300 4000 pA MIN MAX Input Offset Current I 210 pA OS T to T 300 pA MIN MAX Input Voltage Range –0.2 3.0 V Common-Mode Rejection Ratio CMRR V = 0 V to 2 V 66 80 dB CM V = 0 V to 3 V 60 74 dB CM T to T 60 dB MIN MAX 13 Input Impedance 10 �3.3 W�pF Large Signal Voltage Gain A V = 0.2 V to 4.0 V VO O R = 2 kW 20 40 V/mV L R = 10 kW 50 100 V/mV L R = 100 kW 250 1000 V/mV L T to T R = 100 kW 180 400 V/mV MIN MAX, L Offset Voltage Drift DV /DT2 mV/∞C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 20 mA 4.975 4.988 V OH SOURCE T to T 4.97 4.985 V MIN MAX I = 2.5 mA 4.80 4.85 V SOURCE T to T 4.75 4.82 V MIN MAX Output Voltage Low V I = 20 mA1525mV OL SINK T to T 20 30 mV MIN MAX I = 2.5 mA 120 150 mV SINK T to T 140 200 mV MIN MAX Short Circuit Limit I Sink/Source ±12 mA SC T to T ±10 mA MIN MAX Open-Loop Impedance Z f = 1 MHz, A = 1 100 W OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V 70 80 dB S T to T 66 dB MIN MAX Supply Current/Amplifier I T to T 500 600 mA SY MIN MAX DYNAMIC PERFORMANCE Slew Rate SR R = 10 kW, A = 1 2 V/ms L V Full-Power Bandwidth BW 1% Distortion, V = 4 V p-p 150 kHz P O Settling Time t V = 0.2 V to 4.5 V, to 0.01% 2.5 ms S OUT Gain Bandwidth Product GBP 2 MHz Phase Margin foNo Load 50 Degrees Channel Separation CS f = 1 kHz, R = 2 kW –123 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 mV p-p n Voltage Noise Density e f = 1 kHz 16 nV/÷Hz n Current Noise Density i f = 1 kHz 0.8 fA/÷Hz n Total Harmonic Distortion THD f = 10 kHz, R = 0, A = +1 0.005 % L V –2– REV. C AD824 ELECTRICAL SPECIFICATIONS (@ V = �15.0 V, V = 0 V, T = 25�C unless otherwise noted) S OUT A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS 0.5 2.5 mV Offset Voltage AD824A V OS T to T 0.6 4.0 mV MIN MAX Input Bias Current I V = 0 V 4 35 pA B CM T to T 500 4000 pA MIN MAX I V = –10 V 25 pA B CM Input Offset Current I 320 pA OS T to T 500 pA MIN MAX Input Voltage Range –15 13 V Common-Mode Rejection Ratio CMRR V = –15 V to 13 V 70 80 dB CM T to T 66 dB MIN MAX 13 Input Impedance 10 �3.3 W�pF Large Signal Voltage Gain A Vo = –10 V to +10 V; VO R = 2 kW 12 50 V/mV L R = 10 kW 50 200 V/mV L R = 100 kW 300 2000 V/mV L T to T R = 100 kW 200 1000 V/mV MIN MAX, L Offset Voltage Drift DV /DT2 mV/∞C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 20 mA 14.975 14.988 V OH SOURCE T to T 14.970 14.985 V MIN MAX I = 2.5 mA 14.80 14.85 V SOURCE T to T 14.75 14.82 V MIN MAX Output Voltage Low V I = 20 mA –14.985 –14.975 V OL SINK T to T –14.98 –14.97 V MIN MAX I = 2.5 mA –14.88 –14.85 V SINK T to T –14.86 –14.8 V MIN MAX Short Circuit Limit I Sink/Source, T to T ±8 ±20 mA SC MIN MAX Open-Loop Impedance Z f = 1 MHz, A = 1 100 W OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 15 V 70 80 dB S T to T 68 dB MIN MAX Supply Current/Amplifier I V = 0 V 560 625 mA SY O T to T 675 mA MIN MAX DYNAMIC PERFORMANCE Slew Rate SR R = 10 kW, A = 1 2 V/ms L V Full-Power Bandwidth BW 1% Distortion, V = 20 V p-p 33 kHz P O Settling Time t V = 0 V to 10 V, to 0.01% 6 ms S OUT Gain Bandwidth Product GBP 2 MHz Phase Margin fo50 Degrees Channel Separation CS f = 1 kHz, R =2 kW –123 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 mV p-p n Voltage Noise Density e f = 1 kHz 16 nV/÷Hz n Current Noise Density i f = 1 kHz 1.1 fA/÷Hz n Total Harmonic Distortion THD f =10 kHz, V = 3 V rms, O R = 10 kW 0.005 % L REV. C –3– AD824–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = 3.0 V, V = 0 V, V = 0.2 V, T = 25�C unless otherwise noted) S CM OUT A Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage AD824A -3 V V 0.2 1.0 mV OS T to T 1.5 mV MIN MAX Input Bias Current I 212 pA B T to T 250 4000 pA MIN MAX Input Offset Current I 210 pA OS T to T 250 pA MIN MAX Input Voltage Range 0 1 V Common-Mode Rejection Ratio CMRR V = 0 V to 1 V 58 74 dB CM T to T 56 dB MIN MAX 13 Input Impedance 10 �3.3 W�pF Large Signal Voltage Gain A V = 0.2 V to 2.0 V VO O R = 2 kW 10 20 V/mV L R = 10 kW 30 65 V/mV L R = 100 kW 180 500 V/mV L T to T R = 100 kW 90 250 V/mV MIN MAX, L Offset Voltage Drift DV /DT2 mV/∞C OS OUTPUT CHARACTERISTICS Output Voltage High V I = 20 mA 2.975 2.988 V OH SOURCE T to T 2.97 2.985 V MIN MAX I = 2.5 mA 2.8 2.85 V SOURCE T to T 2.75 2.82 V MIN MAX Output Voltage Low V I = 20 mA1525mV OL SINK T to T 20 30 mV MIN MAX I = 2.5 mA 120 150 mV SINK T to T 140 200 mV MIN MAX Short Circuit Limit I Sink/Source ±8mA SC I Sink/Source, T to T ±6mA SC MIN MAX Open-Loop Impedance Z f = 1 MHz, A = 1 100 W OUT V POWER SUPPLY Power Supply Rejection Ratio PSRR V = 2.7 V to 12 V, 70 dB S T to T 66 dB MIN MAX Supply Current/Amplifier I V = 0.2 V, T to T 500 600 mA SY O MIN MAX DYNAMIC PERFORMANCE Slew Rate SR R =10 kW, A = 1 2 V/ms L V Full-Power Bandwidth BW 1% Distortion, V = 2 V p-p 300 kHz P O Settling Time t V = 0.2 V to 2.5 V, to 0.01% 2 ms S OUT Gain Bandwidth Product GBP 2 MHz Phase Margin fo50 Degrees Channel Separation CS f = 1 kHz, R = 2 kW –123 dB L NOISE PERFORMANCE Voltage Noise e p-p 0.1 Hz to 10 Hz 2 mV p-p n Voltage Noise Density e f = 1 kHz 16 nV/÷Hz n Current Noise Density i 0.8 fA/÷Hz n Total Harmonic Distortion THD f = 10 kHz, R = 0, A = +1 0.01 % L V –4– REV. C AD824 WAFER TEST LIMITS (@ V = 5.0 V, V = 0 V, T = 25�C unless otherwise noted) S CM A Parameter Symbol Conditions Limit Unit Offset Voltage V 1.0 mV max OS Input Bias Current I 12 pA max B Input Offset Current I 20 pA OS Input Voltage Range V –0.2 to 3.0 V min CM Common-Mode Rejection Ratio CMRR V = 0 V to 2 V 66 dB min CM Power Supply Rejection Ratio PSRR V = + 2.7 V to +12 V 70 mV/V Large Signal Voltage Gain A R = 2 kW 15 V/mV min VO L Output Voltage High V I = 20 mA 4.975 V min OH SOURCE Output Voltage Low V I = 20 mA25 mV max OL SINK Supply Current/Amplifier I V = 0 V, R = • 600 mA max SY O L NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 ABSOLUTE MAXIMUM RATINGS V CC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –V – 0.2 V to +V S S I5 I6 Q18 Q29 Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±30 V R1 R2 R9 Output Short Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range Q21 Q27 R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C Q4 Q6 C3 Operating Temperature Range Q5 J1 J2 Q19 Q20 AD824A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C +IN R7 Q7 Junction Temperature Range C4 R-14, R-16 Packages . . . . . . . . . . . . . . . . –65∞C to +150∞C R13 R15 Q22 Q23 V C2 OUT Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300∞C –IN 2 Q24 Q25 Package Type q q Unit JA JC Q8 C1 14-Lead SOIC (R) 120 36 ∞C/W Q2 Q3 16-Lead SOIC (R) 92 27 ∞C/W Q31 NOTES Q28 Q26 R12 R14 1 R17 Absolute maximum ratings apply to packaged parts unless otherwise noted. I1 I2 I3 I4 2 q is specified for the worst case conditions, i.e., q is specified for device in socket JA JA for P-DIP packages; q is specified for device soldered in circuit board for SOIC JA V EE package. Figure 1. Simplified Schematic of 1/4 AD824 ORDERING GUIDE Temperature Package Package Model Range Description Option AD824AR-14 –40∞C to +85∞C 14-Pin SOIC R-14 AD824AR-14-3V –40∞C to +85∞C 14-Pin SOIC R-14 AD824AR-16 –40∞C to +85∞C 16-Pin SOIC R-16 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality. REV. C –5– AD824–Typical Performance Characteristics V = 15V S V = 5V 80 80 S NO LOAD NO LOAD 60 60 40 40 45 45 90 20 90 20 135 135 180 0 180 0 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 100 100 90 90 10 10 0% 0% 50mV 1µs 50mV 1µs TPC 1. Open-Loop Gain/Phase and Small Signal TPC 3. Open-Loop Gain/Phase and Small Signal Response, V = ±15 V, No Load Response, V = 5 V, No Load S S V = 15V V = 5V 80 S 60 S C = 100pF L C = 220pF L 60 40 45 40 90 20 45 135 90 180 20 0 135 180 0 –20 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M 100 100 90 90 10 10 0% 0% 50mV 1µs 50mV 1µs TPC 2. Open-Loop Gain/Phase and Small Signal TPC 4. Open-Loop Gain/Phase and Small Signal Response, V = ±15 V, C = 100 pF Response, V = 5 V, C = 220 pF S L S L –6– REV. C GAIN – dB GAIN – dB PHASE – Degrees PHASE – Degrees GAIN – dB GAIN – dB PHASE – Degrees PHASE – Degrees AD824 V = 3V 60 S NO LOAD t µs 9.950 40 100 45 90 20 90 135 180 0 10 0% –20 5V 2µs 1k 10k 100k 1M 10M t 10.810µs 100 100 90 90 10 10 0% 0% 50mV 1µs 5V 2µs TPC 5. Open-Loop Gain/Phase and Small Signal TPC 7. Slew Rate, R = 10k L Response, V = 3 V, No Load S V = 3V 60 S C = 220pF L 100 90 40 45 V OUT 20 90 10 135 0% 180 0 100µs 5V –20 TPC 8. Phase Reversal with Inputs Exceeding Supply by 1 V 1k 10k 100k 1M 10M 0.8 0.7 0.6 100 0.5 90 SOURCE 0.4 0.3 0.2 10 0% SINK 0.1 50mV 1µs 0 1� 5� 10� 50� 100� 500� 1m 5m 10m LOAD CURRENT – A TPC 6. Open-Loop Gain/Phase and Small Signal TPC 9. Output Voltage to Supply Rail vs. Sink and Source Response, V = 3 V, C = 220 pF Load Currents S L REV. C –7– GAIN – dB GAIN – dB PHASE – Degrees PHASE – Degrees OUTPUT TO RAIL – Volts AD824 14 COUNT = 60 12 3V V 15V S 10 60 8 40 6 20 4 2 5 10 15 20 FREQUENCY – kHz 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 OFFSET VOLTAGE DRIFT TPC 10. Voltage Noise Density TPC 13. TC V Distribution, –55∞C to +125∞C, V = 5, 0 OS S 150 0.1 V = 5, 0 S R = 0 L 125 A = +1 V 100 V = +3 S 0.010 75 V = +5 S 50 0.001 25 V = 15 S 0 0.0001 20 100 1k 10k 20k –25 –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz TEMPERATURE – C TPC 11. Total Harmonic Distortion TPC 14. Input Offset Current vs. Temperature 280 100k V = 5, 0 COUNT = 860 S 240 10k 200 1k 160 100 120 10 80 1 40 0 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 20 40 60 80 100 120 140 OFFSET VOLTAGE – mV TEMPERATURE – C TPC 12. Input Offset Distribution, V = 5, 0 TPC 15. Input Bias Current vs. Temperature S –8– REV. C NUMBER OF UNITS THD+N – % NOISE DENSITY – nV/ Hz INPUT OFFSET CURRENT – pA NUMBER OF UNITS INPUT BIAS CURRENT – pA AD824 120 1k 100 80 100 60 40 10 20 0 1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz TPC 16. Common-Mode Rejection vs. Frequency TPC 19. Input Voltage Noise Spectral Density vs. Frequency –40 120 100 –60 80 –80 60 40 –100 20 –120 0 100 1k 10k 100k 10 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz TPC 17. THD vs. Frequency, 3 V rms TPC 20. Power Supply Rejection vs. Frequency 100 100 30 80 80 25 60 60 20 15V 40 40 15 3, 0V 20 20 10 0 0 5 –20 –20 0 10 100 1k 10k 100k 1M 10M 1k 3k 10k 30k 100k 300k 1M FREQUENCY – Hz INPUT FREQUENCY – Hz TPC 18. Open-Loop Gain and Phase vs. Frequency TPC 21. Large Signal Frequency Response REV. C –9– OPEN-LOOP GAIN – dB THD – dB COMMON-MODE REJECTION – dB PHASE MARGIN – Degrees OUTPUT VOLTAGE – Volts POWER SUPPLY REJECTION – dB INPUT VOLTAGE NOISE – nV/÷Hz AD824 –80 –90 5V 5µs 100 –100 90 –110 1 TO 4 –120 10 1 TO 3 1 TO 2 0% –130 –140 10 100 1k 10k 100k FREQUENCY – Hz TPC 22. Crosstalk vs. Frequency TPC 25. Large Signal Response 10k 2750 2500 1k V = 15V S 2250 100 2000 10 V = 3, 0 1750 S 1 1500 .1 1250 .01 1000 10 100 1k 10k 100k 1M 10M –60 –40 –20 0 20 40 60 80 100 120 140 FREQUENCY – Hz TEMPERATURE – C TPC 23. Output Impedance vs. Frequency, Gain = +1 TPC 26. Supply Current vs. Temperature 1000 V = 15V S V = 3, 0 S 20mV 500ns 100 90 100 V – V OL S V – V 10 S OH 10 0% 0 0.01 0.10 1.0 10.0 LOAD CURRENT – mA TPC 24. Small Signal Response, Unity Gain Follower, TPC 27. Output Saturation Voltage 10k�100 pF Load –10– REV. C CROSSTALK – dB OUTPUT IMPEDANCE – SUPPLY CURRENT – µA OUTPUT SATURATION VOLTAGE – mV AD824 APPLICATION NOTES A current-limiting resistor should be used in series with the INPUT CHARACTERISTICS input of the AD824 if there is a possibility of the input voltage In the AD824, n-channel JFETs are used to provide a low exceeding the positive supply by more than 300 mV or if an offset, low noise, high impedance input stage. Minimum input input voltage will be applied to the AD824 when ±V = 0. The S common-mode voltage extends from 0.2 V below –V to 1 V less amplifier will be damaged if left in that condition for more than S than +V . Driving the input voltage closer to the positive rail will 10 seconds. A 1 kW resistor allows the amplifier to withstand up S cause a loss of amplifier bandwidth. to 10 V of continuous overvoltage and increases the input volt- age noise by a negligible amount. The AD824 does not exhibit phase reversal for input voltages up to and including +V . Figure 2a shows the response of an Input voltages less than –V are a completely different story. S S AD824 voltage follower to a 0 V to 5 V (+V ) square wave input. The amplifier can safely withstand input voltages 20 V below S The input and output are superimposed. The output tracks the the minus supply voltage as long as the total voltage from the input up to +V without phase reversal. The reduced bandwidth positive supply to the input terminal is less than 36 V. In addition, S above a 4 V input causes the rounding of the output wave form. the input stage typically maintains picoamp level input currents For input voltages greater than +V , a resistor in series with across that input voltage range. S the AD824’s noninverting input will prevent phase reversal at the expense of greater input voltage noise. This is illustrated in OUTPUT CHARACTERISTICS Figure 2b. The AD824’s unique bipolar rail-to-rail output stage swings within 15 mV of the positive and negative supply voltages. The AD824’s approximate output saturation resistance is 100 W for 1V 2µs both sourcing and sinking. This can be used to estimate output 100 saturation voltage when driving heavier current loads. For 90 instance, the saturation voltage will be 0.5 V from either supply with a 5 mA current load. For load resistances over 20 kW, the AD824’s input error voltage is virtually unchanged until the output voltage is driven 10 GND 0% to 180 mV of either supply. 1V If the AD824’s output is overdriven so as to saturate either of the output devices, the amplifier will recover within 2 ms of its (a) input returning to the amplifier’s linear operating region. 1V 10µs Direct capacitive loads will interact with the amplifier’s effective 1V output impedance to form an additional pole in the amplifier’s 100 +V 90 S feedback loop, which can cause excessive peaking on the pulse response or loss of stability. Worst case is when the amplifier is used as a unity gain follower. TPC 4 and 6 show the AD824’s pulse response as a unity gain follower driving 220 pF. Configu- rations with less loop gain, and as a result less loop bandwidth, 10 GND 0% will be much less sensitive to capacitance load effects. Noise 1V gain is the inverse of the feedback attenuation factor provided by the feedback network in use. (b) Figure 3 shows a method for extending capacitance load drive +5V capability for a unity gain follower. With these component val- R P ues, the circuit will drive 5,000 pF with a 10% overshoot. V IN V OUT +V S 0.01�F 8 100� 1/4 V IN Figure 2. (a) Response with R = 0; V from 0 to +V AD824 P IN S V OUT 0.01�F (b) V = 0 to + V + 200 m V IN S 4 V = 0 to + V OUT S C L –V S R = 49.9 kW P 20pF Since the input stage uses n-channel JFETs, input current during normal operation is positive; the current flows out from 20k� the input terminals. If the input voltage is driven more positive than +V – 0.4 V, the input current will reverse direction as S Figure 3. Extending Unity Gain Follower Capacitive Load internal device junctions become forward biased. This is Capability Beyond 350 pF illustrated in TPC 8. REV. C –11– AD824 APPLICATIONS Table I. AD824 In Amp Performance Single Supply Voltage-to-Frequency Converter Parameters V = 3 V, 0 V V = �5 V S S The circuit shown in Figure 4 uses the AD824 to drive a low power timer, which produces a stable pulse of width t . The 1 CMRR 74 dB 80 dB positive going output pulse is integrated by R1-C1 and used as Common-Mode one input to the AD824, which is connected as a differential Voltage Range –0.2 V to +2 V –5.2 V to +4 V integrator. The other input (nonloading) is the unknown voltage, 3 dB BW, G = 10 180 kHz 180 kHz V . The AD824 output drives the timer trigger input, closing IN G = 100 18 kHz 18 kHz the overall feedback loop. t SETTLING 2 V Step (V = 0 V, 3 V) 2 ms S 10V 5 V (V = ±5 V) 5 ms S U4 REF02 Noise @ f = 1 kHz, G = 10 270 nV/÷Hz 270 nV/÷Hz C5 0.1�F 2 V = 5V G = 100 2.2 mV/÷Hz 2.2 mV/÷Hz REF 6 CMOS R ** 3 5 SCALE OUT2 74HCO4 C3 10k� 0.1�F 4 5µs U3B U3A 4 32 1 100 OUT1 90 U2 CMOS 555 0.01�F, 2% 48 R2 U1 R3* C1 RV+ 499k�, 1% 116k� 6 THR OUT 3 1/4 2 TR 10 AD824 R1 CV 5 0% 7 DIS 499k�, 1% C6 1V GND 390pF 0V TO 2.5V 1 5% FULL SCALE C4 (NPO) C2 0.1�F Figure 5a. Pulse Response of In Amp to a 500 mV p-p 0.01�F, 2% Input Signal; V = 5 V, 0 V; Gain = 10 S NOTES f = V /(VREF � t ), t = 1.1 � R3 � C6 OUT IN 1 1 = 25kHz f AS SHOWN. S R1 R2 R3 R4 R5 R6 OHMTEK * = 1% METAL FILM, <50ppm/�C TC PART # 1043 V 90k� 9k� 1k� 1k� 9k� 90k� REF ** = 10%, 20T FILM, <100ppm/�C TC t = 33�s FOR f = 20kHz @ V = 2.0V 1 OUT IN G = 10 G = 100 G = 100 G = 10 Figure 4. Single Supply Voltage-to-Frequency Converter +V Typical AD824 bias currents of 2 pA allow megaohm-range S 0.1�F source impedances with negligible dc errors. Linearity errors on the order of 0.01% full scale can be achieved with this circuit. 2 6 This performance is obtained with a 5 V single supply, which 1/4 1 1/4 7 AD824 AD824 R P delivers less than 3 mA to the entire circuit. V V 3 5 OUT IN1 11 1k� R Single Supply Programmable Gain Instrumentation Amplifier P V IN2 The AD824 can be configured as a single supply instrumenta- 1k� R6 tion amplifier that is able to operate from single supplies down (G = 10) V = (V – V ) (1+ ) + V OUT IN1 IN2 REF R4 + R5 to 5 V or dual supplies up to ±15 V. AD824 FET inputs’ 2 pA R5 + R6 bias currents minimize offset errors caused by high unbalanced (G = 100) V = (V – V ) (1+ ) + V OUT IN1 IN2 REF R4 source impedances. FOR R1 = R6, R2 = R5 AND R3 = R4 An array of precision thin-film resistors sets the in amp gain to be either 10 or 100. These resistors are laser-trimmed to ratio Figure 5b. A Single Supply Programmable match to 0.01% and have a maximum differential TC of 5 ppm/∞C. Instrumentation Amplifier –12– REV. C AD824 3 Volt, Single Supply Stereo Headphone Driver of 4.5 V can be used to drive an A/D converter front end. The The AD824 exhibits good current drive and THD+N perfor- other half of the AD824 is configured as a unity-gain inverter mance, even at 3 V single supplies. At 1 kHz, total harmonic and generates the other bridge input of –4.5 V. Resistors R1 and distortion plus noise (THD+N) equals –62 dB (0.079%) for a R2 provide a constant current for bridge excitation. The AD620 300 mV p-p output signal. This is comparable to other single low power instrumentation amplifier is used to condition the supply op amps that consume more power and cannot run on 3 V differential output voltage of the bridge. The gain of the AD620 power supplies. is programmed using an external resistor R and determined by: G In Figure 6, each channel’s input signal is coupled via a 1mF 49.4 kW G = + 1 Mylar capacitor. Resistor dividers set the dc voltage at the R G noninverting inputs so that the output voltage is midway between the power supplies (1.5 V). The gain is 1.5. Each half of the A 3.3 V/5 V Precision Sample-and-Hold Amplifier AD824 can then be used to drive a headphone channel. A 5 Hz In battery-powered applications, low supply voltage operational high-pass filter is realized by the 500mF capacitors and the amplifiers are required for low power consumption. Also, low headphones, which can be modeled as 32 ohm load resistors to supply voltage applications limit the signal range in precision ground. This ensures that all signals in the audio frequency analog circuitry. Circuits like the sample-and-hold circuit shown range (20 Hz–20 kHz) are delivered to the headphones. in Figure 8, illustrate techniques for designing precision analog circuitry in low supply voltage applications. To maintain high 3V signal-to-noise ratios (SNRs) in a low supply voltage application requires the use of rail-to-rail, input/output operational amplifi- 0.1�F 0.1�F 95.3k� ers. This design highlights the ability of the AD824 to operate 1�F rail-to-rail from a single 3 V/5 V supply, with the advantages of CHANNEL 1 1/4 1/4 MYLAR high input impedance. The AD824, a quad JFET-input op amp, AD824 47.5k� AD824 500�F is well suited to S/H circuits due to its low input bias currents 13 (3 pA, typical) and high input impedances (3 ¥ 10 W, typical). 95.3k� L 4.99k� The AD824 also exhibits very low supply currents so the total 10k� supply current in this circuit is less than 2.5 mA. HEADPHONES 32� IMPEDANCE 10k� 3.3/5V 3.3/5V R 0.1�F 4.99k� R1 AD824A 50k� 3 4 1/4 1/4 1 1�F 47.5k� A1 FALSE GROUND (FG) A1 AD824 AD824 2 500�F R2 CHANNEL 2 11 R4 50k� MYLAR 2k� 3.3/5V Figure 6. 3 Volt Single Supply Stereo Headphone Driver 13 ADG513 Low Dropout Bipolar Bridge Driver 15 14 R5 16 The AD824 can be used for driving a 350 ohm Wheatstone 2k� 10 11 bridge. Figure 7 shows one half of the AD824 being used to 9 AD824B buffer the AD589—a 1.235 V low power reference. The output CH FG 5 500pF 7 2 3 A2 A2 +V S 6 1 \ 10 49.9k� 8 R1 A3 A3 + +1.235V 9 20� V OUT 7 6 – 1/4 1/4 TO A/D CONVERTER AD824C AD589 AD824 8 AD824 REFERENCE INPUT C AD824D 4 5 10k� 26.4k�, 1% FG 500pF +V 12 S 14 1% SAMPLE/ A4 A4 350� 350� FG 3 13 7 HOLD 6 AD824 R AD620 G 350� 350� 5 Figure 8. 3.3 V/5.5 V Precision Sample and Hold 2 4 10k� V In many single supply applications, the use of a false ground REF 1% –V 10k� S generator is required. In this circuit, R1 and R2 divide the 1/4 1% 1/4 +V supply voltage symmetrically, creating the false ground voltage +5V –4.5V S AD824 AD824 1�F 0.1�F at one-half the supply. Amplifier A1 then buffers this voltage R2 GND 20� creating a low impedance output drive. The S/H circuit is con- 1�F 0.1�F –V S figured in an inverting topology centered around this false –V –5V S ground level. Figure 7. Low Dropout Bipolar Bridge Driver REV. C –13– AD824 A design consideration in sample-and-hold circuits is voltage less than 2 mV over the entire 0 V to 3.3 V/5 V signal range. droop at the output caused by op amp bias and switch leakage Another method of reducing pedestal error is to reduce the pulse currents. By choosing a JFET op amp and a low leakage CMOS amplitude applied to the control pins. In order to control the switch, this design minimizes droop rate error to better than ADG513, only 2.4 V are required for the “ON” state and 0.1mV/ms in this circuit. Higher values of C will yield a lower 0.8V for the “OFF” state. If possible, use an input control H droop rate. For best performance, C and C2 should be poly- signal whose amplitude ranges from 0.8 V to 2.4 V instead of a H styrene, polypropylene or Teflon capacitors. These types of full range 0 V to 3.3 V/5 V for minimum pedestal error. capacitors exhibit low leakage and low dielectric absorption. Addi- Other circuit features include an acquisition time of less than tionally, 1% metal film resistors were used throughout the design. 3ms to 1%; reducing C and C2 will speed up the acquisition H In the sample mode, SW1 and SW4 are closed, and the output time further, but an increased pedestal error will result. Settling is V = –V . The purpose of SW4, which operates in parallel time is less than 300 ns to 1%, and the sample-mode signal BW OUT IN with SW1, is to reduce the pedestal, or hold step, error by is 80 kHz. injecting the same amount of charge into the noninverting input The ADG513 was chosen for its ability to work with 3 V/5 V of A3 that SW1 injects into the inverting input of A3. This supplies and for having normallyopen and normallyclosed preci- creates a common-mode voltage across the inputs of A3 and is sion CMOS switches on a dielectrically isolated process. SW2 is then rejected by the CMR of A3; otherwise, the charge injection not required in this circuit; however, it was used in parallel with from SW1 would create a differential voltage step error that SW3 to provide a lower R analog switch. ON would appear at V . The pedestal error for this circuit is OUT –14– REV. C AD824 * AD824 SPICE Macro-model 9/94, Rev. A * G15 98 18 (9,98) 1E-6 ARG/ADI * * * OUTPUT STAGE * Copyright 1994 by Analog Devices, Inc. * * ES 26 98 * Refer to “README.DOC” file for License Statement. (18,98) 1 Use of this model indicates your acceptance with RS 26 22 the terms and provisions in the License Statement. * 500 * Node assignments IB1 98 21 * noninverting input 2.404E-3 * | inverting input IB2 23 98 * | | positive supply 2.404E-3 * | | | negative supply D10 21 98 * | | | | output DY * | | | | | D11 98 23 .SUBCKT AD824 DY 1 2 99 50 25 C16 20 25 * 2E-12 * INPUT STAGE & POLE AT 3.1 MHz C17 24 25 * 2E-12 R3 5 99 DQ197 20 1.193E3 DQ R4 6 99 Q2 20 21 1.193E3 22 NPN CIN 1 2 Q3 24 23 4E-12 22 PNP C2 5 6 DQ224 51 19.229E-12 DQ I1 4 50 108E-6 Q5 25 20 IOS 1 2 97 PNP 20 1E-12 Q6 25 24 EOS 7 1 51 NPN 20 POLY(1) (12,98) 100E-6 1 VP 96 97 J1 4 2 5 0 JX VN 51 52 J2 4 7 6 0 JX EP 96 0 * (99,0) 1 * GAIN STAGE & DOMINANT POLE EN 52 0 * (50,0) 1 EREF 98 R25 30 99 0 (30,0) 1 5E6 R5 9 98 R26 30 50 2.205E6 5E6 C3 9 25 FSY1 99 54E-12 0 VP 1 G1 98 9 FSY2 0 (6,5) 0.838E-3 50VN 1 V1 8 98 DC1 25 99 -1 DX V2 98 10 DC2 50 25 -1 DX D1 9 10 * DX * MODELS USED D2 8 9 * DX .MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL * NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3 * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz * + RE=4 RC=550 IS=1E-16) R21 11 12 .MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4 1E6 RC=750 IS=1E-16) R22 12 98 .MODEL DX D(IS=1E-15) 100 .MODEL DY D() C14 11 12 .MODEL DQ D(IS=1E-16) 159E-12 .ENDS AD824 E13 11 98 POLY(2) (2,98) (1,98) 0 0.5 0.5 * * POLE AT 10 MHz * R23 18 98 1E6 C15 18 98 15.9E-15 REV. C –15– AD824 OUTLINE DIMENSIONS 14-Lead Standard Small Outline Package [SOIC] 16-Lead Standard Small Outline Package [SOIC] Narrow Body Wide Body (R-14) (R-16) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 10.50 (0.4134) 8.55 (0.3366) 10.10 (0.3976) 14 8 16 9 4.00 (0.1575) 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193) 1.75 (0.0689) 1 8 1.27 (0.0500) 0.50 (0.0197) 10.00 (0.3937) � 45� BSC 1.35 (0.0531) 0.25 (0.0098) 0.25 (0.0098) 0.10 (0.0039) 8� 1.27 (0.0500) 2.65 (0.1043) 0.75 (0.0295) 0.51 (0.0201) 0� BSC SEATING � 45� 1.27 (0.0500) 0.25 (0.0098) COPLANARITY 2.35 (0.0925) 0.25 (0.0098) PLANE 0.33 (0.0130) 0.10 0.40 (0.0157) 0.19 (0.0075) 0.30 (0.0118) 0.10 (0.0039) COMPLIANT TO JEDEC STANDARDS MS-012AB 8� CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.51 (0.0201) 0� SEATING 1.27 (0.0500) (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0.32 (0.0126) COPLANARITY PLANE 0.33 (0.0130) REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.40 (0.0157) 0.10 0.23 (0.0091) COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location Page 2/03–Data Sheet changed from REV. B to REV. C. Deleted N Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1/02–Data Sheet changed from REV. A to REV. B. Edits to ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 –16– REV. C PRINTED IN U.S.A. C00875–0–2/03(C)