ANALOG DEVICES AD8230

16 V Rail-to-Rail, Zero-Drift, Precision Instrumentation Amplifier AD8230 FEATURES CONNECTION DIAGRAM 1 Resistor programmable gain range: 10 to 1000 1 8 –V V S OUT Supply voltage range: ±4 V to ±8 V 2 7 R +V S G Rail-to-rail input and output 3 6 V 1 V 2 REF REF Maintains performance over −40°C to +125°C +IN 4 5 –IN Excellent ac and dc performance AD8230 TOP VIEW 110 dB minimum CMR @ 60 Hz, G = 10 to 1000 (Not to Scale) 10 μV maximum offset voltage (RTI, ±5 V operation) Figure 1. 8-Lead SOIC (R-8) 50 nV/°C maximum offset drift 2.0 20 ppm maximum gain nonlinearity 1.5 APPLICATIONS 1.0 Pressure measurements 0.5 Temperature measurements 0 Strain measurements Automotive diagnostics –0.5 –1.0 GENERAL DESCRIPTION –1.5 The AD8230 is a low drift, differential sampling, precision –2.0 instrumentation amplifier. Auto-zeroing reduces offset voltage –50 –30 –10 10 30 50 70 90 110 130 150 drift to less than 50 nV/°C. The AD8230 is well-suited for TEMPERATURE (°C) thermocouple and bridge transducer applications. The Figure 2. Relative Offset Voltage vs. Temperature AD8230’s high CMR of 110 dB (minimum) rejects line noise in +5V measurements where the sensor is far from the instrumentation. –5V The 16 V rail-to-rail, common-mode input range is useful for 0.1µF noisy environments where ground potentials vary by several 0.1µF volts. Low frequency noise is kept to a minimal 3 μV p-p, 2 4 1 making the AD8230 perfect for applications requiring the V TYPE K THERMOCOUPLE AD8230 8 OUT utmost dc precision. Moreover, the AD8230 maintains its high 7 5 performance over the extended industrial temperature range of 6 34.8kΩ 3 −40°C to +125°C. 284Ω Two external resistors are used to program the gain. By using matched external resistors, the gain stability of the AD8230 is much higher than instrumentation amplifiers that use a single Figure 3. Thermocouple Measurement resistor to set the gain. In addition to allowing users to program 1 the gain between 10 and 1000, users can adjust the output The AD8230 is versatile yet simple to use. Its auto-zeroing offset voltage. topology significantly minimizes the input and output transients typical of commutating or chopper instrumentation amplifiers. The AD8230 operates on ±4 V to ±8 V (+8 V to +16 V) supplies and is available in an 8-lead SOIC. 1 The AD8230 can be programmed for a gain as low as 2, but the maximum input voltage is limited to approximately 750 mV. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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OFFSET VOLTAGE (µV RTI) 05063-041 05063-002 05063-001 AD8230 TABLE OF CONTENTS Features .............................................................................................. 1 Level-Shifting the Output ......................................................... 12 Applications....................................................................................... 1 Source Impedance and Input Settling Time ........................... 12 General Description ......................................................................... 1 Input Voltage Range................................................................... 13 Connection Diagram ....................................................................... 1 Input Protection ......................................................................... 13 Revision History ............................................................................... 2 Power Supply Bypassing............................................................ 13 Specifications..................................................................................... 3 Power Supply Bypassing for Multiple Channel Systems ....... 13 Absolute Maximum Ratings............................................................ 5 Layout .......................................................................................... 14 Thermal Characteristics .............................................................. 5 Applications ................................................................................ 14 ESD Caution.................................................................................. 5 Outline Dimensions ....................................................................... 15 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 15 Theory of Operation ...................................................................... 11 Setting the Gain .......................................................................... 11 REVISION HISTORY 9/07—Rev. A to Rev. B 7/05—Rev. 0 to Rev. A Changes to Features and Layout..................................................... 1 Changes to Excellent AC and DC Performance............................1 Changes to Table 1............................................................................ 3 Changes to Table 1.............................................................................3 Changes to Table 2............................................................................ 4 Changes to Table 2.............................................................................4 Changes to Layout ............................................................................ 5 Changes to Figure 7 and Figure 8....................................................6 Inserted Figure 13, Figure 14, and Figure 15; Renumbered Changes to Figure 10 and Figure 11................................................7 Sequentially ....................................................................................... 7 Changes to Level-Shifting the Output Section........................... 11 Changes to Figure 16 and Figure 19............................................... 8 Changes to Figure 31...................................................................... 11 Updated Outline Dimensions ....................................................... 15 Inserted Figure 32 and Figure 33; Renumbered Sequentially .. 11 Changes to Source Impedance and Input Settling Time Section, Input Protection Section and Power Supply Bypassing for Multiple Channel Systems Section............................................... 12 Changes to Figure 36...................................................................... 13 Changes to Applications Section.................................................. 13 10/04—Revision 0: Initial Version Rev. B | Page 2 of 16 AD8230 SPECIFICATIONS VS = ±5 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted). Table 1. Parameter Conditions Min Typ Max Unit VOLTAGE OFFSET RTI Offset, V V = V = 0 V 10 μV OSI +IN −IN Offset Drift V+IN = V−IN = 0 V, 50 nV/°C TA = −40°C to +125°C COMMON-MODE REJECTION (CMR) CMR to 60 Hz with 1 kΩ Source Imbalance VCM = −5 V to +5 V 110 120 dB VOLTAGE OFFSET RTI vs. SUPPLY (PSR) G = 2 120 120 dB G = 202 120 140 dB GAIN G = 2(1 + R /R) F G 1 Gain Range 10 1000 V/V 2 Gain Error G = 2 0.01 0.04 % G = 10 0.01 0.04 % G = 100 0.01 0.04 % G = 1000 0.02 0.05 % Gain Nonlinearity 20 ppm Gain Drift G = 2, 10, 102 14 ppm/°C G = 1002 60 ppm/°C INPUT Input Common-Mode Operating Voltage Range −VS +VS V Over Temperature T = −40°C to +125°C −V +V V S S Input Differential Operating Voltage Range 750 mV 3 Average Input Offset Current VCM = 0 V 33 300 pA 3 Average Input Bias Current VCM = 0 V 0.15 1 nA OUTPUT Output Swing −VS + 0.1 +VS − 0.2 V Over Temperature T = −40°C to +125°C −VS + 0.1 +VS − 0.2 V Short-Circuit Current 15 mA REFERENCE INPUT 4 Voltage Range −VS + 3.5 +VS − 2.5 V NOISE Voltage Noise Density, 1 kHz, RTI VIN+, VIN−, VREF = 0 V 240 nV/√Hz Voltage Noise f = 0.1 Hz to 10 Hz 3 μV p-p SLEW RATE VIN = 500 mV, G = 10 2 V/μs INTERNAL SAMPLE RATE 6 kHz POWER SUPPLY Operating Range (Dual Supplies) ±4 ±8 V Operating Range (Single Supply) 8 16 V Quiescent Current T = −40°C to +125°C 2.7 3.5 mA TEMPERATURE RANGE Specified Performance −40 +125 °C 1 The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not make use of the full output voltage range. 2 Gain drift is determined by the TC match of the external gain setting resistors. 3 Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors. 4 For G < 10, the reference voltage range is limited to −V + 4.24 V to +V – 2.75 V. S S Rev. B | Page 3 of 16 AD8230 V = ±8 V, V = 0 V, R = 100 kΩ, R = 1 kΩ (@ T = 25°C, G = 202, R = 10 kΩ, unless otherwise noted). S REF F G A L Table 2. Parameter Conditions Min Typ Max Unit VOLTAGE OFFSET RTI Offset, V V = V = 0 V 20 μV OSI +IN −IN Offset Drift V = V = 0 V, 50 nV/°C +IN −IN T = −40°C to +125°C COMMON-MODE REJECTION (CMR) CMR to 60 Hz with 1 kΩ Source Imbalance V = −8 V to +8 V 110 120 dB CM VOLTAGE OFFSET RTI vs. SUPPLY (PSR) G = 2 120 120 dB G = 202 120 140 dB GAIN G = 2(1 + RF/RG) 1 Gain Range 10 1000 V/V 2 Gain Error G = 2 0.01 0.04 % G = 10 0.01 0.04 % G = 100 0.01 0.04 % G = 1000 0.02 0.05 % Gain Nonlinearity 20 ppm Gain Drift G = 2, 10, 102 14 ppm/°C G=1002 60 ppm/°C INPUT Input Common-Mode Operating Voltage Range −VS +VS V Over Temperature T = −40°C to +125°C −VS +VS V Input Differential Operating Voltage Range 750 mV 3 Average Input Offset Current V = 0 V 33 300 pA CM 3 Average Input Bias Current V = 0 V 0.15 1 nA CM OUTPUT Output Swing −V + 0.1 +V − 0.2 V S S Over Temperature T = −40°C to +125°C −V + 0.1 +V − 0.4 V S S Short-Circuit Current 15 mA REFERENCE INPUT 4 Voltage Range −V + 3.5 +V − 2.5 V S S NOISE Voltage Noise Density, 1 kHz, RTI V , V , V = 0 V 240 nV/√Hz IN+ IN− REF Voltage Noise f = 0.1 Hz to 10 Hz 3 μV p-p SLEW RATE V = 500 mV, G = 10 2 V/μs IN INTERNAL SAMPLE RATE 6 kHz POWER SUPPLY Operating Range (Dual Supplies) ±4 ±8 V Operating Range (Single Supply) 8 16 V Quiescent Current T = −40°C to +125°C 3.2 4 mA TEMPERATURE RANGE Specified Performance −40 +125 °C 1 The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not make use of the full output voltage range. 2 Gain drift is determined by the TC match of the external gain setting resistors. 3 Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors. 4 For G < 10, the reference voltage range is limited to −VS + 4.24 V to +VS − 2.75V. Rev. B | Page 4 of 16 AD8230 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 3. Parameter Rating Specification is for device in free air SOIC. Supply Voltage ±8 V, +16 V Table 4. Internal Power Dissipation 304 mW Parameter Value Unit Output Short-Circuit Current 20 mA θJA (4-Layer JEDEC Board) 121 °C/W Input Voltage (Common-Mode) ±V S Differential Input Voltage ±V S Storage Temperature Range −65°C to +150°C ESD CAUTION Operational Temperature Range −40°C to +125°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 16 AD8230 TYPICAL PERFORMANCE CHARACTERISTICS 20 TOTAL NUMBER OF SAMPLES = 2839 FROM 3 LOTS NORMALIZED FOR V = 0V CM 500 15 10 400 5 300 0 200 –5 –10 100 –15 0 –20 –9 –6 –3 0 3 6 9 –6 –4 –2 0 2 4 6 OFFSET VOLTAGE (µV RTI) COMMON-MODE VOLTAGE (V) Figure 4. Offset Voltage (RTI) Distribution at ±5 V, CM = 0 V, TA = 25°C Figure 7. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = ±5 V 40 20 TOTAL NUMBER OF SAMPLES = 300 FROM 3 LOTS NORMALIZED FOR V = 0V CM 35 15 30 10 25 5 20 0 15 –5 10 –10 5 –15 0 –20 –50 –30 –10 10 30 50 –10 –8–6 –4–2 0 2 4 6 8 10 OFFSET VOLTAGE DRIFT (nV/°C) COMMON-MODE VOLTAGE (V) Figure 5. Offset Voltage (RTI) Drift Distribution Figure 8. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = ±8 V 0 0 –2 –1 –4 V =±5V S –2 –6 –8 –3 –10 –4 V =±8V S –12 –5 ±5V SUPPLY –14 –6 –16 –18 –7 ±8V SUPPLY –20 –8 –50 –30 –10 10 30 50 70 90 110 130 150 01 23 4 5 6 TEMPERATURE (°C) SOURCE IMPEDANCE (kΩ) Figure 6. Offset Voltage (RTI) vs. Temperature Figure 9. Offset Voltage (RTI) vs. Source Impedance, 1 μF Across Input Pins Rev. B | Page 6 of 16 OFFSET VOLTAGE (µV RTI) SAMPLES SAMPLES 05063-004 05063-006 05063-005 OFFSET VOLTAGE (µV) OFFSET VOLTAGE (µV RTI) OFFSET VOLTAGE (µV RTI) 05063-009 05063-008 05063-007 AD8230 40 10 –856mV, +8.2V 0V, +8.4V +592mV, +8.2V NORMALIZED FOR V = 0V REF 8 30 V = ±8V S 6 20 –812mV, +5V +644mV, +5V 4 0V, +5.5V 10 2 V = ±5V S 0 0 –2 –10 –652mV, –5V +800mV, –5V –4 0V, –5.5V –20 –6 –30 –8 –616mV, –8.2V +840mV, –8.2V 0V, –8.4V –40 –10 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 V (V) REF OUTPUT VOLTAGE (mV) Figure 13. Input Common-Mode Voltage Range vs. Output Voltage, G = 2 Figure 10. Offset Voltage (RTI) vs. Reference Voltage 130 10 V = ±8V S –7.9V, +8V +7.9V, +8V CMR WITH NO SOURCE IMBALANCE 8 120 –4.9V, +5V +4.88V, +5V 6 110 4 100 V = ±5V S 2 90 0 80 –2 70 CMR WITH 1kΩ SOURCE IMBALANCE –4 60 –6 –4.9V, –5V +4.88V, –5V 50 –8 –7.9V, –8V +7.9V, –8V 40 –10 10 100 1k 10k –10 –8 –6 –4 –2 0 2 4 6 8 10 FREQUENCY (Hz) OUTPUT VOLTAGE (V) Figure 14. Input Common-Mode Voltage Range vs. Output Voltage, G = 10 Figure 11. Common-Mode Rejection (CMR) vs. Frequency 130 10 –7.9V, +8V +7.9V, +8V 128 8 V = ±8V S 126 6 –4.8V, +5.5V +4.8V, +5.5V 124 4 122 2 V = ±5V S 120 ±5V SUPPLY 0 118 –2 ±8V SUPPLY 116 –4 –4.8V, –5.5V +4.8V, –5.5V 114 –6 112 –8 –7.9V, –8V +7.9V, –8V –10 110 02 46 8 10 12 –10 –8 –6 –4 –2 0 2 4 6 8 10 SOURCE IMPEDANCE (kΩ) OUTPUT VOLTAGE (V) Figure 15. Input Common-Mode Voltage Range vs. Output Voltage, G = 100 Figure 12. Common-Mode Rejection (CMR) vs. Source Impedance, 1.1 μF Across Input Pins Rev. B | Page 7 of 16 CMR (dB) CMR (dB) OFFSET VOLTAGE (µV RTI) 05063-012 05063-011 05063-010 INPUT COMMON-MODE VOLTAGE RANGE (V) INPUT COMMON-MODE VOLTAGE RANGE (V) INPUT COMMON-MODE VOLTAGE RANGE (V) 05063-015 05063-014 05063-013 AD8230 90 6.8 80 6.6 70 6.4 60 ±8V 50 6.2 40 6.0 30 ±5V 20 5.8 10 5.6 0 5.4 –10 –50 –30 –10 10 30 50 70 90 110 130 10 100 1k 10k 100k TEMPERATURE (°C) FREQUENCY (Hz) Figure 16. Clock Frequency vs. Temperature Figure 19. Gain vs. Frequency, G = 2 1.0 90 +85°C 0.8 80 +125°C 0.6 70 0.4 –40°C 60 0.2 50 0 40 –0.2 30 –0.4 20 0°C –0.6 10 –0.8 +25°C 0 –1.0 –10 –6 –4 –2 0 2 4 6 10 100 1k 10k 100k COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 17. Average Input Bias Current vs. Common-Mode Voltage, Figure 20. Gain vs. Frequency, G = 10 −40°C, +25°C, +85°C, +125°C 3.5 40 G = +20 3.4 30 ±8V 3.3 20 3.2 10 3.1 3.0 0 ±5V 2.9 –10 2.8 –20 2.7 –30 2.6 –40 2.5 –5 –4 –3 –2 –1 0 1 2 3 4 5 –50 0 50 100 150 V (V) TEMPERATURE (°C) OUT Figure 18. Supply Current vs. Temperature Figure 21. Gain Nonlinearity, G = 20 Rev. B | Page 8 of 16 SUPPLY CURRENT (mA) AVERAGE INPUT BIAS CURRENT (µA) CLOCK FREQUENCY (kHz) 05063-018 05063-017 05063-016 NONLINEARITY (ppm) GAIN (dB) GAIN (dB) 05063-021 05063-020 05063-019 AD8230 90 0.35 80 0.30 70 0.25 60 50 0.20 40 0.15 30 20 0.10 10 0.05 0 –10 0 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Gain vs. Frequency, G = 100 Figure 25. Voltage Noise Spectral Density vs. Frequency 90 3.90 80 3.70 70 3.50 60 50 3.30 40 3.10 30 20 2.90 10 2.70 0 –10 2.50 10 100 1k 10k 100k 2µV/DIV 1s/DIV –50 –30 –10 10 30 50 70 90 110 130 FREQUENCY (Hz) TEMPERATURE (°C) Figure 23. Gain vs. Frequency, G = 1000 Figure 26. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100 0.010 160 0.008 140 0.006 G = +1000 120 0.004 100 0.002 G = +100 G = +10 0 80 G = +2 –0.002 60 –0.004 40 –0.006 20 –0.008 –0.010 0 01 501520 0.1 1 10 SOURCE IMPEDANCE (kΩ) FREQUENCY (kHz) Figure 24. Gain Error vs. Differential Source Impedance Figure 27. Positive PSR vs. Frequency, RTI Rev. B | Page 9 of 16 GAIN ERROR (%) GAIN (dB) GAIN (dB) 05063-024 05063-023 05063-022 PSR (dB) POSITIVE SUPPLY CURRENT (mA) VOLTAGE NOISE (µV/ Hz) 05063-025 05063-027 05063-026 AD8230 140 10 V =±8V –40°C S 8 120 G = +100 6 –40°C +125°C 100 +25°C 4 V =±5V S G = +1000 2 80 +125°C +25°C 0 G = +10 60 +25°C –2 G = +2 +125°C =±5V V S –4 40 +25°C –40°C –6 +125°C 20 –8 V =±8V S –40°C 0 –10 0.1 1 10 02 468 10 12 FREQUENCY (kHz) OUTPUT CURRENT (mA) Figure 28. Negative PSR vs. Frequency, RTI Figure 29. Output Voltage Swing vs. Output Current, −40°C, +25°C, +85°C, +125°C Rev. B | Page 10 of 16 PSR (dB) 05063-028 OUTPUT VOLTAGE SWING (V) 05063-029 AD8230 THEORY OF OPERATION Auto-zeroing is a dynamic offset and drift cancellation In Phase B, the differential signal is transferred to the hold technique that reduces input-referred voltage offset to the capacitors refreshing the value stored on CHOLD. The output of μV level and voltage offset drift to the nV/°C level. A further the preamplifier is held at a common-mode voltage determined advantage of dynamic offset cancellation is the reduction of by the reference potential, VREF. In this manner, the AD8230 is low frequency noise, in particular the 1/f component. able to condition the difference signal and set the output voltage level. The gain amplifier conditions the updated signal stored The AD8230 is an instrumentation amplifier that uses an on the hold capacitors, C . HOLD auto-zeroing topology and combines it with high common- mode signal rejection. The internal signal path consists of an SETTING THE GAIN active differential sample-and-hold stage (preamp) followed by Two external resistors set the gain of the AD8230. The gain is a differential amplifier (gain amp). Both amplifiers implement expressed in the following equation: auto-zeroing to minimize offset and drift. A fully differential R F topology increases the immunity of the signals to parasitic noise Gain= 2(1+ ) (1) R and temperature effects. Amplifier gain is set by two external G resistors for convenient TC matching. +V S –V S The signal sampling rate is controlled by an on-chip, 6 kHz 0.1µF 10µF oscillator and logic to derive the required nonoverlapping 0.1µF 10µF clock phases. For simplification of the functional description, 2 4 two sequential clock phases, A and B, are shown to distinguish 1 AD8230 the order of internal operation, as depicted in Figure 30 and 8 V R OUT G V 2 7 5 REF Figure 31, respectively. 6 V 1 REF R F PREAMP GAIN AMP 3 R G –V S C HOLD V +IN + – V OUT V DIFF C SAMPLE +V Figure 32. Gain Setting CM – + V –IN C HOLD Table 5. Gains Using Standard 1% Resistors –V S Gain R R Actual Gain F G 2 0 Ω (short) None 2 V R R REF G F 10 8.06 kΩ 2 kΩ 10 Figure 30. Phase A of the Sampling Phase 50 12.1 kΩ 499 Ω 50.5 During Phase A, the sampling capacitors are connected to the 100 9.76 kΩ 200 Ω 99.6 inputs. The input signal’s difference voltage, VDIFF, is stored 200 10 kΩ 100 Ω 202 across the sampling capacitors, CSAMPLE. Because the sampling 500 49.9 kΩ 200 Ω 501 capacitors only retain the difference voltage, the common-mode 1000 100 kΩ 200 Ω 1002 voltage is rejected. During this period, the gain amplifier is not connected to the preamplifier so its output remains at the level Figure 32 and Table 5 provide an example of some gain settings. set by the previously sampled input signal held on C , as HOLD As Table 5 shows, the AD8230 accepts a wide range of resistor shown in Figure 30. values. Because the instrumentation amplifier has finite driving GAIN AMP PREAMP capability, ensure that the output load in parallel with the sum of the gain setting resistors is greater than 2 kΩ. –V S C HOLD V R ||(R + R ) > 2 kΩ (2) L F G +IN – V + OUT V DIFF C SAMPLE +V Offset voltage drift at high temperature can be minimized by CM – + V –IN keeping the value of the feedback resistor, R , small. This is due C F HOLD –V S to the junction leakage current on the RG pin, Pin 7. The effect of the gain setting resistor on offset voltage drift is shown in V R R REF G F Figure 33. In addition, experience has shown that wire-wound Figure 31. Phase B of the Sampling Phase resistors in the gain feedback loop may degrade the offset voltage performance. Rev. B | Page 11 of 16 05063-031 05063-030 05063-032 AD8230 0 The following steps can be taken to set the gain and level-shift the output: –1 1. Select an R value. Table 5 shows R values for various gains. F F Solve for R using Equation 4. 2. O –2 V ×R R' F R =− (4) O V DESIRED −LEVEL –3 R = 100kΩ, R = 1kΩ F G where: VR’ is a voltage source, such as a supply voltage. –4 VDESIRED-LEVEL is the desired output bias voltage. R = 10kΩ, R = 100Ω F G 3. Solve for RG. –5 –50 0 50 100 150 R O R = (5) TEMPERATURE (°C) G R Gain ⎛ ⎞ O −1 −1 Figure 33. Effect of Feedback Resistor on Offset Voltage Drift ⎜ ⎟ 2 R ⎝ ⎠ F LEVEL-SHIFTING THE OUTPUT +V S –V S A reference voltage, as shown in Figure 34, can be used to 0.1µF level-shift the output. The reference voltage, VR, is limited to 0.1µF −V + 3.5 V to +V − 2.5 V. (For G < 10, the reference voltage S S 2 range is limited to −V + 4.24 V to +V – 2.75 V.) Otherwise, it S S 4 1 is nominally tied to midsupply. The voltage source used to level- 8 V AD8230 OUT shift the output should have a low output impedance to avoid 7 5 R 6 F contributing to gain error. In addition, it should be able to 3 source and sink current. To minimize offset voltage, the VREF R G R O pins should be connected either to the local ground or to a reference voltage source that is connected to the local ground. V ' R +V S Figure 35. Level-Shifting the Output Without an –V S Additional Voltage Reference 0.1µF +5V 0.1µF –5V 2 0.1µF 4 1 0.1µF 8 V AD8230 OUT 7 5 2 6 4 1 3 R F V AD8230 8 OUT R 7 5 G 6 9.76kΩ 3 V R 203Ω 10.2kΩ Figure 34. Level-Shifting the Output +5V The output can also be level-shifted by adding a resistor, R , as O Figure 36. An AD8230 with its Output Biased at −4.8 V; shown in Figure 35. The benefit is that the output can be level- G = 100; VDESIRED-LEVEL = −4.8 V shifted to as low as 100 mV of the negative supply rail and to as SOURCE IMPEDANCE AND INPUT SETTLING TIME high as 200 mV of the positive supply rail, increasing unipolar The input stage of the AD8230 consists of two actively driven, output swing. This can be useful in applications, such as strain differential switched capacitors, as described in Figure 30 and gauges, where the force is only applied in one direction. Another Figure 31. Differential input signals are sampled on CSAMPLE such benefit of this configuration is that a supply rail can be used for that the associated parasitic capacitances, 70 pF, are balanced V eliminating the need to add an additional external reference R’ between the inputs to achieve high common-mode rejection. voltage. On each sample period (approximately 85 μs), these parasitic The gain changes with the inclusion of R . The full expression is O capacitances must be recharged to the common-mode voltage ⎛ ⎞ ⎛ ⎞ by the signal source impedance (10 kΩ maximum). If resistors R R R() R +R R F F F G O F (3) ⎜ ⎟ ⎜ ⎟ V = 2 + 1 V − V = 2 + 1 V − V OUT IN IN R R' ' ⎜ ⎟ ⎜ ⎟ R ||R R R R R and capacitors are used at the input of the AD8230, care should ⎝ G O ⎠ O ⎝ G O ⎠ O be taken to maintain close match to maximize CMRR. Rev. B | Page 12 of 16 OFFSET VOLTAGE (µV RTI) 05063-034 05063-033 05063-036 05063-035 AD8230 INPUT VOLTAGE RANGE POWER SUPPLY BYPASSING The input common-mode range of the AD8230 is rail to rail. A regulated dc voltage should be used to power the However, the differential input voltage range is limited to instrumentation amplifier. Noise on the supply pins can approximately 750 mV. The AD8230 does not phase invert adversely affect performance. Bypass capacitors should be when its inputs are overdriven. used to decouple the amplifier. The AD8230 has internal clocked circuitry that requires INPUT PROTECTION adequate supply bypassing. A 0.1 μF capacitor should be placed The input voltage is limited to within 0.6 V beyond the supply as close to each supply pin as possible. As shown in Figure 32, a rails by the internal ESD protection diodes. Resistors and low 10 μF tantalum capacitor can be used further away from the part. leakage diodes can be used to limit excessive, external voltage and current from damaging the inputs, as shown in Figure 37. POWER SUPPLY BYPASSING FOR MULTIPLE Figure 39 shows an overvoltage protection circuit between the CHANNEL SYSTEMS thermocouple and the AD8230. The best way to prevent clock interference in multichannel +V S systems is to lay out the PCB with a star node for the positive –V S BAV199 supply and a star node for the negative supply. Using such a 0.1µF +V –V S S technique, crosstalk between clocks is minimized. If laying out 0.1µF star nodes is not feasible, use wide traces to minimize parasitic 2 inductance and decouple frequently along the power supply 4 1 2.49kΩ 8 V AD8230 traces. Examples are shown in Figure 38. Care and forethought OUT 2.49kΩ 7 5 go a long way in maximizing performance. 6 19.1kΩ 3 200Ω +V –V S S BAV199 Figure 37. Overvoltage Input Protection –V S +V S 1µF 1µF 1µF 1µF 10µF 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF –V –V –V –V –V S S S S S 1 8 1 8 1 8 1 8 1 8 +V +V +V +V +V S S S S S 2 7 2 7 2 7 2 7 2 7 3 6 3 6 3 6 3 6 3 6 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 4 5 4 5 4 5 4 5 4 5 AD8230 AD8230 AD8230 AD8230 AD8230 STAR –V S 10µF STAR +V S 10µF 0.1µF 0.1µF 0.1µF 0.1µF –V –V –V –V S S S S 1 1 8 1 8 1 8 8 +V +V +V +V S S S S 2 7 2 7 2 7 2 7 3 6 3 6 3 6 3 6 0.1µF 0.1µF 0.1µF 0.1µF 4 5 4 5 4 5 4 5 AD8230 AD8230 AD8230 AD8230 Figure 38. Use Star Nodes for +VS and −VS or Use Thick Traces and Decouple Frequently Along the Supply Lines Rev. B | Page 13 of 16 05063-037 05063-038 AD8230 An antialiasing filter reduces unwanted high frequency signals. LAYOUT The matched 100 MΩ resistors serve to provide input bias The AD8230 has two reference pins: VREF1 and VREF2. VREF1 current to the input transistors and serve as an indicator as to draws current to set the internal voltage references. In contrast, when the thermocouple connection is broken. Well-matched VREF2 does not draw current. It sets the common mode of the 1% 4.99 kΩ resistors are used to form the antialiasing filter. It is output signal. As such, V 1 and V 2 should be star-connected to REF REF good practice to match the source impedances to ensure high ground (or to a reference voltage). In addition, to maximize CMR. The circuit is configured for a gain of 193, which CMR, the trace between V 2 and the gain resistor, R , should REF G provides an overall temperature sensitivity of 10 mV/°C. be kept short. +V S –V APPLICATIONS S 0.1µF The AD8230 can be used in thermocouple applications, as 0.1µF +V S shown in Figure 3 and Figure 39. Figure 39 is an example of 2 such a circuit for use in an industrial environment. Series 4 1 4kΩ resistors and low leakage diodes serve to clamp overload 8 V AD8230 OUT 350Ω 350Ω 7 voltages (see the Input Protection section for more information). 1µF 5 6 +V 3 102kΩ S BAV199 350Ω 350Ω +V –V –V S S S 1kΩ +V 0.1µF S 0.1µF –V S 100MΩ 2 TYPE J Figure 40. Bridge Measurement with Filtered Output 4 1 THERMOCOUPLE 4.99kΩ V 1µF 8 AD8230 OUT Measuring load cells in industrial environments can be a 4.99kΩ 7 5 challenge. Often, the load cell is located some distance away 6 100MΩ 19.1kΩ 3 from the instrumentation amplifier. The common-mode –V S 200Ω potential can be several volts, exceeding the common-mode input range of many 5 V auto-zero instrumentation amplifiers. +V –V S S BAV199 Fortunately, the wide common-mode input voltage range of the Figure 39. Type J Thermocouple with Overvoltage Protection and RFI Filter AD8230 spans 16 V, relieving designers of having to worry about the common-mode range. Rev. B | Page 14 of 16 05063-039 05063-040 AD8230 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 41. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD8230YRZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8230YRZ-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8230YRZ-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8230-EVAL Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 15 of 16 012407-A AD8230 NOTES ©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05063-0-9/07(B) Rev. B | Page 16 of 16