ANALOG DEVICES AD823

Dual, 16 MHz, Rail-to-Rail FET Input Amplifier Data Sheet AD823 FEATURES CONNECTION DIAGRAM Single-supply operation OUT1 1 8 +V S Output swings rail-to-rail –IN1 2 7 OUT2 +IN1 3 6 –IN2 Input voltage range extends below ground –V 4 5 +IN2 S Single-supply capability from 3 V to 36 V AD823 High load drive Figure 1. 8-Lead PDIP and SOIC Capacitive load drive of 500 pF, G = +1 Output current of 15 mA, 0.5 V from supplies Excellent ac performance on 2.6 mA/amplifier R = 100kΩ L C = 50pF L −3 dB bandwidth of 16 MHz, G = +1 +V = +3V S G = +1 350 ns settling time to 0.01% (2 V step) 3V Slew rate of 22 V/µs Good dc performance 800 µV maximum input offset voltage 2 µV/°C offset voltage drift 25 pA maximum input bias current Low distortion: −108 dBc worst harmonic @ 20 kHz Low noise: 16 nV/√Hz @ 10 kHz GND No phase inversion with inputs to the supply rails 500mV 200µs APPLICATIONS Figure 2. Output Swing, +V = +3 V, G = +1 S Battery-powered precision instrumentation Photodiode preamps 2 +V = +5V S Active filters 1 G = +1 12-bit to 16-bit data acquisition systems 0 Medical instrumentation –1 GENERAL DESCRIPTION –2 The AD823 is a dual precision, 16 MHz, JFET input op amp –3 that can operate from a single supply of 3.0 V to 36 V or from –4 dual supplies of ±1.5 V to ±18 V. It has true single-supply –5 capability with an input voltage range extending below ground –6 in single-supply mode. Output voltage swing extends to within –7 50 mV of each rail for I ≤ 100 µA, providing outstanding OUT –8 output dynamic range. 1k 10k 100k 1M 10M FREQUENCY (Hz) An offset voltage of 800 µV maximum, an offset voltage drift of Figure 3. Small Signal Bandwidth, G = +1 2 µV/°C, input bias currents below 25 pA, and low input voltage noise provide dc precision with source impedances up to a This combination of ac and dc performance, plus the outstanding Gigaohm. It provides 16 MHz, −3 dB bandwidth, −108 dB THD load drive capability, results in an exceptionally versatile ampli- @ 20 kHz, and a 22 V/µs slew rate with a low supply current of fier for applications such as A/D drivers, high speed active 2.6 mA per amplifier. The AD823 drives up to 500 pF of direct filters, and other low voltage, high dynamic range systems. capacitive load as a follower and provides an output current of The AD823 is available over the industrial temperature range of 15 mA, 0.5 V from the supply rails. This allows the amplifier to −40°C to +85°C and is offered in both 8-lead PDIP and 8-lead handle a wide range of load conditions. SOIC packages. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1995–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. OUTPUT (dB) 00901-001 00901-003 00901-002 AD823 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Typical Performance Characteristics ..............................................7  Applications ....................................................................................... 1  Theory of Operation ...................................................................... 13  General Description ......................................................................... 1  Output Impedance ..................................................................... 14  Connection Diagram ....................................................................... 1  Application Notes ........................................................................... 15  Revision History ............................................................................... 2  Input Characteristics .................................................................. 15  Specif ica t ions ..................................................................................... 3  Output Characteristics............................................................... 15  Absolute Maximum Ratings ............................................................ 6  Outline Dimensions ....................................................................... 18  Thermal Resistance ...................................................................... 6  Ordering Guide .......................................................................... 19  ESD Caution .................................................................................. 6  REVISION HISTORY 11/11—Rev. D to Rev. E Changes to Theory of Operation Section .................................... 13 Changes to Ordering Guide .......................................................... 19 6/10—Rev. C to Rev. D Changes to Figure 34 ...................................................................... 11 Changes to Figure 36 ...................................................................... 13 5/10—Rev. B to Rev. C Changes to Table 4 ............................................................................ 6 2/07—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to DC Performance .......................................................... 5 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide ......................................................... 19 5/04—Rev. 0 to Rev. A Changes to Specifications ................................................................ 2 Changes to Ordering Guide ......................................................... 17 Updated Outline Dimensions ....................................................... 17 5/95—Revision 0: Initial Version Rev. E | Page 2 of 20 Data Sheet AD823 SPECIFICATIONS At TA = 25°C, +VS = +5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth, V ≤ 0.2 V p-p G = +1 12 16 MHz O Full Power Response VO = 2 V p-p 3.5 MHz Slew Rate G = −1, VO = 4 V Step 14 22 V/µs Settling Time to 0.1% G = −1, V = 2 V Step 320 ns O to 0.01% G = −1, V = 2 V Step 350 ns O NOISE/DISTORTION PERFORMANCE Input Voltage Noise f = 10 kHz 16 nV/√Hz Input Current Noise f = 1 kHz 1 fA/√Hz Harmonic Distortion RL = 600 Ω to 2.5 V, VO = 2 V p-p, f = 20 kHz −108 dBc Crosstalk f = 1 kHz RL = 5 kΩ −105 dB f = 1 MHz R = 5 kΩ −63 dB L DC PERFORMANCE Initial Offset 0.2 0.8 mV Maximum Offset Over temperature 0.3 2.0 mV Offset Drift 2 µV/°C Input Bias Current V = 0 V to 4 V 3 25 pA CM at TMAX VCM = 0 V to 4 V 0.5 5 nA Input Offset Current 2 20 pA at T 0.5 nA MAX Open-Loop Gain V = 0.2 V to 4 V, R = 2 kΩ 20 45 V/mV O L T to T 20 V/mV MIN MAX INPUT CHARACTERISTICS Input Common-Mode Voltage Range −0.2 to +3 −0.2 to +3.8 V 13 Input Resistance 10 Ω Input Capacitance 1.8 pF Common-Mode Rejection Ratio VCM = 0 V to 3 V 60 76 dB OUTPUT CHARACTERISTICS Output Voltage Swing IL = ±100 µA 0.025 to 4.975 V IL = ±2 mA 0.08 to 4.92 V I = ±10 mA 0.25 to 4.75 V L Output Current V = 0.5 V to 4.5 V 16 mA OUT Short-Circuit Current Sourcing to 2.5 V 40 mA Sinking to 2.5 V 30 mA Capacitive Load Drive G = +1 500 pF POWER SUPPLY Operating Range 3 36 V Quiescent Current TMIN to TMAX, total 5.2 5.6 mA Power Supply Rejection Ratio V = 5 V to 15 V, T to T 70 80 dB S MIN MAX Rev. E | Page 3 of 20 AD823 Data Sheet At T = 25°C, +V = +3.3 V, R = 2 kΩ to 1.65 V, unless otherwise noted. A S L Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth, V ≤ 0.2 V p-p G = +1 12 15 MHz O Full Power Response V = 2 V p-p 3.2 MHz O Slew Rate G = −1, V = 2 V Step 13 20 V/µs O Settling Time to 0.1% G = −1, VO = 2 V Step 250 ns to 0.01% G = −1, VO = 2 V Step 300 ns NOISE/DISTORTION PERFORMANCE Input Voltage Noise f = 10 kHz 16 nV/√Hz Input Current Noise f = 1 kHz 1 fA/√Hz Harmonic Distortion R = 100 Ω, V = 2 V p-p, f = 20 kHz −93 dBc L O Crosstalk f = 1 kHz RL = 5 kΩ −105 dB f = 1 MHz RL = 5 kΩ −63 dB DC PERFORMANCE Initial Offset 0.2 1.5 mV Maximum Offset Over temperature 0.5 2.5 mV Offset Drift 2 µV/°C Input Bias Current V = 0 V to 2 V 3 25 pA CM at T V = 0 V to 2 V 0.5 5 nA MAX CM Input Offset Current 2 20 pA at TMAX 0.5 nA Open-Loop Gain VO = 0.2 V to 2 V, RL = 2 kΩ 15 30 V/mV TMIN to TMAX 12 V/mV INPUT CHARACTERISTICS Input Common-Mode Voltage Range −0.2 to +1 −0.2 to +1.8 V 13 Input Resistance 10 Ω Input Capacitance 1.8 pF Common-Mode Rejection Ratio V = 0 V to 1 V 54 70 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing I = ±100 µA 0.025 to 3.275 V L IL = ±2 mA 0.08 to 3.22 V IL = ±10 mA 0.25 to 3.05 V Output Current VOUT = 0.5 V to 2.5 V 15 mA Short-Circuit Current Sourcing to 1.5 V 40 mA Sinking to 1.5 V 30 mA Capacitive Load Drive G = +1 500 pF POWER SUPPLY Operating Range 3 36 V Quiescent Current TMIN to TMAX, total 5.0 5.7 mA Power Supply Rejection Ratio VS = 3.3 V to 15 V, TMIN to TMAX 70 80 dB Rev. E | Page 4 of 20 Data Sheet AD823 At T = 25°C, V = ±15 V, R = 2 kΩ to 0 V, unless otherwise noted. A S L Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth, V ≤ 0.2 V p-p G = +1 12 16 MHz O Full Power Response V = 2 V p-p 4 MHz O Slew Rate G = −1, V = 10 V Step 17 25 V/µs O Settling Time to 0.1% G = −1, VO = 10 V Step 550 ns to 0.01% G = −1, VO = 10 V Step 650 ns NOISE/DISTORTION PERFORMANCE Input Voltage Noise f = 10 kHz 16 nV/√Hz Input Current Noise f = 1 kHz 1 fA/√Hz Harmonic Distortion R = 600 Ω, V = 10 V p-p, f = 20 kHz −90 dBc L O Crosstalk f = 1 kHz RL= 5 kΩ −105 dB f = 1 MHz RL= 5 kΩ −63 dB DC PERFORMANCE Initial Offset 0.7 3.5 mV Maximum Offset Over temperature 1.0 7 mV Offset Drift 2 µV/°C Input Bias Current V = 0 V 5 30 pA CM V = −10 V 60 pA CM at T V = 0 V 0.5 5 nA MAX CM Input Offset Current 2 20 pA at TMAX 0.5 nA Open-Loop Gain VO = +10 V to −10 V, RL = 2 kΩ 30 60 V/mV T to T 30 V/mV MIN MAX INPUT CHARACTERISTICS Input Common-Mode Voltage Range −15.2 to +13 −15.2 to +13.8 V 13 Input Resistance 10 Ω Input Capacitance 1.8 pF Common-Mode Rejection Ratio VCM = −15 V to +13 V 66 82 dB OUTPUT CHARACTERISTICS Output Voltage Swing IL = ±100 µA −14.95 to +14.95 V IL = ±2 mA −14.92 to +14.92 V IL = ±10 mA −14.75 to +14.75 V Output Current V = −14.5 V to +14.5 V 17 mA OUT Short-Circuit Current Sourcing to 0 V 80 mA Sinking to 0 V 60 mA Capacitive Load Drive G = +1 500 pF POWER SUPPLY Operating Range 3 36 V Quiescent Current TMIN to TMAX, total 7.0 8.4 mA Power Supply Rejection Ratio VS = 5 V to 15 V, TMIN to TMAX 70 80 dB Rev. E | Page 5 of 20 AD823 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Supply Voltage 36 V Internal Power Dissipation Specification is for device in free air. PDIP (N) 1.3 W Table 5. Thermal Resistance SOIC (R) 0.9 W Package Type θ Unit Input Voltage (Common Mode) ±VS JA Differential Input Voltage ±V 8-Lead PDIP 90 °C/W S Output Short-Circuit Duration See Figure 4 8-Lead SOIC 160 °C/W Storage Temperature Range N, R −65°C to +125°C Operating Temperature Range −40°C to +85°C 2.0 T = 150°C J Lead Temperature Range 300°C 8-LEAD PDIP (Soldering, 10 sec) Stresses above those listed under Absolute Maximum Ratings 1.5 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational 1.0 section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect 8-LEAD SOIC 0.5 device reliability. 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Temperature ESD CAUTION Rev. E | Page 6 of 20 MAXIMUM POWER DISSIPATION (W) 00901-004 Data Sheet AD823 TYPICAL PERFORMANCE CHARACTERISTICS 100 80 +V = +5V +V = +5V S S 317 UNITS 314 UNITS 90 70 σ = 40µV σ = 0.4pA 80 60 70 50 60 40 50 40 30 30 20 20 10 10 0 0 –200 –150 –100 –50 0 50 100 150 200 0 1 2 3 4 5 6 7 8 9 10 INPUT OFFSET VOLTAGE (µV) INPUT BIAS CURRENT (pA) Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Bias Current 10000 22 +V = +5V +V = +5V S S V = 0V 20 –55°C TO +125°C CM 103 UNITS 18 1000 16 14 100 12 10 10 8 6 1 4 2 0.1 0 0 25 50 75 100 125 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 TEMPERATURE (°C) INPUT OFFSET VOLTAGE DRIFT (µV/°C) Figure 6. Typical Distribution of Input Offset Voltage Drift Figure 9. Input Bias Current vs. Temperature 3 1000 +V = +5V S V = ±15V S 2 100 1 0 10 –1 –2 1 –3 –4 0.1 –5 –4 –3 –2 –1 0 1 2 3 4 5 –16 –12 –8 –4 0 4 8 12 16 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) Figure 7. Input Bias Current vs. Common-Mode Voltage Figure 10. Input Bias Current vs. Common-Mode Voltage Rev. E | Page 7 of 20 UNITS INPUT BIAS CURRENT (pA) UNITS 00901-007 00901-006 00901-005 INPUT BIAS CURRENT (pA) INPUT BIAS CURRENT (pA) UNITS 00901-008 00901-010 00901-009 AD823 Data Sheet 110 95 R = 2kΩ V = ±2.5V L S +V = +5V S 94 100 93 92 90 91 90 80 89 88 70 87 60 86 100 1k 10k 100k 500k –55 –25 5 35 65 95 125 LOAD RESISTANCE (Ω) TEMPERATURE (°C) Figure 11. Open-Loop Gain vs. Load Resistance Figure 14. Open-Loop Gain vs. Temperature 1000 100 100 R = 2kΩ L C = 20pF L R = 10kΩ L 80 80 100 PHASE 60 60 R = 1kΩ L 10 40 40 GAIN R = 100Ω L 20 20 1 0 0 0.1 –20 –20 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 100 1k 10k 100k 1M 10M 100M OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 12. Open-Loop Gain vs. Output Voltage, V = ±2.5 V Figure 15. Open-Loop Gain and Phase Margin vs. Frequency S –40 100 +V = +5V S –50 –60 +V = +3V S 30 V = 2V p-p OUT ALL R = 100Ω –70 L OTHERS –80 V = ±2.5V S V = 2V p-p OUT +V = +3V S V = ±15V S 10 R = 1kΩ L V = 2V p-p OUT –90 V = 10V p-p OUT R = 5kΩ L R = 600Ω L +V = +5V S –100 V = 2V p-p OUT R = 5kΩ L –110 3 10 100 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Total Harmonic Distortion vs. Frequency Figure 16. Input Voltage Noise vs. Frequency Rev. E | Page 8 of 20 THD (dB) V OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (k ) V 00901-013 00901-011 00901-012 OPEN-LOOP GAIN (dB) INPUT VOLTAGE NOISE (nV/√Hz) OPEN-LOOP GAIN (dB) PHASE MARGIN (Degrees) 00901-016 00901-014 00901-015 Data Sheet AD823 5 90 V = ±15V C = 20pF S L R = 2kΩ 4 L G = +1 80 +V = +5V S 3 70 2 1 60 0 +27°C –55°C 50 –1 +125°C –2 40 –3 30 –4 –5 20 0.30 3.27 6.24 9.21 12.18 15.15 18.12 21.09 24.06 27.03 30.00 10 100 1k 10k 100k 1M 10M FREQUENCY (MHz) FREQUENCY (Hz) Figure 20. Common-Mode Rejection Ratio vs. Frequency Figure 17. Closed-Loop Gain vs. Frequency 100 10 +V = +5V S +V = +5V S GAIN = +1 10 1 V – V S OH 25°C 1 0.1 V OL 25°C 0.1 0.01 0.01 1 10 100 100 1k 10k 100k 1M 10M 0.1 FREQUENCY (Hz) LOAD CURRENT (mA) Figure 21. Output Saturation Voltage vs. Load Current Figure 18. Output Resistance vs. Frequency, +VS = +5 V, Gain = +1 10 10 V = ±15V S C = 20pF 8 L 1% 0.1% 0.01% +125°C 6 8 +25°C 4 2 6 –55°C 0 4 –2 –4 1% 0.1% 0.01% –6 2 –8 0 –10 0 5 10 15 20 100 200 300 400 500 600 700 SUPPLY VOLTAGE (±V) SETTLING TIME (ns) Figure 22. Quiescent Current vs. Supply Voltage Figure 19. Output Step Size vs. Settling Time (Inverter) Rev. E | Page 9 of 20 OUTPUT RESISTANCE (Ω) CLOSED-LOOP GAIN (dB) OUTPUT STEP SIZE FROM 0V TO V (V) SHOWN 00901-019 00901-017 00901-018 CMRR (dB) QUIESCENT CURRENT (mA) OUTPUT SATURATION VOLTAGE (V) 00901-021 00901-022 00901-020 AD823 Data Sheet 21 100 +V = +5V S +V = +5V S R V S 90 IN 18 C 80 L 15 70 +PSRR 60 12 50 9 40 –PSRR Ф = 45° M 30 6 Ф = 20° M 20 3 10 0 0 100 1k 10k 1M 10M 0 1 2 3 4 5 6 7 8 9 10 100k FREQUENCY (Hz) CAPACITOR (pF × 1000) Figure 23. Power Supply Rejection vs. Frequency Figure 26. Series Resistance vs. Capacitive Load –30 30 +V = +5V R = 2kΩ S L –40 G = +1 –50 –60 20 –70 V = ±15V S –80 –90 10 –100 +V = +5V S –110 –120 +V = +3V S 0 –130 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Large Signal Frequency Response Figure 27. Crosstalk vs. Frequency V = 20V p-p V = 2.9V p-p IN IN V = ±15V +V = +3V S S G = +1 G = –1 5V 20µs 500mV 10µs 100kΩ +15V 3V 100kΩ V = 2.9V p-p IN 20kHz, 20V p-p V OUT 604Ω 50pF 50Ω –15V 50pF 100kΩ Figure 25. Output Swing, +VS = +3 V, G = −1 Figure 28. Output Swing, VS = ±15 V, G = +1 Rev. E | Page 10 of 20 OUTPUT VOLTAGE (V p-p) POWER SUPPLY REJECTION (dB) 00901-025 00901-024 00901-023 CROSSTALK (dB) SERIES RESISTANCE (Ω) 00901-028 00901-026 00901-027 Data Sheet AD823 5V R = 300Ω R = 100kΩ L L C = 50pF C = 50pF L L R = R = 2kΩ +V = +3V F G S +V = +5V G = +1 S 3V G = –1 GND 500mV 200µs 500mV 200µs GND Figure 29. Output Swing, +VS = +5 V, G = −1 Figure 32. Output Swing, +VS = +3 V, G = +1 5V V = 100mV STEP R = 2kΩ IN L +V = +3V C = 50pF S L G = +1 +V = +5V S G = +1 1.55V 1.45V 25mV 50ns 500mV 100ns GND Figure 30. Pulse Response, +VS = +3 V, G = +1 Figure 33. Pulse Response, +VS = +5 V, G = +1 5V R = 2kΩ L R = 2kΩ L C = 50pF L C = 470pF L +V = +5V S +V = +5V S G = +2 G = +1 500mV 100ns 500mV 200ns GND Figure 31. Pulse Response, +V = +5 V, G = +2 Figure 34. Pulse Response, +V = +5 V, G = +1, C = 470 pF S S L Rev. E | Page 11 of 20 00901-031 00901-029 00901-030 00901-034 00901-033 00901-032 AD823 Data Sheet R = 100kΩ L C = 50pF L V = ±15V S G = +1 +10V –10V 5V 500ns Figure 35. Pulse Response, VS = ±15 V, G = +1 Rev. E | Page 12 of 20 00901-035 Data Sheet AD823 THEORY OF OPERATION The AD823 is fabricated on the Analog Devices, Inc. proprietary A nested integrator topology is used in the AD823 (see Figure 37). complementary bipolar (CB) process that enables the construction The output stage can be modeled as an ideal op amp with a of PNP and NPN transistors with similar fT’s in the 600 MHz to single-pole response and a unity-gain frequency set by 800 MHz region. In addition, the process also features N-Channel transconductance gm2 and Capacitor C2. R1 is the output JFETs that are used in the input stage of the AD823. These impedance of the input stage; g is the input transconductance. m process features allow the construction of high frequency, low C1 and C5 provide Miller compensation for the overall op amp. distortion op amps with picoamp input currents. This design The unity-gain frequency occurs at g /C5. Solving the node m uses a differential output input stage to maximize bandwidth equations for this circuit yields and headroom (see Figure 36). The smaller signal swings V OUT A0 = required on the S1P/S1N outputs reduce the effect of the Vi    C2 nonlinear currents due to junction capacitances and improve   (sR1[C1(A2+ 1)]+ 1)× s + 1     g  m2 the distortion performance. With this design, harmonic   distortion of better than −91 dB @ 20 kHz into 600 Ω with where: V = 4 V p-p on a single 5 V supply is achieved. The OUT A0 = g g R2R1 (open-loop gain of op amp). m m2 complementary common emitter design of the output stage A2 = g R2 (open-loop gain of output stage). m2 provides excellent load drive without the need for emitter The first pole in the denominator is the dominant pole of the followers, thereby improving the output range of the device amplifier and occurs at ~18 Hz. This equals the input stage considerably with respect to conventional op amps. The output impedance R1 multiplied by the Miller-multiplied value AD823 can drive 20 mA with the outputs within 0.6 V of the of C1. The second pole occurs at the unity-gain bandwidth of supply rails. The AD823 also offers outstanding precision for a the output stage, which is 23 MHz. This type of architecture high speed op amp. Input offset voltages of 1 mV maximum allows more open-loop gain and output drive to be obtained and offset drift of 2 µV/°C are achieved through the use of the than a standard 2-stage architecture would allow. Analog Devices advanced thin film trimming techniques. V CC Q44 Q43 Q55 R42 R37 I6 A = 1 V + 0.3V V1 I5 BE Q57 A = 19 Q49 Q61 Q58 Q72 Q18 C2 J1 Q46 J6 V INP R44 R28 V Q54 OUT Q21 V INN S1P S1N Q62 Q60 V C1 CC Q48 V B Q53 Q35 Q17 A = 19 C6 I1 R33 I2 R43 Q59 I3 I4 Q56 Q52 A = 1 V EE Figure 36. Simplified Schematic Rev. E | Page 13 of 20 00901-036 AD823 Data Sheet OUTPUT IMPEDANCE C1 S1N The low frequency open-loop output impedance of the common- g VI R1 m V emitter output stage used in this design is approximately 30 kΩ. OUT S1P Although this is significantly higher than a typical emitter C2 g VI R1 C5 follower output stage, when it is connected with feedback, the m R2 g output impedance is reduced by the open-loop gain of the op m2 amp. With 109 dB of open-loop gain, the output impedance is reduced to <0.2 Ω. At higher frequencies, the output impedance rises as the open-loop gain of the op amp drops; however, the Figure 37. Small Signal Schematic output also becomes capacitive due to the integrator capacitors C1 and C2. This prevents the output impedance from ever becoming excessively high (see Figure 18), which can cause stability problems when driving capacitive loads. In fact, the AD823 has excellent cap-load drive capability for a high frequency op amp. Figure 34 shows the AD823 connected as a follower while driving 470 pF direct capacitive load. Under these conditions, the phase margin is approximately 20°. If greater phase margin is desired, a small resistor can be used in series with the output to decouple the effect of the load capacitance from the op amp (see Figure 26). In addition, running the part at higher gains also improves the capacitive load drive capability of the op amp. Rev. E | Page 14 of 20 00901-037 Data Sheet AD823 APPLICATION NOTES Because the input stage uses N-Channel JFETs, input current INPUT CHARACTERISTICS during normal operation is negative; the current flows out from In the AD823, N-Channel JFETs are used to provide a low offset, the input terminals. If the input voltage is driven more positive low noise, high impedance input stage. Minimum input common- than +VS − 0.4 V, the input current reverses direction as internal mode voltage extends from 0.2 V below −V to 1 V < +V . Driving S S device junctions become forward biased. This is illustrated in the input voltage closer to the positive rail causes a loss of amplifier Figure 7. bandwidth and increased common-mode voltage error. A current limiting resistor should be used in series with the The AD823 does not exhibit phase reversal for input voltages up input of the AD823 if there is a possibility of the input voltage to and including +VS. Figure 38 shows the response of an AD823 exceeding the positive supply by more than 300 mV, or if an voltage follower to a 0 V to 5 V (+V ) square wave input. The S input voltage is applied to the AD823 when ±VS = 0. The input and output are superimposed. The output polarity tracks amplifier becomes damaged if left in that condition for more the input polarity up to +V , with no phase reversal. The reduced S than 10 seconds. A 1 kΩ resistor allows the amplifier to bandwidth above a 4 V input causes the rounding of the output withstand up to 10 V of continuous overvoltage and increases wave form. For input voltages greater than +VS, a resistor in the input voltage noise by a negligible amount. series with the AD823’s noninverting input prevents phase Input voltages less than −V are a completely different story. S reversal, at the expense of greater input voltage noise. This is The amplifier can safely withstand input voltages 20 V below illustrated in Figure 39. −VS as long as the total voltage from the positive supply to the 1V 2µs input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input currents across that 100 input voltage range. 90 The AD823 is designed for 16 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies (see Figure 16). This noise performance, along with the AD823’s low input current and current noise, means that the AD823 contributes negligible noise for applications with source 10 resistances greater than 10 kΩ and signal bandwidths greater GND 0% than 1 kHz. 1V OUTPUT CHARACTERISTICS Figure 38. AD823 Input Response: R = 0, V = 0 to +V P IN S The AD823’s unique bipolar rail-to-rail output stage swings within 25 mV of the supplies with no external resistive load. 1V 10µs The AD823’s approximate output saturation resistance is 25 Ω sourcing and sinking. This can be used to estimate the output 100 90 saturation voltage when driving heavier current loads. For +V S instance, when driving 5 mA, the saturation voltage to the rails is approximately 125 mV. If the AD823’s output is driven hard against the output saturation voltage, it recovers within 250 ns of the input returning to the amplifier’s linear operating region. GND 10 A/D Driver 0% The rail-to-rail output of the AD823 makes it useful as an A/D 1V driver in a single-supply system. Because it is a dual op amp, it can be used to drive both the analog input of the A/D as well as 5V R P its reference input. The high impedance FET input of the V AD823 is well suited for minimal loading of high output IN AD823 V OUT impedance devices. Figure 39. AD823 Input Response: V = 0 to +V + 200 mV, V = 0 to +V , R = 49.9 kΩ IN S OUT S P Rev. E | Page 15 of 20 00901-039 00901-038 AD823 Data Sheet Figure 40 shows a schematic of an AD823 being used to drive The distortion analysis is important for systems requiring good both the input and reference input of an AD1672, a 12-bit, frequency domain performance. Other systems may require 3-MSPS, single-supply ADC. One amplifier is configured as a good time domain performance. The noise and settling time performance of the AD823 provides the necessary information unity-gain follower to drive the analog input of the AD1672, which is configured to accept an input voltage that ranges from for its applicability for these systems. 0 V to 2.5 V. 1 V = 2.15V p-p IN The other amplifier is configured as a gain of 2 to drive the G = +1 FI = 490kHz reference input from a 1.25 V reference. Although the AD1672 has its own internal reference, there are systems that require greater accuracy than the internal reference provides. On the other 2 hand, if the AD1672 internal reference is used, the second AD823 4 amplifier can be used to buffer the reference voltage for driving 9 7 5 6 other circuitry while minimally loading the reference source. 8 3 +5VA +5VD 10µF 0.1µF 0.1µF 10µF +5VA 28 19 0.1µF +5VD 10µF Figure 41. FFT of AD1672 Output Driven by AD823 2 8 20 0.1µF REFOUT 1 21 AIN1 3 22 15 3 V, Single-Supply Stereo Headphone Driver 49.9Ω AIN2 OTR V IN 13 BIT1 (MSB) The AD823 exhibits good current drive and total harmonic 14 AD823 12 AD1672 BIT2 distortion plus noise (THD+N) performance, even at 3 V 11 BIT3 5 10 single supplies. At 20 kHz, THD+N equals −62 dB (0.079%) for V BIT4 REF 7 23 9 REFIN BIT5 (1.25V) 6 24 8 a 300 mV p-p output signal. This is comparable to other single- BIT6 REFCOM 4 25 NCOMP2 supply op amps that consume more power and cannot run on 7 26 BIT7 NCOMP1 6 BIT8 1kΩ 3 V power supplies. 5 1kΩ BIT9 4 BIT10 3 In Figure 42, each channel’s input signal is coupled via a 1 μF 27 BIT11 ACOM 2 BIT12 (LSB) 1 Mylar capacitor. Resistor dividers set the dc voltage at the 16 REF noninverting inputs so that the output voltage is midway CLOCK between the power supplies (+1.5 V). The gain is 1.5. Each half of the AD823 can then be used to drive a headphone channel. A 19 18 5 Hz high-pass filter is realized by the 500 μF capacitors and the Figure 40. AD823 Driving Input and Reference of the headphones that can be modeled as 32 Ω load resistors to AD1672, a 12-Bit, 3-MSPS ADC ground. This ensures that all signals in the audio frequency range (20 Hz to 20 kHz) are delivered to the headphones. The circuit was tested with a 500 kHz sine wave input that was heavily low-pass filtered (60 dB) to minimize the harmonic content 3V at the input to the AD823. The digital output of the AD1672 was + 0.1µF 0.1µF 95.3kΩ analyzed by performing a fast Fourier transform (FFT). 95.3kΩ 8 CHANNEL 1 3 + 1/2 During the testing, it was observed that at 500 kHz, the output 1µF 1 1 47.5kΩ AD823 MYLAR 2 500µF of the AD823 cannot go below ~350 mV (operating with negative supply at ground) without seriously degrading the L 4.99kΩ 95.3kΩ 10kΩ second harmonic distortion. Another test was performed with a HEADPHONES 200 Ω pull-down resistor to ground that allowed the output to 32Ω IMPEDANCE 10kΩ go as low as 200 mV without seriously affecting the second R harmonic distortion. There was, however, a slight increase in 4.99kΩ the third harmonic term with the resistor added, but it was still 6 500µF 1/2 47.5kΩ 7 1µF AD823 + less than the second harmonic. CHANNEL 2 5 4 MYLAR Figure 41 is an FFT plot of the results of driving the AD1672 Figure 42. 3 V Single-Supply Stereo Headphone Driver with the AD823 with no pull-down resistor. The input amplitude was 2.15 V p-p and the lower voltage excursion was 350 mV. The input frequency was 490 kHz, which was chosen to spread the location of the harmonics. Rev. E | Page 16 of 20 +V CC COM +V DCOM DD 00901-040 15dB/DIV 00901-042 00901-041 Data Sheet AD823 Second-Order Low-Pass Filter Single-Supply Half-Wave and Full-Wave Rectifiers Figure 43 depicts the AD823 configured as a second-order An AD823 configured as a unity-gain follower and operated Butterworth low-pass filter. With the values as shown, the with a single supply can be used as a simple half-wave rectifier. corner frequency equals 200 kHz. Component selection is The AD823 inputs maintain picoamp level input currents even shown in the following equations: when driven well below the minus supply. The rectifier puts that behavior to good use, maintaining an input impedance of R1 = R2 = User Selected (Typical Values: 10 kΩ to 100 kΩ) 11 over 10 Ω for input voltages from within 1 V of the positive 1.414 supply to 20 V below the negative supply.  C1 farads  2πf  R1 cutoff The full-wave and half-wave rectifier shown in Figure 45 0.707 operates as follows: when VIN is above ground, R1 is boot- C2 strapped through the unity-gain follower A1 and the loop of 2πf  R1 cutoff Amplifier A2. This forces the inputs of A2 to be equal, thus no current flows through R1 or R2, and the circuit output tracks the input. When V is below ground, the output of A1 is forced IN +5V C2 to ground. The noninverting input of Amplifier A2 sees the 56pF C3 0.1µF R1 R2 ground level output of A1; therefore, A2 operates as a unity- 20kΩ 20kΩ gain inverter. The output at Node C is then a full-wave rectified V IN 1/2 C1 V AD823 version of the input. Node B is a buffered half-wave rectified OUT 28pF 50pF version of the input. Input voltage supply to ±18 V can be rectified, depending on the voltage supply used. R1 R2 C4 100kΩ 100kΩ 0.1µF –5V +V S 0.01µF Figure 43. Second-Order Low-Pass Filter 6 A 8 3 7 C A plot of the filter is shown in Figure 44; better than 50 dB of A2 A2 5 1 V FULL-WAVE high frequency rejection is provided. IN A1 1/2 2 RECTIFIED OUTPUT AD823 1/2 4 0 AD823 B –10 HALF-WAVE RECTIFIED OUTPUT V – V DB OUT –20 Figure 45. Full-Wave and Half-Wave Rectifier –30 –40 2V 200µs –50 100 A 90 –60 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 44. Frequency Response of Filter B 10 0% C 2V Figure 46. Single-Supply Half-Wave and Full-Wave Rectifier Rev. E | Page 17 of 20 HIGH FREQUENCY REJECTION (dB) 00901-044 00901-043 00901-046 00901-044 AD823 Data Sheet OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 4 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE PLANE 0.014 (0.36) 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.430 (10.92) 0.005 (0.13) 0.018 (0.46) MAX MIN 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 47. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 8 5 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 48. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. E | Page 18 of 20 012407-A 070606-A Data Sheet AD823 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD823ANZ −40°C to +85°C 8-Lead PDIP N-8 AD823AR −40°C to +85°C 8-Lead SOIC_N R-8 AD823AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8 AD823AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8 AD823ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD823ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8 AD823ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8 AD823AR-EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. E | Page 19 of 20 AD823 Data Sheet NOTES ©1995–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00901-0-11/11(E) Rev. E | Page 20 of 20