ANALOG DEVICES AD8227

Wide Supply Range, Rail-to-Rail Output Instrumentation Amplifier AD8227 FEATURES PIN CONFIGURATION Gain set with 1 external resistor AD8227 –IN 1 8 +V S Gain range: 5 to 1000 R 2 7 V G OUT Input voltage goes below ground R 3 6 REF G Inputs protected beyond supplies +IN 4 5 –V S Very wide power supply range Single supply: 2.2 V to 36 V TOP VIEW (Not to Scale) Dual supply: ±1.5 V to ±18 V Figure 1. Bandwidth (G = 5): 250 kHz CMRR (G = 5): 100 dB minimum (B Grade) Input noise: 24 nV/√Hz 1 Table 1. Instrumentation Amplifiers by Category Typical supply current: 350 μA General Zero Military Low High Speed Specified temperature: −40°C to +125°C Purpose Drift Grade Power PGA 8-lead SOIC and MSOP packages AD8220 AD8231 AD620 AD627 AD8250 APPLICATIONS AD8221 AD8290 AD621 AD623 AD8251 AD8222 AD8293 AD524 AD8223 AD8253 Industrial process controls AD8224 AD8553 AD526 AD8226 Bridge amplifiers Medical instrumentation AD8228 AD8556 AD624 AD8227 Portable data acquisition AD8295 AD8557 Multichannel systems 1 See www.analog.com for the latest selection of instrumentation amplifiers. GENERAL DESCRIPTION The AD8227 is ideal for multichannel, space-constrained The AD8227 is a low cost, wide supply range instrumentation applications. With its MSOP package and 125°C temperature amplifier that requires only one external resistor to set any gain rating, the AD8227 thrives in tightly packed, zero airflow designs. between 5 and 1000. The AD8227 is available in 8-pin MSOP and SOIC packages. The AD8227 is designed to work with a variety of signal voltages. It is fully specified for −40°C to +125°C operation. A wide input range and rail-to-rail output allow the signal to make full use of the supply rails. Because the input range can For a similar instrumentation amplifier with a gain range of 1 to also go below the negative supply, small signals near ground can 1000, see the AD8226. be amplified without requiring dual supplies. The AD8227 operates on supplies ranging from ±1.5 V to ±18 V (2.2 V to 36 V single supply). The robust AD8227 inputs are designed to connect to real- world sensors. In addition to its wide operating range, the AD8227 can handle voltages beyond the rails. For example, with a ±5 V supply, the part is guaranteed to withstand ±35 V at the input with no damage. Minimum as well as maximum input bias currents are specified to facilitate open wire detection. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 07759-001 AD8227 TABLE OF CONTENTS Features .............................................................................................. 1  Gain Selection ............................................................................. 19  Applications ....................................................................................... 1  Reference Terminal .................................................................... 20  Pin Configuration ............................................................................. 1  Input Voltage Range ................................................................... 20  General Description ......................................................................... 1  Layout .......................................................................................... 20  Revision History ............................................................................... 2  Input Bias Current Return Path ............................................... 21  Specif ica t ions ..................................................................................... 3  Input Protection ......................................................................... 21  Absolute Maximum Ratings ............................................................ 7  Radio Frequency Interference (RFI) ........................................ 21  Thermal Resistance ...................................................................... 7  Applications Information .............................................................. 22  ESD Caution .................................................................................. 7  Differential Drive ....................................................................... 22  Pin Configuration and Function Descriptions ............................. 8  Precision Strain Gage ................................................................. 22  Typical Performance Characteristics ............................................. 9  Driving an ADC ......................................................................... 23  Theory of Operation ...................................................................... 19  Outline Dimensions ....................................................................... 24  Architec ture ................................................................................. 19  Ordering Guide .......................................................................... 24  REVISION HISTORY 5/09—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8227 SPECIFICATIONS +VS = +15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 5, RL = 10 kΩ, specifications referred to input, unless otherwise noted. Table 2. Test Conditions/ A Grade B Grade Parameter Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO VCM = −10 V to +10 V DC to 60 Hz G = 5 90 100 dB G = 10 96 105 dB G = 100 105 110 dB G = 1000 105 110 dB 5 kHz G = 5 80 80 dB G = 10 86 86 dB G = 100 86 86 dB G = 1000 86 86 dB NOISE Total noise: 2 2 e = √(e + (e /G) ) N NI NO Voltage Noise, 1 kHz Input Voltage Noise, eNI 24 25 24 25 nV/√Hz Output Voltage Noise, eNO 310 315 310 315 nV/√Hz RTI f = 0.1 Hz to 10 Hz G = 5 1.5 1.5 μV p-p G = 10 0.9 0.9 μV p-p G = 100 to 1000 0.5 0.5 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET Total offset voltage: VOS = VOSI + (VOSO/G) Input Offset, VOSI VS = ±5 V to ±15 V 200 100 μV Average Temperature Drift T = −40°C to +125°C 0.2 2 0.2 1 μV/°C A Output Offset, V V = ±5 V to ±15 V 1000 500 μV OSO S Average Temperature Drift T = −40°C to +125°C 2 10 2 5 μV/°C A Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V G = 5 90 100 dB G = 10 96 105 dB G = 100 105 110 dB G = 1000 105 110 dB INPUT CURRENT 1 Input Bias Current T = +25°C 5 20 27 5 20 27 nA A T = +125°C 5 15 25 5 15 25 nA A TA = −40°C 5 30 35 5 30 35 nA Average Temperature Drift TA = −40°C to +125°C 70 70 pA/°C Input Offset Current TA = +25°C 1.5 1.5 nA T = +125°C 1.5 1.5 nA A T = −40°C 2 2 nA A Average Temperature Drift T = −40°C to +125°C 5 5 pA/°C A REFERENCE INPUT R 60 60 kΩ IN I 12 12 μA IN Voltage Range −VS +VS −VS +VS V Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 % Rev. 0 | Page 3 of 24 AD8227 Test Conditions/ A Grade B Grade Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 5 250 250 kHz G = 10 200 200 kHz G = 100 50 50 kHz G = 1000 5 5 kHz Settling Time 0.01% 10 V step G = 5 14 14 μs G = 10 15 15 μs G = 100 35 35 μs G = 1000 275 275 μs 2 Slew Rate G = 5 to 100 0.8 0.8 V/μs 3 GAIN G = 5 + (80 kΩ/RG) Gain Range 5 1000 5 1000 V/V Gain Error VOUT = −10 V to +10 V G = 5 0.04 0.02 % G = 10 to 1000 0.3 0.15 % Gain Nonlinearity V = −10 V to +10 V OUT G = 5 RL ≥ 2 kΩ 10 10 ppm G = 10 RL ≥ 2 kΩ 15 15 ppm G = 100 RL ≥ 2 kΩ 15 50 ppm G = 1000 R ≥ 2 kΩ 750 150 ppm L Gain vs. Temperature T = −40°C to +125°C A G = 5 5 5 ppm/°C G > 5 −100 −100 ppm/°C INPUT V = ±1.5 V to +36 V S Impedance Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF 4 Operating Voltage Range T = +25°C −V − 0.1 +V − 0.8 −V − 0.1 +V − 0.8 V A S S S S T = +125°C −V − 0.05 +V − 0.6 −V − 0.05 +V − 0.6 V A S S S S T = −40°C −V − 0.15 +V − 0.9 −V − 0.15 +V − 0.9 V A S S S S Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V OUTPUT Output Swing RL = 10 kΩ to ground TA = −40°C to +85°C −VS + 0.2 +VS − 0.2 −VS + 0.2 +VS − 0.2 V TA = +85°C to +125°C −VS + 0.2 +VS − 0.3 −VS + 0.2 +VS − 0.3 V R = 100 kΩ to ground T = −40°C to +125°C −V + 0.1 +V − 0.1 −V + 0.1 +V − 0.1 V L A S S S S Short-Circuit Current 13 13 mA POWER SUPPLY Operating Range Dual-supply operation ±1.5 ±18 ±1.5 ±18 V Quiescent Current T = +25°C 350 425 350 425 μA A T = −40°C 250 325 250 325 μA A TA = +85°C 450 525 450 525 μA TA = +125°C 525 600 525 600 μA TEMPERATURE RANGE −40 +125 −40 +125 °C 1 The input stage uses pnp transistors, so input bias current always flows into the part. 2 At high gains, the part is bandwidth limited rather than slew rate limited. 3 For G > 5, gain error specifications do not include the effects of External Resistor R . G 4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. Rev. 0 | Page 4 of 24 AD8227 +V = 2.7 V, −V = 0 V, V = 0 V, T = 25°C, G = 5, R = 10 kΩ, specifications referred to input, unless otherwise noted. S S REF A L Table 3. Test Conditions/ A Grade B Grade Parameter Comments Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO V = 0 V to 1.7 V CM DC to 60 Hz G = 5 90 100 dB G = 10 96 105 dB G = 100 105 110 dB G = 1000 105 110 dB 5 kHz G = 5 80 80 dB G = 10 86 86 dB G = 100 86 86 dB G = 1000 86 86 dB NOISE Total noise: 2 2 eN = √(eNI + (eNO/G) ) Voltage Noise, 1 kHz Input Voltage Noise, e 25 28 25 28 nV/√Hz NI Output Voltage Noise, e 310 330 310 330 nV/√Hz NO RTI f = 0.1 Hz to 10 Hz G = 5 1.5 1.5 μV p-p G = 10 0.8 0.8 μV p-p G = 100 to 1000 0.5 0.5 μV p-p Current Noise f = 1 kHz 100 100 fA/√Hz f = 0.1 Hz to 10 Hz 3 3 pA p-p VOLTAGE OFFSET Total offset voltage: V = V + (V /G) OS OSI OSO Input Offset, V V = 0 V to 1.7 V 200 100 μV OSI S Average Temperature Drift TA = −40°C to +125°C 0.2 2 0.2 1 μV/°C Output Offset, VOSO VS = 0 V to 1.7 V 1000 500 μV Average Temperature Drift TA = −40°C to +125°C 2 10 2 5 μV/°C Offset RTI vs. Supply (PSR) V = 0 V to 1.7 V S G = 5 90 100 dB G = 10 96 105 dB G = 100 105 110 dB G = 1000 105 110 dB INPUT CURRENT 1 Input Bias Current TA = +25°C 5 20 27 5 20 27 nA TA = +125°C 5 15 25 5 15 25 nA T = −40°C 5 30 35 5 30 35 nA A Average Temperature Drift T = −40°C to +125°C 70 70 pA/°C A Input Offset Current T = +25°C 1.5 1.5 nA A TA = +125°C 1.5 1.5 nA TA = −40°C 2 2 nA Average Temperature Drift T = −40°C to +125°C 5 5 pA/°C A REFERENCE INPUT RIN 60 60 kΩ I 12 12 μA IN Voltage Range −V +V −V +V V S S S S Reference Gain to Output 1 1 V/V Reference Gain Error 0.01 0.01 % Rev. 0 | Page 5 of 24 AD8227 Test Conditions/ A Grade B Grade Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 5 250 250 kHz G = 10 200 200 kHz G = 100 50 50 kHz G = 1000 5 5 kHz Settling Time 0.01% 2 V step G = 5 6 6 μs G = 10 6 6 μs G = 100 30 30 μs G = 1000 275 275 μs 2 Slew Rate G = 5 to 10 0.6 0.6 V/μs 3 GAIN G = 5 + (80 kΩ/RG) Gain Range 5 1000 5 1000 V/V Gain Error G = 5 V = 0.8 V to 1.8 V 0.04 0.04 % OUT G = 10 to 1000 V = 0.2 V to 2.5 V 0.3 0.3 % OUT Gain vs. Temperature T = −40°C to +125°C A G = 5 5 5 ppm/°C G > 5 −100 −100 ppm/°C INPUT −VS = 0 V; +VS = 2.7 V to 36 V Impedance Differential 0.8||2 0.8||2 GΩ||pF Common Mode 0.4||2 0.4||2 GΩ||pF 4 Operating Voltage Range T = +25°C −0.1 +V − 0.7 −0.1 +V − 0.7 V A S S TA = −40°C −0.15 +VS − 0.9 −0.15 +VS − 0.9 V TA = +125°C −0.05 +VS − 0.6 −0.05 +VS − 0.6 V Overvoltage Range TA = −40°C to +125°C +VS − 40 −VS + 40 +VS − 40 −VS + 40 V OUTPUT Output Swing T = −40°C to +125°C A R = 2 kΩ to 1.35 V 0.2 +V − 0.2 0.2 +V − 0.2 V L S S RL = 10 kΩ to 1.35 V 0.1 +VS − 0.1 0.1 +VS − 0.1 V Short-Circuit Current 13 13 mA POWER SUPPLY Operating Range Single-supply operation 2.2 36 2.2 36 V Quiescent Current +VS = 2.7 V T = +25°C 325 400 325 400 μA A T = −40°C 250 325 250 325 μA A T = +85°C 425 500 425 500 μA A TA = +125°C 475 550 475 550 μA TEMPERATURE RANGE −40 +125 −40 +125 °C 1 Input stage uses pnp transistors, so input bias current always flows into the part. 2 At high gains, the part is bandwidth limited rather than slew rate limited. 3 For G > 5, gain error specifications do not include the effects of External Resistor R . G 4 Input voltage range of the AD8227 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. See the Input Voltage Range section for more information. Rev. 0 | Page 6 of 24 AD8227 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating θ is specified for a device in free air. JA Supply Voltage ±18 V Table 5. Output Short-Circuit Current Indefinite Package θ Unit JA Maximum Voltage at −IN or +IN −V + 40 V S 8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W Minimum Voltage at −IN or +IN +VS − 40 V 8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W REF Voltage ±VS Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +125°C ESD CAUTION Maximum Junction Temperature 140°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 24 AD8227 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8227 –IN 1 8 +V S R 2 7 V G OUT R 3 6 REF G 4 5 +IN –V S TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input. 2, 3 R Gain Setting Pins. Place a gain resistor between these two pins. G 4 +IN Positive Input. 5 −V Negative Supply. S 6 REF Reference. This pin must be driven by low impedance. 7 VOUT Output. 8 +VS Positive Supply. Rev. 0 | Page 8 of 24 07759-002 AD8227 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, VS = ±15 V, RL = 10 kΩ, unless otherwise noted. 500 MEAN: 15.9 MEAN: 0.0668 SD: 196.50 SD: 0.065827 1000 400 800 300 600 200 400 100 200 0 0 –900 –600 –300 0 300 600 900 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 OUTPUT V (µV) INPUT V DRIFT (µV) OS OS Figure 3. Typical Distribution of Output Offset Voltage Figure 6. Typical Distribution of Input Offset Voltage Drift, G = 100 MEAN: 20.4 MEAN: –0.701 1000 SD: 0.5893 700 SD: 0.676912 600 800 500 600 400 300 400 200 200 100 0 0 –6 –4 –2 0 2 4 6 16 18 20 22 24 26 OUTPUT V DRIFT (µV) POSITIVE I (nA) OS BIAS Figure 4. Typical Distribution of Output Offset Voltage Drift Figure 7. Typical Distribution of Input Bias Current MEAN: –5.90 MEAN: –0.027 1000 SD: 15.8825 1000 SD: 0.079173 800 800 600 600 400 400 200 200 0 0 –200 –150 –100 –50 0 50 100 150 200 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 INPUT V (µV) I (nA) OS OS Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current Rev. 0 | Page 9 of 24 HITS HITS HITS 07759-004 07759-003 07759-005 HITS HITS HITS 07759-008 07759-007 07759-006 AD8227 1.6 1.6 +0.02V, +1.5V +0.02V, +1.5V V = 0V V = 0V REF REF 1.4 1.4 +2.67V, +1.2V +2.67V, +1.2V 1.2 1.2 +0.02V, +1.35V +0.02V, +1.35V +2.67V, +1.1V +2.7V, +1.1V 1.0 1.0 V = 1.35V V = 1.35V REF REF 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 +2.7V, 0V 0 0 +0.02V, –0.15V +0.02V, –0.25V +2.67V, –0.25V –0.2 –0.2 +2.67V, –0.15V +2.67V, –0.25V +0.02V, –0.3V +1.35V, –0.3V +0.02V, –0.3V +1.35V, –0.3V –0.4 –0.4 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 9. Input Common-Mode Voltage vs. Output Voltage, Figure 12. Input Common-Mode Voltage vs. Output Voltage, Single Supply, Vs = 2.7 V, G = 5 Single Supply, Vs = 2.7 V, G = 100 5 5 V = 0V V = 0V REF REF +0.02V, +4.25V +0.02V, +4.25V 4 +4.96V, +3.75V +4.96V, +3.75V 4 +0.02V, +4V +0.02V, +4V +4.96V, +3.5V +4.96V, +3.5V 3 V = 2.5V V = 2.5V REF 3 REF 2 2 1 1 +4.96V, +0.2V +0.01V, –0.05V 0 +4.96V, –0.2V 0 +0.02V, –0.25V +4.96V, –0.05V +4.96V, –0.25V +0.02V, –0.3V +2.5V, –0.3V +0.02V, –0.3V +2.5V, –0.3V –1 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 10. Input Common-Mode Voltage vs. Output Voltage, Figure 13. Input Common-Mode Voltage vs. Output Voltage, Single Supply, V = 5 V, G = 5 Single Supply, V = 5 V, G = 100 s s 6 6 0V, +4.2V 0V, +4.2V –4.98V, +3.7V +4.96V, +3.7V –4.96V, +3.75V 4 4 +4.96V, +3.25V 2 2 0 0 –2 –2 –4 –4 0V, –5.3V 0V, –5.3V –4.97V, –4.8V +4.96V, –4.8V –4.96V, –5.1V +4.96V, –5.1V –6 –6 –6 –4 –2 0 2 4 6 –6 –4 –2 024 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 11. Input Common-Mode Voltage vs. Output Voltage, Figure 14. Input Common-Mode Voltage vs. Output Voltage, Dual Supply, Vs = ±5 V, G = 5 Dual Supply, Vs = ±5 V, G = 100 Rev. 0 | Page 10 of 24 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) 07759-011 07759-010 07759-009 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) 07759-014 07759-013 07759-012 AD8227 20 16 0.5 V = ±15V, G = 5 V = ±15V 14 S S 0.4 0V, +14.2V 15 +14.94V, +12.7V 12 –14.96V, +12.7V V OUT 0V, +11.2V 10 0.3 10 8 –11.96V, +11.94V, 0.2 6 +10V +10V 5 4 0.1 2 I IN 0 V = ±12V 0 0 S –2 –0.1 –5 –4 –6 –11.96V, +11.94V, –0.2 –11.1V –10 –11.1V –8 –0.3 –10 0V, –12.3V –15 –12 –0.4 –14.96V, –13.8V +14.94V, –13.8V 0V, –15.3V –14 –20 –16 –0.5 –20 –15 –10 –5 0 5 10 15 20 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 15. Input Common-Mode Voltage vs. Output Voltage, Figure 18. Input Overvoltage Performance, G = 5, Vs = ±15 V Dual Supply, Vs = ±15 V, G = 5 20 3.00 0.6 V = 2.7V, G = 100 V = ±15V S S 2.75 0.5 0V, +14.2V 15 –14.96V, +12.7V +14.94V, +12.7V V OUT 2.50 0.4 0V, +11.2V 10 2.25 0.3 –11.96V, +11.94V, +10V +10V 2.00 0.2 5 1.75 0.1 V = ±12V 0 1.50 0 S I IN 1.25 –0.1 –5 1.00 –0.2 –11.96V, +11.94V, –10 0.75 –0.3 –11.3V –11.3V 0.50 –0.4 0V, –12.3V –15 –14.96V, –14V +14.94V, –14V 0.25 –0.5 0V, –15.3V –20 0 –0.6 –20 –15 –10 –5 0 5 10 15 20 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 16. Input Common-Mode Voltage vs. Output Voltage, Figure 19. Input Overvoltage Performance, G = 100, V = 2.7 V s Dual Supply, V = ±15 V, G = 100 s 3.00 0.6 16 0.5 V = 2.7V, G = 5 V = ±15V, G = 100 S 14 S 2.75 0.5 0.4 12 2.50 0.4 10 V 0.3 V OUT OUT 2.25 0.3 8 0.2 6 2.00 0.2 4 0.1 1.75 0.1 2 1.50 0 0 0 I IN I –2 IN 1.25 –0.1 –0.1 –4 1.00 –0.2 –6 –0.2 0.75 –0.3 –8 –0.3 –10 0.50 –0.4 –12 –0.4 0.25 –0.5 –14 –16 –0.5 0 –0.6 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 17. Input Overvoltage Performance, G = 5, Vs = 2.7 V Figure 20. Input Overvoltage Performance, G = 100, Vs = ±15 V Rev. 0 | Page 11 of 24 OUTPUT VOLTAGE (V) COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) 07759-016 07759-015 07759-017 INPUT CURRENT (mA) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 07759-020 INPUT CURRENT (mA) 07759-018 INPUT CURRENT (mA) 07759-019 INPUT CURRENT (mA) AD8227 33 140 31 120 –0.14V 29 G = 1000 100 27 G = 100 +4.23V 80 25 23 60 G = 10 21 40 G = 5 19 20 17 15 0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.1 1 10 100 1k 10k 100k COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 21. Input Bias Current vs. Common-Mode Voltage, Vs = 5 V Figure 24. Negative PSRR vs. Frequency 40 70 –15.01V G = 1000 60 35 50 30 G = 100 40 25 30 +14.03V G = 10 20 20 G = 5 10 15 0 10 –10 5 –20 0 –30 –16 –12 –8 –4 0 4 8 12 16 100 1k 10k 100k 1M 10M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 22. Input Bias Current vs. Common-Mode Voltage, V = ±15 V Figure 25. Gain vs. Frequency, V = ±15 V s S 160 70 G = 1000 G = 1000 G = 100 60 140 G = 10 50 120 G = 100 G = 5 40 100 30 G = 10 80 20 G = 5 10 60 0 40 –10 20 –20 0 –30 0.1 1 10 100 1k 10k 100k 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 23. Positive PSRR vs. Frequency, RTI Figure 26. Gain vs. Frequency, VS = 2.7 V Rev. 0 | Page 12 of 24 POSITIVE PSRR (dB) INPUT BIAS CURRENT (nA) INPUT BIAS CURRENT (nA) 07759-022 07759-021 07759-023 GAIN (dB) GAIN (dB) NEGATIVE PSRR (dB) 07759-026 07759-025 07759-024 AD8227 160 35 150 V = ±15V –IN BIAS CURRENT S G = 1000 V = 0V +IN BIAS CURRENT REF 140 OFFSET CURRENT G = 100 30 125 G = 10 120 G = 5 25 100 100 80 20 75 60 15 50 40 10 25 20 0 5 0 0.1 1 10 100 1k 10k 100k –45 –30 –15 0 15 30 45 60 75 90 105 120 135 FREQUENCY (Hz) TEMPERATURE (°C) Figure 27. CMRR vs. Frequency, RTI Figure 30. Input Bias Current and Offset Current vs. Temperature 160 300 140 G = 1000 200 G = 100 G = 10 120 G = 5 100 100 0 80 60 –100 40 –200 20 –300 0 –20 0.1 1 10 100 1k 10k 100k –40 0 20 40 60 80 100 120 FREQUENCY (Hz) TEMPERATURE (°C) Figure 28. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Figure 31. Gain Error vs. Temperature, G = 5 0.3 10 8 0.2 6 4 0.1 2 0 0 –2 –0.1 –4 –6 –0.2 –8 –0.3 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 –40 –20 0 20 40 60 80 100 120 WARM-UP TIME (s) TEMPERATURE (°C) Figure 29. Change in Input Offset Voltage vs. Warm-Up Time Figure 32. CMRR vs. Temperature, G = 5 Rev. 0 | Page 13 of 24 CHANGE IN INPUT OFFSET (µV) CMRR (dB) CMRR (dB) 07759-029 07759-028 07759-027 INPUT BIAS CURRENT (nA) GAIN ERROR (µV/V) CMRR (µV/V) 07759-032 07759-031 INPUT OFFSET CURRENT (pA) 07759-030 AD8227 +V 15 S –40°C –0.2 +25°C +85°C 10 –0.4 +105°C –40°C +125°C +25°C –0.6 5 +85°C –0.8 +105°C +125°C 0 –V S –5 –0.2 –0.4 –10 –0.6 –0.8 –15 2 4 6 8 10 12 14 16 18 100 1k 10k 100k LOAD (Ω) SUPPLY VOLTAGE (±V ) S Figure 33. Input Voltage Limit vs. Supply Voltage Figure 36. Output Voltage Swing vs. Load Resistance +V +V S S –0.1 –0.2 –40°C –0.2 –0.4 +25°C –40°C –0.3 –0.6 +85°C +25°C +105°C +85°C –0.4 –0.8 +125°C +105°C +125°C +0.4 +0.8 +0.3 +0.6 +0.2 +0.4 +0.1 +0.2 –V –V S S 2 4 6 8 10 12 14 16 18 0.01 0.1 1 10 SUPPLY VOLTAGE (±V ) OUTPUT CURRENT (mA) S Figure 34. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ Figure 37. Output Voltage Swing vs. Output Current 40 +V S G = 5 –0.2 30 –0.4 –40°C –0.6 +25°C 20 –0.8 +85°C –1.0 +105°C 10 –1.2 +125°C 0 +1.2 –10 +1.0 +0.8 –20 +0.6 +0.4 –30 +0.2 –40 –V S –10 –8 –6 –4 –2 0 2 4 6 8 10 2 4 6 8 10 12 14 16 18 OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (±V ) S Figure 35. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ Figure 38. Gain Nonlinearity, G = 5, RL ≥ 2 kΩ Rev. 0 | Page 14 of 24 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 07759-035 07759-034 07759-033 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) NONLINEARITY (10ppm/DIV) REFERRED TO SUPPLY VOLTAGES 07759-038 07759-036 07759-037 AD8227 40 1k G = 10 30 20 10 0 100 G = 5 (67nV/ Hz) –10 G = 10 (40nV/ Hz) G = 100 (26nV/ Hz) –20 G = 1000 (25nV/ Hz) –30 BANDWIDTH LIMITED –40 10 –10 –8 –6 –4 –2 0 2 4 6 8 10 1 10 100 1k 10k 100k OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 39. Gain Nonlinearity, G = 10, RL ≥ 2 kΩ Figure 42. Voltage Noise Spectral Density vs. Frequency 160 G = 1000, 200nV/DIV G = 100 120 80 40 0 G = 5, 1µV/DIV –40 –80 –120 –160 –10 –8–6–4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) Figure 40. Gain Nonlinearity, G = 100, R ≥ 2 kΩ Figure 43. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 5, G = 1000 L 400 1k G = 1000 300 200 100 0 100 –100 –200 –300 –400 10 1 10 100 1k 10k –10 –8–6–4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 41. Gain Nonlinearity, G = 1000, RL ≥ 2 kΩ Figure 44. Current Noise Spectral Density vs. Frequency Rev. 0 | Page 15 of 24 NONLINEARITY (40ppm/DIV) NONLINEARITY (100ppm/DIV) NONLINEARITY (10ppm/DIV) 07759-039 07759-041 07759-040 NOISE (fA/ Hz) NOISE (nV/ Hz) 07759-043 07759-044 07759-042 AD8227 5V/DIV 13.8µs TO 0.01% 16.8µs TO 0.001% 0.002%/DIV 40µs/DIV 1.5pA/DIV 1s/DIV Figure 45. 0.1 Hz to 10 Hz Current Noise Figure 48. Large-Signal Pulse Response and Settling Time, G = 10, 10 V Step, V = ±15 V S 30 25 5V/DIV 20 35µs TO 0.01% 15 50µs TO 0.001% 10 0.002%/DIV 5 40µs/DIV 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 46. Large-Signal Frequency Response Figure 49. Large-Signal Pulse Response and Settling Time, G = 100, 10 V Step, V = ±15 V S 5V/DIV 5V/DIV 275µs TO 0.01% 13.4µs TO 0.01% 350µs TO 0.001% 16.6µs TO 0.001% 0.002%/DIV 0.002%/DIV 40µs/DIV 200µs/DIV Figure 50. Large-Signal Pulse Response and Settling Time, G = 1000, Figure 47. Large-Signal Pulse Response and Settling Time, G = 5, 10 V Step, V = ±15 V 10 V Step, VS = ±15 V S Rev. 0 | Page 16 of 24 OUTPUT VOLTAGE (V p-p) 07759-047 07759-045 07759-046 07759-050 07759-048 07759-049 AD8227 20mV/DIV 4µs/DIV 20mV/DIV 20µs/DIV Figure 51. Small-Signal Pulse Response, G = 5, R = 10 kΩ, C = 100 pF Figure 53. Small-Signal Pulse Response, G = 100, R = 10 kΩ, C = 100 pF L L L L 20mV/DIV 4µs/DIV 20mV/DIV 100µs/DIV Figure 52. Small-Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF Figure 54. Small-Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF Rev. 0 | Page 17 of 24 07759-052 07759-051 07759-054 07759-053 AD8227 340 330 C = 47pF L NO LOAD 320 C = 100pF L 310 C = 147pF L 300 290 20mV/DIV 4µs/DIV 0 2 4 6 8 1012 1416 18 SUPPLY VOLTAGE (±V ) S Figure 55. Small-Signal Pulse Response with Various Capacitive Loads, Figure 57. Supply Current vs. Supply Voltage G = 5, R = Infinity L 35 30 25 SETTLED TO 0.001% 20 15 SETTLED TO 0.01% 10 5 0 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) Figure 56. Settling Time vs. Step Size, V = ±15 V, Dual Supply S Rev. 0 | Page 18 of 24 SETTLING TIME (µs) 07759-055 07759-056 SUPPLY CURRENT (µA) 07759-057 AD8227 THEORY OF OPERATION +V +V S S R NODE 3 G NODE 4 R3 50kΩ –V –V S S R1 R2 +V S R4 8kΩ 8kΩ 10kΩ NODE 2 A3 V OUT NODE 1 +V R5 S 10kΩ R6 –V S ESD AND ESD AND 50kΩ REF OVERVOLTAGE OVERVOLTAGE +IN Q1 Q2 –IN A1 A2 PROTECTION PROTECTION –V S V R R B BIAS B –V DIFFERENCE S GAIN STAGE AMPLIFIER STAGE Figure 58. Simplified Schematic ARCHITECTURE GAIN SELECTION The AD8227 is based on the classic three op amp topology. This Placing a resistor across the R terminals sets the gain of the G topology has two stages: a preamplifier to provide differential AD8227. The gain can be calculated by referring to Table 7 or amplification followed by a difference amplifier that removes by using the following gain equation: the common-mode voltage and provides additional amplifica- 80 kΩ R = tion. Figure 58 shows a simplified schematic of the AD8227. G G− 5 The first stage works as follows. To maintain a constant voltage across the bias resistor, R , Amplifier A1 must keep Node 3 at a B Table 7. Gains Achieved Using Common Resistor Values constant diode drop above the positive input voltage. Similarly, Standard Table Value of RG Calculated Gain Amplifier A2 keeps Node 4 at a constant diode drop above the No resistor 5 negative input voltage. Therefore, a replica of the differential 100 kΩ 5.8 input voltage is placed across the gain setting resistor, RG. The 49.9 kΩ 6.6 current that flows across this resistance must also flow through 26.7 kΩ 8 the R1 and R2 resistors, creating a gained differential signal 20 kΩ 9 between the A2 and A1 outputs. Note that, in addition to a 16 kΩ 10 gained differential signal, the original common-mode signal, 10 kΩ 13 shifted a diode drop up, is also still present. 5.36 kΩ 19.9 2 kΩ 45 The second stage is a difference amplifier, composed of 1.78 kΩ 49.9 Amplifier A3 and the R3 through R6 resistors. This stage 1 kΩ 85 removes the common-mode signal from the amplified 845 Ω 99.7 differential signal and gains it by 5. 412 Ω 199 The transfer function of the AD8227 is 162 Ω 499 V = G × (V − V ) + V OUT IN+ IN− REF 80.6 Ω 998 where: The AD8227 defaults to G = 5 when no gain resistor is used. 80 kΩ The tolerance and gain drift of the RG resistor should be added G= 5+ to the specifications of the AD8227 to determine the total gain RG accuracy of the system. When the gain resistor is not used, gain error and gain drift are minimal. Rev. 0 | Page 19 of 24 07759-058 AD8227 Common-Mode Rejection Ratio over Frequency REFERENCE TERMINAL Poor layout can cause some of the common-mode signals to be The output voltage of the AD8227 is developed with respect to converted to differential signals before reaching the in-amp. the potential on the reference terminal. This is useful when the Such conversions occur when one input path has a frequency output signal needs to be offset to a precise midsupply level. For response that is different from the other. To keep CMRR over example, a voltage source can be tied to the REF pin to level- frequency high, the input source impedance and capacitance of shift the output so that the AD8227 can drive a single-supply each path should be closely matched. Additional source resis- ADC. The REF pin is protected with ESD diodes and should tance in the input path (for example, for input protection) should or −V by more than 0.3 V. not exceed either +VS S be placed close to the in-amp inputs, which minimizes the For best performance, source impedance to the REF terminal interaction of the source resistance with parasitic capacitance should be kept below 2 Ω. As shown in Figure 58, the reference from the PCB traces. terminal, REF, is at one end of a 50 kΩ resistor. Additional imped- Parasitic capacitance at the gain setting pins can also affect CMRR ance at the REF terminal adds to this 50 kΩ resistor and results over frequency. If the board design has a component at the gain in amplification of the signal connected to the positive input. setting pins (for example, a switch or jumper), the component The amplification from the additional R can be calculated as REF should be chosen so that the parasitic capacitance is as small as follows: possible. 6(50 kΩ + RREF)/(60 kΩ + RREF) Power Supplies Only the positive signal path is amplified; the negative path A stable dc voltage should be used to power the instrumentation is unaffected. This uneven amplification degrades CMRR. amplifier. Noise on the supply pins can adversely affect perfor- INCORRECT CORRECT mance. See the PSRR performance curves in Figure 23 and Figure 24 for more information. A 0.1 μF capacitor should be placed as close as possible to each AD8227 AD8227 REF REF supply pin. As shown in Figure 61, a 10 μF tantalum capacitor V V can be used farther away from the part. In most cases, it can be shared by other precision integrated circuits. + +V OP1177 S – 0.1µF 10µF Figure 59. Driving the Reference Pin +IN INPUT VOLTAGE RANGE V OUT R Most instrumentation amplifiers have a very limited output G AD8227 voltage swing when the common-mode voltage is near the LOAD REF –IN upper or lower limit of the part’s input range. The AD8227 has very little of this limitation. See Figure 9 through Figure 16 for the input common-mode range vs. output voltage of the part. 0.1µF 10µF LAYOUT –V S Figure 61. Supply Decoupling, REF, and Output Referred to Local Ground To ensure optimum performance of the AD8227 at the PCB level, care must be taken in the design of the board layout. The References pins of the AD8227 are arranged in a logical manner to aid in The output voltage of the AD8227 is developed with respect to this task. the potential on the reference terminal. Care should be taken to tie REF to the appropriate local ground. 1 8 +V –IN S R 2 7 V OUT G R 3 6 REF G 5 +IN 4 –V S AD8227 TOP VIEW (Not to Scale) Figure 60. Pinout Diagram Rev. 0 | Page 20 of 24 07759-060 07759-059 07759-061 AD8227 The other AD8227 terminals should be kept within the supplies. INPUT BIAS CURRENT RETURN PATH All terminals of the AD8227 are protected against ESD. The input bias current of the AD8227 must have a return path to For applications where the AD8227 encounters voltages beyond ground. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 62. the allowed limits, external current limiting resistors and low leakage diode clamps such as the BAV199L, the FJH1100s, or INCORRECT CORRECT the SP720 should be used. +V +V S S RADIO FREQUENCY INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications that have strong RF signals. The disturbance can AD8227 AD8227 appear as a small dc offset voltage. High frequency signals can REF REF be filtered with a low-pass RC network placed at the input of the instrumentation amplifier, as shown in Figure 63. The filter –V –V limits the input signal bandwidth, according to the following S S relationship: TRANSFORMER TRANSFORMER 1 +V +V S S FilterFrequency = DIFF 2πR(2C + C ) D C 1 FilterFrequency = CM 2πRC AD8227 AD8227 C REF REF where C ≥ 10 C . D C 10MΩ +V S –V –V S S 0.1µF 10µF THERMOCOUPLE THERMOCOUPLE C C 1nF +V +V S S R +IN 4.02kΩ C C V C OUT D R G AD8227 10nF 1 R R REF f = HIGH-PASS AD8227 2πRC AD8227 –IN 4.02kΩ C C REF REF C C 1nF R 0.1µF 10µF –V –V S S –V S CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 63. RFI Suppression Figure 62. Creating an Input Bias Current Return Path C affects the differential signal and C affects the common- D C INPUT PROTECTION mode signal. Values of R and CC should be chosen to minimize The AD8227 has very robust inputs and typically does not need RFI. A mismatch between R × CC at the positive input and additional input protection. Input voltages can be up to 40 V R × CC at the negative input degrades the CMRR of the AD8227. from the opposite supply rail. For example, with a +5 V positive By using a value of CD one magnitude larger than CC, the effect supply and a −8 V negative supply, the part can safely withstand of the mismatch is reduced, and performance is improved. voltages from −35 V to +32 V. Unlike some other instrumentation amplifiers, the part can handle large differential input voltages even when the part is in high gain. Figure 17 through Figure 20 show the behavior of the part under overvoltage conditions. Rev. 0 | Page 21 of 24 07759-062 07759-063 AD8227 APPLICATIONS INFORMATION Tips for Best Differential Output Performance DIFFERENTIAL DRIVE For best ac performance, an op amp with at least 2 MHz gain Figure 64 shows how to configure the AD8227 for differential bandwidth and 1 V/μs slew rate is recommended. Good choices output. for op amps are the AD8641, AD8515, or AD820. +IN Keep trace lengths from resistors to the inverting terminal of AD8227 +OUT the op amp as short as possible. Excessive capacitance at this –IN node can cause the circuit to be unstable. If capacitance cannot REF R V BIAS be avoided, use lower value resistors. – + PRECISION STRAIN GAGE R OP AMP The low offset and high CMRR over frequency of the AD8227 make it an excellent choice for bridge measurements. The bridge can be connected directly to the inputs of the amplifier –OUT (see Figure 65). RECOMMENDED OP AMPS: AD8515, AD8641, AD820. RECOMMENDED R VALUES: 5kΩ to 20kΩ. 5V Figure 64. Differential Output Using an Op Amp 10µF 0.1µF The differential output is set by the following equation: 350Ω 350Ω +IN + VDIFF_OUT = VOUT+ − VOUT− = Gain × (VIN+ − VIN−) 350Ω 350Ω R G AD8227 The common-mode output is set by the following equation: – –IN 2.5V V = (V − V )/2 = V CM_OUT OUT+ OUT− BIAS The advantage of this circuit is that the dc differential accuracy Figure 65. Precision Strain Gage depends on the AD8227 and not on the op amp or the resistors. This circuit takes advantage of the AD8227’s precise control of its output voltage relative to the reference voltage. Op amp dc performance and resistor matching affect the dc common-mode output accuracy. However, because common-mode errors are likely to be rejected by the next device in the signal chain, these errors typically have little effect on overall system accuracy. Rev. 0 | Page 22 of 24 07759-064 07759-065 AD8227 Option 2 shows a circuit for driving higher frequency signals. DRIVING AN ADC It uses a precision op amp (AD8616) with relatively high band- Figure 66 shows several different methods for driving an ADC. width and output drive. This amplifier can drive a resistor and The ADC in the ADuC7026 microcontroller was chosen for capacitor with a much higher time constant and is, therefore, this example because it has an unbuffered charge sampling suited for higher frequency applications. architecture that is typical of most modern ADCs. This type of architecture typically requires an RC buffer stage between the Option 3 is useful for applications where the AD8227 needs to ADC and the amplifier to work correctly. run off a large voltage supply but drives a single-supply ADC. In normal operation, the AD8227 output stays within the ADC Option 1 shows the minimum configuration required to drive range, and the AD8616 simply buffers it. However, in a fault a charge sampling ADC. The capacitor provides charge to the condition, the output of the AD8227 may go outside the supply ADC sampling capacitor, and the resistor shields the AD8227 range of both the AD8616 and the ADC. This is not an issue in from the capacitance. To keep the AD8227 stable, the RC time the circuit, because the 10 kΩ resistor between the two amplifiers constant of the resistor and capacitor needs to stay above 5 μs. limits the current into the AD8616 to a safe level. This circuit is mainly useful for lower frequency signals. OPTION 1: DRIVING LOW FREQUENCY SIGNALS 3.3V 3.3V AV DD 100Ω ADC0 AD8227 REF 100nF ADuC7026 OPTION 2: DRIVING HIGH FREQUENCY SIGNALS 3.3V 3.3V AD8227 10Ω REF AD8616 ADC1 10nF OPTION 3: PROTECTING ADC FROM LARGE VOLTAGES +15V 3.3V 10kΩ AD8227 10Ω REF AD8616 ADC2 10nF AGND –15V Figure 66. Driving an ADC Rev. 0 | Page 23 of 24 07759-066 AD8227 OUTLINE DIMENSIONS 3.20 5.00 (0.1968) 3.00 4.80 (0.1890) 2.80 85 6.20 (0.2441) 4.00 (0.1574) 8 5 5.15 1 5.80 (0.2284) 3.20 3.80 (0.1497) 4 4.90 3.00 4.65 1 2.80 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) PIN 1 1.35 (0.0532) 0.25 (0.0098) 0.65 BSC 8° 0.10 (0.0040) 0° 0.95 0.51 (0.0201) COPLANARITY 0.85 1.10 MAX 1.27 (0.0500) 0.10 0.31 (0.0122) 0.75 0.25 (0.0098) SEATING 0.40 (0.0157) 0.80 PLANE 0.17 (0.0067) 8° 0.15 0.60 0.38 0.23 0° 0.00 0.22 0.40 0.08 COMPLIANT TO JEDEC STANDARDS MS-012-AA COPLANARITY SEATING CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.10 PLANE (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 67. 8-Lead Mini Small Outline Package [MSOP] Figure 68. 8-Lead Standard Small Outline Package [SOIC_N] (RM-8) Narrow Body Dimensions shown in millimeters (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 1 AD8227ARMZ −40°C to +125°C 8-Lead MSOP RM-8 Y1S 1 AD8227ARMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1S 1 AD8227ARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1S 1 AD8227ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8227ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8227ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8227BRMZ −40°C to +125°C 8-Lead MSOP RM-8 Y1U 1 AD8227BRMZ-RL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 Y1U 1 AD8227BRMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 Y1U 1 AD8227BRZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8227BRZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8227BRZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07759-0-5/09(0) Rev. 0 | Page 24 of 24 012407-A