ANALOG DEVICES AD8224

Precision, Dual-Channel, JFET Input, Rail-to-Rail Instrumentation Amplifier AD8224 FEATURES FUNCTIONAL BLOCK DIAGRAM Two channels in a small 4 mm × 4 mm LFCSP Custom LFCSP package with hidden paddle 16 15 14 13 Permits routing and vias underneath package Allows full bias current performance AD8224 –IN1 1 12 –IN2 Low input currents 2 11 R R G1 G2 10 pA maximum input bias current (B Grade) R 3 10 R G1 G2 0.6 pA maximum input offset current (B Grade) +IN1 4 9 +IN2 High CMRR 100 dB CMRR (minimum), G = 10 (B Grade) 56 7 8 90 dB CMRR (minimum) to 10 kHz, G = 10 (B Grade) Excellent ac specifications and low power 1.5 MHz bandwidth (G = 1) Figure 1. 14 nV/√Hz input noise (1 kHz) Slew rate: 2 V/μs Table 1. In Amps and Difference Amplifiers by Category 750 μA quiescent current per amplifier High Low High Mil Low Digital Versatility Perform Cost Voltage Grade Power Gain 1 1 1 1 Rail-to-rail output AD8220 AD8553 AD628 AD620 AD627 AD8231 1 Input voltage range to below negative supply rail AD8221 AD623 AD629 AD621 AD8250 4 kV ESD protection AD8222 AD524 AD8251 4.5 V to 36 V single supply 1 AD526 AD8555 ±2.25 V to ±18 V dual supply 1 AD624 AD8556 Gain set with single resistor (G = 1 to 1000) 1 AD8557 1 Rail-to-rail output. APPLICATIONS Medical instrumentation Precision data acquisition Transducer interfaces Differential drives for high resolution input ADCs Remote sensors GENERAL DESCRIPTION to alleviate this problem, the AD8224 can operate on a ±18 V The AD8224 is the first single-supply, JFET input instrumentation dual supply, as well as on a single +5 V supply. The device’s rail- amplifier available in the space-saving 16-lead, 4 mm × 4 mm to-rail output stage maximizes dynamic range on the low LFCSP. It requires the same board area as a typical single voltage supplies common in portable applications. Its ability to instrumentation amplifier yet doubles the channel density run on a single 5 V supply eliminates the need for higher and offers a lower cost per channel without compromising voltage, dual supplies. The AD8224 draws 750 μA of quiescent performance. current per amplifier, making it ideal for battery powered Designed to meet the needs of high performance, portable devices. instrumentation, the AD8224 has a minimum common-mode In addition, the AD8224 can be configured as a single-channel, rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR differential output, instrumentation amplifier. Differential of 80 dB at 10 kHz for G = 1. Maximum input bias current is outputs provide high noise immunity, which can be useful when 10 pA and typically remains below 300 pA over the entire the output signal must travel through a noisy environment, such industrial temperature range. Despite the JFET inputs, the as with remote sensors. The configuration can also be used to AD8224 typically has a noise corner of only 10 Hz. drive differential input ADCs. For a single-channel version, use With the proliferation of mixed-signal processing, the number the AD8220. of power supplies required in each system has grown. Designed Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. +V +V S S REF1 OUT1 REF2 OUT2 –V –V S S 06286-001 AD8224 TABLE OF CONTENTS Features .............................................................................................. 1 Layout .......................................................................................... 21 Applications ....................................................................................... 1 Solder Wash ................................................................................. 22 Functional Block Diagram .............................................................. 1 Input Bias Current Return Path ............................................... 22 General Description ......................................................................... 1 Input Protection ......................................................................... 22 Revision History ............................................................................... 2 RF Interference ........................................................................... 23 Specif ica t ions ..................................................................................... 3 Common-Mode Input Voltage Range ..................................... 23 Absolute Maximum Ratings ............................................................ 9 Applications Information .............................................................. 24 Thermal Resistance ...................................................................... 9 Driving an ADC ......................................................................... 24 ESD Caution .................................................................................. 9 Differential Output .................................................................... 24 Pin Configuration and Function Descriptions ........................... 10 Driving a Differential Input ADC ............................................ 25 Typical Performance Characteristics ........................................... 11 Driving Cabling .......................................................................... 25 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 26 Gain Selection ............................................................................. 20 Ordering Guide .......................................................................... 27 Reference Terminal .................................................................... 21 REVISION HISTORY Changes to Table 6 and Table 7 ....................................................... 8 5/10—Rev. A to Rev. B Changes to Figure 2 ........................................................................... 9 Changes to Features Section............................................................ 1 Changes to Figure 3 ........................................................................ 10 Added Table 10 ................................................................................. 9 Inserted Figure 4, Figure 5, and Figure 6; Renumbered Changes to Figure 3 and Table 11 ................................................. 10 Sequentially ..................................................................................... 11 Added Hidden Paddle Package Section and Exposed Paddle Changes to Figure 7 ........................................................................ 11 Package Section and Figure 58 ...................................................... 21 Changes to Figure 20 and Figure 21............................................. 13 Updated Outline Dimensions ....................................................... 26 Changes to Figure 28 ...................................................................... 15 Changes to Ordering Guide .......................................................... 27 Changes to Theory of Operation and Figure 55 ........................ 20 4/07—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 26 Changes to Features, General Description, and Figure 1 ............ 1 1/07—Revision 0: Initial Version Changes to Table 2 ............................................................................ 3 Changes to Table 3 and Table 4 ....................................................... 5 Changes to Table 5 ............................................................................ 6 Rev. B | Page 2 of 28 AD8224 SPECIFICATIONS 1 VS+ = +15 V, VS− = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ , unless otherwise noted. Table 2 displays the specifications for an individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential outputs as shown in Figure 63. 2 Table 2. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration , VS = ±15 V A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with V = ±10 V CM 1 kΩ Source Imbalance G = 1 78 86 dB G = 10 94 100 dB G = 100 94 100 dB G = 1000 94 100 dB CMRR at 10 kHz VCM = ±10 V G = 1 74 80 dB G = 10 84 90 dB G = 100 84 90 dB G = 1000 84 90 dB NOISE RTI noise = 2 2 √(e + (e /G) ) ni no Voltage Noise, 1 kHz Input Voltage Noise, eni VIN+, VIN− = 0 V 14 14 17 nV/√Hz Output Voltage Noise, eno VIN+, VIN− = 0 V 90 90 100 nV/√Hz RTI, 0.1 Hz to 10 Hz G = 1 5 5 μV p-p G = 1000 0.8 0.8 μV p-p Current Noise f = 1 kHz 1 1 fA/√Hz VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G) Input Offset, VOSI 300 175 μV Average TC T = −40°C to +85°C 10 5 μV/°C Output Offset, VOSO 1200 800 μV Average TC T = −40°C to +85°C 10 5 μV/°C Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V G = 1 86 86 dB G = 10 96 100 dB G = 100 96 100 dB G = 1000 96 100 dB INPUT CURRENT (PER CHANNEL) Input Bias Current 25 10 pA 3 Over Temperature T = −40°C to +85°C 300 300 pA Input Offset Current 2 0.6 pA 3 Over Temperature T = −40°C to +85°C 5 5 pA REFERENCE INPUT RIN 40 40 kΩ IIN VIN+, VIN− = 0 V 70 70 μA Voltage Range −V +V −V +V V S S S S Gain to Output 1 ± 1 ± V/V 0.0001 0.0001 Rev. B | Page 3 of 28 AD8224 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit GAIN G = 1 + (49.4 kΩ/RG) Gain Range 1 1000 1 1000 V/V Gain Error V = ±10 V OUT G = 1 0.06 0.04 % G = 10 0.3 0.2 % G = 100 0.3 0.2 % G = 1000 0.3 0.2 % Gain Nonlinearity VOUT = −10 V to +10 V G = 1 RL = 10 kΩ 8 15 8 15 ppm G = 10 RL = 10 kΩ 5 10 5 10 ppm G = 100 R = 10 kΩ 15 25 15 25 ppm L G = 1000 RL = 10 kΩ 100 150 100 150 ppm G = 1 RL = 2 kΩ 15 20 15 20 ppm G = 10 RL = 2 kΩ 12 20 12 20 ppm G = 100 R = 2 kΩ 35 50 35 50 ppm L G=1000 RL = 2 kΩ 180 250 180 250 ppm Gain vs. Temperature G = 1 3 10 2 5 ppm/°C G > 10 −50 −50 ppm/°C INPUT 4 4 4 Impedance (Pin to Ground) 10||5 10||5 GΩ||pF 5 Input Operating Voltage Range V = ±2.25 V to ±18 V −VS − 0.1 +VS − 2 −VS − 0.1 +VS − 2 V S for dual supplies Over Temperature T = −40°C to +85°C −V − 0.1 +V − 2.1 −V − 0.1 +V − 2.1 V S S S S OUTPUT Output Swing R = 2 kΩ −14.25 +14.25 −14.25 +14.25 V L Over Temperature T = −40°C to +85°C −14.3 +14.1 −14.3 +14.1 V Output Swing RL = 10 kΩ −14.7 +14.7 −14.7 +14.7 V Over Temperature T = −40°C to +85°C −14.6 +14.6 −14.6 +14.6 V Short-Circuit Current 15 15 mA POWER SUPPLY (PER AMPLIFIER) 6 6 Operating Range ±2.25 ±18 ±2.25 ±18 V Quiescent Current 750 800 750 800 μA Over Temperature T = −40°C to +85°C 850 900 850 900 μA TEMPERATURE RANGE For Specified Performance −40 +85 −40 +85 °C 7 Operational −40 +125 −40 +125 °C 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 63. 3 Refer to Figure 14 and Figure 15 for the relationship between input current and temperature. 4 Differential and common-mode input impedance can be calculated from the pin impedance: Z = 2(Z ); Z = Z /2. DIFF PIN CM PIN 5 The AD8224 can operate up to a diode drop below the negative supply; however, the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. 7 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in this temperature range. Rev. B | Page 4 of 28 AD8224 1 V + = +15 V, V − = −15 V, V = 0 V, T = 25°C, G = 1, R = 2 kΩ , unless otherwise noted. Table 3 displays the specifications for the S S REF A L dynamic performance of each individual instrumentation amplifier. Table 3. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, V = ±15 V S A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G =1000 14 14 kHz Settling Time 0.01% ΔV = ±10 V step O G = 1 5 5 μs G = 10 4.3 4.3 μs G = 100 8.1 8.1 μs G =1000 58 58 μs Settling Time 0.001% ΔV = ±10 V step O G = 1 6 6 μs G = 10 4.6 4.6 μs G = 100 9.6 9.6 μs G =1000 74 74 μs Slew Rate G = 1 to 100 2 2 V/μs 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 1 V + = +15 V, V − = −15 V, V = 0 V, T = 25°C, G = 1, R = 2 kΩ , unless otherwise noted. Table 4 displays the specifications for the S S REF A L dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 63. 2 Table 4. Dynamic Performance of Both Amplifiers—Differential Output Configuration , VS = ±15 V A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G =1000 14 14 kHz Settling Time 0.01% ΔVO = ±10 V step G = 1 5 5 μs G = 10 4.3 4.3 μs G = 100 8.1 8.1 μs G =1000 58 58 μs Settling Time 0.001% ΔVO = ±10 V step G = 1 6 6 μs G = 10 4.6 4.6 μs G = 100 9.6 9.6 μs G =1000 74 74 μs Slew Rate G = 1 to 100 2 2 V/μs 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 63. Rev. B | Page 5 of 28 AD8224 1 V + = 5 V, V − = 0 V, V = 2.5 V, T = 25°C, G = 1, R = 2 kΩ , unless otherwise noted. Table 5 displays the specifications for an S S REF A L individual instrumentation amplifier configured for a single-ended output or dual instrumentation amplifiers configured for differential outputs as shown in Figure 63. 2 Table 5. Individual Amplifier in Single-Ended Configuration or Dual Amplifiers in Differential Output Configuration , VS =+5 V A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with VCM = 0 to 2.5 V 1 kΩ Source Imbalance G = 1 78 86 dB G = 10 94 100 dB G = 100 94 100 dB G = 1000 94 100 dB CMRR at 10 kHz G = 1 74 80 dB G = 10 84 90 dB G = 100 84 90 dB G = 1000 84 90 dB 2 2 NOISE RTI noise = √(e + (e /G)) ni no Voltage Noise, 1 kHz V = ±2.5 V S Input Voltage Noise, e V +, V − = 0 V, V = 0 V 14 14 17 nV/√Hz ni IN IN REF Output Voltage Noise, eno VIN+, VIN− = 0 V, VREF = 0 V 90 90 100 nV/√Hz RTI, 0.1 Hz to 10 Hz G = 1 5 5 μV p-p G = 1000 0.8 0.8 μV p-p Current Noise f = 1 kHz 1 1 fA/√Hz VOLTAGE OFFSET RTI VOS = (VOSI) + (VOSO/G) Input Offset, V 300 250 μV OSI Average TC T = −40°C to +85°C 10 5 μV/°C Output Offset, VOSO 1200 800 μV Average TC T = −40°C to +85°C 10 5 μV/°C Offset RTI vs. Supply (PSR) G = 1 86 86 dB G = 10 96 100 dB G = 100 96 100 dB G = 1000 96 100 dB INPUT CURRENT (PER CHANNEL) Input Bias Current 25 10 pA 3 Over Temperature T = −40°C to +85°C 300 300 pA Input Offset Current 2 0.6 pA 3 Over Temperature T = −40°C to +85°C 5 5 pA REFERENCE INPUT RIN 40 40 kΩ I V +, V − = 0 V 70 70 μA IN IN IN Voltage Range −V +V −V +V V S S S S Gain to Output 1 ± 1 ± V/V 0.0001 0.0001 Rev. B | Page 6 of 28 AD8224 A Grade B Grade Parameter Test Conditions Min Typ Max Min Typ Max Unit GAIN G = 1 + (49.4 kΩ/RG) Gain Range 1 1000 1 1000 V/V Gain Error G = 1 V = 0.3 V to 2.9 V 0.06 0.04 % OUT G = 10 VOUT = 0.3 V to 3.8 V 0.3 0.2 % G = 100 VOUT = 0.3 V to 3.8 V 0.3 0.2 % G = 1000 VOUT = 0.3 V to 3.8 V 0.3 0.2 % Nonlinearity V = 0.3 V to 2.9 V for G = 1 OUT V = 0.3 V to 3.8 V for G > 1 OUT G = 1 RL = 10 kΩ 35 50 35 50 ppm G = 10 RL = 10 kΩ 35 50 35 50 ppm G = 100 RL = 10 kΩ 50 75 50 75 ppm G = 1000 R = 10 kΩ 90 115 90 115 ppm L G = 1 R = 2 kΩ 35 50 35 50 ppm L G = 10 R = 2 kΩ 35 50 35 50 ppm L G = 100 RL = 2 kΩ 50 75 50 75 ppm G = 1000 RL = 2 kΩ 175 200 175 200 ppm Gain vs. Temperature G = 1 3 10 2 5 ppm/°C G > 10 −50 −50 ppm/°C INPUT 4 4 4 Impedance (Pin to Ground) 10||6 10||6 GΩ||pF 5 Input Voltage Range −0.1 +V − 2 −0.1 +V − 2 V S S Over Temperature T = −40°C to +85°C −0.1 +VS − 2.1 −0.1 +VS − 2.1 V OUTPUT Output Swing R = 2 kΩ 0.25 4.75 0.25 4.75 V L Over Temperature T = −40°C to +85°C 0.3 4.70 0.3 4.70 V Output Swing RL = 10 kΩ 0.15 4.85 0.15 4.85 V Over Temperature T = −40°C to +85°C 0.2 4.80 0.2 4.80 V Short-Circuit Current 15 15 mA POWER SUPPLY (PER AMPLIFIER) Operating Range 4.5 36 4.5 36 V Quiescent Current 750 800 750 800 μA Over Temperature T = −40°C to +85°C 850 900 850 900 μA TEMPERATURE RANGE For Specified Performance −40 +85 −40 +85 °C 6 Operational −40 +125 −40 +125 °C 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 63. 3 Refer to Figure 14 and Figure 15 for the relationship between input current and temperature. 4 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. 5 The AD8224 can operate up to a diode drop below the negative supply, but the bias current increases sharply. The input voltage range reflects the maximum allowable voltage where the input bias current is within the specification. 6 The AD8224 is characterized from −40°C to +125°C. See the Typical Performance Characteristics section for expected operation in that temperature range. Rev. B | Page 7 of 28 AD8224 1 V + = 5 V, V − = 0 V, V = 2.5 V, T = 25°C, G = 1, R = 2 kΩ , unless otherwise noted. Table 6 displays the specifications for the S S REF A L dynamic performance of each individual instrumentation amplifier. Table 6. Dynamic Performance of Each Individual Amplifier—Single-Ended Output Configuration, V = +5 V S A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G =1000 14 14 kHz Settling Time 0.01% G = 1 ΔVO = 3 V step 2.5 2.5 μs G = 10 ΔVO = 4 V step 2.5 2.5 μs G = 100 ΔVO = 4 V step 7.5 7.5 μs G =1000 ΔV = 4 V step 60 60 μs O Settling Time 0.001% G = 1 ΔV = 3 V step 3.5 3.5 μs O G = 10 ΔVO = 4 V step 3.5 3.5 μs G = 100 ΔV = 4 V step 8.5 8.5 μs O G =1000 ΔVO = 4 V step 75 75 μs Slew Rate G = 1 to 100 2 2 V/μs 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 1 VS + = 5 V, VS− = 0 V, VREF = 2.5 V, TA = 25°C, G = 1, RL = 2 kΩ unless otherwise noted. Table 7 displays the specifications for the dynamic performance of both amplifiers when used in the differential output configuration shown in Figure 63. 2 Table 7. Dynamic Performance of Both Amplifiers—Differential Output Configuration , VS = +5 V A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth −3 dB G = 1 1500 1500 kHz G = 10 800 800 kHz G = 100 120 120 kHz G =1000 14 14 kHz Settling Time 0.01% G = 1 ΔVO = 3 V step 2.5 2.5 μs G = 10 ΔV = 4 V step 2.5 2.5 μs O G = 100 ΔV = 4 V step 7.5 7.5 μs O G =1000 ΔVO = 4 V step 60 60 μs Settling Time 0.001% G = 1 ΔVO = 3 V step 3.5 3.5 μs G = 10 ΔV = 4 V step 3.5 3.5 μs O G = 100 ΔVO = 4 V step 8.5 8.5 μs G =1000 ΔVO = 4 V step 75 75 μs Slew Rate G = 1 to 100 2 2 V/μs 1 When the output sinks more than 4 mA, use a 47 pF capacitor in parallel with the load to prevent ringing. Otherwise, use a larger load, such as 10 kΩ. 2 Refers to the differential configuration shown in Figure 63. Rev. B | Page 8 of 28 AD8224 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Rating Table 9. Supply Voltage ±18 V Exposed Paddle Package θ Unit JA Power Dissipation See Figure 2 CP-16-13: LFCSP Soldered to Board 48 °C/W 1 Output Short-Circuit Current Indefinite CP-16-13: LFCSP Not Soldered to Board 86 °C/W Input Voltage (Common Mode) ±VS Table 10. Differential Input Voltage ±VS Hidden Paddle Package θ Unit JA Storage Temperature Range −65°C to +130°C 2 CP-16-19: LFCSP 86 °C/W Operating Temperature Range −40°C to +125°C Lead Temperature (Soldering, 10 sec) 300°C The θJA values in Table 9 and Table 10 assume a 4-layer JEDEC Junction Temperature 130°C standard board. If the thermal pad is soldered to the board, it is Package Glass Transition Temperature 130°C also assumed it is connected to a plane. θJC at the exposed pad is ESD (Human Body Model) 4 kV 4.4°C/W. ESD (Charge Device Model) 1 kV ESD (Machine Model) 0.4 kV Maximum Power Dissipation Stresses above those listed under Absolute Maximum Ratings The maximum safe power dissipation for the AD8224 is limited may cause permanent damage to the device. This is a stress by the associated rise in junction temperature (TJ) on the die. At rating only; functional operation of the device at these or any approximately 130°C, which is the glass transition temperature, other conditions above those indicated in the operational the plastic changes its properties. Even temporarily exceeding section of this specification is not implied. Exposure to absolute this temperature limit may change the stresses that the package maximum rating conditions for extended periods may affect exerts on the die, permanently shifting the parametric performance device reliability. of the amplifiers. Exceeding a temperature of 130°C for an extended period can result in a loss of functionality. Figure 2 1 Assumes the load is referenced to midsupply. shows the maximum safe power dissipation in the package vs. 2 Temperature for specified performance is −40°C to +85°C. For performance the ambient temperature for the LFCSP on a 4-layer JEDEC to 125°C, see the Typical Performance Characteristics section. standard board. 4.0 3.5 3.0 θ = 48°C/W WHEN THERMAL PAD JA IS SOLDERED TO BOARD 2.5 2.0 1.5 1.0 θ = 86°C/W WHEN THERMAL PAD JA IS NOT SOLDERED TO BOARD 0.5 0 –60 –40 –20 0 20 40 60 80 100 120 140 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. B | Page 9 of 28 MAXIMUM POWER DISSIPATION (W) 06286-002 AD8224 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 12 –IN1 1 –IN2 INDICATOR R 2 11 R G1 G2 AD8224 R 3 10 R G1 G2 TOP VIEW +IN1 4 9 +IN2 NOTES 1. THE AD8224 COMES IN TWO PACKAGE TYPES—EACH IS A 16 LEAD 4mm × 4mm LFCSP. ONE PACKAGE HAS AN EXPOSED THERMAL PAD, WHICH IS CONNECTED TO +V . THE OTHER PACKAGE TYPE DOES NOT S EXPOSE THE THERMAL PAD. SEE THE PACKAGE CONSIDERATIONS SECTION FOR MORE INFORMATION. Figure 3. Pin Configuration Table 11. Pin Function Descriptions Pin Number Mnemonic Description 1 −IN1 Negative Input Instrumentation Amplifier (In-Amp) 1 2 R Gain Resistor In-Amp 1 G1 3 R Gain Resistor In-Amp 1 G1 4 +IN1 Positive Input In-Amp 1 5 +VS Positive Supply 6 REF1 Reference Adjust In-Amp 1 7 REF2 Reference Adjust In-Amp 2 8 −V Negative Supply S 9 +IN2 Positive Input In-Amp 2 10 R Gain Resistor In-Amp 2 G2 11 RG2 Gain Resistor In-Amp 2 12 −IN2 Negative Input In-Amp 2 13 −VS Negative Supply 14 OUT2 Output In-Amp 2 15 OUT1 Output In-Amp 1 16 +VS Positive Supply Rev. B | Page 10 of 28 +V +V 5 16 S S REF1 6 15 OUT1 REF2 7 14 OUT2 –V –V 8 13 S S 06286-003 AD8224 TYPICAL PERFORMANCE CHARACTERISTICS 25°C, VS = ±15 V, RL =10 kΩ, unless otherwise noted. 1000 400 350 GAIN = 100 BANDWIDTH ROLL-OFF 300 100 GAIN = 1 250 GAIN = 10 200 150 GAIN = 100/GAIN = 1000 10 100 GAIN = 1000 BANDWIDTH ROLL-OFF 50 0 1 –40 –20 0 20 40 1 10 100 1k 10k 100k CMRR (µV/V) FREQUENCY (Hz) Figure 4. Typical Distribution of CMRR (G = 1) Figure 7. Voltage Spectral Density vs. Frequency XX 400 350 300 250 200 150 100 50 5µV/DIV 1s/DIV 0 XX –200 –100 0 100 200 XX XX V (µV) OSI XXX (X) Figure 5. Typical Distribution of Input Offset Voltage Figure 8. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) XX 400 300 200 100 1µV/DIV 1s/DIV 0 XX –1200 –900 –600 –300 0 300 600 900 1200 XX XX V (µV) OSO XXX (X) Figure 6. Typical Distribution of Output Offset Voltage Figure 9. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Rev. B | Page 11 of 28 NUMBER OF UNITS NUMBER OF UNITS NUMBER OF UNITS 06286-071 06286-072 06286-070 VOLTAGE NOISE RTI (nV/ Hz) XXX (X) XXX (X) 06286-011 06286-010 06286-009 AD8224 0.3 4.5 INPUT OFFSET 9 CURRENT ±15 4.0 INPUT OFFSET 3.5 CURRENT ±5 0.1 7 3.0 2.5 5 –15.1V INPUT BIAS –0.1 CURRENT ±15 2.0 3 1.5 –5.1V INPUT BIAS –0.3 1.0 CURRENT ±5 1 0.5 0 –1 –0.5 0.1 1 10 100 1000 –16 –12 –8 –4 0 4 8 12 16 TIME (s) COMMON-MODE VOLTAGE (V) Figure 13. Input Bias Current and Input Offset Current vs. Common-Mode Voltage Figure 10. Change in Input Offset Voltage vs. Warmup Time 150 10n GAIN = 1000 130 BANDWIDTH GAIN = 100 1n 110 LIMITED I BIAS GAIN = 10 100p 90 10p GAIN = 1 70 I OS 1p 50 0.1p 30 10 –50 –25 0 25 50 75 100 125 150 11 10 100 1k 10k 100kM TEMPERATURE (°C) FREQUENCY (Hz) Figure 14. Input Bias Current and Offset Current vs. Temperature, Figure 11. Positive PSRR vs. Frequency, RTI V = ±15 V, V = 0 V S REF 150 10n 130 1n 110 GAIN = 1000 I BIAS 100p 90 GAIN = 1 10p 70 GAIN = 10 I OS 1p 50 GAIN = 100 0.1p 30 10 –50 –25 0 25 50 75 100 125 150 11 10 100 1k 10k 100kM TEMPERATURE (°C) FREQUENCY (Hz) Figure 15. Input Bias Current and Offset Current vs. Temperature, Figure 12. Negative PSRR vs. Frequency, RTI VS = 5 V, VREF = 2.5 V Rev. B | Page 12 of 28 PSRR (dB) PSRR (dB) DELTA V (µV) OSI 06286-012 06286-014 06286-013 INPUT BIAS CURRENT (pA) CURRENT (A) INPUT BIAS CURRENT (A) 06286-017 06286-016 INPUT OFFSET CURRENT (pA) 06286-068 AD8224 70 160 60 GAIN = 1000 140 GAIN = 1000 50 BANDWIDTH 40 GAIN = 100 LIMITED GAIN = 100 120 30 GAIN = 10 20 GAIN = 10 100 GAIN = 1 10 0 80 GAIN = 1 –10 –20 60 –30 40 –40 10 100 1000 10000 100000 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. Gain vs. Frequency Figure 16. CMRR vs. Frequency 160 140 GAIN = 1000 GAIN = 100 R = 2kΩ LOAD 120 GAIN = 10 R = 10kΩ LOAD GAIN = 1 100 BANDWIDTH LIMITED 80 60 V = ±15V S 40 1 10 100 1000 10000 100000 –10 –8 –6 –4 –2 0 2 4 6 8 10 FREQUENCY (Hz) OUTPUT VOLTAGE (V) Figure 17. CMRR vs. Frequency, 1 kΩ Source Imbalance Figure 20. Gain Nonlinearity, G = 1 7 6 5 R = 2kΩ LOAD 4 R = 10kΩ LOAD 3 2 1 V = ±15V S 0 –50 –30 –10 10 30 50 70 90 110 130 –10 –8 –6 –4 –2 0 2 4 6 8 10 TEMPERATURE (°C) OUTPUT VOLTAGE (V) Figure 18. Change in CMRR vs. Temperature, G = 1 Figure 21. Gain Nonlinearity, G = 10 Rev. B | Page 13 of 28 CMRR (dB) CMRR (dB) CMRR (µV/V) 06286-020 06286-019 06286-018 GAIN (dB) XXX XXX NONLINEARITY (10ppm/DIV) NONLINEARITY (10ppm/DIV) 06286-023 06286-022 06286-021 AD8224 4 +3V 3 R = 2kΩ LOAD 2 +0.1V, +1.7V +4.9V, +1.7V R = 10kΩ LOAD +5V SINGLE SUPPLY, V = +2.5V REF 1 +0.1V, +0.5V +4.9V, +0.5V 0 –0.3V V = ±15V S –1 –1 012 34 5 6 –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 25. Input Common-Mode Voltage Range vs. Output Voltage, Figure 22. Gain Nonlinearity, G = 100 G = 1, V = 5 V, V = 2.5 V S REF 18 +13V ±15V SUPPLIES 12 R = 2kΩ LOAD 6 +3V –14.9V, +5.4V +14.9V, +5.4V –4.9V, +0.4V +4.9V, +0.5V R = 10kΩ 0 LOAD ±5V SUPPLIES –4.9V, –4.1V +4.9V, –4.1V –6 –5.3V –14.8V, –9V +14.9V, –9V –12 –15.3V V = ±15V S –18 –16 –12 –8 –4 0 4 8 12 16 –10 –8 –6 –4 –2 0 2 4 6 8 10 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 23. Gain Nonlinearity, G = 1000 Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, V = 0 V REF 18 4 +13V +3V 12 ±15V SUPPLIES 3 6 –14.8V, +5.5V +3V +14.9V, +5.5V 2 –4.8V, +0.6V +4.95V, +0.6V +0.1V, +1.7V +4.9V, +1.7V 0 ±5V SUPPLIES +5V SINGLE SUPPLY, –4.8V, –3.3V +4.95V, –3.3V 1 V = +2.5V REF –6 –14.8V, –8.3V +14.9V, –8.3V –5.3V 0 –12 +0.1V, –0.5V +4.9V, –0.5V –0.3V –15.3V –18 –1 –16 –12 –8 –4 0 4 8 12 16 –1 012 34 5 6 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 24. Input Common-Mode Voltage Range vs. Output Voltage, Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, V = 0 V G = 100, V = 5 V, V = 2.5 V REF S REF Rev. B | Page 14 of 28 INPUT COMMON-MODE VOLTAGE (V) XXX XXX NONLINEARITY (100ppm/DIV) NONLINEARITY (20ppm/DIV) 06286-024 06286-025 06286-026 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 06286-029 06286-027 06286-028 AD8224 V + 15 S –1 –40°C +125°C 10 –40°C +25°C –2 +85°C 5 +25°C +85°C +125°C NOTES 1. THE AD8224 CAN OPERATE UP TO A V BELOW BE 0 THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT WILL INCREASE SHARPLY. +125°C –5 +1 +85°C –40°C +25°C +85°C +125°C –10 +25°C V – S –40°C –1 –15 21 4 6 8 10 12 14 168 100 1k 10k SUPPLY VOLTAGE (V) R (Ω) LOAD Figure 28. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V Figure 31. Output Voltage Swing vs. Load Resistance, VS = ±15 V, VREF = 0 V V + 5 S –1 –40°C +85°C –40°C +85°C +25°C +25°C –2 4 +125°C –3 +125°C –4 3 +4 2 +3 +125°C +2 1 +25°C +125°C –40°C +85°C +85°C +25°C +1 –40°C V – 0 S 21 4 6 8 10 12 14 168 100 1k 10k DUAL SUPPLY VOLTAGE (±V) R (Ω) LOAD Figure 32. Output Voltage Swing vs. Load Resistance, V = 5 V, V = 2.5 V Figure 29. Output Voltage Swing vs. Dual Supply Voltage, S REF R = 2 kΩ, G = 10, V = 0 V LOAD REF V + V + S S –40°C –0.2 –1 +125°C +85°C +25°C –0.4 –2 +125°C +85°C –40°C +25°C –3 –4 +4 +3 +2 +85°C +25°C +0.4 +125°C +125°C +85°C +25°C –40°C +0.2 +1 –40°C V – V – S S 21 4 6 8 10 12 14 168 01 2 4 6 8 1012146 DUAL SUPPLY VOLTAGE (±V) I (mA) OUT Figure 33. Output Voltage Swing vs. Output Current, V = ±15 V, V = 0 V Figure 30. Output Voltage Swing vs. Dual Supply Voltage, S REF RLOAD = 10 kΩ, G = 10, VREF = 0 V Rev. B | Page 15 of 28 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) INPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES REFERRED TO SUPPLY VOLTAGES 06286-030 06286-032 06286-031 OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 06286-035 06286-034 06286-033 AD8224 V + 35 S GAIN = 10, 100, 1000 30 –1 +25°C GAIN = 1 +85°C 25 +125°C –2 20 15 +2 10 +25°C +85°C +1 +125°C 5 –40°C V – 0 S 01 2 4 6 8 1012146 100 1k 10k 100k 1M 10M I (mA) FREQUENCY (Hz) OUT Figure 34. Output Voltage Swing vs. Output Current, VS = 5 V, VREF = 2.5 V Figure 37. Output Voltage Swing vs. Large Signal Frequency Response XX XX 47pF NO LOAD 100pF 5V/DIV 5µs TO 0.01% 6µs TO 0.001% 0.002%/DIV 20µs/DIV 20mV/DIV 5µs/DIV XX XX XX XX XX XX XXX (X) XXX (X) Figure 35. Small Signal Pulse Response for Various Capacitive Loads, Figure 38. Large Signal Pulse Response and Settle Time, G = 1, VS = ±15 V, VREF = 0 V RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V XX XX 47pF 100pF NO LOAD 5V/DIV 4.3μs TO 0.01% 0.002%/DIV 4.6μs TO 0.001% 20µs/DIV 20mV/DIV 5µs/DIV XX XX XX XX XX XX XXX (X) XXX (X) Figure 36. Small Signal Pulse Response for Various Capacitive Loads, Figure 39. Large Signal Pulse Response and Settle Time, G = 10, VS = 5 V, VREF = 2.5 V RLOAD = 10 kΩ, VS = ±15 V, VREF = 0 V Rev. B | Page 16 of 28 XXX (X) XXX (X) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 06286-036 06286-038 06286-037 OUTPUT VOLTAGE SWING (V p-p) XXX (X) XXX (X) 06286-041 06286-040 06286-039 AD8224 XX 5V/DIV 8.1μs TO 0.01% 0.002%/DIV 9.6μs TO 0.001% 20mV/DIV 20µs/DIV XX 4µs/DIV XX XX XXX XXX (X) Figure 40. Large Signal Pulse Response and Settle Time, Figure 43. Small Signal Pulse Response, G = 100, R = 10 kΩ, V = ±15 V, V = 0 V G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V LOAD S REF XX 5V/DIV 58μs TO 0.01% 0.002%/DIV 74μs TO 0.001% 20mV/DIV 200µs/DIV XX XX XX 4µs/DIV XXX (X) XXX Figure 41. Large Signal Pulse Response and Settle Time, G = 1000, Figure 44. Small Signal Pulse Response, R = 10 kΩ, V = ±15 V, V = 0 V LOAD S REF G = 100, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V 20mV/DIV 20mV/DIV 4µs/DIV 40µs/DIV XXX XXX Figure 42. Small Signal Pulse Response, Figure 45. Small Signal Pulse Response, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V G = 1000, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = ±15 V, VREF = 0 V Rev. B | Page 17 of 28 XXX (X) XXX (X) XXX 06286-044 06286-043 06286-042 XXX XXX XXX 06286-047 06286-046 06286-045 AD8224 20mV/DIV 20mV/DIV 4µs/DIV 40µs/DIV XXX XXX Figure 46. Small Signal Pulse Response, Figure 49. Small Signal Pulse Response, G = 1000, RLOAD = 2 kΩ, G = 1, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V 15 10 SETTLED TO 0.001% 5 SETTLED TO 0.01% 20mV/DIV 0 4µs/DIV 02 510 150 XXX OUTPUT VOLTAGE STEP SIZE (V) Figure 47. Small Signal Pulse Response, Figure 50. Settling Time vs. Output Voltage Step Size, (G = 1) ±15 V, VREF = 0 V G = 10, RLOAD = 2 kΩ, CLOAD = 100 pF, VS = 5 V, VREF = 2.5 V 100 SETTLED TO 0.001% 10 SETTLED TO 0.01% 20mV/DIV 1 4µs/DIV 1 10 100 1000 XXX GAIN (V/V) Figure 48. Small Signal Pulse Response, Figure 51. Settling Time vs. Gain for a 10 V Step, VS = ±15 V, VREF = 0 V G = 100, R = 2 kΩ, C = 100 pF, V = 5 V, V = 2.5 V LOAD LOAD S REF Rev. B | Page 18 of 28 XXX XXX XXX 06286-050 06286-049 06286-048 SETTLING TIME (µs) SETTLING TIME (µs) XXX 06286-051 06286-052 06286-053 AD8224 180 100 SOURCE SOURCE V OUT V DIFF_OUT GAIN = 1000 V = 20V p-p SMALLER TO CMR = 20 log OUT OUT 90 V AVOID SLEW CM_OUT 160 RATE LIMIT 80 THERMAL CROSSTALK 140 70 VARIES WITH LOAD LIMITED BY MEASUREMENT 60 SYSTEM 120 GAIN = 1 50 100 40 30 80 20 60 10 40 0 1 10 100 1k 10k 100k 1M 11 10 100 1k0k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 52. Channel Separation vs. Frequency, Figure 54. Differential Output Configuration: R = 2 kΩ, Source Channel at G = 1 Common-Mode Output (CMROUT) vs. Frequency LOAD 60 GAIN = 1000 40 GAIN = 100 20 GAIN = 10 0 GAIN = 1 –20 –40 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 53. Differential Output Configuration: Gain vs. Frequency Rev. B | Page 19 of 28 GAIN (dB) CHANNEL SEPARATION (dB) 06286-069 06286-055 CMR (dB) OUT 06286-056 AD8224 THEORY OF OPERATION +V +V +V +V S S S S NODE A R NODE B G 20kΩ R2 NODE F R1 +V 24.7kΩ S 24.7kΩ –V 20kΩ –V S S OUTPUT A3 20kΩ +V +V S S –V S NODE E +V NODE C NODE D S +IN J1 Q2 J2 –IN Q1 C1 C2 REF 20kΩ A1 A2 V PINCH V –V –V PINCH S S –V S I VB I –V S Figure 55. Simplified Schematic The AD8224 is a JFET input, monolithic instrumentation amplifier The AD8224 has none of these problems; its input bias current based on the classic three op amp topology (see Figure 55). Input is limited to less than 10 μA, and the output does not phase Transistor J1 and Input Transistor J2 are biased at a fixed current so reverse under overdrive fault conditions. that any input signal forces the output voltages of A1 and A2 to The AD8224 has extremely low load induced nonlinearity. All change accordingly. The input signal creates a current through R G amplifiers that comprise the AD8224 have rail-to-rail output that flows in R1 and R2 such that the outputs of A1 and A2 provide capability for enhanced dynamic range. The input of the AD8224 the correct, gained signal. Topologically, J1, A1, and R1 and J2, A2, can amplify signals with wide common-mode voltages even and R2 can be viewed as precision current feedback amplifiers with slightly lower than the negative supply rail. The AD8224 operates a gain bandwidth of 1.5 MHz. The common-mode voltage and over a wide supply voltage range. It can operate from either a amplified differential signal from A1 and A2 are applied to a single +4.5 V to +36 V supply or a dual ±2.25 V to ±18 V. The difference amplifier that rejects the common-mode voltage but transfer function of the AD8224 is amplifies the differential signal. The difference amplifier employs 20 kΩ laser trimmed resistors that result in an in-amp with a gain 49.4 kΩ G= 1+ error of less than 0.04%. New trim techniques were developed to R G ensure that the CMRR exceeds 86 dB (G = 1). Users can easily and accurately set the gain using a single, Using JFET transistors, the AD8224 offers an extremely high standard resistor. Because the input amplifiers employ a current input impedance, extremely low bias currents of 10 pA maximum, feedback architecture, the AD8224 gain bandwidth product low offset current of 0.6 pA maximum, and no input bias increases with gain, resulting in a system that does not experience current noise. In addition, input offset is less than 175 μV as much bandwidth loss as voltage feedback architectures at and drift is less than 5 μV/°C. Ease of use and robustness were higher gains. considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive GAIN SELECTION milliampere input bias current can result, and the output can Placing a resistor across the RG terminals sets the gain of the undergo phase reversal. AD8224. This is calculated by referring to Table 12 or by using the following gain equation Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot 49.4 kΩ R = G output the gained signal. For example, at a gain of 100, driving G− 1 the amplifier with 10 V on ±15 V constitutes overdriving the inputs because the amplifier cannot output 100 V. Rev. B | Page 20 of 28 06286-057 AD8224 LAYOUT Table 12. Gains Achieved Using 1% Resistors The AD8224 is a high precision device. To ensure optimum 1% Standard Table Value of R (Ω) Calculated Gain G performance at the PCB level, care must be taken in the design 49.9 k 1.990 of the board layout. The AD8224 pinout is arranged in 12.4 k 4.984 a logical manner to aid in this task. 5.49 k 9.998 2.61 k 19.93 Package Considerations 1.00 k 50.40 The AD8224 is available in two version s of the 16-lead, 4 mm × 499 100.0 4 mm LFCSP package: with or without an exposed paddle. Blindly 249 199.4 copying the footprint from another 4 mm × 4 mm LFCSP part 100 495.0 is not recommended because it may not have the same thermal 49.9 991.0 pad size and leads. Refer to the Outline Dimensions section to The AD8224 defaults to G = 1 when no gain resistor is used. verify that the PCB symbol has the correct dimensions. The tolerance and gain drift of the RG resistor should be added Hidden Paddle Package to the AD8224 specifications to determine the total gain accuracy of the system. When the gain resistor is not used, The AD8224 is available in an LFCSP package with a hidden gain error and gain drift are kept to a minimum. paddle. It is the preferred package for the AD8224. Unlike chip scale packages where the pad limits routing capability, REFERENCE TERMINAL this package allows routes and vias directly underneath the The output voltage of the AD8224 is developed with respect to chip, so that the full space savings of the small LFCSP can be the potential on the reference terminal. This is useful when the realized. Although the package has no metal in the center of output signal needs to be offset to a precise midsupply level. For the part, the manufacturing process does leave a very small example, a voltage source can be tied to the REF1 pin or the section of exposed metal at each of the package corners, shown REF2 pin to level-shift the output so that the AD8224 can drive in Figure 57 as well as Figure 68 in the Outline Dimensions a single-supply ADC. Pin REFx is protected with ESD diodes section. This metal is connected to +V through the part. S and should not exceed either +VS or −VS by more than 0.5 V. Because of a possibility of a short, vias should not be placed underneath these exposed metal tabs. For best performance, source impedance to the REF terminal should be kept below 1 Ω. As shown in Figure 55, the reference HIDDEN terminal, REF, is at one end of a 20 kΩ resistor. Additional PADDLE impedance at the REF terminal adds to this 20 kΩ resistor and results in amplification of the signal connected to the positive EXPOSED LEAD input. The amplification from the additional RREF can be FRAME TABS BOTTOM VIEW computed by NOTES 1. EXPOSED LEAD FRAME TABS AT THE FOUR CORNERS 2(20 kΩ+R ) REF OF THE PACKAGE ARE INTERNALLY CONNECTED TO +V . REFER TO THE OUTLINE DIMENSIONS PAGE, FOR S 40 kΩ+R REF FURTHER INFORMATION ON PACKAGE AVAILABILITY. Figure 57. Hidden Paddle Package: Bottom View Only the positive signal path is amplified; the negative path is Exposed Paddle Package unaffected. This uneven amplification degrades the CMRR of the amplifier. The AD8224 4 mm × 4 mm LFCSP is also available with an INCORRECT CORRECT CORRECT exposed thermal paddle package version. This pad is connected internally to +V . The pad can either be left unconnected or S connected to the positive supply rail. Space between the leads and thermal pad should be kept as wide as possible for the best AD8224 AD8224 AD8224 V V bias current performance. To maintain the AD8224 ultralow REF REF V REF bias current performance, the thermal pad area can be reduced + + to extend the gap between the leads and the pad. OP2177 AD8224 To preserve maximum pin compatibility with other dual – – instrumentation amplifiers, such as the AD8222, leave the pad unconnected. This can be done by not soldering the paddle at Figure 56. Driving the Reference Pin all or by soldering the part to a landing that is a not connected to any other net. For high vibration applications, a landing is recommended. Rev. B | Page 21 of 28 06286-058 06286-101 AD8224 Because the AD8224 dissipates little power, heat dissipation is rarely an issue. If improved heat dissipation is desired (for example, when driving heavy loads), connect the exposed pad to the 0.1µF positive supply rail. For the best heat dissipation performance, the positive supply rail should be a plane in the board. See the Thermal Resistance section for more information. Common-Mode Rejection over Frequency 16 15 14 13 The AD8224 has a higher CMRR over frequency than typical AD8224 in-amps, which gives it greater immunity to disturbances, such 1 12 as line noise and its associated harmonics. A well-implemented 2 11 layout is required to maintain this high performance. Input R R G G source impedances should be matched closely. Source resistance 3 10 should be placed close to the inputs so that it interacts with as 4 9 little parasitic capacitance as possible. 567 8 Parasitics at the R pins can also affect CMRR over frequency. Gx The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance. 0.1µF Reference Errors introduced at the reference terminal feed directly to the output. Take care to tie the REFx pins to the appropriate local ground. Figure 58. Example Layout Power Supplies SOLDER WASH A stable dc voltage should be used to power the instrumentation The solder process can leave flux and other contaminants on amplifier. Noise on the supply pins can adversely affect the board. When these contaminants are between the AD8224 performance. leads and thermal pad, they can create leakage paths that are The AD8224 has two positive supply pins (Pin 5 and Pin 16) larger than the AD8224 bias currents. A thorough washing and two negative supply pins (Pin 8 and Pin 13). While the part process removes these contaminants and restores the device’s functions with only one pin from each supply pair connected, excellent bias current performance. both pins should be connected for specified performance and INPUT BIAS CURRENT RETURN PATH optimum reliability. The input bias current of the AD8224 must have a return path The AD8224 should be decoupled with 0.1 μF bypass capacitors, to common. When the source, such as a transformer, cannot one for each supply. Place the positive supply decoupling provide a return current path, one should be created, as shown capacitor near Pin 16, and the negative supply decoupling in Figure 59. capacitor near Pin 8. Each supply should also be decoupled with a 10 μF tantalum capacitor. The tantalum capacitor can be INPUT PROTECTION placed further away from the AD8224 and can generally be All terminals of the AD8224 are protected against ESD. ESD shared by other precision integrated circuits. Figure 58 shows an protection is guaranteed to 4 kV (human body model). In example layout. addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +Vs. In either scenario, the AD8224 safely handles a continuous 6 mA current at room temperature. Rev. B | Page 22 of 28 06286-059 AD8224 For applications where the AD8224 encounters extreme The relationship between external, matched series resistors and the overload voltages, as in cardiac defibrillators, external series internal gate capacitance is expressed as resistors and low leakage diode clamps, such as BAV199Ls, 1 FilterFreq = FJH1100s, or SP720s, should be used. DIFF 2πRC G INCORRECT CORRECT 1 +V +V FilterFreq = S S CM 2πRC G To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass RC network can be placed at AD8224 AD8224 the input of the instrumentation amplifier (see Figure 61). The REF REF filter limits the input signal bandwidth according to the following relationship: –V –V S S 1 TRANSFORMER TRANSFORMER FilterFreq = DIFF 2πR(2 CD+ CC+ C ) G +V +V S S 1 FilterFreq = CM C C 2πR(CC+ C ) G R 1 f = HIGH-PASS Mismatched C capacitors result in mismatched low-pass filters. AD8224 2πRC AD8224 C C C REF REF The imbalance causes the AD8224 to treat what would have been a common-mode signal as a differential signal. To reduce R the effect of mismatched external C capacitors, select a value of C –V –V S S CD greater than 10 times CC. This sets the differential filter CAPACITIVELY COUPLED CAPACITIVELY COUPLED frequency lower than the common-mode frequency. Figure 59. Creating an I Path BIAS +15V RF INTERFERENCE + 0.1µF 10µF RF rectification is often a problem in applications where there are C 1nF large RF signals. The problem appears as a small dc offset voltage. C R The AD8224 by its nature has a 5 pF gate capacitance (CG) at its +IN 4.02kΩ inputs. Matched series resistors form a natural low-pass filter that V OUT C 10nF AD8224 reduces rectification at high frequency (see Figure 60). D R REF +15V –IN 4.02kΩ C 1nF C + 0.1µF 10µF 0.1µF 10µF + –15V Figure 61. RFI Suppression +IN R COMMON-MODE INPUT VOLTAGE RANGE C G V OUT AD8224 The 3-op amp architecture of the AD8224 applies gain and then –V S removes the common-mode voltage. Therefore, internal nodes R C G REF –V in the AD8224 experience a combination of both the gained S –IN signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 24 through Figure 27 show the 0.1µF 10µF + allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. –15V Figure 60. RFI Filtering Without External Capacitors Rev. B | Page 23 of 28 06286-061 06286-060 06286-062 AD8224 APPLICATIONS INFORMATION DRIVING AN ADC +IN + An instrumentation amplifier is often used in front of an ADC R AD8224 +OUT G to provide CMRR and additional conditioning such as a voltage 20kΩ –IN – level shift and gain (see Figure 62). In this example, a 2.7 nF 33pF capacitor and a 500 Ω resistor create an antialiasing filter for the AD8224 AD7685. The 2.7 nF capacitor also serves to store and deliver +IN2 the necessary charge to the switched capacitor input of the ADC. The 500 Ω series resistor reduces the burden REF2 of the 2.7 nF load from the amplifier. However, large source –OUT impedance in front of the ADC can degrade the total harmonic Figure 63. Differential Circuit Schematic distortion (THD). Setting the Common-Mode Voltage For applications where THD performance is critical, the series The output common-mode voltage is set by the average of +IN2 resistor needs to be small. At worst, a small series resistor can and REF2. The transfer function is load the AD8224, potentially causing the output to overshoot VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2 or ring. In such cases, a buffer amplifier, such as the AD8615 should be used after the AD8224 to drive the ADC. +IN2 and REF2 have different properties that allow the +5V reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the positive + 10µF 0.1µF ADR435 supply rail. REF2 must be driven with a low impedance but +5V 4.7µF can go 300 mV beyond the supply rails. +IN 500Ω A common application sets the common-mode output voltage ±50mV 1.07kΩ AD8224 AD7685 to the midscale of a differential ADC. In this case, the ADC REF 2.7nF –IN reference voltage is sent to the +IN2 terminal, and ground is +2.5V connected to the REF2 terminal. This produces a common- mode output voltage of half the ADC reference voltage. Figure 62. Driving an ADC in a Low Frequency Application 2-Channel Differential Output Using a Dual Op Amp Another differential output topology is shown in Figure 64. DIFFERENTIAL OUTPUT Instead of a second in-amp, ½ of a dual OP2177 op amp creates The differential configuration of the AD8224 has the same the inverted output. Because the OP2177 comes in an MSOP, excellent dc precision specifications as the single-ended output this configuration allows the creation of a dual-channel, configuration and is recommended for applications in the precision differential output in-amp with little board area. frequency range of dc to 1 MHz. Errors from the op amp are common to both outputs and are, The circuit configuration, outlined in Table 4 and Table 7, refers thus, common mode. Errors from mismatched resistors also to the configuration shown in Figure 63 only. The circuit includes create a common-mode dc offset. Because these errors are an RC filter that maintains the stability of the loop. common mode, they are likely to be rejected by the next device in the signal chain. The transfer function for the differential output is V = V − V = (V − V ) × G DIFF_OUT +OUT −OUT +IN −IN +IN where: AD8224 +OUT –IN 49.4 kΩ G= 1+ REF 4.99kΩ V REF RG + – 4.99kΩ OP2177 –OUT Figure 64. Differential Output Using Op Amp Rev. B | Page 24 of 28 06286-063 06286-064 06286-065 + – AD8224 +12V + 10µF 0.1µF +5V 100pF 0.1µF NPO 1kΩ 5% +IN 806Ω +OUT VDD IN+ AD8224 806Ω AD7688 1000pF (DIFF OUT) IN– 1kΩ –OUT GND REF 2.7nF 2.7nF –IN REF2 +IN2 100pF 10µF NPO X5R 5% +12V +5V REF 0.1µF 10µF 0.1µF + V IN V +5V REF OUT –12V 0.1µF ADR435 GND Figure 65. Driving a Differential ADC However, other converters have less robust inputs and may need DRIVING A DIFFERENTIAL INPUT ADC the added protection. The AD8224 can be configured in differential output mode Reference to drive a differential ADC. Figure 65 illustrates several of the concepts. The ADR435 supplies a reference voltage to both the ADC and the AD8224. Because REF2 on the AD8224 is grounded, the First Antialiasing Filter common-mode output voltage is precisely half the reference The 1 kΩ resistor, 1000 pF capacitor, and 100 pF capacitors in voltage, exactly where it needs to be for the ADC. front of the in-amp form a 76 kHz filter. This is the first of two antialiasing filters in the circuit and helps to reduce the noise of DRIVING CABLING the system. The 100 pF capacitors protect against common- All cables have a certain capacitance per unit length, which mode RFI signals. Note that they are 5% COG/NPO types. varies widely with cable type. The capacitive load from the cable These capacitors match well over time and temperature, may cause peaking in the AD8224 output response. To reduce which keeps the CMRR of the system high over frequency. peaking, use a resistor between the AD8224 and the cable. Because cable capacitance and desired output response vary Second Antialiasing Filter widely, this resistor is best determined empirically. A good An 806 Ω resistor and a 2.7 nF capacitor are located between starting point is 50 Ω. each AD8224 output and ADC input. These components create a 73 kHz low-pass filter for another stage of antialiasing The AD8224 operates at a low enough frequency that protection. transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of These four elements also isolate the ADC from loading the the cable. AD8224. The 806 Ω resistor shields the AD8224 from the switched capacitor input of the ADC, which looks like a time- varying load. The 2.7 nF capacitor provides a charge to the AD8224 switched capacitor front end of the ADC. If the application (DIFF OUT) requires a lower frequency antialiasing filter, increase the value of the capacitor rather than the resistor. The 806 Ω resistors can also protect an ADC from overvoltages. Because the AD8224 runs on wider supply voltages than a AD8224 typical ADC, there is a possibility of overdriving the ADC. This (SINGLE OUT) is not an issue with a PulSAR® converter, such as the AD7688. Its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8224. Figure 66. Driving a Cable Rev. B | Page 25 of 28 06286-066 06286-067 AD8224 OUTLINE DIMENSIONS 0.50 0.40 0.30 4.00 0.60 MAX BSC SQ 1 12 13 16 PIN 1 2.65 3.75 EXPOSED INDICATOR 2.50 SQ BSC SQ PAD 2.35 4 8 5 0.65 9 BSC 0.25 MIN TOP VIEW 1.95 BCS BOTTOM VIEW 12° MAX 0.80 MAX 0.65 TYP 1.00 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 FUNCTION DESCRIPTIONS 0.02 NOM SEATING SECTION OF THIS DATA SHEET. 0.30 COPLANARITY PLANE 0.20 REF 0.08 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. Figure 67. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-13) Dimensions are shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX 13 16 12 1 0.65 PIN 1 3.75 BSC 1.95 REF INDICATOR BCS SQ SQ 9 4 8 5 0.75 TOP VIEW BOTTOM VIEW 0.60 0.50 0.80 MAX 12° MAX 1.00 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY 0.35 SEATING 0.08 PLANE 0.30 0.20 REF 0.25 COMPLIANT TO JEDEC STANDARDS MO-263-VBBC Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad, with Hidden Paddle CP-16-19 Dimensions shown in millimeters Rev. B | Page 26 of 28 PIN 1 INDICATOR 062309-B 031006-A AD8224 ORDERING GUIDE 1 Model Temperature Range Product Description Package Option AD8224ACPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13 AD8224ACPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13 AD8224ACPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13 AD8224BCPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13 AD8224BCPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13 AD8224BCPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-13 AD8224HACPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19 AD8224HACPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19 AD8224HACPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19 AD8224HBCPZ-R7 −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19 AD8224HBCPZ-RL −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19 AD8224HBCPZ-WP −40°C to +85°C 16-Lead LFCSP_VQ CP-16-19 AD8224-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 27 of 28 AD8224 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06286-0-5/10(B) Rev. B | Page 28 of 28