ANALOG DEVICES AD8221

Precision Instrumentation Amplifier AD8221 FEATURES CONNECTION DIAGRAM Easy to use 1 8 +V –IN S Available in space-saving MSOP R 2 7 V OUT G Gain set with 1 external resistor (gain range 1 to 1000) 3 6 R REF G Wide power supply range: ±2.3 V to ±18 V 4 5 +IN –V S AD8221 Temperature range for specified performance: TOP VIEW −40°C to +85°C 1 Figure 1. Operational up to 125°C 120 Excellent AC specifications 80 dB minimum CMRR to 10 kHz (G = 1) 110 825 kHz, –3 dB bandwidth (G = 1) AD8221 100 2 V/µs slew rate Low noise 90 8 nV/√Hz, @ 1 kHz, maximum input voltage noise COMPETITOR 1 80 0.25 µV p-p input noise (0.1 Hz to 10 Hz) High accuracy dc performance (AD8221BR) 70 90 dB minimum CMRR (G = 1) 60 25 µV maximum input offset voltage COMPETITOR 2 0.3 µV/°C maximum input offset drift 50 0.4 nA maximum input bias current 40 10 100 1k 10k 100k APPLICATIONS FREQUENCY (Hz) Weigh scales Figure 2. Typical CMRR vs. Frequency for G = 1 Industrial process controls Bridge amplifiers Low voltage offset, low offset drift, low gain drift, high gain Precision data acquisition systems accuracy, and high CMRR make this part an excellent choice Medical instrumentation in applications that demand the best dc performance possible, Strain gages such as bridge signal conditioning. Transducer interfaces Programmable gain affords the user design flexibility. A single GENERAL DESCRIPTION resistor sets the gain from 1 to 1000. The AD8221 operates on both single and dual supplies and is well suited for applications The AD8221 is a gain programmable, high performance where ±10 V input voltages are encountered. instrumentation amplifier that delivers the industry’s highest CMRR over frequency in its class. The CMRR of instrumentation The AD8221 is available in a low cost 8-lead SOIC and 8-lead amplifiers on the market today falls off at 200 Hz. In contrast, MSOP, both of which offer the industry’s best performance. The the AD8221 maintains a minimum CMRR of 80 dB to 10 kHz MSOP requires half the board space of the SOIC, making it ideal for all grades at G = 1. High CMRR over frequency allows the for multichannel or space-constrained applications. AD8221 to reject wideband interference and line harmonics, Performance is specified over the entire industrial temperature greatly simplifying filter requirements. Possible applications range of −40°C to +85°C for all grades. Furthermore, the AD8221 include precision data acquisition, biomedical analysis, and 1 is operational from −40°C to +125°C . aerospace instrumentation. 1 See Typical Performance Characteristics for expected operation from 85°C to 125°C. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2003–2011 Analog Devices, Inc. All rights reserved. CMRR (dB) 03149-001 03149-002 AD8221 TABLE OF CONTENTS Features .............................................................................................. 1 Layout .......................................................................................... 18 Applications ....................................................................................... 1 Reference Terminal .................................................................... 19 General Description ......................................................................... 1 Power Supply Regulation and Bypassing ................................ 19 Connection Diagram ....................................................................... 1 Input Bias Current Return Path ............................................... 19 Revision History ............................................................................... 2 Input Protection ......................................................................... 19 Specifications ..................................................................................... 3 RF Interference ........................................................................... 20 Absolute Maximum Ratings ............................................................ 8 Precision Strain Gage ................................................................. 20 Thermal Characteristics .............................................................. 8 Conditioning ±10 V Signals for a +5 V Differential Input ADC ............................................................................................. 20 ESD Caution .................................................................................. 8 AC-Coupled Instrumentation Amplifier ................................ 21 Pin Configuration and Function Descriptions ............................. 9 Die Information .............................................................................. 22 Typical Performance Characteristics ........................................... 10 Outline Dimensions ....................................................................... 23 Theory of Operation ...................................................................... 17 Ordering Guide .......................................................................... 24 Gain Selection ............................................................................. 18 REVISION HISTORY 3/11—Rev. B to Rev. C Added Pin Configuration and Function Descriptions Section .. 9 Added Die Information Section ................................................... 22 Updated Outline Dimensions ....................................................... 23 Changes to Ordering Guide .......................................................... 24 9/07—Rev. A to Rev. B Changes to Features .......................................................................... 1 Changes to Table 1 Layout ............................................................... 3 Changes to Table 2 Layout ............................................................... 5 Changes to Figure 15 ...................................................................... 11 Changes to Figures 32 .................................................................... 13 Changes to Figure 33, Figure 34, and Figure 35 ......................... 14 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 11/03—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Specifications Section .................................................. 4 Changes to Theory of Operation Section .................................... 13 Changes to Gain Selection Section............................................... 14 10/03—Revision 0: Initial Version Rev. C | Page 2 of 24 AD8221 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 1. AR Grade BR Grade Parameter Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO CMRR DC to 60 Hz with 1 kΩ VCM = −10 V to +10 V Source Imbalance G = 1 80 90 dB G = 10 100 110 dB G = 100 120 130 dB G = 1000 130 140 dB CMRR at 10 kHz VCM = −10 V to +10 V G = 1 80 80 dB G = 10 90 100 dB G = 100 100 110 dB G = 1000 100 110 dB NOISE RTI noise = 2 2 √ e + (e /G) NI NO Voltage Noise, 1 kHz Input Voltage Noise, eNI VIN+, VIN−, VREF = 0 8 8 nV/√Hz Output Voltage Noise, eNO 75 75 nV/√Hz RTI f = 0.1 Hz to 10 Hz G = 1 2 2 μV p-p G = 10 0.5 0.5 μV p-p G = 100 to 1000 0.25 0.25 μV p-p Current Noise f = 1 kHz 40 40 fA/√Hz f = 0.1 Hz to 10 Hz 6 6 pA p-p 1 VOLTAGE OFFSET Input Offset, VOSI VS = ±5 V to ±15 V 60 25 μV Over Temperature T = −40°C to +85°C 86 45 μV Average TC 0.4 0.3 μV/°C Output Offset, V V = ±5 V to ±15 V 300 200 μV OSO S Over Temperature T = −40°C to +85°C 0.66 0.45 mV Average TC 6 5 μV/°C Offset RTI vs. Supply (PSR) VS = ±2.3 V to ±18 V G = 1 90 110 94 110 dB G = 10 110 120 114 130 dB G = 100 124 130 130 140 dB G = 1000 130 140 140 150 dB INPUT CURRENT Input Bias Current 0.5 1.5 0.2 0.4 nA Over Temperature T = −40°C to +85°C 2.0 1 nA Average TC 1 1 pA/°C Input Offset Current 0.2 0.6 0.1 0.4 nA Over Temperature T = −40°C to +85°C 0.8 0.6 nA Average TC 1 1 pA/°C REFERENCE INPUT R 20 20 kΩ IN I V , V , V = 0 50 60 50 60 μA IN IN+ IN− REF Voltage Range –VS +VS –VS +VS V Gain to Output 1 ± 0.0001 1 ± 0.0001 V/V Rev. C | Page 3 of 24 AD8221 AR Grade BR Grade Parameter Conditions Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range V = ±2.3 V to ±18 V ±2.3 ±18 ±2.3 ±18 V S Quiescent Current 0.9 1 0.9 1 mA Over Temperature T = −40°C to +85°C 1 1.2 1 1.2 mA DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G = 1 825 825 kHz G = 10 562 562 kHz G = 100 100 100 kHz G = 1000 14.7 14.7 kHz Settling Time 0.01% 10 V step G = 1 to 100 10 10 µs G = 1000 80 80 µs Settling Time 0.001% 10 V step G = 1 to 100 13 13 µs G = 1000 110 110 µs Slew Rate G = 1 1.5 2 1.5 2 V/µs G = 5 to 100 2 2.5 2 2.5 V/µs GAIN G = 1 + (49.4 kΩ/R ) G Gain Range 1 1000 1 1000 V/V Gain Error V ± 10 V OUT G = 1 0.03 0.02 % G = 10 0.3 0.15 % G = 100 0.3 0.15 % G = 1000 0.3 0.15 % Gain Nonlinearity V = −10 V to +10 V OUT G = 1 to 10 R = 10 kΩ 3 10 3 10 ppm L G = 100 R = 10 kΩ 5 15 5 15 ppm L G = 1000 R = 10 kΩ 10 40 10 40 ppm L G = 1 to 100 R = 2 kΩ 10 95 10 95 ppm L Gain vs. Temperature G = 1 3 10 2 5 ppm/°C 2 G > 1 –50 –50 ppm/°C INPUT Input Impedance Differential 100||2 100||2 GΩ||pF Common Mode 100||2 100||2 GΩ||pF 3 Input Operating Voltage Range V = ±2.3 V to ±5 V –V + 1.9 +V − 1.1 –V + 1.9 +V − 1.1 V S S S S S Over Temperature T = −40°C to +85°C –V + 2.0 +V − 1.2 –V + 2.0 +V − 1.2 V S S S S Input Operating Voltage Range V = ±5 V to ±18 V –V + 1.9 +V − 1.2 –V + 1.9 +V − 1.2 V S S S S S Over Temperature T =−40°C to +85°C –V + 2.0 +V − 1.2 –V + 2.0 +V − 1.2 V S S S S OUTPUT R = 10 kΩ L Output Swing V = ±2.3 V to ±5 V –V + 1.1 +V − 1.2 –V + 1.1 +V − 1.2 V S S S S S Over Temperature T = −40°C to +85°C –V + 1.4 +Vs − 1.3 –V + 1.4 +V − 1.3 V S S S Output Swing V = ±5 V to ±18 V –V + 1.2 +V − 1.4 –V + 1.2 +V − 1.4 V S S S S S Over Temperature T = –40°C to +85°C –V + 1.6 +V − 1.5 –V + 1.6 +V − 1.5 V S S S S Short-Circuit Current 18 18 mA Rev. C | Page 4 of 24 AD8221 AR Grade BR Grade Parameter Conditions Min Typ Max Min Typ Max Unit TEMPERATURE RANGE Specified Performance –40 +85 –40 +85 °C 4 Operating Range –40 +125 –40 +125 °C 1 Total RTI V = (V ) + (V /G). OS OSI OSO 2 Does not include the effects of external resistor R . G 3 One input grounded. G = 1. 4 See Typical Performance Characteristics for expected operation between 85°C to 125°C. Table 2. ARM Grade Parameter Conditions Min Typ Max Unit COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 kΩ Source Imbalance V = −10 V to +10 V CM G = 1 80 dB G = 10 100 dB G = 100 120 dB G = 1000 130 dB CMRR at 10 kHz V = –10 V to +10 V CM G = 1 80 dB G = 10 90 dB G = 100 100 dB G = 1000 100 dB 2 2 RTI noise = √ NOISE e + (e /G) NI NO Voltage Noise, 1 kHz Input Voltage Noise, e V , V , V = 0 8 nV/√Hz NI IN+ IN− REF Output Voltage Noise, e 75 nV/√Hz NO RTI f = 0.1 Hz to 10 Hz G = 1 2 µV p-p G = 10 0.5 µV p-p G = 100 to 1000 0.25 µV p-p Current Noise f = 1 kHz 40 fA/√Hz f = 0.1 Hz to 10 Hz 6 pA p-p 1 VOLTAGE OFFSET Input Offset, V V = ±5 V to ±15 V 70 µV OSI S Over Temperature T = −40°C to +85°C 135 µV Average TC 0.9 µV/°C Output Offset, V V = ±5 V to ±15 V 600 µV OSO S Over Temperature T = −40°C to +85°C 1.00 mV Average TC 9 µV/°C Offset RTI vs. Supply (PSR) V = ±2.3 V to ±18 V S G = 1 90 100 dB G = 10 100 120 dB G = 100 120 140 dB G = 1000 120 140 dB INPUT CURRENT Input Bias Current 0.5 2 nA Over Temperature T = −40°C to +85°C 3 nA Average TC 3 pA/°C Input Offset Current 0.3 1 nA Over Temperature T = −40°C to +85°C 1.5 nA Average TC 3 pA/°C Rev. C | Page 5 of 24 AD8221 ARM Grade Parameter Conditions Min Typ Max Unit REFERENCE INPUT R 20 kΩ IN I V , V , V = 0 50 60 µA IN IN+ IN− REF Voltage Range −V +V V S S Gain to Output 1 ± 0.0001 V/V POWER SUPPLY Operating Range V = ±2.3 V to ±18 V ±2.3 ±18 V S Quiescent Current 0.9 1 mA Over Temperature T = −40°C to +85°C 1 1.2 mA DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G = 1 825 kHz G = 10 562 kHz G = 100 100 kHz G = 1000 14.7 kHz Settling Time 0.01% 10 V step G = 1 to 100 10 µs G = 1000 80 µs Settling Time 0.001% 10 V step G = 1 to 100 13 µs G = 1000 110 µs Slew Rate G = 1 1.5 2 V/µs G = 5 to 100 2 2.5 V/µs GAIN G = 1 + (49.4 kΩ/R ) G Gain Range 1 1000 V/V Gain Error V ± 10 V OUT G = 1 0.1 % G = 10 0.3 % G = 100 0.3 % G = 1000 0.3 % Gain Nonlinearity V = −10 V to +10 V OUT G = 1 to 10 R = 10 kΩ 5 15 ppm L G = 100 R = 10 kΩ 7 20 ppm L G = 1000 R = 10 kΩ 10 50 ppm L G = 1 to 100 R = 2 kΩ 15 100 ppm L Gain vs. Temperature G = 1 3 10 ppm/°C 2 G > 1 –50 ppm/°C INPUT Input Impedance Differential 100||2 GΩ/pF Common Mode 100||2 GΩ/pF 3 Input Operating Voltage Range V = ±2.3 V to ±5 V –V + 1.9 +V − 1.1 V S S S Over Temperature T = −40°C to +85°C –V + 2.0 +V − 1.2 V S S Input Operating Voltage Range V = ±5 V to ±18 V –V + 1.9 +V − 1.2 V S S S Over Temperature T = −40°C to +85°C –V + 2.0 +V − 1.2 V S S OUTPUT R = 10 kΩ L Output Swing V = ±2.3 V to ±5 V –V + 1.1 +V − 1.2 V S S S Over Temperature T = −40°C to +85°C –V + 1.4 +V − 1.3 V S S Output Swing V = ±5 V to ±18 V –V + 1.2 +V − 1.4 V S S S Over Temperature T = −40°C to +85°C –V + 1.6 +V − 1.5 V S S Short-Circuit Current 18 mA Rev. C | Page 6 of 24 AD8221 ARM Grade Parameter Conditions Min Typ Max Unit TEMPERATURE RANGE Specified Performance −40 +85 °C 4 Operating Range −40 +125 °C 1 Total RTI V = (V ) + (V /G). OS OSI OSO 2 Does not include the effects of external resistor R . G 3 One input grounded. G = 1. 4 See Typical Performance Characteristics for expected operation between 85°C to 125°C. Rev. C | Page 7 of 24 AD8221 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Supply Voltage ±18 V other conditions above those indicated in the operational Internal Power Dissipation 200 mW section of this specification is not implied. Exposure to absolute Output Short-Circuit Current Indefinite maximum rating conditions for extended periods may affect Input Voltage (Common-Mode) ±V S device reliability. Differential Input Voltage ±V S Storage Temperature Range −65°C to +150°C THERMAL CHARACTERISTICS 1 Operating Temperature Range −40°C to +125°C Specification for a device in free air. 1 Temperature range for specified performance is –40°C to +85°C. See Typical Performance Characteristics for expected operation from 85°C to 125°C. Table 4. Package θ Unit JA 8-Lead SOIC, 4-Layer JEDEC Board 121 °C/W 8-Lead MSOP, 4-Layer JEDEC Board 135 °C/W ESD CAUTION Rev. C | Page 8 of 24 AD8221 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8221 1 8 –IN +V S R 2 7 V G OUT R 3 6 REF G 4 5 +IN –V S TOP VIEW (Not to Scale) Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Terminal. 2 R Gain Setting Terminal. Place resistor across the R pins to set the gain. G = 1 + (49.4 kΩ/R ). G G G 3 R Gain Setting Terminal. Place resistor across the R pins to set the gain. G = 1 + (49.4 kΩ/R ). G G G 4 +IN Positive Input Terminal. 5 −V Negative Power Supply Terminal. S 6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output. 7 V Output Terminal. OUT 8 +V Positive Power Supply Terminal. S Rev. C | Page 9 of 24 03149-103 AD8221 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = ±15 V, R = 10 kΩ, unless otherwise noted. S L 1600 3500 1400 3000 1200 2500 1000 2000 800 1500 600 1000 400 500 200 0 0 –150 –100 –50 0 50 100 150 –0.9 –0.6 –0.3 0 0.3 0.6 0.9 CMR (µV/V) INPUT OFFSET CURRENT (nA) Figure 4. Typical Distribution for CMR (G = 1) Figure 7. Typical Distribution of Input Offset Current 2400 15 2100 10 1800 V = ±15V S 5 1500 1200 0 900 V = ±5V S –5 600 –10 300 0 –15 –60 –40 –20 0 20 40 60 –15 –10 –5 0 5 10 15 INPUT OFFSET VOLTAGE (µV) OUTPUT VOLTAGE (V) Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Input Common-Mode Range vs. Output Voltage, G = 1 3000 15 2500 10 V = ±15V S 2000 5 1500 0 V = ±5V S 1000 –5 500 –10 0 –15 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 –15 –10 –5 0 5 10 15 INPUT BIAS CURRENT (nA) OUTPUT VOLTAGE (V) Figure 6. Typical Distribution of Input Bias Current Figure 9. Input Common-Mode Range vs. Output Voltage, G = 100 Rev. C | Page 10 of 24 UNITS UNITS UNITS 03149-005 03149-003 03149-004 INPUT COMMON-MODE VOLTAGE (V) UNITS INPUT COMMON-MODE VOLTAGE (V) 03149-008 03149-006 03149-007 AD8221 0.80 180 0.75 160 GAIN = 1000 0.70 140 GAIN = 100 0.65 V = ±15V 120 S GAIN = 10 GAIN = 1000 0.60 100 GAIN = 1 V = ±5V S 0.55 80 0.50 60 0.45 40 0.40 20 –15 –10 –5 0 5 10 15 0.1 1 10 100 1k 10k 100k 1M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 10. I vs. CMV BIAS Figure 13. Positive PSRR vs. Frequency, RTI (G = 1 to 1000) 2.00 180 1.75 160 GAIN = 1000 1.50 140 GAIN = 100 1.25 120 GAIN = 10 1.00 100 GAIN = 1 0.75 80 0.50 60 0.25 40 0 20 0.01 0.1 1 10 0.1 1 10 100 1k 10k 100k 1M WARM-UP TIME (min) FREQUENCY (Hz) Figure 11. Change in Input Offset Voltage vs. Warm-Up Time Figure 14. Negative PSRR vs. Frequency, RTI (G = 1 to 1000) 5 100k VS = ±15V 4 3 10k 2 BEST AVAILABLE FET 1 INPUT IN-AMP GAIN = 1 INPUT OFFSET CURRENT 0 1k BEST AVAILABLE FET INPUT IN-AMP GAIN = 1000 INPUT BIAS CURRENT –1 –2 AD8221 GAIN = 1 100 –3 –4 AD8221 GAIN = 1000 –5 10 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) SOURCE RESISTANCE (Ω) Figure 12. Input Bias Current and Offset Current vs. Temperature Figure 15. Total Drift vs. Source Resistance Rev. C | Page 11 of 24 CHANGE IN INPUT OFFSET VOLTAGE (µV) INPUT CURRENT (nA) INPUT BIAS CURRENT (nA) 03149-011 03149-009 03149-010 POSITIVE PSRR (dB) TOTAL DRIFT 25°C – 85°C RTI (µV) NEGATIVE PSRR (dB) 03149-012 03149-014 03149-013 AD8221 70 100 GAIN = 1000 60 80 60 50 GAIN = 100 40 40 30 20 GAIN = 10 0 20 10 –20 GAIN = 1 0 –40 –60 –10 –20 –80 –30 –100 100 1k 10k 100k 1M 10M –40 –20 0 20 40 60 80 100 120 140 FREQUENCY (Hz) TEMPERATURE (°C) Figure 16. Gain vs. Frequency Figure 19. CMR vs. Temperature 160 +V –0 S GAIN = 1000 –0.4 –0.8 140 GAIN = 100 –1.2 –1.6 120 –2.0 GAIN = 10 –2.4 100 GAIN = 1 +2.4 +2.0 80 +1.6 +1.2 60 +0.8 +0.4 40 –V +0 S 0.1 1 10 100 1k 10k 100k 1M 0 5 10 15 20 FREQUENCY (Hz) SUPPLY VOLTAGE (±V) Figure 17. CMRR vs. Frequency, RTI Figure 20. Input Voltage Limit vs. Supply Voltage, G = 1 160 +V –0 S GAIN = 1000 –0.4 GAIN = 100 140 –0.8 R = 10kΩ L –1.2 GAIN = 10 120 R = 2kΩ L –1.6 –2.0 GAIN = 1 100 +2.0 80 +1.6 R = 2kΩ L +1.2 60 +0.8 R = 10kΩ L +0.4 40 –V +0 S 0.1 1 10 100 1k 10k 100k 1M 0 5 10 15 20 FREQUENCY (Hz) SUPPLY VOLTAGE (±V) Figure 18. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Figure 21. Output Voltage Swing vs. Supply Voltage, G = 1 Rev. C | Page 12 of 24 GAIN (dB) CMRR (dB) CMRR (dB) 03149-015 03149-017 03149-016 INPUT VOLTAGE LIMIT (V) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES CMR (µV/V) REFERRED TO SUPPLY VOLTAGES 03149-018 03149-019 03149-020 AD8221 30 V = ±15V V = ±15V S S 20 10 0 –10 –8 –6 –4 –2 0 2 4 6 8 10 1 10 100 1k 10k OUTPUT VOLTAGE (V) LOAD RESISTANCE (Ω) Figure 25. Gain Nonlinearity, G = 100, R = 10 kΩ Figure 22. Output Voltage Swing vs. Load Resistance L +V –0 S V = ±15V S –1 SOURCING –2 –3 +3 +2 SINKING +1 –V +0 S –10 –8 –6 –4 –2 0 2 4 6 8 10 0 1 2 3 4 5 6 7 8 9 10 11 12 OUTPUT VOLTAGE (V) OUTPUT CURRENT (mA) Figure 23. Output Voltage Swing vs. Output Current, G = 1 Figure 26. Gain Nonlinearity, G = 1000, R = 10 kΩ L 1k V = ±15V S GAIN = 1 100 GAIN = 10 GAIN = 100 10 GAIN = 1000 GAIN = 1000 BW LIMIT 1 –10 –8 –6 –4 –2 0 2 4 6 8 10 1 10 100 1k 10k 100k OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 27. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000) Figure 24. Gain Nonlinearity, G = 1, R = 10 kΩ L Rev. C | Page 13 of 24 OUTPUT VOLTAGE SWING (V p-p) OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES ERROR (1ppm/DIV) 03149-023 03149-021 03149-022 VOLTAGE NOISE RTI (nV/ Hz) ERROR (100ppm/DIV) ERROR (10ppm/DIV) 03149-024 03149-025 03149-026 AD8221 2µV/DIV 1s/DIV 5pA/DIV 1s/DIV Figure 28. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Figure 31. 0.1 Hz to 10 Hz Current Noise 30 V = ±15V S 25 20 GAIN = 1 GAIN = 10, 100, 1000 15 10 5 0 1k 10k 100k 1M 0.1µV/DIV 1s/DIV FREQUENCY (Hz) Figure 29. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) Figure 32. Large Signal Frequency Response 1k 5V/DIV 100 7.9µs TO 0.01% 0.002%/DIV 8.5µs TO 0.001% 10 1 10 100 1k 10k 20µs/DIV FREQUENCY (Hz) Figure 30. Current Noise Spectral Density vs. Frequency Figure 33. Large Signal Pulse Response and Settling Time (G = 1), 0.002%/DIV Rev. C | Page 14 of 24 CURRENT NOISE (fA/ Hz) 03149-027 03149-029 03149-028 OUTPUT VOLTAGE (V p-p) 03149-031 03149-032 03149-030 AD8221 5V/DIV 4.9µs TO 0.01% 0.002%/DIV 5.6µs TO 0.001% 20mV/DIV 20µs/DIV 4µs/DIV Figure 34. Large Signal Pulse Response and Settling Time (G = 10), Figure 37. Small Signal Response, G = 1, R = 2 kΩ, C = 100 pF L L 0.002%/DIV 5V/DIV 10.3µs TO 0.01% 0.002%/DIV 13.4µs TO 0.001% 20mV/DIV 20µs/DIV 4µs/DIV Figure 35. Large Signal Pulse Response and Settling Time (G = 100), Figure 38. Small Signal Response, G = 10, R = 2 kΩ, C = 100 pF L L 0.002%/DIV 5V/DIV 83µs TO 0.01% 0.002%/DIV 112µs TO 0.001% 20mV/DIV 200µs/DIV 10µs/DIV Figure 36. Large Signal Pulse Response and Settling Time (G = 1000), Figure 39. Small Signal Response, G = 100, R = 2 kΩ, C = 100 pF L L 0.002%/DIV Rev. C | Page 15 of 24 03149-035 03149-034 03149-033 03149-038 03149-037 03149-036 AD8221 1000 100 2 SETTLED TO 0.001% 10 SETTLED TO 0.01% 20mV/DIV 1 1 10 100 1000 100µs/DIV GAIN Figure 42. Settling Time vs. Gain for a 10 V Step Figure 40. Small Signal Response, G = 1000, R = 2 kΩ, C = 100 pF L L 15 10 SETTLED TO 0.001% SETTLED TO 0.01% 5 0 0 5 10 15 20 OUTPUT VOLTAGE STEP SIZE (V) Figure 41. Settling Time vs. Step Size (G = 1) Rev. C | Page 16 of 24 SETTLING TIME (µs) 03149-040 03149-039 SETTLING TIME (µs) 03149-041 AD8221 THEORY OF OPERATION V I I B I COMPENSATION A1 A2 I COMPENSATION B B 10kΩ C1 C2 +V S 10kΩ OUTPUT A3 10kΩ +V S +V S +V R1 24.7kΩ R2 24.7kΩ S –V S 400Ω +V +V 400Ω S S Q2 –IN Q1 +IN REF 10kΩ R G –V –V S S –V S –V –V S S Figure 43. Simplified Schematic The AD8221 is a monolithic instrumentation amplifier based Because the input amplifiers employ a current feedback on the classic 3-op amp topology. Input transistors Q1 and Q2 architecture, the gain-bandwidth product of the AD8221 are biased at a fixed current so that any differential input signal increases with gain, resulting in a system that does not suffer forces the output voltages of A1 and A2 to change accordingly. from the expected bandwidth loss of voltage feedback A signal applied to the input creates a current through R , R1, architectures at higher gains. G and R2, such that the outputs of A1 and A2 deliver the correct To maintain precision even at low input levels, special attention voltage. Topologically, Q1, A1, R1 and Q2, A2, R2 can be was given to the design and layout of the AD8221, resulting in viewed as precision current feedback amplifiers. The amplified an in-amp whose performance satisfies the most demanding differential and common-mode signals are applied to a applications. difference amplifier that rejects the common-mode voltage A unique pinout enables the AD8221 to meet a CMRR but amplifies the differential voltage. The difference amplifier specification of 80 dB at 10 kHz (G = 1) and 110 dB at 1 kHz employs innovations that result in low output offset voltage as (G = 1000). The balanced pinout, shown in Figure 44, reduces well as low output offset voltage drift. Laser-trimmed resistors the parasitics that had, in the past, adversely affected CMRR allow for a highly accurate in-amp with gain error typically less performance. In addition, the new pinout simplifies board than 20 ppm and CMRR that exceeds 90 dB (G = 1). layout because associated traces are grouped together. For Using superbeta input transistors and an I compensation B example, the gain setting resistor pins are adjacent to the scheme, the AD8221 offers extremely high input impedance, inputs, and the reference pin is next to the output. low I , low I drift, low I , low input bias current noise, and B B OS extremely low voltage noise of 8 nV/√Hz. 1 8 +V –IN S 2 R 7 V G OUT The transfer function of the AD8221 is 3 6 R REF G 49.4 kΩ 4 5 +IN –V S G= 1+ AD8221 RG TOP VIEW Users can easily and accurately set the gain using a single Figure 44. Pinout Diagram standard resistor. Rev. C | Page 17 of 24 03149-043 03149-042 AD8221 Grounding GAIN SELECTION The output voltage of the AD8221 is developed with respect to Placing a resistor across the R terminals set the gain of G the potential on the reference terminal. Care should be taken to AD8221, which can be calculated by referring to Table 6 or tie REF to the appropriate local ground. by using the gain equation. In mixed-signal environments, low level analog signals need to 49.4 kΩ RG= be isolated from the noisy digital environment. Many ADCs G−1 have separate analog and digital ground pins. Although it is Table 6. Gains Achieved Using 1% Resistors convenient to tie both grounds to a single ground plane, the 1% Standard Table Value of R (Ω) Calculated Gain current traveling through the ground wires and PC board may G 49.9 k 1.990 cause hundreds of millivolts of error. Therefore, separate analog 12.4 k 4.984 and digital ground returns should be used to minimize the 5.49 k 9.998 current flow from sensitive points to the system ground. An 2.61 k 19.93 example layout is shown in Figure 45 and Figure 46. 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 The AD8221 defaults to G = 1 when no gain resistor is used. Gain accuracy is determined by the absolute tolerance of R . G The TC of the external gain resistor increases the gain drift of the instrumentation amplifier. Gain error and gain drift are kept to a minimum when the gain resistor is not used. LAYOUT Careful board layout maximizes system performance. Traces from the gain setting resistor to the R pins should be kept as G short as possible to minimize parasitic inductance. To ensure Figure 45. Top Layer of the AD8221-EVAL the most accurate output, the trace from the REF pin should either be connected to the local ground of the AD8221, as shown in Figure 47, or connected to a voltage that is referenced to the local ground of the AD8221. Common-Mode Rejection One benefit of the high CMRR over frequency of the AD8221 is that it has greater immunity to disturbances, such as line noise and its associated harmonics, than do typical instrumentation amplifiers. Typically, these amplifiers have CMRR fall-off at 200 Hz; common-mode filters are often used to compensate for this shortcoming. The AD8221 is able to reject CMRR over a greater frequency range, reducing the need for filtering. A well implemented layout helps to maintain the high CMRR over frequency of the AD8221. Input source impedance and capacitance should be closely matched. In addition, source resistance and capacitance should be placed as close to the Figure 46. Bottom Layer of the AD8221-EVAL inputs as permissible. Rev. C | Page 18 of 24 03149-045 03149-044 AD8221 +V S REFERENCE TERMINAL As shown in Figure 43, the reference terminal, REF, is at one end of a 10 kΩ resistor. The output of the instrumentation AD8221 amplifier is referenced to the voltage on the REF terminal; this REF is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to level-shift the output so that the AD8221 can interface –V S with an ADC. The allowable reference voltage range is a function TRANSFORMER of the gain, input, and supply voltage. The REF pin should not exceed either +V or –V by more than 0.5 V. S S +V S For best performance, source impedance to the REF terminal should be kept low, because parasitic resistance can adversely affect CMRR and gain accuracy. AD8221 POWER SUPPLY REGULATION AND BYPASSING REF A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect –V S performance. Bypass capacitors should be used to decouple THERMOCOUPLE the amplifier. +V A 0.1 µF capacitor should be placed close to each supply pin. S As shown in Figure 47, a 10 µF tantalum capacitor can be used C further away from the part. In most cases, it can be shared by 1 R other precision integrated circuits. f = HIGH-PASS 2πRC AD8221 +V S C REF R 0.1µF 10µF –V S +IN CAPACITOR COUPLED V Figure 48. Creating an I Path OUT BIAS AD8221 LOAD INPUT PROTECTION REF –IN All terminals of the AD8221 are protected against ESD, 1 kV Human Body Model. In addition, the input structure allows for dc overload conditions below the negative supply, −V . The 0.1µF 10µF S internal 400 Ω resistors limit current in the event of a negative –V S fault condition. However, in the case of a dc overload voltage Figure 47. Supply Decoupling, REF, and Output Referred to Local Ground above the positive supply, +V , a large current flows directly S through the ESD diode to the positive rail. Therefore, an external INPUT BIAS CURRENT RETURN PATH resistor should be used in series with the input to limit current The input bias current of the AD8221 must have a return path for voltages above +Vs. In either scenario, the AD8221 can to common. When the source, such as a thermocouple, cannot safely handle a continuous 6 mA current, I = V /R for IN EXT provide a return current path, one should be created, as shown positive overvoltage and I = V /(400 Ω + R ) for negative IN EXT in Figure 48. overvoltage. For applications where the AD8221 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors, and low leakage diode clamps, such as BAV199Ls, FJH1100s, or SP720s should be used. Rev. C | Page 19 of 24 03149-046 03149-047 AD8221 C affects the difference signal, and C affects the common- RF INTERFERENCE D C mode signal. Values of R and C should be chosen to minimize C RF rectification is often a problem when amplifiers are used in RFI. Mismatch between the R × C at the positive input and the C applications where there are strong RF signals. The disturbance R × C at the negative input degrades the CMRR of the AD8221. C can appear as a small dc offset voltage. High frequency signals By using a value of C one magnitude larger than C , the effect D C can be filtered with a low-pass RC network placed at the input of the mismatch is reduced, and therefore, performance is of the instrumentation amplifier, as shown in Figure 49. The improved. filter limits the input signal bandwidth according to the following relationship: PRECISION STRAIN GAGE 1 The low offset and high CMRR over frequency of the AD8221 FilterFreqDiff= make it an excellent candidate for bridge measurements. As 2πR(2CD+CC) shown in Figure 50, the bridge can be directly connected to 1 FilterFreqCM= the inputs of the amplifier. 2πRCC +5V where C ≥ 10C . D C 10µF 0.1µF +15V 350Ω 350Ω +IN + 0.1µF 10µF 350Ω 350Ω R AD8221 C 1nF C – –IN R +IN +2.5V 4.02kΩ V R1 OUT C 10nF D AD8221 Figure 50. Precision Strain Gage 499Ω R REF –IN CONDITIONING ±10 V SIGNALS FOR A +5 V 4.02kΩ C 1nF DIFFERENTIAL INPUT ADC C There is a need in many applications to condition ±10 V signals. 0.1µF 10µF However, many of today’s ADCs and digital ICs operate on –15V much lower, single-supply voltages. Furthermore, new ADCs Figure 49. RFI Suppression have differential inputs because they provide better common- mode rejection, noise immunity, and performance at low supply voltages. Interfacing a ±10 V, single-ended instrumentation amplifier to a +5 V, differential ADC can be a challenge. Interfacing the instrumentation amplifier to the ADC requires attenuation and a level shift. A solution is shown in Figure 51. +12V +2.5V +12V R3 1kΩ 0.1µF +5V +5V R6 +12V 10µF 0.1µF 27.4Ω 10nF AD8022 C1 (½) 470pF 0.1µF +IN AV DV DD DD VIN(+) 0.1µF AD8221 OP27 R1 –12V C2 AD7723 10kΩ REF 220µF R5 –IN +12V 499Ω R2 VIN(–) 0.1µF 10kΩ AGND DGND REF1 REF2 0.1µF 10µF 0.1µF R7 27.4Ω –12V AD8022 –12V R4 (½) 1kΩ 220nF 10nF 0.1µF 2.5V +5V +V V IN OUT –12V 10µF 0.1µF 22µF AD780 GND Figure 51. Interfacing to a Differential Input ADC Rev. C | Page 20 of 24 03149-048 03149-050 03149-049 AD8221 In this topology, an OP27 sets the reference voltage of the reduces the referred input noise of the amplifier to 8 nV/√Hz. AD8221. The output signal of the instrumentation amplifier is Thus, smaller signals can be measured because the noise floor is taken across the OUT pin and the REF pin. Two 1 kΩ resistors lower. DC offsets that would have been gained by 100 are and a 499 Ω resistor attenuate the ±10 V signal to +4 V. An eliminated from the output of the AD8221 by the integrator optional capacitor, C1, can serve as an antialiasing filter. An feedback network. AD8022 is used to drive the ADC. At low frequencies, the OP1177 forces the output of the AD8221 to This topology has five benefits. In addition to level-shifting and 0 V. Once a signal exceeds f , the AD8221 outputs the HIGH-PASS attenuation, very little noise is contributed to the system. Noise amplified input signal. from R1 and R2 is common to both of the inputs of the ADC +V S and is easily rejected. R5 adds a third of the dominant noise and 0.1µF therefore makes a negligible contribution to the noise of the system. The attenuator divides the noise from R3 and R4. Likewise, its noise contribution is negligible. The fourth benefit of this +IN 1 f = HIGH-PASS interface circuit is that the acquisition time of the AD8221 is 2πRC R reduced by a factor of 2. With the help of the OP27, the AD8221 AD8221 499Ω R only needs to deliver one-half of the full swing; therefore, signals REF C 15.8kΩ 1µF –IN can settle more quickly. Lastly, the AD8022 settles quickly, which is helpful because the shorter the settling time, the +V S more bits that can be resolved when the ADC acquires data. 0.1µF 0.1µF This configuration provides attenuation, a level-shift, and a –V S convenient interface with a differential input ADC while OP1177 maintaining performance. AC-COUPLED INSTRUMENTATION AMPLIFIER +V –V S S Measuring small signals that are in the noise or offset of the 10µF 10µF 0.1µF amplifier can be a challenge. Figure 52 shows a circuit that can –V S improve the resolution of small ac signals. The large gain Figure 52. AC-Coupled Circuit Rev. C | Page 21 of 24 03149-051 AD8221 DIE INFORMATION Die size: 1575 μm × 2230 μm Die thickness: 381 μm To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 2A and Pad 2B in parallel to one end of RG and Pad 3A and Pad 3B in parallel to the other end of RG. For unity gain applications where R is not required, Pad 2A and Pad 2B must be bonded together as well as the Pad 3A and Pad 3B. G 1 2A 8 2B 3A 7 3B 6 4 5 LOGO Figure 53. Bond Pad Diagram Table 7. Bond Pad Information 1 Pad Coordinates Pad No. Mnemonic X (μm) Y (μm) 1 −IN –379 +951 2A RG –446 +826 2B RG –615 +474 3A R –619 +211 G 3B R –490 –190 G 4 +IN –621 –622 5 −VS +635 –823 6 REF +649 –339 7 V +612 +84 OUT 8 +V +636 +570 S 1 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 53. Rev. C | Page 22 of 24 03149-104 AD8221 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 54. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 5 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. C | Page 23 of 24 10-07-2009-B 012407-A AD8221 ORDERING GUIDE 2 Temperature Range for Operating Package 1 Model Specified Performance Temperature Range Package Description Option Branding AD8221AR –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8 AD8221AR-REEL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8221AR-REEL7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8221ARZ –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8 AD8221ARZ-R7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8221ARZ-RL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8221ARM –40°C to +85°C –40°C to +125°C 8-Lead MSOP RM-8 JLA AD8221ARM-REEL –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 JLA AD8221ARM REEL7 –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 JLA AD8221ARMZ –40°C to +85°C –40°C to +125°C 8-Lead MSOP RM-8 JLA# AD8221ARMZ-R7 –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 JLA# AD8221ARMZ-RL –40°C to +85°C –40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 JLA# AD8221BR –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8 AD8221BR-REEL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8221BR-REEL7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8221BRZ –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N R-8 AD8221BRZ-R7 –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8221BRZ-RL –40°C to +85°C –40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8221AC-P7 –40°C to +85°C –40°C to +125°C Die 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. 2 See Typical Performance Characteristics for expected operation from 85°C to 125°C. ©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03149–0–3/11(C) Rev. C | Page 24 of 24