ANALOG DEVICES AD817

High Speed, Low Power a Wide Supply Range Amplifier AD817 CONNECTION DIAGRAM FEATURES Low Cost 8-Pin Plastic Mini-DIP (N) and High Speed SOIC (R) Packages 50 MHz Unity Gain Bandwidth 350 V/ms Slew Rate 45 ns Settling Time to 0.1% (10 V Step) NULL NULL 1 8 AD817 Flexible Power Supply –IN 7 2 +V S Specified for Single (+5 V) and Dual (65 V to 615 V) Power Supplies +IN 3 6 OUTPUT Low Power: 7.5 mA max Supply Current High Output Drive Capability –V 4 S 5 NC TOP VIEW Drives Unlimited Capacitive Load 50 mA Minimum Output Current NC = NO CONNECT Excellent Video Performance 70 MHz 0.1 dB Bandwidth (Gain = +1) The AD817 is fully specified for operation with a single +5 V 0.04% & 0.088 Differential Gain & Phase Errors power supply and with dual supplies from ±5 V to ±15 V. This @ 3.58 MHz power supply flexibility, coupled with a very low supply current Available in 8-Pin SOIC and 8-Pin Plastic Mini-DIP of 7.5 mA and excellent ac characteristics under all power sup- ply conditions, make the AD817 the ideal choice for many de- manding yet power sensitive applications. PRODUCT DESCRIPTION In applications such as ADC buffers and line drivers the AD817 The AD817 is a low cost, low power, single/dual supply, high simplifies the design task with its unique combination of a speed op amp which is ideally suited for a broad spectrum of 50 mA minimum output current and the ability to drive signal conditioning and data acquisition applications. This unlimited capacitive loads. breakthrough product also features high output current drive capability and the ability to drive an unlimited capacitive load The AD817 is available in 8-pin plastic mini-DIP and SOIC while still maintaining excellent signal integrity. packages. The 50 MHz unity gain bandwidth, 350 V/μs slew rate and set- ORDERING GUIDE tling time of 45 ns (0.1%) make possible the processing of high speed signals common to video and imaging systems. Further- Temperature Package Package more, professional video performance is attained by offering dif- Model Range Description Option ferential gain & phase errors of 0.04% & 0.08° @ 3.58 MHz AD817AN –40°C to +85°C 8-Pin Plastic DIP N-8 and 0.1 dB flatness to 70 MHz (gain = +1). AD817AR –40°C to +85°C 8-Pin Plastic SOIC R-8 1kW 3.3mF 5V 500ns +V S 100 90 0.01mF 100pF HP V 1kWLOAD IN 7 PULSE 2 TEKTRONIX GENERATOR V OUT P6201 FET 6 AD817 50WPROBE C L 3 4 0.01mF 10 1000pF 0% 1000pF 3.3mF LOAD –V S AD817 Driving a Large Capacitive Load REV. B Information furnished by Analog Devices is believed to be accurate and © Analog Devices, Inc., 1995 reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703 (@ T = +258C, unless otherwise noted) AD817–SPECIFICATIONS A AD817A Parameter Conditions V Min Typ Max Units S DYNAMIC PERFORMANCE Unity Gain Bandwidth ±5 V 30 35 MHz ±15 V 45 50 MHz 0, +5 V 25 29 MHz Bandwidth for 0.1 dB Flatness Gain = +1 ±5 V 18 30 MHz ±15 V 40 70 MHz 0, +5 V 10 20 MHz 1 Full Power Bandwidth V = 5 V p-p OUT R = 500 Ω±5 V 15.9 MHz LOAD V = 20 V p-p OUT R = 1 kΩ±15 V 5.6 MHz LOAD Slew Rate R = 1 kΩ±5 V 200 250 V/μs LOAD Gain = 1 ±15 V 300 350 V/μs 0, +5 V 150 200 V/μs Settling Time to 0.1% –2.5 V to +2.5 V ±5 V 45 ns 0 V–10 V Step, A = –1 ±15 V 45 ns V Settling Time to 0.01% –2.5 V to +2.5 V ±5 V 70 ns 0 V–10 V Step, A = –1 ±15 V 70 ns V Total Harmonic Distortion F = 1 MHz ±15 V 63 dB C Differential Gain Error NTSC ±15 V 0.04 0.08 % (R = 150 Ω) Gain = +2 ±5 V 0.05 0.1 % LOAD 0, +5 V 0.11 % Differential Phase Error NTSC ±15 V 0.08 0.1 Degrees (R = 150 Ω) Gain = +2 ±5 V 0.06 0.1 Degrees LOAD 0, +5 V 0.14 Degrees INPUT OFFSET VOLTAGE ±5 V to ±15 V 0.5 2 mV T to T 3mV MIN MAX Offset Drift 10 μV/°C INPUT BIAS CURRENT ±5 V, ±15 V 3.3 6.6 μA T 10 μA MIN T 4.4 μA MAX INPUT OFFSET CURRENT ±5 V, ±15 V 25 200 nA T to T 500 nA MIN MAX Offset Current Drift 0.3 nA/°C OPEN LOOP GAIN V = ±2.5 V ±5 V OUT R = 500 Ω 2 4 V/mV LOAD T to T 1.5 V/mV MIN MAX R = 150 Ω 1.5 3 V/mV LOAD V = ±10 V ±15 V OUT R = 1 kΩ 4 6 V/mV LOAD T to T 2.5 5 V/mV MIN MAX V = ±7.5 V ±15 V OUT R = 150 Ω LOAD (50 mA Output) 2 4 V/mV COMMON-MODE REJECTION V = ±2.5 V ±5 78 100 dB CM V = ±12 V ±15 V 86 120 dB CM ±15 V 80 100 dB POWER SUPPLY REJECTION V = ±5 V to ±15 V 75 86 dB S T to T 72 dB MIN MAX INPUT VOLTAGE NOISE f = 10 kHz ±5 V, ±15 V 15 nV/√Hz INPUT CURRENT NOISE f = 10 kHz ±5 V, ±15 V 1.5 pA/√Hz –2– REV. B AD817 AD817A Parameter Conditions V Min Typ Max Units S INPUT COMMON-MODE ±5 V +3.8 +4.3 V VOLTAGE RANGE –2.7 –3.4 V ±15 V +13 +14.3 V –12 –13.4 V 0, +5 V +3.8 +4.3 V +1.2 +0.9 V OUTPUT VOLTAGE SWING R = 500 Ω±5 V 3.3 3.8 ±V LOAD R = 150 Ω±5 V 3.2 3.6 ±V LOAD R = 1 kΩ±15 V 13.3 13.7 ±V LOAD R = 500 Ω±15 V 12.8 13.4 ±V LOAD R = 500 Ω 0, +5 V +1.5, LOAD +3.5 V Output Current ±15 V 50 mA ±5 V 50 mA 0, +5 V 30 mA Short-Circuit Current ±15 V 90 mA INPUT RESISTANCE 300 kΩ INPUT CAPACITANCE 1.5 pF OUTPUT RESISTANCE Open Loop 8 Ω POWER SUPPLY Operating Range Dual Supply ±2.5 ±18 V Single Supply +5 +36 V Quiescent Current ±5 V 7.0 7.5 mA T to T ±5 V 7.5 mA MIN MAX ±15 V 7.5 mA T to T ±15 V 7.0 7.5 mA MIN MAX NOTES 1 Full power bandwidth = slew rate/2 π V . PEAK Specifications subject to change without notice. 1 ABSOLUTE MAXIMUM RATINGS 2.0 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V 8-PIN MINI-DIP PACKAGE T = +150°C J 2 Internal Power Dissipation Plastic (N) . . . . . . . . . . . . . . . . . . . . . . See Derating Curves 1.5 Small Outline (R) . . . . . . . . . . . . . . . . . See Derating Curves Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6V 1.0 Output Short Circuit Duration . . . . . . . . See Derating Curves Storage Temperature Range N, R . . . . . . . . .–65°C to +125°C 8-PIN SOIC PACKAGE Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C 0.5 Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause 0 permanent damage to the device. This is a stress rating only and functional –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 operation of the device at these or any other conditions above those indicated in the AMBIENT TEMPERATURE – °C operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-pin plastic package: θ = 100°C/watt; JA Maximum Power Dissipation vs. Temperature 8-pin SOIC package: θ = 160°C/watt. JA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD817 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– MAXIMUM POWER DISSIPATION – Watts AD817–Typical Characteristics 20 8.0 – 15 7.5 +V CM +85°C +25°C 10 7.0 -40°C –V CM 5 6.5 0 6.0 02 510 150 02 510 150 SUPPLY VOLTAGE – – Volts SUPPLY VOLTAGE – –Volts Figure 1. Common-Mode Voltage Range vs. Supply Figure 4. Quiescent Supply Current vs. Supply Voltage for Various Temperatures 20 400 350–15 m R = 500WL 300 10 R = 150WL 5 250 200 0 02 510 150 01 5 105 20 SUPPLY VOLTAGE – –Volts SUPPLY VOLTAGE – –Volts Figure 5. Slew Rate vs. Supply Voltage Figure 2. Output Voltage Swing vs. Supply 100 30 25 10 V = –15V S 20 1 15 10 0.1 V = –5V S 5 0.01 0 1k 10k 100k 1M 10M 100M 10 100 1k 10k FREQUENCY – Hz LOAD RESISTANCE – W Figure 3. Output Voltage Swing vs. Load Resistance Figure 6. Closed-Loop Output Impedance vs. Frequency –4– REV. B OUTPUT VOLTAGE SWING – Volts p-p INPUT COMMON-MODE RANGE – Volts OUTPUT VOLTAGE SWING – Volts CLOSED-LOOP OUTPUT IMPEDANCE – Ohms SLEW RATE – V/ s QUIESCENT SUPPLY CURRENT – mA AD817 7 100 +100 PHASE –5V OR –15V SUPPLIES 6 80 +80 mGAIN –15V SUPPLIES 5 60 +60 4 40 +40 GAIN –5V SUPPLIES 3 20 +20 2 0 0 R = 1kW L 1 –20 –60 –40 –20 0 20 40 60 80 100 120 140 1k 10k 100k 1M 10M 100M 1G TEMPERATURE – °C FREQUENCY – Hz Figure 7. Input Bias Current vs. Temperature Figure 10. Open-Loop Gain and Phase Margin vs. Frequency 130 7 –15V 6 110 SOURCE CURRENT 5 90–5V 4 SINK CURRENT 70 3 50 2 1 30 –60 –40 –20 0 20 40 60 80 100 120 140 100 1k 10k TEMPERATURE – °C LOAD RESISTANCE – Ohms Figure 8. Short Circuit Current vs. Temperature Figure 11. Open Loop Gain vs. Load Resistance 100 100 90 80 80 80 POSITIVE PHASE MARGIN 70 SUPPLY 60 60 60 NEGATIVE 50 SUPPLY GAIN BANDWIDTH 40 40 40 30 20 20 20 10 –60 –40 –20 0 20 40 60 80 100 120 140 100 1k 10k 100k 1M 10M 100M TEMPERATURE – °C FREQUENCY – Hz Figure 9. Unity Gain Bandwidth and Phase Margin Figure 12. Power Supply Rejection vs. Frequency vs. Temperature REV. B –5– PHASE MARGIN – Degrees SHORT CIRCUIT CURRENT – mA INPUT BIAS CURRENT – A UNITY GAIN BANDWIDTH – MHz OPEN-LOOP GAIN – dB PSR – dB OPEN-LOOP GAIN – V/mV PHASE MARGIN – Degrees AD817–Typical Characteristics 120 –40 V = 1V p-p IN GAIN = +2 –50 100 –60 80 –70 2nd HARMONIC –80 3rd HARMONIC 60 –90 40 –100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz Figure 13. Common-Mode Rejection vs. Frequency Figure 16. Harmonic Distortion vs. Frequency 30 50 R = 1kWL 40 20 30 R = 150WL 20 10 10 0 0 100k 1M 10M 100M 31 10 100 1k 10k 100kM 10M FREQUENCY – Hz FREQUENCY – Hz Figure 14. Large Signal Frequency Response Figure 17. Input Voltage Noise Spectral Density 10 380 0.1% 8 6 – 360 4 1% 0.01% m 2 0 340 –2 1% 0.01% –4 320 –6 0.1% –8 –10 300 0 20 40 60 80 100 120 140 160 –60 –40 –20 0 20 40 60 80 100 120 140 SETTLING TIME – ns TEMPERATURE – °C Figure 15. Output Swing and Error vs. Settling Time Figure 18. Slew Rate vs. Temperature –6– REV. B OUTPUT SWING FROM 0 TO V OUTPUT VOLTAGE – Volts p-p CMR – dB SLEW RATE – V/ s HARMONIC DISTORTION – dB INPUT VOLTAGE NOISE – nV/ Hz AD817 0.05 1kW DIFF GAIN 3.3mF +V 0.04 S 0.01mF 0.1 0.03 7 TEKTRONIX TEKTRONIX 2 V HP OUT P6201 FET 7A24 6 AD817 PULSE (LS) 0.08 V 100WIN PROBE PREAMP OR FUNCTION 3 DIFF PHASE 4 0.01mF (SS) GENERATOR 50W R 0.06 L 3.3mF –V S 0.04 –5–10–15 SUPPLY VOLTAGE – Volts Figure 19. Differential Gain and Phase vs. Figure 22. Noninverting Amplifier Connection Supply Voltage 5 5V 50ns 4 0.1dB 1kW V C FLATNESS S C 1kW 100 3 V V–15V 3pF 16MHz IN OUT C 90–5V 4pF C 14MHz 2 +5V 6pF 12MHz 1 V = –15V S 0 –1 V = –5V –2 S 10 0% –3 V = +5V S –4 5V –5 100k 1M 10M 100M FREQUENCY – Hz Figure 20. Closed-Loop Gain vs. Frequency, Figure 23. Noninverting Large Signal Pulse Gain = –1 Response, R = 1 kΩ L 5 200mV 20ns 0.1dB 4 1kW V FLATNESS S 100–15V 70MHz 3 V OUT–5V 26MHz 90 V IN 150W2 +5V 17MHz 1 V = –15V S 0 –1 V = –5V S –2 10 0% –3 V = +5V S 200mV –4 –5 100k 1M 10M 100M FREQUENCY – Hz Figure 21. Closed-Loop Gain vs. Frequency, Figure 24. Noninverting Small Signal Pulse Gain = +1 Response, R = 1 kΩ L REV. B –7– DIFFERENTIAL PHASE – Degrees GAIN – dB GAIN – dB DIFFERENTIAL GAIN – Percent AD817–Typical Characteristics 5V 5V 50ns 50ns 100 100 90 90 10 10 0% 0% 5V 5V Figure 25. Noninverting Large Signal Pulse Figure 28. Inverting Large Signal Pulse Response, R = 150 Ω Response, R = 1 kΩ L L 200mV 20ns 200mV 50ns 100 100 90 90 10 10 0% 0% 200mV 200mV Figure 26. Noninverting Small Signal Pulse Figure 29. Inverting Small Signal Pulse Response, R Response, R = 150 Ω = 1 kΩ L L 1kW 3.3mF +V S 0.01mF HP R IN PULSE (L ) SIG V 1kWIN 7 OR FUNCTION TEKTRONIX 2 TEKTRONIX V OUT (S ) 7A24 SIG P6201 FET 6 AD817 GENERATOR PROBE PREAMP 50W 3 4 0.01mF R L 3.3mF –V S Figure 27. Inverting Amplifier Connection –8– REV. B AD817 +V DRIVING CAPACITIVE LOADS S The internal compensation of the AD817, together with its high output current drive, permit excellent large signal performance while driving extremely high capacitive loads. 1kW OUTPUT 3.3mF C +V F S –IN 0.01mF R IN HP V 1kWIN 7 PULSE TEKTRONIX TEKTRONIX 2 V OUT GENERATOR 7A24 P6201 FET +IN 6 AD817 PREAMP PROBE 50W 3 0.01mF 4 C L 1000pF –V S 3.3mF NULL 1 NULL 8 –V S Figure 31. Simplified Schematic Figure 30a. Inverting Amplifier Driving a 1000 pF INPUT CONSIDERATIONS Capacitive Load An input protection resistor (R in Figure 22) is required in cir- IN cuits where the input to the AD817 will be subjected to tran- 5V 500ns sient or continuous overload voltages exceeding the +6 V 100 maximum differential limit. This resistor provides protection for 90 100pF the input transistors by limiting their maximum base current. For high performance circuits, it is recommended that a “bal- ancing” resistor be used to reduce the offset errors caused by bias current flowing through the input and feedback resistors. The balancing resistor equals the parallel combination of R IN and R and thus provides a matched impedance at each input F 10 1000pF terminal. The offset voltage error will then be reduced by more 0% than an order of magnitude. 5V GROUNDING & BYPASSING When designing high frequency circuits, some special precau- Figure 30b. Inverting Amplifier Pulse Response While tions are in order. Circuits must be built with short interconnect Driving Capacitive Loads leads. When wiring components, care should be taken to pro- vide a low resistance, low inductance path to ground. Sockets THEORY OF OPERATION should be avoided, since their increased interlead capacitance The AD817 is a low cost, wide band, high performance opera- can degrade circuit bandwidth. tional amplifier which effectively drives heavy capacitive or resis- Feedback resistors should be of low enough value (<1 kΩ) to tive loads. It also provides a constant slew rate, bandwidth and assure that the time constant formed with the inherent stray settling time over its entire specified temperature range. capacitance at the amplifier’s summing junction will not limit The AD817 (Figure 31) consists of a degenerated NPN differ- performance. This parasitic capacitance, along with the parallel ential pair driving matched PNPs in a folded-cascode gain stage. resistance of R /R , form a pole in the loop transmission which F IN The output buffer stage employs emitter followers in a class AB may result in peaking. A small capacitance (1 pF–5 pF) may be amplifier which delivers the necessary current to the load while used in parallel with the feedback resistor to neutralize this effect. maintaining low levels of distortion. Power supply leads should be bypassed to ground as close as The capacitor, C , in the output stage mitigates the effect of F possible to the amplifier pins. Ceramic disc capacitors of 0.1 μF capacitive loads. At low frequencies, and with low capacitive are recommended. loads, the gain from the compensation node to the output is +V very close to unity. In this case, C is bootstrapped and does not S F contribute to the overall compensation capacitance of the device. As the capacitive load is increased, a pole is formed with the 2 7 output impedance of the output stage. This reduces the gain, 6 AD817 and therefore, C is incompletely bootstrapped. Effectively, 8 F 3 1 some fraction of C contributes to the overall compensation F 4 10kW capacitance, reducing the unity gain bandwidth. As the load V ADJUST OS capacitance is further increased, the bandwidth continues to fall, –V S maintaining the stability of the amplifier. Figure 32. Offset Null Configuration REV. B –9– AD817 OFFSET NULLING Measuring the rapid settling time of AD817 (45 ns to 0.1% and The input offset voltage of the AD817 is inherently very low. 70 ns to 0.01%–10 V step) requires applying an input pulse with However, if additional nulling is required, the circuit shown in a very fast edge and an extremely flat top. With the AD817 con- Figure 32 can be used. The null range of the AD817 in this con- figured in a gain of –1, a clamped false summing junction re- figuration is ±15 mV. sponds when the output error is within the sum of two diode voltages (ª1 volt). The signal is then amplified 20 times by a AD817 SETTLING TIME clamped amplifier whose output is connected directly to a sam- Settling time is comprised primarily of two regions. The first is pling oscilloscope. Figures 33 and 34 show the settling time of the slew time in which the amplifier is overdriven, where the the AD817, with a 10 volt step applied. output voltage rate of change is at its maximum. The second is the linear time period required for the amplifier to settle to 0 within a specified percent of the final value. –2 –4 –6 10 –8 8 –10 6 4 0.20 2 0.15 0 0.10 0.05 0.05 0 0 0.05 0.05 0.10 0 50 100 150 200 250 300 350 400 0.15 0.20 Figure 34. Settling Time in ns 0 V to –10 V 0 50 100 150 200 250 300 350 400 Figure 33. Settling Time in ns 0 V to +10 V 2· HP2835 1MW15pF ERROR AMPLIFIER V OUTPUT · 10 ERROR 5 3 100W2·SETTLING AD829 6 HP2835 OUTPUT 0.47mF 4 2 SHORT, DIRECT 7 CONNECTION TO 0.01mF TEKTRONIX TYPE 11402 0.01mF OSCILLOSCOPE PREAMP ERROR INPUT SECTION 0.47mF SIGNAL –V +V OUTPUT S S 100W1.9kW 0 TO –10V NOTE: POWER USE CIRCUIT BOARD EI&S FALSE SUPPLY WITH GROUND PLANE NULL DL1A05GM SUMMING ADJUST MERCURY RELAY NODE 7, 8 1kW100W1kW 500W 2 50WDEVICE 13 TTL LEVEL COAX 5–18pF UNDER SIGNAL TEKTRONIX P6201 CABLE 1, 14 500WTEST GENERATOR FET PROBE TO 2 50Hz TEKTRONIX TYPE OUTPUT 11402 AD817 6 50WOSCILLOSCOPE 10pF 7 PREAMP INPUT 3 SCOPE PROBE SECTION 4 CAPACITANCE 0.01mF 2.2mF DIGITAL GROUND 2.2mF 0.01mF +V S ANALOG GROUND –V S Figure 35. Settling Time Test Circuit REV. B –10– SETTLING TIME TO % OF FINAL VALUE OUTPUT SWING – Volts SETTLING TIME TO % OF FINAL VALUE OUTPUT SWING – Volts AD817 +V A HIGH PERFORMANCE ADC INPUT BUFFER S High performance analog to digital converters (ADCs) require input buffers with correspondingly high bandwidths and very R3 low levels of distortion. Typical requirements include distortion 1kW3.3mF SELECT C1, R1, R2 & R3 levels of –60 dB to –70 dB for a 1 volt p-p signal and band- FOR DESIRED LOW widths of 10 MHz or more. In addition, an ADC buffer may C2 0.01mF FREQUENCY CORNER. 0.1mF need to drive very large capacitive loads. (R2 = R1 + R3) R1 9kW The circuit of Figure 36 is useful for driving high speed convert- 7 C OUT 2 C1 ers such as the differential input of the AD733, 10-bit ADC. 0.1mF 6 V AD817 OUT This circuit may be used with other converters with only minor V 3 R IN L 4 modifications. Using the AD817 provides the user with the op- C 150WL R2 200pF tion of either operating the buffer in differential mode or from a C3 10kW 0.1mF single +5 volt supply. Operating from a +5 volt power supply helps to avoid overdriving the ADC—a common problem with buffers operating at higher supply voltages. Figure 37. Single Supply Amplifier Configuration SINGLE SUPPLY OPERATION Combining R3 with C2 forms a low-pass filter with a corner Another exciting feature of the AD817 is its ability to perform frequency of 1.5 kHz. This is needed to maintain amplifier well in a single supply configuration. The AD817 is ideally PSRR, since the supply is connected to V through the input IN suited for applications that require low power dissipation and divider. The values for R and C were chosen to demonstrate L L high output current and those which need to drive large capaci- the AD817’s exceptional output drive capability. In this con- tive loads, such as high speed buffering and instrumentation. figuration, the output is centered around 2.5 V. In order to eliminate the static dc current associated with this level, C3 was Referring to Figure 37, careful consideration should be given to inserted in series with R . L the proper selection of component values. The choices for this particular circuit are: R1+ R3//R2 combine with C1 to form a low frequency corner of approximately 300 Hz. 1kW +V S 0.1mF 1kW 7 2 V AD817 6 26 INA 50W COAX 3 0.1mF 4 CABLE V IN 500mVp-p MAX –V AD773 S 52.5W10-BIT 18MHz +V ADC S 0.1mF 7 3 AD817 6 27 V INB 1kW 2 4 0.1mF +V +5V S –V S 100mF ADREF43 25V VOLTAGE COMMON 1kWREFERENCE 100mF +2.5V 25V –5V –V S Figure 36. A Differential Input Buffer for High Bandwidth ADCs REV. B –11– AD817 HIGH SPEED DAC BUFFER (10.24 V for a 1 kΩ resistor). Note that since the DAC gener- The wide bandwidth and fast settling time of the AD817 make ates a positive current to ground, the voltage at the amplifier it a very good output buffer for high speed current output D/A output will be negative. A 100 Ω series resistor between the converters like the AD668. As shown in Figure 38, the op amp noninverting amplifier input and ground minimizes the offset establishes a summing node at ground for the DAC output. The effects of op amp input bias currents. output voltage is determined by the amplifier’s feedback resistor +15V 10mF TO ANALOG GROUND PLANE 0.1mF 1 MSB V 24 CC 2 REFCOM 23 1V NOMINAL REFERENCE INPUT 3 REFIN1 22 10kW 4 21 REFIN2 1kW 5 I 20 OUT 100WANALOG AD668 DIGITAL OUTPUT 6 R 19 LOAD INPUTS AD817 ANALOG GROUND PLANE 7 ACOM 18 ANALOG 8 17 LCOM SUPPLY 10mF GROUND 9 16 IBPO 0.1mF –15V 10 15 V EE 11 THCOM 14 1kW100pF 12 +5V LSB VTH 13 Figure 38. High Speed DAC Buffer OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Plastic Mini-DIP 8-Pin SOIC (N-8) (SO-8) 8 5 0.25 8 5 (6.35) 0.31 PIN 1 0.1574 (4.00) (7.87) 0.1497 (3.80) PIN 1 1 4 0.2440 (6.20) 4 1 0.2284 (5.80) 0.30 (7.62) 0.39 (9.91) MAX REF 0.035–0.01 0.1968 (5.00) 0.0196 (0.50) x 45° (0.89–0.25) 0.1890 (4.80) 0.0099 (0.25) 0.165–0.01 (4.19–0.25) 0.0688 (1.75) 0.0098 (0.25) 0.0532 (1.35) 0.0040 (0.10) 0.18–0.03 0.011–0.003 8° 0.125 (4.57–0.76) (0.28–0.08) 0° 0.0500 (1.27) (3.18) 0.0500 0.0192 (0.49) 0.0098 (0.25) (1.27) MIN 0.0160 (0.41) 0.0138 (0.35) 0.0075 (0.19) 15° BSC 0° 0.10 0.018–0.003 0.033 SEATING (2.54) (0.46–0.08) (0.84) PLANE BSC NOM REV. B –12– PRINTED IN U.S.A. C1707b–5–6/95