ANALOG DEVICES AD815

High Output Current a Differential Driver AD815 FUNCTIONAL BLOCK DIAGRAM FEATURES Flexible Configuration Differential Input and Output Driver NC 1 24 NC or Two Single-Ended Drivers NC 2 23 NC Industrial Temperature Range NC 3 22 NC High Output Power NC 4 21 NC Thermally Enhanced SOIC 5 20 AD815 THERMAL 400 mA Minimum Output Drive/Amp, R = 10� THERMAL 6 19 L TOP VIEW HEAT TABS HEAT TABS Low Distortion (Not to Scale) 7 18 +V * +V * S S –66 dB @ 1 MHz THD, R = 200�, V = 40 V p-p 8 17 L OUT 0.05% and 0.45� Differential Gain and Phase, R = 25� +IN1 9 16 L +IN2 (6 Back-Terminated Video Loads) –IN1 10 15 –IN2 High Speed OUT1 11 14 OUT2 120 MHz Bandwidth (–3 dB) –V 12 13 +V S S 900 V/�s Differential Slew Rate NC = NO CONNECT 70 ns Settling Time to 0.1% *HEAT TABS ARE CONNECTED TO THE POSITIVE SUPPLY. Thermal Shutdown APPLICATIONS ADSL, HDSL, and VDSL Line Interface Driver Coil or Transformer Driver combined with the wide bandwidth and high current drive make CRT Convergence and Astigmatism Adjustment the differential driver ideal for communication applications such Video Distribution Amp as subscriber line interfaces for ADSL, HDSL and VDSL. Twisted Pair Cable Driver The AD815 differential slew rate of 900 V/µs and high load drive are suitable for fast dynamic control of coils or transformers, GENERAL DESCRIPTION and the video performance of 0.05% and 0.45° differential gain The AD815 consists of two high speed amplifiers capable of and phase into a load of 25 Ω enable up to 12 back-terminated supplying a minimum of 500 mA. They are typically configured loads to be driven. as a differential driver enabling an output signal of 40 V p-p on The 24-lead SOIC (RB) is capable of driving 26 dBm for full ±15 V supplies. This can be increased further with the use of a rate ADSL with proper heat sinking. coupling transformer with a greater than 1:1 turns ratio. The low harmonic distortion of –66 dB @ 1 MHz into 200 Ω +15V 1/2 100� –40 AD815 R = 15� 1 V = �15V S AMP1 G = +10 –50 V = 40V p-p OUT 499� –60 R V = V = L IN D V = G = +10 OUT 110� 120� 4Vp-p 40Vp-p 40Vp-p –70 499� R = 50� L R = 15� –80 2 (DIFFERENTIAL) AMP2 100� 1:2 1/2 R = 200� L TRANSFORMER –90 AD815 (DIFFERENTIAL) –15V –100 Figure 2. Subscriber Line Differential Driver –110 100 1k 10k 100k 1M 10M FREQUENCY – Hz Figure 1. Total Harmonic Distortion vs. Frequency REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. 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TOTAL HARMONIC DISTORTION – dBc AD815–SPECIFICATIONS (@ T = +25�C, V = �15 V dc, R = 1 k� and R = 100� unless otherwise noted) A S FB LOAD AD815A Model Conditions V Min Typ Max Units S DYNAMIC PERFORMANCE Small Signal Bandwidth (–3 dB) G = +1 ±15 100 120 MHz G = +1 ±590 110 MHz Bandwidth (0.1 dB) G = +2 ±15 40 MHz G = +2 ±510 MHz Differential Slew Rate V = 20 V p-p, G = +2 ±15 800 900 V/µs OUT Settling Time to 0.1% 10 V Step, G = +2 ±15 70 ns NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion f = 1 MHz, R = 200 Ω, V = 40 V p-p ±15 –66 dBc LOAD OUT Input Voltage Noise f = 10 kHz, G = +2 (Single Ended) ±5, ±15 1.85 nV/√Hz Input Current Noise (+I)f = 10 kHz, G = +2 ±5, ±15 1.8 pA/√Hz IN Input Current Noise (–I)f = 10 kHz, G = +2 ±5, ±15 19 pA/√Hz IN Differential Gain Error NTSC, G = +2, R = 25 Ω±15 0.05 % LOAD Differential Phase Error NTSC, G = +2, R = 25 Ω±15 0.45 Degrees LOAD DC PERFORMANCE Input Offset Voltage ±558mV ±15 10 15 mV T – T 30 mV MIN MAX Input Offset Voltage Drift 20 µV/°C Differential Offset Voltage ± 5 0.5 2 mV ±15 0.5 4 mV T – T 5mV MIN MAX Differential Offset Voltage Drift 10 µV/°C –Input Bias Current ±5, ±15 10 90 µA T – T 150 µA MIN MAX +Input Bias Current ±5, ±15 2 5 µA T – T 5 µA MIN MAX Differential Input Bias Current ±5, ±15 10 75 µA T – T 100 µA MIN MAX Open-Loop Transresistance ±5, ±15 1.0 5.0 MΩ T – T 0.5 MΩ MIN MAX INPUT CHARACTERISTICS Differential Input Resistance +Input ±15 7 MΩ –Input 15 Ω Differential Input Capacitance ±15 1.4 pF Input Common-Mode Voltage Range ±15 13.5 ± V ± 5 3.5 ± V Common-Mode Rejection Ratio T – T ±5, ±15 57 65 dB MIN MAX Differential Common-Mode Rejection Ratio T – T ±5, ±15 80 100 dB MIN MAX OUTPUT CHARACTERISTICS Voltage Swing Single Ended, R = 25Ω±15 11.0 11.7 ± V LOAD ± 5 1.1 1.8 ± V Differential, R = 50Ω±15 21 23 ± V LOAD T – T ±15 22.5 24.5 ± V MIN MAX 1 Output Current RB-24 R = 10Ω±15 400 500 mA LOAD Short Circuit Current ±15 1.0 A Output Resistance ±15 13 Ω MATCHING CHARACTERISTICS Crosstalk f = 1 MHz ±15 –65 dB POWER SUPPLY 2 Operating Range T – T ±18 V MIN MAX Quiescent Current ±52330mA ±15 30 40 mA T – T ±540mA MIN MAX ±15 55 mA Power Supply Rejection Ratio T – T ±5, ±15 –55 –66 dB MIN MAX NOTES 1 Output current is limited in the 24-lead SOIC package to the maximum power dissipation. See absolute maximum ratings and derating curves. 2 Observe derating curves for maximum junction temperature. Specifications subject to change without notice. –2– REV. C AD815 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V Total The maximum power that can be safely dissipated by the AD815 2 Internal Power Dissipation is limited by the associated rise in junction temperature. The Small Outline (RB) . . 2.4 Watts (Observe Derating Curves) maximum safe junction temperature for the plastic encapsulated Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V parts is determined by the glass transition temperature of the S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±6 V plastic, about 150°C. Exceeding this limit temporarily may Output Short Circuit Duration cause a shift in parametric performance due to a change in the . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves stresses exerted on the die by the package. Exceeding a junction Can Only Short to Ground temperature of 175°C for an extended period can result in Storage Temperature Range device failure. RB Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C The AD815 has thermal shutdown protection, which guarantees Operating Temperature Range that the maximum junction temperature of the die remains below a AD815A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C safe level, even when the output is shorted to ground. Shorting Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C the output to either power supply will result in device failure. NOTES To ensure proper operation, it is important to observe the 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- derating curves and refer to the section on power considerations. nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational It must also be noted that in high (noninverting) gain configurations section of this specification is not implied. Exposure to absolute maximum rating (with low values of gain resistor), a high level of input overdrive conditions for extended periods may affect device reliability. can result in a large input error current, which may result in a 2 Specification is for device in free air with 0 ft/min air flow: 24-Lead Surface Mount: significant power dissipation in the input stage. This power θ = 52°C/W. JA must be included when computing the junction temperature rise PIN CONFIGURATION due to total internal power. 24-Lead Thermally-Enhanced SOIC (RB-24) 14 T = 150�C J 13 NC 1 24 NC 12 NC 2 23 NC 11 NC 3 22 NC 10 NC 4 21 9 NC 8 5 20 AD815 7 THERMAL THERMAL 6 19 TOP VIEW HEAT TABS HEAT TABS 6 (Not to Scale) 7 18 +V * +V * S S 5 8 17 4 +IN1 9 16 +IN2 3 θ = 52�C/W –IN1 10 15 –IN2 JA 2 (STILL AIR = 0 FT/MIN) AD815ARB-24 OUT1 11 14 OUT2 1 NO HEAT SINK –V 12 0 13 +V S S –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 NC = NO CONNECT AMBIENT TEMPERATURE – �C *HEAT TABS ARE CONNECTED TO THE POSITIVE SUPPLY. Figure 3. Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model Option Temperature Range Package Description Package AD815ARB-24 –40°C to +85°C 24-Lead Thermally Enhanced SOIC RB-24 AD815ARB-24-REEL –40°C to +85°C 24-Lead Thermally Enhanced SOIC RB-24 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD815 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– MAXIMUM POWER DISSIPATION – Watts AD815–Typical Performance Characteristics 20 36 34 V = �15V S 32 15 30 28 10 26 V = �5V S 24 5 22 20 0 18 02 5 10 150 –40 –20 0 20 4060 80 100 SUPPLY VOLTAGE – �Volts JUNCTION TEMPERATURE – �C Figure 4. Input Common-Mode Voltage Range vs. Supply Figure 7. Total Supply Current vs. Temperature Voltage 40 80 33 T = +25�C A 30 30 60 NO LOAD 27 20 R = 50� 40 L (DIFFERENTIAL) 24 R = 25� L (SINGLE-ENDED) 10 20 21 0 18 0 01 2 46 8 10 12 146 02 510 150 SUPPLY VOLTAGE – �Volts SUPPLY VOLTAGE – �Volts Figure 5. Output Voltage Swing vs. Supply Voltage Figure 8. Total Supply Current vs. Supply Voltage 60 30 10 SIDE A, B V = �15V S +I B 0 50 V = �15V, �5V 25 S –10 20 40 –20 V = �5V S –30 SIDE B 30 15 –I B –40 SIDE A 10 20 –50 V = �5V S SIDE B –60 10 SIDE A 5 –I B –70 V = �15V S 0 0 –80 10 100 1k 10k –40 –20 0 20 40 60 80 100 LOAD RESISTANCE – (Differential – �) (Single-Ended – �/2) JUNCTION TEMPERATURE – �C Figure 6. Output Voltage Swing vs. Load Resistance Figure 9. Input Bias Current vs. Temperature –4– REV. C SINGLE-ENDED OUTPUT VOLTAGE – Volts p-p SINGLE-ENDED OUTPUT VOLTAGE – V p-p COMMON-MODE VOLTAGE RANGE – �Volts DIFFERENTIAL OUTPUT VOLTAGE – Volts p-p DIFFERENTIAL OUTPUT VOLTAGE – V p-p INPUT BIAS CURRENT – �A TOTAL SUPPLY CURRENT – mA SUPPLY CURRENT – mA AD815 80 0 T = 25�C A 60 –2 V = S �15V 40 –4 V = V = �5V S S �10V 20 –6 V = S �5V 0 –8 V IN 1/2 f = 0.1Hz AD815 100� V –20 OUT –10 49.9� V = �15V S R = L –40 –12 5� 1k� 1k� –14 –60 0 –40 –20 020 40 60 80 100 –2.0 –1.6 –1.2 –0.8 –0.4 0.4 0.8 1.2 1.6 2.0 JUNCTION TEMPERATURE – �C LOAD CURRENT – Amps Figure 10. Input Offset Voltage vs. Temperature Figure 13. Thermal Nonlinearity vs. Output Current Drive 750 V = �15V S 100 700 SOURCE 10 650 V = �5V S 600 1 V = �15V S SINK 550 0.1 500 0.01 450 –60 –40 –20 0 20 40 60 80 100 120 140 30k 100k 300k 1M 3M 10M 30M 100M 300M JUNCTION TEMPERATURE – �C FREQUENCY – Hz Figure 11. Short Circuit Current vs. Temperature Figure 14. Closed-Loop Output Resistance vs. Frequency 15 T = 25�C A V = �10V 40 T = 25�C S A V = ±15V S 10 R = 25� L V = �5V V = �15V S R = 100� S L 5 30 R = 50� L 0 20 V IN 1/2 f = 0.1Hz AD815 100� –5 R = 25� V L OUT 49.9� 10 R = L –10 25� 1k� 1k� R = 1� L 0 –15 01 24 6 8 10 124 –20 –16 –12 –8 –4 0 4 8 12 16 20 FREQUENCY – MHz V – Volts OUT Figure 12. Gain Nonlinearity vs. Output Voltage Figure 15. Large Signal Frequency Response REV. C –5– SHORT CIRCUIT CURRENT – mA INPUT OFFSET VOLTAGE – mV RTI OFFSET – mV CLOSED-LOOP OUTPUT RESISTANCE – � RTI OFFSET – mV DIFFERENTIAL OUTPUT VOLTAGE – V p-p AD815 100 100 120 TRANSIMPEDANCE 110 INVERTING INPUT 100 100 CURRENT NOISE 90 500 80 0 PHASE 10 10 70 –50 60 –100 NONINVERTING INPUT CURRENT NOISE 50 –150 40 –200 30 –250 INPUT VOLTAGE NOISE 1 1 10 100 1k 10k 100k 100 1k 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz Figure 16. Input Current and Voltage Noise vs. Frequency Figure 19. Open-Loop Transimpedance vs. Frequency 90 –40 V = �15V S G = +10 80 –50 V = �15V V = 40V p-p S OUT 70 –60 SIDE B 60 SIDE A –70 50 562� R = 50� L –80 (DIFFERENTIAL) 562� 40 V V OUT IN R = 200� L 562� –90 (DIFFERENTIAL) 30 1/2 562� AD815 –100 20 10 –110 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY – Hz FREQUENCY – Hz Figure 17. Common-Mode Rejection vs. Frequency Figure 20. Total Harmonic Distortion vs. Frequency 0 10 –10 V = �15V 8 S 1% 0.1% G = +2 –20 6 R = 100� L GAIN = +2 –30 4 V = �15V S –40 2 –PSRR 0 –50 +PSRR –60 –2 –70 –4 –80 –6 1% 0.1% –90 –8 –100 –10 0.01 0.1 110 100 300 020 40 60 70 80 100 FREQUENCY – MHz SETTLING TIME – ns Figure 18. Power Supply Rejection vs. Frequency Figure 21. Output Swing and Error vs. Settling Time –6– REV. C VOLTAGE NOISE – nV/√Hz PSRR – dB COMMON-MODE REJECTION – dB CURRENT NOISE – pA/√Hz TRANSIMPEDANCE – dB TOTAL HARMONIC DISTORTION – dBc OUTPUT SWING FROM ±V TO 0 – Volts PHASE – Degrees AD815 700 1400 5 G = +10 600 1200 4 SIDE B 500 1000 SIDE A G = +2 3 400 800 +T Z SIDE A 300 600 2 –T Z 200 400 SIDE B 1 100 200 0 0 0 02 510 15 205 –40 –20 02040 6080 100 OUTPUT STEP SIZE – V p-p JUNCTION TEMPERATURE – �C Figure 22. Slew Rate vs. Output Step Size Figure 25. Open-Loop Transresistance vs. Temperature –85 15 V = �15V S V = �15V S SIDE B R = 150� L –80 14 +PSRR +V OUT SIDE A | –V | OUT –75 13 +V OUT R = 25� L –70 12 SIDE A | –V | OUT SIDE B –65 11 –PSRR –60 10 –40 –20 02040 6080 100 –40 –20 020 40 60 80 100 JUNCTION TEMPERATURE – �C JUNCTION TEMPERATURE – �C Figure 23. PSRR vs. Temperature Figure 26. Single-Ended Output Swing vs. Temperature –74 27 –73 26 V = �15V –72 S R = 50� L –71 25 –V OUT –70 +V OUT 24 –69 –CMRR –68 23 +CMRR –67 –66 22 –40 –20 0 20 4060 80 100 –40 –20 020 40 6080 100 JUNCTION TEMPERATURE – �C JUNCTION TEMPERATURE – �C Figure 27. Differential Output Swing vs. Temperature Figure 24. CMRR vs. Temperature REV. C –7– SINGLE-ENDED SLEW RATE – V/�s (PER AMPLIFIER) CMRR – dB PSRR – dB DIFFERENTIAL SLEW RATE – V/�s OUTPUT SWING – Volts OUTPUT SWING – Volts OPEN-LOOP TRANSRESISTANCE – M� AD815 6 BACK TERMINATED LOADS (25�) 1 �15V 0.04 0.5 0.03 0.4 0 0.02 0.3 �5V PHASE G = +2 0.1 0.01 �15V –1 R = 1k� 0.2 F 0.00 NTSC 0.1 –0.01 0 –2 0.0 –0.02 –0.1 B A GAIN –0.1 –3 –0.03 –0.2 –0.04 –0.3 –0.2 A –4 123 456 789 10 11 B 2 BACK TERMINATED LOADS (75�) V –0.3 –5 IN 0.010 0.12 100� V OUT 0.005 0.10 PHASE –0.4 –6 0.08 �5V 0.000 GAIN 49.9� –0.005 G = +2 0.06 –0.5 100� –7 R = 1k� 499� 499� F –0.010 0.04 NTSC –0.015 0.02 –8 GAIN –0.6 –0.020 0.00 PHASE –0.025 –0.02 –0.7 –9 –0.030 –0.04 0.1 1 10 100 300 123 456 789 10 11 FREQUENCY – MHz Figure 28. Differential Gain and Differential Phase Figure 31. Bandwidth vs. Frequency, G = +2 (per Amplifier) –10 1 V = �15V S –20 G = +2 0 R = 499� F SIDE A –30 V = �15V, �5V SIDE B S –1 V = 400mVrms IN –40 R = 100� L –2 SIDE B –50 –60 –3 V IN 100� V –70 OUT –4 SIDE A 49.9� –80 100� –5 124� 499� –90 –6 –100 –110 –7 0.03 0.1 110 100 300 0.1 1 10 100 300 FREQUENCY – MHz FREQUENCY – MHz Figure 29. Output-to-Output Crosstalk vs. Frequency Figure 32. –3 dB Bandwidth vs. Frequency, G = +5 2 V = �15V S 1 V = 0 dBm SIDE B IN 0 100 90 SIDE A –1 –2 –3 V IN 100� V OUT –4 49.9� –5 10 100� 562� 0% –6 5V 1�s –7 –9 0.1 1 10 100 300 FREQUENCY – MHz Figure 30. –3 dB Bandwidth vs. Frequency, G = +1 Figure 33. 40 V p-p Differential Sine Wave, R = 50 Ω, L f = 100 kHz –8– REV. C DIFF GAIN – % DIFF GAIN – % CROSSTALK – dB OUTPUT VOLTAGE – dB DIFF PHASE – Degrees DIFF PHASE – Degrees NORMALIZED FLATNESS – dB NORMALIZED OUTPUT VOLTAGE – dB NORMALIZED FREQUENCY RESPONSE – dB AD815 R 562� F 10�F 10�F +15V +15V 0.1�F 0.1�F R S 8 8 1/2 AD815 1/2 AD815 100� 100� 0.1�F 0.1�F V R = 100� V R = 100� L IN L IN 7 7 PULSE PULSE 50� 10�F 50� 10�F GENERATOR GENERATOR –15V –15V T /T = 250ps T /T = 250ps R F R F Figure 34. Test Circuit, Gain = +1 Figure 38. Test Circuit, Gain = 1 + R /R F S SIDE A G = +5 G = +1 R = 698� R = 562� F F SIDE A R = 100� R = 100� L L R = 140� S SIDE B SIDE B 100mV 5V 100ns 20ns Figure 35. 500 mV Step Response, G = +1 Figure 39. 20 V Step Response, G = +5 G = +1 562� R = 562� F SIDE A R = 100� L 10�F +15V SIDE B 0.1�F 562� 8 V IN PULSE 55� 1/2 AD815 GENERATOR 100� 0.1�F R = 100� L 7 T /T = 250ps R F 10�F –15V 1V 20ns Figure 36. 4 V Step Response, G = +1 Figure 40. Test Circuit, Gain = –1 SIDE A SIDE A G = –1 G = +1 R = 562� R = 562� F F R = 100� R = 100� L L SIDE B SIDE B 2V 100mV 20ns 50ns Figure 37. 10 V Step Response, G = +1 Figure 41. 500 mV Step Response, G = –1 REV. C –9– AD815 Choice of Feedback and Gain Resistors G = –1 The fine scale gain flatness will, to some extent, vary with R = 562� F SIDE A feedback resistance. It therefore is recommended that once R = 100� L optimum resistor values have been determined, 1% tolerance values should be used if it is desired to maintain flatness over SIDE B a wide range of production lots. Table I shows optimum values for several useful configurations. These should be used as starting point in any application. Table I. Resistor Values R (�)R (�) F G 1V 20ns G = +1 562 � –1 499 499 Figure 42. 4 V Step Response, G = –1 +2 499 499 +5 499 125 THEORY OF OPERATION +10 1 k 110 The AD815 is a dual current feedback amplifier with high (500 mA) output current capability. Being a current feedback amplifier, the AD815’s open-loop behavior is expressed PRINTED CIRCUIT BOARD LAYOUT as transimpedance, ∆V /∆I , or T . The open-loop O –IN Z CONSIDERATIONS transimpedance behaves just as the open-loop voltage gain As to be expected for a wideband amplifier, PC board parasitics of a voltage feedback amplifier, that is, it has a large dc value can affect the overall closed-loop performance. Of concern are and decreases at roughly 6 dB/octave in frequency. stray capacitances at the output and the inverting input nodes. If a ground plane is to be used on the same side of the board as Since R is proportional to 1/g , the equivalent voltage gain is IN M the signal traces, a space (5 mm min) should be left around the just T × g , where the g in question is the transconductance Z M M signal lines to minimize coupling. of the input stage. Using this amplifier as a follower with gain, Figure 43, basic analysis yields the following result: POWER SUPPLY BYPASSING T S () V Z O Adequate power supply bypassing can be critical when optimizing = G × V T S + G × R + R the performance of a high frequency circuit. Inductance in the () IN Z IN F power supply leads can form resonant circuits that produce where: peaking in the amplifier’s response. In addition, if large current transients must be delivered to the load, then bypass capacitors R F G=+ 1 (typically greater than 1 µF) will be required to provide the best R G settling time and lowest distortion. A parallel combination of R = 1/g ≈ 25 Ω IN M 10.0 µF and 0.1 µF is recommended. Under some low frequency applications, a bypass capacitance of greater than 10 µF may be R F necessary. Due to the large load currents delivered by the R AD815, special consideration must be given to careful bypassing. G The ground returns on both supply bypass capacitors as well as R IN V signal common must be “star” connected as shown in Figure 44. OUT R N +V S V IN +IN +OUT R F Figure 43. Current Feedback Amplifier Operation R G Recognizing that G × R << R for low gains, it can be seen to R IN F F (OPTIONAL) the first order that bandwidth for this amplifier is independent –OUT of gain (G). Considering that additional poles contribute excess phase at –IN high frequencies, there is a minimum feedback resistance below –V which peaking or oscillation may result. This fact is used to S determine the optimum feedback resistance, R . In practice F parasitic capacitance at the inverting input terminal will also add Figure 44. Signal Ground Connected in “Star” phase in the feedback loop, so picking an optimum value for R F Configuration can be difficult. Achieving and maintaining gain flatness of better than 0.1 dB at frequencies above 10 MHz requires careful consideration of several issues. –10– REV. C AD815 DC ERRORS AND NOISE T J θA (JUNCTION TO There are three major noise and offset terms to consider in DIE MOUNT) a current feedback amplifier. For offset errors refer to the equation below. For noise error the terms are root-sum-squared to give a net output error. In the circuit below (Figure 45), they θ (DIE MOUNT B T TO CASE) A are input offset (V ) which appears at the output multiplied by IO the noise gain of the circuit (1 + R /R ), noninverting input F G θ + θ = θ CASE A B JC current (I × R ) also multiplied by the noise gain, and the BN N inverting input current, which when divided between R and R θ F G T θ JC CA J and subsequently multiplied by the noise gain always appear at T P A IN the output as I × R . The input voltage noise of the AD815 is θ BI F JA less than 2 nV/√Hz. At low gains though, the inverting input WHERE: current noise times R is the dominant noise source. Careful F P = DEVICE DISSIPATION IN layout and device matching contribute to better offset and T = AMBIENT TEMPERATURE A T = JUNCTION TEMPERATURE drift specifications for the AD815 compared to many other J θ = THERMAL RESISTANCE – JUNCTION TO CASE JC current feedback amplifiers. The typical performance curves θ = THERMAL RESISTANCE – CASE TO AMBIENT CA in conjunction with the equations below can be used to predict the performance of the AD815 in any application. Figure 46. A Breakdown of Various Package Thermal     R R F F Resistances V = V × 1+ ± I × R × 1+ ± I × R OUT IO   BN N   BI F  R   R  G G Figure 47 gives the relationship between output voltage swing R F into various loads and the power dissipated by the AD815 (P ). IN I This data is given for both sine wave and square wave (worst BI R G case) conditions. It should be noted that these graphs are for I mostly resistive (phase < ±10°) loads. BN V OUT R N R = 50� f = 1kHz L 4 Figure 45. Output Offset Voltage SQUARE WAVE SINE WAVE POWER CONSIDERATIONS 3 R = 100� L The 500 mA drive capability of the AD815 enables it to drive a 50 Ω load at 40 V p-p when it is configured as a differential 2 driver. This implies a power dissipation, P , of nearly 5 watts. IN To ensure reliability, the junction temperature of the AD815 R = 200� L should be maintained at less than 175°C. For this reason, the 1 AD815 will require some form of heat sinking in most appli- cations. The thermal diagram of Figure 46 gives the basic relationship between junction temperature (T ) and various J 10 20 30 40 V – Volts p-p components of θ . OUT JA Figure 47. Total Power Dissipation vs. Differential Output Equation 1 TT=+P θ JJ AIN A Voltage REV. C –11– P – Watts IN AD815 Other Power Considerations a small resistor should be placed in series with each output. There are additional power considerations applicable to the See Figure 50. This circuit can deliver 800 mA into loads of AD815. First, as with many current feedback amplifiers, there is an up to 12.5 Ω. increase in supply current when delivering a large peak-to-peak 499� 499� voltage to a resistive load at high frequencies. This behavior is affected by the load present at the amplifier’s output. Figure 15 +15V summarizes the full power response capabilities of the AD815. 0.1�F These curves apply to the differential driver applications (e.g., 10�F Figure 51 or Figure 55). In Figure 15, maximum continuous 5 8 1� 1/2 6 peak-to-peak output voltage is plotted vs. frequency for various 100� AD815 4 resistive loads. Exceeding this value on a continuous basis can 50� damage the AD815. 499� 499� R L The AD815 is equipped with a thermal shutdown circuit. This circuit ensures that the temperature of the AD815 die remains 10 1� 1/2 below a safe level. In normal operation, the circuit shuts down 9 100� AD815 11 the AD815 at approximately 180°C and allows the circuit to 7 turn back on at approximately 140°C. This built-in hysteresis 0.1�F 10�F means that a sustained thermal overload will cycle between –15V power-on and power-off conditions. The thermal cycling Figure 50. Parallel Operation for High Current Output typically occurs at a rate of 1 ms to several seconds, depending on the power dissipation and the thermal time constants of the Differential Operation package and heat sinking. Figures 48 and 49 illustrate the Various circuit configurations can be used for differential thermal shutdown operation after driving OUT1 to the + rail, operation of the AD815. If a differential drive signal is avail- and OUT2 to the – rail, and then short-circuiting to ground able, the two halves can be used in a classic instrumentation each output of the AD815. The AD815 will not be damaged by configuration to provide a circuit with differential input and momentary operation in this state, but the overload condition output. The circuit in Figure 51 is an illustration of this. With should be removed. the resistors shown, the gain of the circuit is 11. The gain can be changed by changing the value of R . This circuit, however, G provides no common-mode rejection. OUT 1 100 +15V 90 0.1�F 10�F 100� +IN 4 8 OUT 1 1/2 OUT 2 6 AD815 5 10 R F 0% 499� 5V 200�s V R IN G V R OUT L 100� R Figure 48. OUT2 Shorted to Ground, Square Wave Is F 499� 10 OUT1, R = 1 kΩ, R = 222 Ω F G 1/2 OUT 2 9 AD815 100� –IN 11 7 10�F 0.1�F 100 90 –15V OUT 1 Figure 51. Fully Differential Operation Creating Differential Signals OUT 2 If only a single ended signal is available to drive the AD815 and 10 0% a differential output signal is desired, several circuits can be 5V 5ms used to perform the single-ended-to-differential conversion. One circuit to perform this is to use a dual op amp as a predriver that is configured as a noninverter and inverter. The Figure 49. OUT1 Shorted to Ground, Square Wave Is circuit shown in Figure 52 performs this function. It uses an OUT2, R = 1 kΩ, R = 222 Ω F G AD826 dual op amp with the gain of one amplifier set at +1 and the gain of the other at –1. The 1 kΩ resistor across the input Parallel Operation terminals of the follower makes the noise gain (NG = 1) equal To increase the drive current to a load, both of the amplifiers to the inverter’s. The two outputs then differentially drive the within the AD815 can be connected in parallel. Each ampli- inputs to the AD815 with no common-mode signal to first order. fier should be set for the same gain and driven with the same signal. In order to ensure that the two amplifiers share current, –12– REV. C AD815 +15V +15V +15V 0.1�F 0.1�F 10�F 100� 4 8 V IN 4 8 3 8 1/2 6 1/2 1/2 6 1 AD815 AMP 1 1k� AD815 AD826 5 2 5 R F R F1 499� 1k� 402� R G R R G V L R OUT L 100� 100� 1k� 1k� R F R F2 6 499� 10 499� 1/2 10 AD826 7 1/2 1/2 9 9 100� AD815 AMP 2 4 AD815 5 0.1�F 11 7 11 7 10�F 0.1�F –15V –15V –15V Figure 52. Differential Driver with Single-Ended Figure 54. Direct Single-Ended-to-Differential Conversion Differential Converter Amp 1 has its + input driven with the input signal, while the Another means for creating a differential signal from a single- + input of Amp 2 is grounded. Thus the – input of Amp 2 is ended signal is to use a transformer with a center-tapped driven to virtual ground potential by its output. Therefore secondary. The center tap of the transformer is grounded and Amp 1 is configured for a noninverting gain of five, (1 + R /R ), F1 G the two secondary windings are connected to obtain opposite because R is connected to the virtual ground of Amp 2’s – input. G polarity signals to the two inputs of the AD815 amplifiers. The When the + input of Amp 1 is driven with a signal, the same bias currents for the AD815 inputs are provided by the center signal appears at the – input of Amp 1. This signal serves as an tap ground connection through the transformer windings. input to Amp 2 configured for a gain of –5, (–R /R ). Thus the F2 G One advantage of using a transformer is its ability to provide two outputs move in opposite directions with the same gain and isolation between circuit sections and to provide good common- create a balanced differential signal. mode rejection. The disadvantages are that transformers have This circuit can work at various gains with proper resistor no dc response and can sometimes be large, heavy, and expensive. selection. But in general, in order to change the gain of the This circuit is shown in Figure 53. circuit, at least two resistor values will have to be changed. In addition, the noise gain of the two op amps in this configuration +15V will always be different by one, so the bandwidths will not match. 0.1�F A second circuit that has none of the disadvantages mentioned 10�F 100� 4 8 in the above circuit creates a differential output voltage feedback 1/2 6 op amp out of the pair of current feedback op amps in the AD815. AD815 50� 5 This circuit, drawn in Figure 55, can be used as a high power 1k� 50� differential line driver, such as required for ADSL (asymmetrical digital subscriber loop) line driving. R 200� L 1k� Each of the AD815’s op amps is configured as a unity gain follower by the feedback resistors (R ). Each op amp output A 10 1/2 also drives the other as a unity gain inverter via the two R s, B 9 AD815 100� creating a totally symmetrical circuit. 11 7 If the + input to Amp 2 is grounded and a small positive signal 0.1�F 10�F is applied to the + input of Amp 1, the output of Amp 1 will be –15V driven to saturation in the positive direction and the output of Amp 2 driven to saturation in the negative direction. This is Figure 53. Differential Driver with Transformer Input similar to the way a conventional op amp behaves without any Direct Single-Ended-to-Differential Conversion feedback. Two types of circuits can create a differential output signal from a single-ended input without the use of any other components than resistors. The first of these is illustrated in Figure 54. REV. C –13– AD815 ~20pF Twelve Channel Video Distribution Amplifier The high current of the AD815 enables it to drive up to twelve standard 75 Ω reverse terminated video loads. Figure 56 is a R +15V F 499� schematic of such an application. R I V 0.1�F (OPTIONAL) The input video signal is terminated in 75 Ω and applied to the 10�F 499� CC V 4 8 IN 50� noninverting inputs of both amplifiers of the AD815. Each 1/2 6 AMP1 AD815 amplifier is configured for a gain of two to compensate for the 5 divide-by-two feature of each cable termination. Six separate 75 Ω resistors for each amplifier output are used for the cable R A R back termination. In this manner, all cables are relatively B 250 499� 499� (50�) independent of each other and small disturbances on any cable 100� (OPTIONAL) R B R A will not have an effect on the other cables. 499� 499� When driving six video cables in this fashion, the load seen by each amplifier output is resistive and is equal to 150 Ω/6 or 10 50� 1/2 25 Ω. The differential gain is 0.05% and the differential phase is 9 AMP2 AD815 0.45°. 11 7 V CC +15V 10�F 0.1�F –15V 0.1�F10�F 499� Figure 55. Single-Ended-to-Differential Driver 12 � 75� If a resistor (R ) is connected from the output of Amp 2 to the F 499� + input of Amp 1, negative feedback is provided which closes 5 8 the loop. An input resistor (R ) will make the circuit look like a I 6 100� 4 conventional inverting op amp configuration with differential outputs. The inverting input to this dual output op amp becomes 12 � VIDEO OUT Pin 4, the positive input of Amp 1. VIDEO IN AD815 TO 75� 75� CABLES The gain of this circuit from input to either output will be ± R / F 100� 11 R . Or the single-ended-to-differential gain will be 2 × R /R I F I. 9 The differential outputs can be applied to the primary of a 10 7 transformer. If each output can swing ±10 V, the effective swing on the transformer primary is 40 V p-p. The optional capacitor 499� 499� can be added to prevent any dc current in the transformer due 10�F 0.1�F to dc offsets at the output of the AD815. –15V Figure 56. AD815 Video Distribution Amp Driving 12 Video Cables –14– REV. C AD815 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Thermally Enhanced SOIC (RB-24) 0.6141 (15.60) 0.5985 (15.20) 24 13 1 12 PIN 1 0.1043 (2.65) 0.0291 (0.74) x 45° 0.0926 (2.35) 0.0098 (0.25) 0.0500 (1.27) 8° 0.0118 (0.30) 0.0500 0.0201 (0.51) 0° 0.0157 (0.40) SEATING 0.0125 (0.32) (1.27) 0.0040 (0.10) 0.0130 (0.33) PLANE BSC 0.0091 (0.23) REV. C –15– 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) AD815 Revision History Location Page 4/05—Data Sheet changed from REV. B to REV. C. Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Figure numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Deleted VR-15, Y-15, and YS-15 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to Power Considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Deleted Figure 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Deleted Figures 55, 56, 57, and 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 –16– REV. C C00868–0–4/05(C)