ANALOG DEVICES AD8145

+ + High Speed, Triple Differential Receiver with Comparators AD8145 FEATURES FUNCTIONAL BLOCK DIAGRAM High speed: 500 MHz, 2000 V/μs @ G = 1, V = 2 V p-p OUT 0.1 dB flatness out to 75 MHz High CMRR: 69 dB @ 10 MHz 32 31 30 29 28 27 26 25 C High differential input impedance: 1 MΩ GND 1 R 24 GND Wide input common-mode range: ±3.5 V (±5 V supplies) R 2 23 REF_G OUT_B + On-chip, gain setting resistors can be configured for gain of 1 or 2 C – Fast settling: 15 ns to 0.1% @ 2 V p-p GAIN_G 3 22 OUT_G RR Low input referred noise: 13 nV/√Hz 4 21 IN+_G OUT_R Disable feature + – Small packaging: 32-lead, 5 mm × 5 mm LFCSP IN–_G 5 20 V S+ AD8145 AEC-Q10 qualified (AD8145W) 6 + REF_R 19 COMPB_IN+ C – B GAIN_R 7 18 APPLICATIONS COMPB_IN– A RR RGB video receivers – 8 GND 17 GND YPbPr video receivers 9 10111213141516 Keyboard, video, mouse (KVM) Unshielded twisted pair (UTP) receivers Automotive driver assistance (AD8145W) Automotive Infotainment (AD8145W) Figure 1. GENERAL DESCRIPTION The AD8145 is a triple, low cost, differential-to-single-ended The AD8145 can be configured for a differential-to-single-ended receiver specifically designed for receiving red-green-blue (RGB) gain of 1 or 2 by connecting the GAIN_x pin of each channel to video signals over twisted pair cable or differential printed circuit its respective output (G = 1) or connecting it to a reference voltage board (PCB) traces. It can also be used to receive any type of (G = 2), which is normally grounded. analog signal or high speed data transmission. Two auxiliary A REF_x input is provided on each channel that allows designers to comparators with hysteresis are provided that can be used to level shift the output signals. decode video sync signals, which are encoded on the received The AD8145W is the automotive grade version that is qualified common-mode voltages, to receive digital signals or as general- per the AEC-Q100 for use in automotive applications. See the purpose comparators. The AD8145 can be used in conjunction Automotive Products section for more details. with the AD8133 or AD8134 triple differential drivers to provide a complete low cost solution for RGB over Category 5 UTP cable The AD8145 is available in a 5 mm × 5 mm, 32-lead LFCSP and applications, including KVM. is rated to work over the extended industrial temperature range of −40°C to +105°C. The excellent common-mode rejection (69 dB @ 10 MHz) of the AD8145 allows for the use of low cost, unshielded twisted pair cables in noisy environments. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GND GND IN+_R IN–_B + IN–_R IN+_B COMPA_IN+ GAIN_B COMPA_IN– REF_B COMPA_OUT DIS/PD COMPB_OUT V S– GND GND 06307-001 – – AD8145 TABLE OF CONTENTS Features .............................................................................................. 1  Overview ..................................................................................... 15  Applications ....................................................................................... 1  Basic Closed-Loop Gain Configurations ................................ 15  Functional Block Diagram .............................................................. 1  Terminating the Input................................................................ 16  General Description ......................................................................... 1  Input Clamping ........................................................................... 17  Revision History ............................................................................... 2  PCB Layout Considerations ...................................................... 18  Specif ica t ions ..................................................................................... 3  Driving a Capacitive Load ......................................................... 19  Absolute Maximum Ratings ............................................................ 7  Power-Down ............................................................................... 19  Thermal Resistance ...................................................................... 7  Automotive Products ................................................................. 19  Maximum Power Dissipation ..................................................... 7  Comparators ............................................................................... 19  ESD Caution .................................................................................. 7  Sync Pulse Extraction Using Comparators ............................. 20  Pin Configuration and Function Description .............................. 8  Outline Dimensions ....................................................................... 21  Typical Performance Characteristics ............................................. 9  Ordering Guide .......................................................................... 21  Theory of Operation ...................................................................... 14  Applications Information .............................................................. 15  REVISION HISTORY 1/10—Rev. 0 to Rev. A Changes to Features Section, Applications Section, and General Description Section .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Added Automotive Products Section .......................................... 19 Added Exposed Paddle Notation to Outline Dimensions ........ 21 Changes to Ordering Guide .......................................................... 21 10/06—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8145 SPECIFICATIONS TA = 25°C, VS = ±5 V, REF_x = 0 V, RL = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +105°C, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.2 V p-p 530 MHz OUT VOUT = 2 V p-p 500 MHz VOUT = 0.2 V p-p, G = 2 200 MHz VOUT = 2 V p-p, G = 2 200 MHz Bandwidth for 0.1 dB Flatness V = 2 V p-p 75 MHz OUT V = 2 V p-p, G = 2 100 MHz OUT Slew Rate V = 2 V p-p 2100 V/μs OUT VOUT = 2 V p-p, G = 2 2100 V/μs Settling Time VOUT = 2 V p-p, 0.1% 15 ns Output Overdrive Recovery 20 ns NOISE/DISTORTION Second Harmonic VOUT = 2 V p-p, 1 MHz −67 dBc Third Harmonic V = 2 V p-p, 1 MHz −88 dBc OUT Crosstalk V = 2 V p-p, 10 MHz −62 dB OUT Input Voltage Noise (RTI) f ≥ 10 kHz 13 nV/√Hz Differential Gain Error NTSC, 200 IRE, RL ≥ 150 Ω 0.25 % Differential Phase Error NTSC, 200 IRE, RL ≥ 150 Ω 0.1 Degrees INPUT CHARACTERISTICS Common-Mode Rejection DC, VCM = −2 V to +2 V 81 90 dB AD8145W only, TMIN to TMAX 78 dB V = 1 V p-p, f = 10 MHz 69 dB CM V = 1 V p-p, f = 100 MHz 41 dB CM Common-Mode Voltage Range V − V = 0 V ±3.5 V +IN −IN Differential Operating Range ±2.5 V Resistance Differential 1 MΩ Common mode 1.3 MΩ Capacitance Differential 1 pF Common mode 2 pF DC PERFORMANCE Closed-Loop Gain DC, G = 2 1.955 1.985 2.020 V/V AD8145W only, T to T 1.930 2.030 V/V MIN MAX Output Offset Voltage G = 2 −17.5 +7.0 +1.0 mV AD8145W only, TMIN to TMAX −25 +8.0 mV Output Offset Voltage Drift TMIN to TMAX −18 μV/°C Input Bias Current (+IN, −IN) −6 −3.4 −0.9 μA AD8145W only, T to T −7 −0.5 μA MIN MAX Input Bias Current Drift T to T (+IN, −IN) 25 nA/°C MIN MAX Input Offset Current −400 −65 +300 nA AD8145W only, TMIN to TMAX −650 +650 nA OUTPUT PERFORMANCE Voltage Swing −3.64 +3.55 V AD8145W only, TMIN to TMAX −3.45 +3.35 V Output Current 50 mA Short-Circuit Current Short to GND, source/sink +195/−230 mA Rev. A | Page 3 of 24 AD8145 Parameter Conditions Min Typ Max Unit COMPARATOR PERFORMANCE VOH RL = 1 kΩ 3.205 3.310 V AD8145W only, TMIN to TMAX 2.950 V V R = 1 kΩ 0.390 0.420 V OL L AD8145W only, T to T 0.440 V MIN MAX Input Offset Voltage ±2.5 mV Hysteresis Width 18 mV Input Bias Current 1.5 μA Propagation Delay, t 6 ns PLH Propagation Delay, t 6 ns PHL Rise Time 10% to 90% 6 ns Fall Time 10% to 90% 2 ns POWER-DOWN PERFORMANCE Power-Down V V − 1.65 V IH S+ Power-Down VIL VS+ − 2.65 V Power-Down IIH 0.5 μA Power-Down IIL −250 μA Power-Down Assert Time 1 μs POWER SUPPLY Operating Range 4.5 11 V Quiescent Current, Positive Supply 48.5 57.5 mA AD8145W only, T to T 70 mA MIN MAX Disabled 16 19.5 mA AD8145W only, TMIN to TMAX 25 mA Quiescent Current, Negative Supply −52 −43.5 mA AD8145W only, T to T −65 mA MIN MAX Disabled −13.9 −11 mA AD8145W only, T to T −20 mA MIN MAX PSRR, Positive Supply DC −79 −70 dB AD8145W only, TMIN to TMAX −66 dB PSRR, Negative Supply DC −68 −57 dB AD8145W only, T to T −54 dB MIN MAX Rev. A | Page 4 of 24 AD8145 T = 25°C, V = ±2.5 V, REF_x = 0 V, R = 1 kΩ, C = 2 pF, G = 1, T to T = −40°C to +105°C, unless otherwise noted. A S L L MIN MAX Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth V = 0.2 V p-p 450 MHz OUT V = 2 V p-p 425 MHz OUT V = 0.2 V p-p, G = 2, R = 150 Ω 180 MHz OUT L VOUT = 2 V p-p, G = 2, RL = 150 Ω 180 MHz Bandwidth for 0.1 dB Flatness VOUT = 2 V p-p 53 MHz VOUT = 2 V p-p, G = 2, RL = 150 Ω 100 MHz Slew Rate V = 2 V p-p 2000 V/μs OUT V = 2 V p-p, G = 2, R = 150 Ω 2000 V/μs OUT L Settling Time V = 2 V p-p, 0.1% 16 ns OUT Output Overdrive Recovery 10 ns NOISE/DISTORTION Second Harmonic VOUT = 1 V p-p, 1 MHz −71 dBc Third Harmonic VOUT = 1 V p-p, 1 MHz −76 dBc Crosstalk VOUT = 1 V p-p, 10 MHz −62 dB Input Voltage Noise (RTI) f ≥ 10 kHz 13 nV/√Hz INPUT CHARACTERISTICS Common-Mode Rejection DC, VCM = −1 V to +1 V 78 86 dB AD8145W only, T to T 75 dB MIN MAX V = 1 V p-p, f = 10 MHz 72 dB CM V = 1 V p-p, f = 100 MHz 43 dB CM Common-Mode Voltage Range V+IN − V−IN = 0 V ±1.25 V Differential Operating Range ±1.6 V Resistance Differential 1 MΩ Common mode 1.3 MΩ Capacitance Differential 1 pF Common mode 2 pF DC PERFORMANCE Closed-Loop Gain DC, G = 2 1.960 1.985 2.016 V/V AD8145W only, TMIN to TMAX 1.930 2.030 V/V Output Offset Voltage G = 2 −13.5 −4.5 +2 mV AD8145W only, TMIN to TMAX −18 +8 mV Output Offset Voltage Drift T to T −18 μV/°C MIN MAX Input Bias Current (+IN, −IN) −6 −3.5 −0.9 μA AD8145W only, T to T −7 −0.5 μA MIN MAX Input Bias Current Drift TMIN to TMAX (+IN, −IN) 25 nA/°C Input Offset Current −400 −60 +300 nA AD8145W only, TMIN to TMAX −650 +650 nA OUTPUT PERFORMANCE Voltage Swing RL = 150 Ω −1.35 +1.3 V AD8145W only, TMIN to TMAX −1.20 +1.15 V Output Current 25 mA Short-Circuit Current Short to GND, source/sink +100/−100 mA POWER-DOWN PERFORMANCE Power-Down V V − 1.5 V IH S+ Power-Down V V − 2.5 V IL S+ Power-Down IIH 0.25 μA Power-Down IIL 50 μA Power-Down Assert Time 1 μs Rev. A | Page 5 of 24 AD8145 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range 4.5 11 V Quiescent Current, Positive Supply 40 47 mA AD8145W only, T to T 57 mA MIN MAX Disabled 13.5 16 mA AD8145W only, T to T 21 mA MIN MAX Quiescent Current, Negative Supply −43.5 −36 mA AD8145W only, TMIN to TMAX −54 mA Disabled −12.5 −10 mA AD8145W only, T to T −17 mA MIN MAX PSRR, Positive Supply DC −83 −73 dB AD8145W only, TMIN to TMAX −68 dB PSRR, Negative Supply DC −67 −62 dB AD8145W only, TMIN to TMAX −59 dB Rev. A | Page 6 of 24 AD8145 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 3. Parameter Rating The maximum safe power dissipation in the AD8145 package is limited by the associated rise in junction temperature (T ) on Supply Voltage 12 V J the die. At approximately 150°C, which is the glass transition Power Dissipation See Figure 2 Storage Temperature Range −65°C to +125°C temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the Operating Temperature Range −40°C to +105°C package exerts on the die, permanently shifting the parametric Lead Temperature (Soldering, 10 sec) 300°C performance of the AD8145. Exceeding a junction temperature Junction Temperature 150°C of 150°C for an extended period can result in changes in the Stresses above those listed under Absolute Maximum Ratings silicon devices, potentially causing failure. may cause permanent damage to the device. This is a stress The power dissipated in the package (P ) is the sum of the D rating only; functional operation of the device at these or any quiescent power dissipation and the power dissipated in the other conditions above those indicated in the operational package due to the load drive for all outputs. The quiescent section of this specification is not implied. Exposure to absolute power is the voltage between the supply pins (VS) times the maximum rating conditions for extended periods may affect quiescent current (IS). The power dissipated due to the load device reliability. drive depends on the particular application. For each output, the THERMAL RESISTANCE power due to load drive is calculated by multiplying the load θ is specified for the worst-case conditions, that is, θ is current by the associated voltage drop across the device. The JA JA specified for a device soldered in the circuit board with its power dissipated due to all of the loads is equal to the sum of exposed paddle soldered to a pad on the PCB surface, which is the power dissipation due to each individual load. RMS voltages thermally connected to a copper plane. and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. In Table 4. Thermal Resistance addition, more metal directly in contact with the package leads Package Type θJA θJC Unit from metal traces, through-holes, ground, and power planes 5 mm × 5 mm, 32-Lead LFCSP 47 8.5 °C/W reduces the θ . The exposed paddle on the underside of the JA package must be soldered to a pad on the PCB surface, which is 4.5 thermally connected to a copper plane to achieve the specified θ . JA 4.0 Figure 2 shows the maximum safe power dissipation in the 3.5 package vs. the ambient temperature for the 32-lead LFCSP (47°C/W) on a JEDEC standard 4-layer board with the underside 3.0 paddle soldered to a pad, which is thermally connected to a 2.5 PCB plane. 2.0 1.5 ESD CAUTION 1.0 0.5 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board Rev. A | Page 7 of 24 MAXIMUM POWER DISSIPATION (W) 06307-002 AD8145 PIN CONFIGURATION AND FUNCTION DESCRIPTION GND 1 24 GND PIN 1 REF_G 2 23 OUT_B INDICATOR GAIN_G 3 22 OUT_G IN+_G 4 21 OUT_R AD8145 IN–_G 5 20 V TOP VIEW S+ REF_R 6 19 COMPB_IN+ (Not to Scale) GAIN_R 7 18 COMPB_IN– GND 8 17 GND NOTES 1. EXPOSED PAD ON UNDERSIDE OF DEVICE MUST BE CONNECTED TO GROUND. Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 8, 9, 16, 17, 24, 25, 32 GND Signal Ground and Thermal Plane Connection. (See the Absolute Maximum Ratings section.) 2 REF_G Reference Input, Green Channel. 3 GAIN_G Gain Connection, Green Channel. 4 IN+_G Noninverting Input, Green Channel. 5 IN−_G Inverting Input, Green Channel. 6 REF_R Reference Input, Red Channel. 7 GAIN_R Gain Connection, Red Channel. 10 IN+_R Noninverting Input, Red Channel. 11 IN−_R Inverting Input, Red Channel. 12 COMPA_IN+ Positive Input, Comparator A. 13 COMPA_IN− Negative Input, Comparator A. 14 COMPA_OUT Output, Comparator A. 15 COMPB_OUT Output, Comparator B. 18 COMPB_IN− Negative Input, Comparator B. 19 COMPB_IN+ Positive Input, Comparator B. 20 VS+ Positive Power Supply. 21 OUT_R Output, Red Channel. 22 OUT_G Output, Green Channel. 23 OUT_B Output, Blue Channel. 26 VS− Negative Power Supply. 27 DIS/PD Disable/Power Down. 28 REF_B Reference Input, Blue Channel. 29 GAIN_B Gain Connection, Blue Channel. 30 IN+_B Noninverting Input, Blue Channel. 31 IN−_B Inverting Input, Blue Channel. Exposed Underside Pad GND Signal Ground and Thermal Plane Connection. Rev. A | Page 8 of 24 06307-003 32 GND GND 9 IN+_R 10 31 IN–_B IN–_R 11 30 IN+_B COMPA_IN+ 12 29 GAIN_B COMPA_IN– 13 28 REF_B COMPA_OUT 14 27 DIS/PD COMPB_OUT 15 26 V S– GND 16 25 GND AD8145 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, G = 1, RL = 150 Ω, CL = 2 pF, REF_x = midsupply, VS = ±5 V, TA = 25°C. Refer to the circuit in Figure 35. 3 3 2 2 +5V +5V 1 1 0 0 ±5V ±5V –1 –1 –2 –2 –3 –3 –4 –4 –5 –5 –6 –6 V = 2V p-p V = 0.2V p-p OUT OUT –7 –7 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response at Various Power Supplies, G = 1 Figure 7. Large Signal Frequency Response at Various Power Supplies, G = 1 9 9 8 8 7 7 6 6 5 5 4 4 3 3 +5V ±5V +5V ±5V 2 2 1 1 0 0 V = 0.2V p-p V = 2V p-p OUT OUT –1 –1 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response at Various Power Supplies, G = 2 Figure 8. Large Signal Frequency Response at Various Power Supplies, G = 2 3 3 2 2 1 1 0 0 –1 –1 G = 2, C = 10 + 2pF, R = 20Ω L SNUB G = 2, C = 10 + 2pF, R = 20Ω G = 2, C = 0 + 2pF, R = 0Ω L SNUB L SNUB –2 G = 2, C = 0 + 2pF, R = 0Ω –2 G = 1, C = 10 + 2pF, R = 20Ω L SNUB L SNUB G = 1, C = 10 + 2pF, R = 20Ω G = 1, C = 0 + 2pF, R = 0Ω L SNUB L SNUB G = 1, C = 0 + 2pF, R = 0Ω –3 –3 L SNUB –4 –4 –5 –5 –6 –6 V = 2V p-p V = 0.2V p-p OUT OUT –7 –7 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response at Various Gains Figure 9. Large Signal Frequency Response at Various Gains and 10 pF Capacitive Load Buffered by 20 Ω Resistor and 10 pF Capacitive Load Buffered by 20 Ω Resistor Rev. A | Page 9 of 24 GAIN (dB) GAIN (dB) GAIN (dB) 06307-006 06307-005 06307-004 GAIN (dB) GAIN (dB) GAIN (dB) 06307-009 06307-008 06307-007 AD8145 3 3 2 2 1 1 G = 1 G = 1 0 0 –1 –1 G = 2 –2 –2 G = 2 –3 –3 –4 –4 –5 –5 –6 –6 V = 0.2V p-p OUT V = 2V p-p OUT –7 –7 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Large Signal Frequency Response at Various Gains Figure 10. Small Signal Frequency Response at Various Gains 0.5 1000 G = 1, V = +5V S 0.4 G = 1, V = ±5V S 0.3 0.2 0.1 0 100 G = 2, V = +5V –0.1 S G = 2, V = ±5V S –0.2 –0.3 –0.4 V = 2V p-p OUT 10 –0.5 1 10 100 1000 0.01 0.1 1 10 100 1000 10000 100000 FREQUENCY (MHz) FREQUENCY (kHz) Figure 11. 0.1 dB Flatness for Various Power Supplies and Gains Figure 14. Input Referred Voltage Noise vs. Frequency 110 4 R = OPEN CIRCUIT L 100 G = 1 3 V = ±5V S 90 2 80 V = +5V S 1 70 V = ±5V S 60 0 50 –1 40 –2 30 –3 20 10 –4 0.1 1 10 100 1000 –5 –4 –3 –2 –1 0123 4 5 FREQUENCY (MHz) DIFFERENTIAL INPUT VOLTAGE (V) Figure 12. Common-Mode Rejection vs. Frequency at Various Supplies Figure 15. Differential Input Operating Range Rev. A | Page 10 of 24 COMMON-MODE REJECTION (dB) GAIN (dB) GAIN (dB) 06307-012 06307-011 06307-010 INPUT VOLTAGE NOISE (nV/ Hz) GAIN (dB) OUTPUT VOLTAGE (V) 06307-047 06307-013 06307-046 AD8145 150 1.5 100 1.0 BLACK = +5V BLACK = +5V GRAY = ±5V GRAY = ±5V 50 0.5 0 0 –50 –0.5 –100 –1.0 V = 0.2V p-p V = 2V p-p OUT OUT –150 –1.5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) TIME (ns) Figure 16. Small Signal Transient Response at Various Power Supplies, G = 1 Figure 19. Large Signal Transient Response at Various Power Supplies, G = 1 150 1.5 100 1.0 BLACK = +5V BLACK = +5V GRAY = ±5V GRAY = ±5V 50 0.5 0 0 –50 –0.5 –100 –1.0 V = 2V p-p V = 0.2V p-p OUT OUT –150 –1.5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) TIME (ns) Figure 17. Small Signal Transient Response at Various Power Supplies, G = 2 Figure 20. Large Signal Transient Response at Various Power Supplies, G = 2 150 1.5 G = 1, C = 0 + 2pF, R = 0Ω G = 1, C = 0 + 2pF, R = 0Ω L SNUB L SNUB G = 1, C = 10 + 2pF, R = 20Ω G = 1, C = 10 + 2pF, R = 20Ω L SNUB L SNUB 100 1.0 50 0.5 V = 2V p-p V = 0.2V p-p OUT OUT 0 0 –50 –0.5 –100 –1.0 G = 2, C = 0 + 2pF, R = 0Ω G = 2, C = 0 + 2pF, R = 0Ω L SNUB L SNUB G = 2, C = 10 + 2pF, R = 20Ω G = 2, C = 10 + 2pF, R = 20Ω L SNUB L SNUB –150 –1.5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) TIME (ns) Figure 18. Small Signal Transient Response at Various Gains Figure 21. Large Signal Transient Response at Various Gains and 10 pF Capacitive Load Buffered by 20 Ω Resistor and 10 pF Capacitive Load Buffered by 20 Ω Resistor Rev. A | Page 11 of 24 VOLTAGE (mV) VOLTAGE (mV) VOLTAGE (mV) 06307-018 06307-017 06307-016 VOLTAGE (V) VOLTAGE (V) VOLTAGE (V) 06307-021 06307-020 06307-019 AD8145 2.0 0.5 4500 POSITIVE 1.6 0.4 4000 OUTPUT SLEW RATE INPUT 1.2 0.3 3500 0.8 0.2 NEGATIVE 3000 SLEW RATE 0.4 0.1 2500 ERROR 0 0 2000 –0.4 –0.1 1500 –0.8 –0.2 1000 –0.3 –1.2 500 –1.6 –0.4 –2.0 –0.5 0 05 5 10152025303540450 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 TIME (ns) OUTPUT VOLTAGE (V p-p) Figure 22. Settling Time Figure 25. Slew Rate vs. Output Voltage Swing –50 –50 –60 –55 V = +5V S –70 –60 –80 V = ±5V –65 S V = ±5V S –90 –70 –100 V = +5V S –75 –110 V = 2V p-p V = 2V p-p OUT OUT –80 –120 0.1 110 100 0.1 110 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 26. Third Harmonic Distortion vs. Frequency and Power Supplies, Figure 23. Second Harmonic Distortion vs. Frequency and Power Supplies, V = 2 V p-p, G = 1 VOUT = 2 V p-p, G = 1 OUT –50 –50 V = 2V p-p OUT –60 –55 V = +5V S –70 –60 V = ±5V S –80 –65 –90 –70 V = ±5V S –100 –75 V = +5V S –110 V = 2V p-p OUT –80 –120 0.1 110 100 0.1 110 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Second Harmonic Distortion vs. Frequency and Power Supplies, Figure 27. Third Harmonic Distortion vs. Frequency and Power Supplies, VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p, G = 2 Rev. A | Page 12 of 24 VOLTAGE (V) DISTORTION (dBc) DISTORTION (dBc) 06307-024 06307-023 ERROR (%) 06307-048 SLEW RATE (V/µs) DISTORTION (dBc) DISTORTION (dBc) 06307-027 06307-026 06307-049 AD8145 65 5 R = OPEN CIRCUIT L 60 4 55 3 I (±5V) CC 50 2 I (±5V) 45 1 EE 40 0 35 –1 +5V OUTPUT I (±2.5V) EE 30 –2 +5V 2 × V IN 25 –3 I (±2.5V) ±5V OUTPUT CC 20 –4 ±5V 2 × V IN G = 2 15 –5 –60 –40 –20 0 20 40 60 80 100 120 05 50 100 150 200 250 300 350 400 45000 TEMPERATURE (°C) TIME (ns) Figure 28. Power Supply Current vs. Temperature Figure 31. Output Overdrive Recovery 10 10 0 0 –10 –10 –20 –20 BLACK = +5V BLACK = ±2.5V –30 –30 GRAY = ±5V GRAY = ±5V –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 32. Negative Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 29. Positive Power Supply Rejection Ratio (PSRR) vs. Frequency 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –15 –10 –5 0 5 10 15 V (mV) IN Figure 30. Comparator Hysteresis Rev. A | Page 13 of 24 SUPPLY CURRENT (mA) V (V) PSRR (dB) OUT 06307-051 06307-029 06307-050 PSRR (dB) VOLTAGE (V) 06307-032 06307-030 AD8145 THEORY OF OPERATION The two differential input stages of the AD8145 are each The AD8145 amplifiers use an architecture called active feedback, which differs from that of conventional op amps. The most transconductance stages that are well matched. These stages obvious differentiating feature is the presence of two separate convert the respective differential input voltages to internal pairs of differential inputs compared to a conventional op amp’s currents. The currents are then summed and converted to a single pair. Typically, for the active feedback architecture, one of voltage, which is buffered to drive the output. The compensation these input pairs is driven by a differential input signal while capacitor is included in the summing circuit. When the feedback the other is used for the feedback. This active stage in the feedback path is closed around the part, the output drives the feedback path is where the term active feedback is derived. The AD8145 input to the voltage that causes the internal currents to sum to zero. This occurs when the two differential inputs are equal and has an internal feedback resistor from each amplifier output to the negative input of its feedback input stage. This limits the opposite; that is, their algebraic sum is zero. possible closed-loop gain configurations for the AD8145. In a closed-loop application, a conventional op amp has its The active feedback architecture offers several advantages over a differential input voltage driven to near zero under non- conventional op amp in several types of applications. Among transient conditions. The AD8145 generally has differential these are excellent common-mode rejection, wide input common- input voltages at each of its input pairs, even under equilibrium mode range, and a pair of inputs that are high impedance and conditions. As a practical consideration, it is necessary to limit completely balanced in a typical application. In addition, while the differential input voltage internally with a clamp circuit. an external feedback network establishes the gain response as in a Therefore, the input dynamic ranges are limited to approximately conventional op amp, its separate path makes it entirely independent 2.5 V (see the Specifications section for more details). For this of the signal input. This eliminates any interaction between the reason, it is not recommended to reverse the input and feedback feedback and input circuits, which traditionally causes problems stages of the AD8145, even though some normal functionality with CMRR in conventional differential-input op amp circuits. may be observed under some conditions. Another advantage of active feedback is the ability to change the polarity of the gain merely by switching the differential inputs. A high input impedance inverting amplifier can therefore be made. Besides high input impedance, a unity-gain inverter with the AD8145 has a noise gain of unity, producing lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity-gain inverter. Rev. A | Page 14 of 24 AD8145 APPLICATIONS INFORMATION +5V OVERVIEW The AD8145 contains three independent active feedback amplifiers 0.01µF that can be effectively applied as differential line receivers for red-green-blue (RGB) signals or component video signals, such V IN as YPbPr, transmitted over UTP cable. The AD8145 also contains OUT two general-purpose comparators with hysteresis that can be V REF OUT used to receive digital signals or to extract video synchronization pulses from received common-mode signals that contain V REF encoded synchronization signals. R The comparators, which receive power from the positive supply, are R referenced to GND and require greater than 4.5 V on the positive GAIN C supply for proper operation. If the comparators are not used, then a split ±2.5 V can be used with the amplifiers operating normally. 0.01µF –5V The AD8145 includes a power-down feature that can be asserted to Figure 33. Basic Gain = 1 Circuit: VOUT = VIN + VREF reduce the supply current when a particular device is not in use. The gain equation for the circuit in Figure 33 is BASIC CLOSED-LOOP GAIN CONFIGURATIONS V = V + V (1) OUT IN REF Each amplifier in the AD8145 comprises two transconductance amplifiers—one for the input signal and one for negative feedback. In this configuration, the voltage applied to the REF pin appears Note that the closed-loop gain of the amplifier used in the signal at the output with a gain of 1. path is defined as the single-ended output voltage of the amplifier Figure 34 illustrates one way to operate an AD8145 amplifier divided by its differential input voltage. Therefore, each amplifier with a gain of 2. in the AD8145 provides differential-to-single-ended gain. +5V Additionally, the amplifier used for feedback has two high impedance inputs—the feedback input, where the negative 0.01µF feedback is applied, and the REF input, that can be used as an independent single-ended input to apply a dc offset to the V IN output signal. The AD8145 contains on-chip feedback networks between each REF V OUT amplifier output and its respective feedback input. The closed- V REF C loop gain of the amplifier is set to 1 by connecting the amplifier output directly to its respective GAIN_x pin. Doing this places GAIN R R the on-chip resistors and capacitor in parallel across the amplifier output and feedback pin. The small feedback capacitor mitigates 0.01µF the effects of the summing-node capacitance, which is most –5V problematic in the unity gain case. Closed-loop gain of an Figure 34. Basic Gain = 2 Circuit: VOUT = 2(VIN + VREF) amplifier is set to 2 by connecting the respective GAIN_x pin The gain equation for the circuit in Figure 34 is to a reference voltage, often directly to ground. In Figure 1, R = 350 Ω and C = 2 pF. VOUT = 2(VIN + VREF) (2) Some basic gain configurations implemented with an AD8145 amplifier are shown in Figure 33 through Figure 36. Rev. A | Page 15 of 24 06307-034 06307-035 AD8145 To achieve unity gain from V to V in this configuration, REF OUT TERMINATING THE INPUT divide V by the same factor used in the feedback loop; the REF One of the key benefits of the active feedback architecture is the divider resistors, R , need not be the same values used in the D separation that exists between the differential input signal and internal feedback loop. Figure 35 illustrates this approach. the feedback network. Because of this separation, the differential +5V input maintains its high CMRR and provides high differential and common-mode input impedances, making line termination 0.01µF a simple task. V Most applications that use the AD8145 involve transmitting broad- IN band video signals over 100 Ω UTP cables and use dc-coupled R REF terminations. The two most common types of dc-coupled D V OUT terminations are differential and common-mode. Differential R V D REF C termination of 100 Ω UTP cables is implemented by simply connecting a 100 Ω resistor across the amplifier input, as shown GAIN R R in Figure 37. +5V 0.01µF –5V 0.01µF Figure 35. Basic Gain Circuit: V = 2V + V OUT IN REF 100Ω The gain equation for the circuit in Figure 35 is 100Ω V IN UTP OUT V = 2V + V (3) OUT IN REF REF V OUT Another configuration that provides the same gain equation as Equation 3 is shown in Figure 36. In this configuration, it is important to keep the source resistance of VREF much smaller R than 350 Ω to avoid gain errors. R +5V GAIN C 0.01µF 0.01µF –5V V IN Figure 37. Differential-Mode Termination with G = 1 REF V OUT Some applications require common-mode terminations for common-mode currents generated at the transmitter. In these C cases, the 100 Ω termination resistor is split into two 50 Ω resistors. The required common-mode termination voltage is R R GAIN applied at the tap between the two resistors. In many of these V REF 0.01µF applications, the common-mode tap is connected to ground –5V (V (CM) = 0). This scheme is illustrated in Figure 38. TERM Figure 36. Basic Gain Circuit: VOUT = 2VIN + VREF +5V For stability reasons, the inductance of the trace connected to 0.01µF the REF_x pin must be kept to less than 10 nH. The typical 50Ω inductance of 50 Ω traces on the outer layers of the FR-4 boards 100Ω V IN UTP is 7 nH/in, and on the inner layers, it is typically 9 nH/in. Vias 50Ω OUT must be accounted for as well. The inductance of a typical via in REF V V (CM) a 0.062-inch board is 1.5 nH. If longer traces are required, a 200 Ω TERM OUT resistor should be placed in series with the trace to reduce the Q-factor of the inductance. R In many dual-supply applications, VREF can be directly connected to R ground right at the device. GAIN C 0.01µF –5V Figure 38. Common-Mode Termination with G = 1 Rev. A | Page 16 of 24 06307-037 06307-036 06307-039 06307-038 AD8145 A simple way to implement a clamp is to use a number of diodes in INPUT CLAMPING series. The resultant clamping voltage is then the sum of the The differential input that is assigned to receive the input signal clamping voltages of individual diodes. includes clamping diodes that limit the differential input swing to approximately 5.5 V p-p at 25°C. Because of this, the input A 1N4448 diode has a forward voltage of approximately 0.70 V and feedback stages should never be interchanged. to 0.75 V at typical current levels that are seen when it is being used as a clamp, and 2 pF maximum capacitance at 0 V bias. The supply current drawn by the AD8145 has a strong dependence (The capacitance of a diode decreases as its reverse-bias voltage on the input signal magnitude because the input transconductance is increased.) The series connection of two 1N4448 diodes, stages operate with differential input signals that can be up to a therefore, has a clamping voltage of 1.4 V to 1.5 V. Figure 40 few volts peak-to-peak. This behavior is distinctly different shows how to limit the differential input voltage applied to an from that of traditional op amps, where the differential input AD8145 amplifier to ±1.4 V to ±1.5 V (2.8 V p-p to 3.0 V p-p). signal is driven to essentially 0 V by negative feedback. Note that the capacitance of the two series diodes is half that of For most applications, including receiving RGB video signals, one diode. Different numbers of series diodes can be used to the input signal magnitudes encountered are well within the obtain different clamping voltages. safe operating limits of the AD8145 over its full power supply RT is the differential termination resistor, and the series and operating temperature ranges. In some extreme applications resistances, RS, limit the current into the diodes. The series where large differential and/or common-mode voltages are resistors should be highly matched in value to preserve high encountered, external clamping may be necessary. External frequency CMRR. common-mode clamping is also sometimes required when an +5V unpowered AD8145 receives a signal from an active driver. In POSITIVE CLAMP NEGATIVE CLAMP this case, external diodes are required when the current drawn 0.01µF + by the internal ESD diodes cannot be kept to less than 5 mA. R S Figure 39 shows a general approach to external differential-mode V IN R T clamping. R OUT S – +5V REF V POSITIVE CLAMP NEGATIVE CLAMP OUT + 0.01µF R S R V IN R T R OUT GAIN R C S – V REF OUT 0.01µF –5V R Figure 40. Using Two 1N4448 Diodes in Series as a Clamp R Many other nonlinear devices can be used as clamps. The best GAIN C choice for a particular application depends upon the desired clamping voltage, response time, parasitic capacitance, and 0.01µF –5V other factors. Figure 39. Differential-Mode Clamping with G = 1 When using external differential-mode clamping, it is important to ensure that the series resistors (R ), the sum of the parasitic S The positive and negative clamps are nonlinear devices that exhibit capacitance of the clamping devices, and the input capacitance very low impedance when the voltage across them reaches a of the AD8145 are small enough to preserve the desired signal critical threshold (clamping voltage), thereby limiting the voltage bandwidth. across the AD8145 input. The positive clamp has a positive threshold, and the negative clamp has a negative threshold. A diode is a simple example of such a clamp. Schottky diodes generally have lower clamping voltages than typical signal diodes. The clamping voltage should be larger than the largest expected signal amplitude, with enough margin to ensure that the received signal passes without being distorted. Rev. A | Page 17 of 24 06307-040 06307-041 AD8145 Figure 41 shows a specific example of external common-mode not required. In these cases, small series resistors should be used to clamping. buffer the capacitance presented by the load. V+ Broadband power supply decoupling networks should be placed 2 as close as possible to the supply pins. Small surface-mount ceramic +5V 3 capacitors are recommended for these networks, and tantalum + R S capacitors are recommended for bulk supply decoupling. 0.01µF HBAT-540C 1 Minimizing Parasitic Feedback Reactances V– V R IN T Parasitic trace capacitance and inductance are both reduced in V+ 2 the unity-gain configuration when the feedback trace that connects OUT the OUT_x pin to the GAIN_x pin is reduced in length. Removing REF V OUT R S 3 – the copper from the planes below the trace reduces trace capacitance, but increases trace inductance, because the loop area formed by R 1 HBAT-540C the trace and ground plane is increased. A reasonable compromise V– R that works well is to void all copper directly under the feedback trace and component pads with margins on each side approximately GAIN C equal to one trace width. Combining this technique with minimizing trace length is effective in keeping parasitic trace reactance in 0.01µF –5V the unity-gain feedback loop to a minimum. Figure 41. External Common-Mode Clamping Maximizing Heat Removal A square array of thermal vias works well to connect the exposed The series resistances, RS, limit the current in each leg, and the paddle to internal ground planes. The vias should be placed Schottky diodes limit the voltages on each input to approximately inside the PCB pad that is soldered to the exposed paddle and 0.3 V to 0.4 V over the positive power supply, V+, and to 0.3 V to 0.4 V below the negative power supply, V−. The required should connect to all ground planes. signal bandwidth, the line impedance, and the effective The AD8145 includes ground connections on its corner pins. differential capacitance due to the AD8145 inputs and the These pins can be used to provide additional heat removal from diodes determine the maximum R value. S the AD8145 by connecting them between the PCB pad that is soldered to the exposed paddle and a ground plane on the As with the differential clamp, the series resistors should be component side of the board. This layout technique lowers the highly matched in value to preserve high frequency CMRR. overall package thermal resistance. Use of this technique is not PCB LAYOUT CONSIDERATIONS required, but it does result in a lower junction temperature. Designs The two most important issues with regard to PCB layout are must often conform to Design for Manufacturing (DFM) rules minimizing parasitic signal trace reactances in the feedback that stipulate how to lay out PCBs in such a way as to facilitate network and providing sufficient thermal relief. the manufacturing process. Some of these rules require thermal relief on pads that connect to planes, and the rules may limit the Excessive parasitic reactances in the feedback network cause extent to which this technique can be used. excessive peaking in the frequency response of the amplifier and excessive overshoot in its step response due to a reduction in phase margin. Oscillation occurs when these parasitic reactances are increased to a critical point where the phase margin is reduced to zero. Minimizing these reactances is important to obtain optimal performance from the AD8145. General high speed layout practices should be adhered to when applying the AD8145. Controlled impedance transmission lines are required for incoming and outgoing signals, referenced to a ground plane. Typically, the input signals are received over 100 Ω differential transmission lines. A 100 Ω differential transmission line is readily realized on the PCB using two well-matched, closely-spaced, 50 Ω single-ended traces that are coupled through the ground plane. The traces that carry the single-ended output signals are most often 75 Ω for video signals. Output signal connections should include series termination resistors that are matched to the impedance of the line they are driving. When driving high impedance loads over very short traces, impedance matching is Rev. A | Page 18 of 24 06307-042 AD8145 DRIVING A CAPACITIVE LOAD POWER-DOWN The AD8145 typically drives either high impedance loads over The power-down feature can be used to reduce power consumption short PCB traces, such as crosspoint switch inputs, or doubly when a particular device is not in use and does not place the output terminated coaxial cables. A gain of 1 is commonly used in in a high-Z state when asserted. The power-down feature is the high impedance case because a 6 dB transmission line asserted when the voltage applied to the power-down pin drops termination loss is not incurred. A gain of 2 is required when to approximately 2 V below the positive supply. The AD8145 is driving cables to compensate for the 6 dB termination loss. enabled by pulling the power-down pin to the positive supply. In all cases, the output must drive the parasitic capacitance of AUTOMOTIVE PRODUCTS the feedback loop, conservatively estimated to be 1 pF, in addition The AD8145W product is qualified per the AEC-Q100 for use to the capacitance presented by the actual load. When driving a in automotive applications. This model meets stringent automotive high impedance input, it is recommended that a small series performance and quality requirements and offers the same resistor be used to buffer the input capacitance of the device functionalities as the commercial and industrial grade devices but being driven. Clearly, the resistor value must be small enough to operates over a temperature range of −40°C to +105°C. For more preserve the required bandwidth. In the ideal doubly terminated information, contact your local Analog Devices, Inc., sales cable case, the AD8145 output sees a purely resistive load. In representative. reality, there is some residual capacitance, which is buffered by COMPARATORS the series termination resistor. Figure 42 illustrates the high impedance case, and Figure 43 illustrates the cable driving case. In addition to general-purpose applications, the two on-chip +5V comparators can be used to decode video sync pulses from the received common-mode voltages or to receive differential digital 0.01µF information. Built-in hysteresis helps to eliminate false triggers from noise. V IN The comparator outputs are designed to drive source-terminated R OUT S transmission lines. The source termination technique uses a resistor REF C in-series with each comparator output such that the sum of the IN comparator source resistance (≈20 Ω) and the series resistor V REF equals the transmission line characteristic impedance. The load R end of the transmission line is high impedance. When the signal is launched into the source termination, its initial value is one- R half of its source value because its amplitude is divided-by-2 by GAIN C the voltage divider formed by the source termination and the transmission line. At the load, the signal experiences nearly 0.01µF 100% positive reflection due to the high impedance load and –5V is restored to nearly its full value. This technique is commonly Figure 42. Buffering the Input Capacitance of a High-Z Load with G = 1 used in PCB layouts that involve high speed digital logic. An internal linear voltage regulator derives power for the +5V comparators from the positive supply; therefore, the AD8145 must always have a minimum positive supply voltage of 4.5 V. 0.01µF V IN R OUT S REF C R S L V REF C GAIN R R 0.01µF –5V Figure 43. Driving a Doubly Terminated Cable with G = 2 Rev. A | Page 19 of 24 06307-043 06307-044 AD8145 The AD8134 encoding equations are given in Equation 4, SYNC PULSE EXTRACTION USING COMPARATORS Equation 5, and Equation 6. The AD8145 is particularly useful in KVM applications. KVM networks transmit and receive computer video signals that typically K Red V = [V− H] (4) CM comprise red, green, and blue (RGB) video signals and separate 2 horizontal and vertical sync signals. Because the sync signals are K [ ] Green V = − 2 V (5) separate and not embedded in the color signals, it is advantageous CM 2 to transmit them using a simple scheme that encodes them among K the three common-mode voltages of the RGB signals. The AD8134 [ ] Blue V = V+ H (6) CM 2 triple differential driver is a natural complement to the AD8145 and performs the sync pulse encoding with the necessary where: circuitry on-chip. Red V , Green V , and Blue V are the transmitted common- CM CM CM mode voltages of the respective color signals. K is an adjustable gain constant that is set by the AD8134. V and H are the vertical and horizontal sync pulses, defined with a weight of −1 when the pulses are in their low states and a weight of +1 when they are in their high states. The AD8134 data sheet contains further details regarding the encoding scheme. Figure 44 illustrates how the AD8145 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the RGB common-mode voltages by the AD8134. 50Ω RED CMV RECEIVED R S RED VIDEO HSYNC 50Ω 1kΩ 47pF 50Ω 475Ω GREEN CMV RECEIVED R S GREEN VIDEO VSYNC 50Ω 47pF 1kΩ 50Ω RECEIVED BLUE CMV BLUE VIDEO 50Ω Figure 44. Extracting Sync Signals from Received Common-Mode Signal Rev. A | Page 20 of 24 06307-045 AD8145 OUTLINE DIMENSIONS 5.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 25 32 1 24 PIN 1 INDICATOR 0.50 EXPOSED 3.45 BSC TOP 4.75 PAD VIEW 3.30 SQ BSC SQ (BOTTOM VIEW) 3.15 0.50 17 0.40 8 16 9 0.30 0.25 MIN 0.80 MAX 3.50 REF 12° MAX 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 1.00 0.02 NOM THE PIN CONFIGURATION AND 0.85 COPLANARITY FUNCTION DESCRIPTIONS 0.30 SECTION OF THIS DATA SHEET. 0.08 0.80 0.20 REF 0.23 SEATING 0.18 PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 45. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8145YCPZ-R2 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 AD8145YCPZ-RL −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 AD8145YCPZ-R7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 2 AD8145WYCPZ-R7 −40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-3 1 Z = RoHS Compliant Part. 2 W = automotive qualified product. Rev. A | Page 21 of 24 112408-A AD8145 NOTES Rev. A | Page 22 of 24 AD8145 NOTES Rev. A | Page 23 of 24 AD8145 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06307-0-1/10(A) Rev. A | Page 24 of 24