ANALOG DEVICES AD8139

Low Noise, Rail-to-Rail, Differential ADC Driver AD8139 FEATURES APPLICATIONS Fully differential ADC drivers to 18 bits Low noise Single-ended-to-differential converters 2.25 nV/√Hz Differential filters 2.1 pA/√Hz Level shifters Low harmonic distortion Differential PCB drivers 98 dBc SFDR @ 1 MHz Differential cable drivers 85 dBc SFDR @ 5 MHz 72 dBc SFDR @ 20 MHz FUNCTIONAL BLOCK DIAGRAMS High speed AD8139 410 MHz, 3 dB BW (G = 1) –IN 1 8 +IN 800 V/μs slew rate V 2 7 NC OCM 45 ns settling time to 0.01% V+ 3 6 V– 69 dB output balance @ 1 MHz +OUT 4 5 –OUT 80 dB dc CMRR Low offset: ±0.5 mV maximum NC = NO CONNECT Low input offset current: 0.5 μA maximum Figure 1. 8-Lead SOIC Differential input and output AD8139 Differential-to-differential or single-ended-to-differential TOP VIEW (Not to Scale) operation Rail-to-rail output –IN 1 8+IN Adjustable output common-mode voltage V 2 7NC OCM V+ 3 6V– Wide supply voltage range: 5 V to 12 V +OUT 4 5–OUT Available in a small SOIC package and an 8-lead LFCSP NC = NO CONNECT Figure 2. 8-Lead LFCSP The AD8139 is available in an 8-lead SOIC package with an GENERAL DESCRIPTION exposed paddle (EP) on the underside of its body and a 3 mm × The AD8139 is an ultralow noise, high performance differential 3 mm LFCSP. It is rated to operate over the temperature range amplifier with rail-to-rail output. With its low noise, high of −40°C to +125°C. SFDR, and wide bandwidth, it is an ideal choice for driving 100 ADCs with resolutions to 18 bits. The AD8139 is easy to apply, and its internal common-mode feedback architecture allows its output common-mode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides outstanding output balance as well as suppression of even-order harmonic distortion products. Fully differential and single- 10 ended-to-differential gain configurations are easily realized by the AD8139. Simple external feedback networks consisting of four resistors determine the closed-loop gain of the amplifier. The AD8139 is manufactured on the Analog Devices, Inc. proprietary, second-generation XFCB process, enabling it to achieve low levels of distortion with input voltage noise of only 1 10 100 1k 10k 100k 1M 10M 100M 1G 2.25 nV/√Hz. FREQUENCY (Hz) Figure 3. Input Voltage Noise vs. Frequency Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. INPUT VOLTAGE NOISE (nV/ Hz) 04679-102 04679-001 04679-078 AD8139 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................8 Applications....................................................................................... 1 Typical Performance Characteristics ..............................................9 Functional Block Diagrams............................................................. 1 Test Circuits ................................................................................ 17 General Description ......................................................................... 1 Theory of Operation ...................................................................... 18 Revision History ............................................................................... 2 Typical Connection and Definition of Terms ........................ 18 Specifications..................................................................................... 3 Applications..................................................................................... 19 V = ±5 V, V = 0 V.................................................................. 3 Estimating Noise, Gain, and Bandwidth with Matched S OCM Feedback Networks .................................................................... 19 V = 5 V, V = 2.5 V ................................................................. 5 S OCM Outline Dimensions ....................................................................... 24 Absolute Maximum Ratings............................................................ 7 Ordering Guide .......................................................................... 24 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 REVISION HISTORY 10/07—Rev. A to Rev. B. 8/04—Rev. 0 to Rev. A. Changes to General Description .................................................... 1 Added 8-Lead LFCSP.........................................................Universal Inserted Figure 2; Renumbered Sequentially................................ 1 Changes to General Description .....................................................1 Changes to Table 1............................................................................ 3 Changes to Figure 2...........................................................................1 Changes to Table 2............................................................................ 5 Changes to V = ±5 V, V = 0 V Specifications .........................3 S OCM Changes to Table 6 and Layout ....................................................... 8 Changes to V = 5 V, V = 2.5 V Specifications.........................5 S OCM Inserted Figure 6; Renumbered Sequentially................................ 8 Changes to Table 4.............................................................................7 Changes to Figure 30...................................................................... 12 Changes to Maximum Power Dissipation Section........................7 Changes to Layout .......................................................................... 17 Changes to Figure 26 and Figure 29............................................. 12 Changes to Figure 63...................................................................... 22 Inserted Figure 39 and Figure 42.................................................. 14 Changes to Exposed Paddle (EP) Section ................................... 23 Changes to Figure 45 to Figure 47................................................ 15 Updated Outline Dimensions ....................................................... 24 Inserted Figure 48........................................................................... 15 Changes to Figure 52 and Figure 53............................................. 16 Changes to Figure 55 and Figure 56............................................. 17 Changes to Table 6.......................................................................... 19 Changes to Voltage Gain Section ................................................. 19 Changes to Driving a Capacitive Load Section .......................... 22 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions....................................................... 24 5/04—Revision 0: Initial Version Rev. B | Page 2 of 24 AD8139 SPECIFICATIONS V = ±5 V, V = 0 V S OCM T = 25°C, differential gain = 1, R = 1 kΩ, R = R = 200 Ω, unless otherwise noted. T to T = −40°C to +125°C. A L, dm F G MIN MAX Table 1. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth V = 0.1 V p-p 340 410 MHz O, dm −3 dB Large Signal Bandwidth V = 2 V p-p 210 240 MHz O, dm Bandwidth for 0.1 dB Flatness VO, dm = 0.1 V p-p 45 MHz Slew Rate VO, dm = 2 V step 800 V/μs Settling Time to 0.01% VO, dm = 2 V step, CF = 2 pF 45 ns Overdrive Recovery Time G = 2, V = 12 V p-p triangle wave 30 ns IN, dm Noise/Harmonic Performance SFDR V = 2 V p-p, f = 1 MHz 98 dBc O, dm C VO, dm = 2 V p-p, fC = 5 MHz 85 dBc VO, dm = 2 V p-p, fC = 20 MHz 72 dBc Third-Order IMD VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz −90 dBc Input Voltage Noise f = 100 kHz 2.25 nV/√Hz Input Current Noise f = 100 kHz 2.1 pA/√Hz DC Performance Input Offset Voltage VIP = VIN = VOCM = 0 V −500 ±150 +500 μV Input Offset Voltage Drift TMIN to TMAX 1.25 μV/°C Input Bias Current T to T 2.25 8.0 μA MIN MAX Input Offset Current 0.12 0.5 μA Open-Loop Gain 114 dB Input Characteristics Input Common-Mode Voltage Range −4 +4 V Input Resistance Differential 600 kΩ Common mode 1.5 MΩ Input Capacitance Common mode 1.2 pF CMRR ∆VICM = ±1 V dc, RF = RG = 10 kΩ 80 84 dB Output Characteristics Output Voltage Swing Each single-ended output, RF = RG = 10 kΩ −VS + 0.20 +VS – 0.20 V Each single-ended output, −V + 0.15 +V − 0.15 V S S R = open circuit, R = R = 10 kΩ L, dm F G Output Current Each single-ended output 100 mA Output Balance Error f = 1 MHz −69 dB V TO V PERFORMANCE OCM O, cm V Dynamic Performance OCM −3 dB Bandwidth VO, cm = 0.1 V p-p 515 MHz Slew Rate VO, cm = 2 V p-p 250 V/μs Gain 0.999 1.000 1.001 V/V V Input Characteristics OCM Input Voltage Range −3.8 +3.8 V Input Resistance 3.5 MΩ Input Offset Voltage VOS, cm = VO, cm − VOCM; VIP = VIN = VOCM = 0 V −900 ±300 +900 μV Input Voltage Noise f = 100 kHz 3.5 nV/√Hz Input Bias Current 1.3 4.5 μA CMRR ∆V /∆V , ∆V = ±1 V 74 88 dB OCM O, dm OCM Rev. B | Page 3 of 24 AD8139 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range +4.5 ±6 V Quiescent Current 24.5 25.5 mA +PSRR Change in +V = ±1 V 95 112 dB S −PSRR Change in −V = ±1 V 95 109 dB S OPERATING TEMPERATURE RANGE −40 +125 °C Rev. B | Page 4 of 24 AD8139 V = 5 V, V = 2.5 V S OCM TA = 25°C, differential gain = 1, RL, dm = 1 kΩ, RF = RG = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +125°C. Table 2. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth VO, dm = 0.1 V p-p 330 385 MHz −3 dB Large Signal Bandwidth VO, dm = 2 V p-p 135 165 MHz Bandwidth for 0.1 dB Flatness V = 0.1 V p-p 34 MHz O, dm Slew Rate V = 2 V step 540 V/μs O, dm Settling Time to 0.01% VO, dm = 2 V step 55 ns Overdrive Recovery Time G = 2, VIN, dm = 7 V p-p triangle wave 35 ns Noise/Harmonic Performance SFDR V = 2 V p-p, f = 1 MHz 99 dBc O, dm C V = 2 V p-p, f = 5 MHz, R = 800 Ω 87 dBc O, dm C L V = 2 V p-p, f = 20 MHz, R = 800 Ω 75 dBc O, dm C L Third-Order IMD VO, dm = 2 V p-p, fC = 10.05 MHz ± 0.05 MHz −87 dBc Input Voltage Noise f = 100 kHz 2.25 nV/√Hz Input Current Noise f = 100 kHz 2.1 pA/√Hz DC Performance Input Offset Voltage V = V = V = 2.5 V −500 ±150 +500 μV IP IN OCM Input Offset Voltage Drift T to T 1.25 μV/°C MIN MAX Input Bias Current TMIN to TMAX 2.2 7.5 μA Input Offset Current 0.13 0.5 μA Open-Loop Gain 112 dB Input Characteristics Input Common-Mode Voltage Range 1 4 V Input Resistance Differential 600 kΩ Common mode 1.5 MΩ Input Capacitance Common mode 1.2 pF CMRR ΔV = ±1 V dc, R = R = 10 kΩ 75 79 dB ICM F G Output Characteristics Output Voltage Swing Each single-ended output, R = R = 10 kΩ −V + 0.15 +V − 0.15 V F G S S Each single-ended output, −VS + 0.10 +VS − 0.10 V RL, dm = open circuit, RF = RG = 10 kΩ Output Current Each single-ended output 80 mA Output Balance Error f = 1 MHz −70 dB VOCM TO VO, cm PERFORMANCE V Dynamic Performance OCM −3 dB Bandwidth V = 0.1 V p-p 440 MHz O, cm Slew Rate V = 2 V p-p 150 V/μs O, cm Gain 0.999 1.000 1.001 V/V VOCM Input Characteristics Input Voltage Range 1.0 3.8 V Input Resistance 3.5 MΩ Input Offset Voltage V = V − V ; V = V = V = 2.5 V −1.0 ±0.45 +1.0 mV OS, cm O, cm OCM IP IN OCM Input Voltage Noise f = 100 kHz 3.5 nV/√Hz Input Bias Current 1.3 4.2 μA CMRR ΔVOCM/ΔVO, dm, ΔVOCM = ±1 V 67 79 dB Rev. B | Page 5 of 24 AD8139 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range +4.5 ±6 V Quiescent Current 21.5 22.5 mA +PSRR Change in +V = ±1 V 86 97 dB S −PSRR Change in −V = ±1 V 92 105 dB S OPERATING TEMPERATURE RANGE −40 +125 °C Rev. B | Page 6 of 24 AD8139 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (PD) is the sum of the Table 3. quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage 12 V power is the voltage between the supply pins (VS) times the V ±V OCM S quiescent current (I ). The load current consists of differential S Power Dissipation See Figure 4 and common-mode currents flowing to the load, as well as Input Common-Mode Voltage ±VS currents flowing through the external feedback networks and Storage Temperature Range −65°C to +125°C the internal common-mode feedback loop. The internal resistor Operating Temperature Range −40°C to +125°C tap used in the common-mode feedback loop places a 1 kΩ Lead Temperature (Soldering 10 sec) 300°C differential load on the output. RMS output voltages should be Junction Temperature 150°C considered when dealing with ac signals. Stresses above those listed under Absolute Maximum Ratings Airflow reduces θJA. In addition, more metal directly in contact may cause permanent damage to the device. This is a stress with the package leads from metal traces, through holes, rating only; functional operation of the device at these or any ground, and power planes reduce the θ . JA other conditions above those indicated in the operational Figure 4 shows the maximum safe power dissipation in the section of this specification is not implied. Exposure to absolute package vs. the ambient temperature for the exposed paddle maximum rating conditions for extended periods may affect (EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP device reliability. (θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values THERMAL RESISTANCE are approximations. 4.0 θ is specified for the worst-case conditions, that is, θ is JA JA specified for device soldered in circuit board for surface-mount 3.5 packages. 3.0 Table 4. 2.5 Package Type θ Unit JA 2.0 8-Lead SOIC with EP/4-Layer 70 °C/W 8-Lead LFCSP/4-Layer 70 °C/W 1.5 SOIC AND LFCSP 1.0 Maximum Power Dissipation The maximum safe power dissipation in the AD8139 package 0.5 is limited by the associated rise in junction temperature (TJ) on 0 the die. At approximately 150°C, which is the glass transition –40 –20 0 20 40 60 80 100 120 AMBIENT TEMPERATURE (°C) temperature, the plastic will change its properties. Even Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8139. Exceeding a junction ESD CAUTION temperature of 175°C for an extended period can result in changes in the silicon devices potentially causing failure. Rev. B | Page 7 of 24 MAXIMUM POWER DISSIPATION (W) 04679-055 AD8139 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD8139 TOP VIEW (Not to Scale) AD8139 –IN 1 8 +IN –IN 1 8+IN V 2 7 NC OCM V 2 7NC OCM 6 V– V+ 3 V+ 3 6V– +OUT 4 5–OUT +OUT 4 5 –OUT NC = NO CONNECT NC = NO CONNECT Figure 5. 8-Lead SOIC Pin Configuration Figure 6. 8-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Inverting Input. 2 V An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to OCM the V pin, provided the operation of the amplifier remains linear. OCM 3 V+ Positive Power Supply Voltage. 4 +OUT Positive Side of the Differential Output. 5 −OUT Negative Side of the Differential Output. 6 V− Negative Power Supply Voltage. 7 NC No Internal Connection. 8 +IN Noninverting Input. 9 Exposed Paddle Solder exposed paddle on back of package to ground plane or to a power plane. Rev. B | Page 8 of 24 04679-003 04679-103 AD8139 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, differential gain = +1, RG = RF = 200 Ω, RL, dm = 1 kΩ, VS = ±5 V, TA = 25°C, VOCM = 0 V. Refer to the basic test circuit in Figure 57 for the definition of terms. 2 2 G = 1 1 1 G = 1 0 0 G = 2 –1 –1 G = 5 G = 2 –2 –2 –3 –3 –4 –4 –5 –5 G = 5 –6 –6 G = 10 –7 –7 G = 10 –8 –8 –9 –9 –10 –10 –11 –11 R = 200Ω G R = 200Ω G –12 –12 V = 2.0V p-p O, dm V = 0.1V p-p O, dm –13 –13 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Small Signal Frequency Response for Various Gains Figure 10. Large Signal Frequency Response for Various Gains 5 3 4 2 V = +5V S 3 1 2 0 1 –1 0 –2 V = ±5V V = ±5V S S –1 –3 –2 –4 V = +5V S –3 –5 –4 –6 –5 –7 –6 –8 –7 –9 –8 –10 –9 –11 V = 2.0V p-p V = 0.1V p-p O, dm O, dm –10 –12 10 100 1000 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various Power Supplies Figure 11. Large Signal Frequency Response for Various Power Supplies 3 3 +125°C +85°C +125°C 2 2 +85°C 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 –4 –5 –5 –40°C –6 –6 –7 –7 –8 –8 –9 –9 –40°C +25°C –10 –10 –11 V = 0.1V p-p –11 O, dm V = 2.0V p-p O, dm +25°C –12 –12 10 100 1000 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Small Signal Frequency Response at Various Temperatures Figure 12. Large Signal Frequency Response at Various Temperatures Rev. B | Page 9 of 24 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 04679-006 04679-005 04679-004 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 04679-009 04679-008 04679-007 AD8139 3 2 R = 100Ω R = 200Ω R = 100Ω L L L 2 1 1 0 R = 500Ω L 0 –1 –1 –2 –2 –3 R = 500Ω L –3 –4 –4 –5 –5 –6 –6 –7 –7 –8 R = 1kΩ L –8 –9 –10 –9 –10 –11 –12 –11 V = 0.1V p-p V = 2.0V p-p O, dm R = 1kΩ O, dm R = 200Ω L L –12 –13 10 100 1000 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Large Signal Frequency Response for Various Loads Figure 13. Small Signal Frequency Response for Various Loads 3 2 C = 0pF C = 0pF C = 1pF F F F 1 2 1 0 C = 1pF F –1 0 –1 –2 C = 2pF F –2 –3 –4 –3 C = 2pF F –4 –5 –6 –5 –6 –7 –8 –7 –8 –9 –9 –10 –11 –10 –11 –12 V = 2.0V p-p V = 0.1V p-p O, dm O, dm –13 –12 10 100 1000 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. Small Signal Frequency Response for Various C Figure 17. Large Signal Frequency Response for Various CF F 6 0.5 R = 100Ω L V = +4.3V V = +4V OCM OCM 5 (V = 0.1V p-p) O, dm 0.4 V = –4.3V OCM 4 R = 100Ω L 3 0.3 (V = 2.0V p-p) O, dm V = –4V OCM 2 R = 1kΩ 0.2 L 1 (V = 2.0V p-p) O, dm 0.1 0 V = 0V OCM –1 R = 1kΩ L 0 (V = 0.1V p-p) O, dm –2 –0.1 –3 –4 –0.2 –5 –6 –0.3 –7 –0.4 –8 V = 0.1V p-p O, dm –0.5 –9 1 10 100 10 100 1000 FREQUENCY (Hz) FREQUENCY (MHz) Figure 18. 0.1 dB Flatness for Various Loads and Output Amplitudes Figure 15. Small Signal Frequency Response at Various VOCM Rev. B | Page 10 of 24 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) 04679-012 04679-011 04679-040 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) 04679-0-042 04679-014 04679-041 AD8139 –30 –30 V = 2.0V p-p V = 2.0V p-p O, dm O, dm –40 –40 –50 –50 V = +5V S –60 –60 V = ±5V S –70 –70 V = ±5V S –80 –80 V = +5V S –90 –90 –100 –100 –110 –110 –120 –120 –130 –130 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. Second Harmonic Distortion vs. Frequency and Supply Voltage Figure 22. Third Harmonic Distortion vs. Frequency and Supply Voltage –30 –30 V = 2.0V p-p V = 2.0V p-p O, dm O, dm –40 –40 –50 –50 –60 –60 G = 1 –70 –70 –80 –80 G = 5 –90 –90 –100 –100 G = 2 –110 –110 G = 1 G = 2 –120 –120 –130 –130 G = 5 –140 –140 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Second Harmonic Distortion vs. Frequency and Gain Figure 23. Third Harmonic Distortion vs. Frequency and Gain –30 –30 V = 2.0V p-p V = 2.0V p-p O, dm O, dm –40 –40 –50 –50 R = 100Ω L –60 –60 R = 100Ω L R = 200Ω L –70 –70 R = 200Ω L –80 –80 –90 –90 R = 500Ω L –100 –100 R = 1kΩ L R = 500Ω L –110 –110 –120 –120 R = 1kΩ L –130 –130 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 21. Second Harmonic Distortion vs. Frequency and Load Figure 24. Third Harmonic Distortion vs. Frequency and Load Rev. B | Page 11 of 24 DISTORTION (dBc) DISTORTION (dB) DISTORTION (dBc) 04679-017 04679-016 04679-015 DISTORTION (dBc) DISTORTION (dB) DISTORTION (dBc) 04679-020 04679-019 04679-018 AD8139 –30 –30 V = 2.0V p-p V = 2.0V p-p O, dm O, dm –40 –40 –50 –50 –60 –60 –70 –70 R = 200Ω F –80 –80 R = 500Ω F –90 –90 R = 200Ω F –100 –100 –110 –110 R = 1kΩ F R = 1kΩ F –120 –120 R = 500Ω F –130 –130 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. Second Harmonic Distortion vs. Frequency and RF Figure 28. Third Harmonic Distortion vs. Frequency and RF –80 –80 F = 2MHz F = 2MHz C C V = ±5V S –90 –90 V = +5V V = +5V S S –100 –100 V = ±5V S –110 –110 –120 –120 –130 –130 –140 –140 –150 –150 0 1234 5678 08 1 2 3 4 5 6 7 V (V p-p) V (V p-p) O, dm O, dm Figure 26. Second Harmonic Distortion vs. Output Amplitude Figure 29. Third Harmonic Distortion vs. Output Amplitude –60 –60 V = 2V p-p V = 2V p-p O, dm O, dm F = 2MHz F = 2MHz C C –70 –70 –80 –80 –90 –90 SECOND HARMONIC SECOND HARMONIC –100 –100 –110 –110 –120 –120 THIRD HARMONIC THIRD HARMONIC –130 –130 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –5 –4 –3 –2 –1 0 1 2 3 4 5 V (V) V (V) OCM OCM Figure 27. Harmonic Distortion vs. VOCM, VS = +5 V Figure 30. Harmonic Distortion vs. VOCM, VS = ±5 V Rev. B | Page 12 of 24 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 04679-022 04679-023 04679-021 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 04679-026 04679-025 04679-024 AD8139 100 2.5 V = 100mV p-p C = 0pF O, dm F 4V p-p 2.0 75 C = 2pF F 1.5 C = 0pF F 50 C = 0pF F 1.0 V O, dm (C = 0pF, 2V p-p F C = 2pF (C = 2pF, V = ±5V) F 25 F S V = ±5V) S 0.5 0 0 –0.5 –25 –1.0 –50 –1.5 –75 –2.0 5ns/DIV 5ns/DIV –100 –2.5 TIME (ns) TIME (ns) Figure 31. Small Signal Transient Response for Various CF Figure 34. Large Signal Transient Response for Various CF 0.100 1.5 R = 63.4Ω R = 31.6Ω S S C = 15pF C = 30pF L, dm L, dm 0.075 1.0 0.050 0.5 R = 31.6Ω S 0.025 C = 30pF L, dm R = 63.4Ω S C = 15pF L, dm 0 0 –0.025 –0.5 –0.050 –1.0 –0.075 5ns/DIV 5ns/DIV –0.100 –1.5 TIME (ns) TIME (ns) Figure 32. Small Signal Transient Response for Capacitive Loads Figure 35. Large Signal Transient Response for Capacitive Loads 5 1.5 600 V = 2V p-p O, dm C = 2pF 0 F F 1 = 10MHz C V = 2.0V p-p –5 O, dm F 2 = 10.1MHz C –10 1.0 400 –15 –20 –25 –30 0.5 200 –35 –40 –45 0 0 –50 –55 ERROR –60 –65 –0.5 –200 V O, dm –70 –75 –80 –1.0 –400 –85 –90 35ns/DIV V –95 IN –100 –1.5 –600 9.55 9.65 9.75 9.85 9.95 10.05 10.15 10.25 10.35 10.45 10.55 TIME (ns) FREQUENCY (MHz) Figure 36. Settling Time (0.01%) Figure 33. Intermodulation Distortion Rev. B | Page 13 of 24 NORMALIZED OUTPUT (dBc) V (V) O, dm V (V) O, dm 04679-043 04679-027 04679-064 AMPLITUDE (V) V (V) O, dm V (V) O, dm 04679-044 ERROR (µV) 1DIV = 0.01% 04679-065 04679-034 AD8139 1.5 6 ±5V 5 4 1.0 V = +5V S 3 2 +5V 0.5 1 0 V = 0.1V p-p O, cm –1 0 –2 V = ±5V V = ±5V S S –3 V = 2.0V p-p O, cm –0.5 –4 –5 V = 2V p-p O, cm V = 0V –6 IN, dm –1.0 –7 V = +5V S 10ns/DIV –8 –1.5 –9 10 100 1000 TIME (ns) FREQUENCY (MHz) Figure 37. V Large Signal Transient Response OCM Figure 40. VOCM Frequency Response for Various Supplies 0 0 V = 0.2V p-p V = 0.2V p-p IN, cm O, cm INPUT CMRR = ΔV /ΔV V CMRR = ΔV /ΔV O, cm IN, cm OCM O, dm O, cm –10 –10 –20 –20 –30 –30 –40 –40 R = R = 10kΩ F G –50 –50 –60 –60 R = R = 200Ω F G –70 –70 –80 –80 –90 –90 1 10 100 500 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 41. V CMRR vs. Frequency Figure 38. CMRR vs. Frequency OCM 100 100 10 10 1 1 10 100 1k 10k 100k 1M 10M 100M 1G 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) Figure 42. V Voltage Noise vs. Frequency Figure 39. Input Voltage Noise vs. Frequency OCM Rev. B | Page 14 of 24 V (V) CMRR (dB) OCM INPUT VOLTAGE NOISE (nV/ Hz) 04679-079 04679-066 04679-069 CLOSED-LOOP GAIN (dB) V CMRR (dB) V VOLTAGE NOISE (nV/ Hz) OCM OCM 04679-080 04679-045 04679-038 AD8139 0 14 2 × V R = 1kΩ G = 2 IN, dm L, dm 12 PSRR = ΔV /ΔV O, dm S –10 10 V O, dm –20 8 6 –30 4 –40 2 –PSRR –50 0 +PSRR –2 –60 –4 –70 –6 –8 –80 –10 –90 –12 50ns/DIV –100 –14 1 10 100 500 TIME (ns) FREQUENCY (MHz) Figure 43. PSRR vs. Frequency Figure 46. Overdrive Recovery 100 0 V = 1V p-p O, dm OUTPUT BALANCE = ΔV /ΔV V = +5V S O, cm O, dm –10 10 –20 V = ±5V –30 S 1 –40 –50 0.1 –60 –70 –80 0.01 1 10 100 500 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 44. Single-Ended Output Impedance vs. Frequency Figure 47. Output Balance vs. Frequency 300 –50 700 V = ±5V S 600 G = 1 (R = R = 200Ω) F G 500 R = 1kΩ L, dm 250 –100 400 V – V S+ OP 300 V – V S+ OP 200 200 –150 100 0 V = +5V V = ±5V S S –100 150 –200 –200 V – V ON S– –300 V – V ON S– –400 100 –250 –500 –600 –700 50 –300 100 1k 10k –40 –20 0 20 40 60 80 100 120 RESISTIVE LOAD (Ω) TEMPERATURE (°C) Figure 45. Output Saturation Voltage vs. Output Load Figure 48. Output Saturation Voltage vs. Temperature Rev. B | Page 15 of 24 SINGLE-ENDED OUTPUT SWING FROM RAIL (mV) OUTPUT IMPEDANCE (Ω) PSRR (dB) 04679-068 04679-028 04679-047 V SWING FROM RAIL (mV) OP OUTPUT BALANCE (dB) VOLTAGE (V) 04679-046 V SWING FROM RAIL (mV) ON 04679-067 04679-077 AD8139 3.0 170 26 V = ±5V S I OS 25 2.5 145 24 I BIAS 2.0 120 23 V = +5V S 22 1.5 95 21 1.0 70 20 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 49. Input Bias and Offset Current vs. Temperature Figure 52. Supply Current vs. Temperature 10 300 600 8 V OS, cm 250 400 6 V = ±5V S 4 V = +5V S 200 200 2 0 150 0 V OS, dm –2 100 –200 –4 –6 50 –400 –8 –10 0 –600 –5 –4 –3 –2 –1 0 1 2 3 4 5 –40 –20 0 20 40 60 80 100 120 V (V) TEMPERATURE (°C) ACM Figure 53. Offset Voltage vs. Temperature Figure 50. Input Bias Current vs. Input Common-Mode Voltage 50 5 COUNT = 350 MEAN = –50µV 45 4 STD DEV = 100µV V = ±2.5V S 40 3 35 2 V = ±5V S 30 1 25 0 20 –1 15 –2 10 –3 5 –4 0 –5 –5 –4 –3 –2 –1 0 1 2 3 4 5 V (V) OCM V (µV) OS, dm Figure 51. VOUT, cm vs. VOCM Input Voltage Figure 54. VOS, dm Distribution Rev. B | Page 16 of 24 INPUT BIAS CURRENT (µA) V (V) INPUT BIAS CURRENT (µA) OUT, cm 04679-048 04679-073 OFFSET CURRENT (nA) 04679-062 V (µV) OS, dm FREQUENCY SUPPLY CURRENT (mA) –500 –450 –400 –350 –300 –250 –200 –150 –100 –50 0 50 100 150 200 250 300 350 400 450 500 04679-071 04679-060 V (µV) OS, cm 04679-061 AD8139 1.7 6 1.6 4 1.5 V = ±5V S 1.4 2 V = +5V S 1.3 1.2 0 1.1 –2 1.0 0.9 –4 0.8 0.7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) V (V) OCM Figure 55. V Bias Current vs. Temperature OCM Figure 56. VOCM Bias Current vs. VOCM Input Voltage TEST CIRCUITS R F 50Ω C F R = 200Ω G – 60.4Ω V TEST V AD8139 R = 1kΩ V OCM L, dm O, dm 60.4Ω + TEST R = 200Ω G C F SIGNAL 50Ω SOURCE R F Figure 57. Basic Test Circuit R = 200Ω F 50Ω R = 200Ω R S G 60.4Ω – V V C R V TEST AD8139 OCM L, dm L, dm O, dm 60.4Ω + TEST R = 200Ω R G S SIGNAL 50Ω SOURCE R = 200Ω F Figure 58. Capacitive Load Test Circuit, G = +1 Rev. B | Page 17 of 24 V BIAS CURRENT (µA) OCM 04679-063 V BIAS CURRENT (µA) OCM 04679-072 04679-075 04679-074 AD8139 THEORY OF OPERATION The AD8139 is a high speed, low noise differential amplifier outputs of identical amplitude and exactly 180° out of phase. The fabricated on the Analog Devices second-generation eXtra Fast output balance performance does not require tightly matched Complementary Bipolar (XFCB) process. It is designed to external components, nor does it require that the feedback factors provide two closely balanced differential outputs in response to of each loop be equal to each other. Low frequency output balance either differential or single-ended input signals. Differential is limited ultimately by the mismatch of an on-chip voltage divider, gain is set by external resistors, similar to traditional voltage- which is trimmed for optimum performance. feedback operational amplifiers. The common-mode level of Output balance is measured by placing a well-matched resistor the output voltage is set by a voltage at the V pin and is OCM divider across the differential voltage outputs and comparing independent of the input common-mode voltage. The AD8139 the signal at the midpoint of the divider with the magnitude of has an H-bridge input stage for high slew rate, low noise, and the differential output. By this definition, output balance is low distortion operation and rail-to-rail output stages that equal to the magnitude of the change in output common-mode provide maximum dynamic output range. This set of features voltage divided by the magnitude of the change in output allows for convenient single-ended-to-differential conversion, a differential-mode voltage: common need to take advantage of modern high resolution ΔV ADCs with differential inputs. O, cm Output Balance= (3) ΔV O, dm TYPICAL CONNECTION AND DEFINITION OF TERMS The block diagram of the AD8139 in Figure 60 shows the external differential feedback loop (R /R networks and the Figure 59 shows a typical connection for the AD8139, using F G matched external RF/RG networks. The differential input differential input transconductance amplifier, GDIFF) and the terminals of the AD8139, VAP and VAN, are used as summing internal common-mode feedback loop (voltage divider across junctions. An external reference voltage applied to the V VOP and VON and the common-mode input transconductance OCM terminal sets the output common-mode voltage. The two amplifier, GCM). The differential negative feedback drives the output terminals, V and V , move in opposite directions in a voltages at the summing junctions VAN and VAP to be essentially OP ON balanced fashion in response to an input signal. equal to each other. C F V = V (4) AN AP The common-mode feedback loop drives the output common- R F mode voltage, sampled at the midpoint of the two 500 Ω resistors, R G V V AP ON V – IP + to equal the voltage set at the VOCM terminal. This ensures that V OCM R V AD8139 L, dm O, dm V R O, dm G V V AN OP V V = V + (5) – IN + OP OCM 2 R F and V O, dm C F V = V − (6) ON OCM 2 Figure 59. Typical Connection R R G F V IN The differential output voltage is defined as 10pF VO, dm = VOP − VON (1) + G V O OP Common-mode voltage is the average of two voltages. The 500Ω output common-mode voltage is defined as MIDSUPPLY V AN G G CM 500Ω DIFF V + V OP ON V V AP OCM V = (2) O, cm 2 G V O Output Balance ON + Output balance is a measure of how well VOP and VON are 10pF matched in amplitude and how precisely they are 180° out of V IP R R G F phase with each other. It is the internal common-mode feedback Figure 60. Block Diagram loop that forces the signal component of the output common-mode towards zero, resulting in the near perfectly balanced differential Rev. B | Page 18 of 24 04679-050 04679-051 AD8139 APPLICATIONS Voltage Gain ESTIMATING NOISE, GAIN, AND BANDWIDTH The behavior of the node voltages of the single-ended-to- WITH MATCHED FEEDBACK NETWORKS differential output topology can be deduced from the previous Estimating Output Noise Voltage definitions. Referring to Figure 59, (C = 0) and setting V = 0, F IN The total output noise is calculated as the root-sum-squared one can write total of several statistically independent sources. Because the V −V V −V IP sources are statistically independent, the contributions of each AP AP ON = (11) R R G F must be individually included in the root-sum-square calculation. Table 6 lists recommended resistor values and estimates of R ⎡ ⎤ G V = V = V (12) bandwidth and output differential voltage noise for various AN AP OP ⎢ ⎥ R + R F G ⎣ ⎦ closed-loop gains. For most applications, 1% resistors are Solving the above two equations and setting V to V gives the sufficient. IP i gain relationship for VO, dm/Vi. Table 6. Recommended Values of Gain-Setting Resistors and R F Voltage Noise for Various Closed-Loop Gains V − V = V = V (13) OP ON O, dm i R G 3 dB Total Output Gain RG (Ω) RF (Ω) Bandwidth (MHz) Noise (nV/√Hz) An inverting configuration with the same gain magnitude can 1 200 200 400 5.8 be implemented by simply applying the input signal to VIN and 2 200 400 160 9.3 setting VIP = 0. For a balanced differential input, the gain from 5 200 1 k 53 19.7 V to V is also equal to R /R , where V = V − V . IN, dm O, dm F G IN, dm IP IN 10 200 2 k 26 37 Feedback Factor Notation When working with differential amplifiers, it is convenient to The differential output voltage noise contains contributions introduce the feedback factor β, which is defined as from the input voltage noise and input current noise of the R AD8139 as well as those from the external feedback networks. G β= (14) R + R F G The contribution from the input voltage noise spectral density is computed as This notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are ⎛ ⎞ R F ⎜ ⎟ Vo_n1= v 1+ , or equivalently, v/β (7) n not matched. n ⎜ ⎟ R G ⎝ ⎠ Input Common-Mode Voltage where vn is defined as the input-referred differential voltage The linear range of the VAN and VAP terminals extends to within noise. This equation is the same as that of traditional op amps. approximately 1 V of either supply rail. Because VAN and VAP are The contribution from the input current noise of each input is essentially equal to each other, they are both equal to the input computed as common-mode voltage of the amplifier. Their range is indicated in the Specifications tables as input common-mode range. The Vo_n2 = in (RF) (8) voltage at V and V for the connection diagram in Figure 59 AN AP where in is defined as the input noise current of one input. can be expressed as Each input needs to be treated separately because the two V = V = V = input currents are statistically independent processes. AN AP ACM R (V +V ) R ⎛ ⎞ ⎛ ⎞ The contribution from each R is computed as F IP IN G G ⎜ × ⎟+⎜ ×V ⎟ (15) OCM R + R 2 R + R F G F G ⎝ ⎠ ⎝ ⎠ ⎛ ⎞ R F ⎜ ⎟ Vo_n3= 4kTR (9) G ⎜ ⎟ where VACM is the common-mode voltage present at the R ⎝ G⎠ amplifier input terminals. This result can be intuitively viewed as the thermal noise of Using the β notation, Equation 15 can be written as follows: each R multiplied by the magnitude of the differential gain. G VACM = βVOCM + (1 − β)VICM (16) The contribution from each RF is computed as or equivalently, Vo_n4 = √4kTRF (10) V = V + β(V − V) (17) ACM ICM OCM ICM where V is the common-mode voltage of the input signal, ICM that is, VICM = VIP + VIN/2. Rev. B | Page 19 of 24 AD8139 For proper operation, the voltages at V and V must stay The input impedance of a conventional inverting op amp AN AP within their respective linear ranges. configuration is simply R , but it is higher in Equation 19 G because a fraction of the differential output voltage appears at Calculating Input Impedance the summing junctions, VAN and VAP. This voltage partially The input impedance of the circuit in Figure 59 depends on bootstraps the voltage across the input resistor RG, leading to whether the amplifier is being driven by a single-ended or a the increased input resistance. differential signal source. For balanced differential input Input Common-Mode Swing Considerations signals, the differential input impedance (R ) is simply IN, dm In some single-ended-to-differential applications, when using a R = 2R (18) IN, dm G single-supply voltage, attention must be paid to the swing of the For a single-ended signal (for example, when V is grounded IN input common-mode voltage, V . ACM and the input signal drives VIP), the input impedance becomes Consider the case in Figure 61, where VIN is 5 V p-p swinging R G about a baseline at ground, and VREF is connected to ground. R = (19) IN R F 1− The circuit has a differential gain of 1.6 and β = 0.38. VICM has 2(R + R ) G F an amplitude of 2.5 V p-p and is swinging about ground. Using the results in Equation 16, the common-mode voltage at the inputs of the AD8139, V , is a 1.5 V p-p signal swinging ACM about a baseline of 0.95 V. The maximum negative excursion of VACM in this case is 0.2 V, which exceeds the lower input common-mode voltage limit. 5V 20Ω 0.1µF 0.1µF 0.1µF 324Ω 15Ω 3 2.7nF 200Ω 8 5 + AVDD DVDD V OCM 2 IN– 2.5V AD8139 +2.5V 1 V – GND IN AD7674 4 –2.5V 6 V IN+ REF 200Ω 324Ω 15Ω DGND AGND REFGND REF REFBUFIN PDBUF 2.7nF 47µF +1.7V V ACM +0.95V WITH V = 0 REF +0.2V ADR431 0.1µF 2.5V REFERENCE Figure 61. AD8139 Driving AD7674, 18-Bit, 800 kSPS ADC Rev. B | Page 20 of 24 04679-052 AD8139 One way to avoid the input common-mode swing limitation is Estimating DC Errors to bias V and V at midsupply. In this case, V is 5 V p-p IN REF IN Primary differential output offset errors in the AD8139 are due swinging about a baseline at 2.5 V, and V is connected to a REF to three major components: the input offset voltage, the offset low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and between the VAN and VAP input currents interacting with the is swinging about 2.5 V. Using the results in Equation 17, VACM feedback network resistances, and the offset produced by the dc is calculated to be equal to VICM because VOCM = VICM. Therefore, voltage difference between the input and output common-mode VACM swings from 1.25 V to 3.75 V, which is well within the voltages in conjunction with matching errors in the feedback input common-mode voltage limits of the AD8139. Another network. benefit seen in this example is that because V = V = V OCM ACM ICM The first output error component is calculated as no wasted common-mode current flows. Figure 62 illustrates how to provide the low-Z bias voltage. For situations that do not ⎛ ⎞ R + R F G ⎜ ⎟ Vo _e1= V , or equivalently as VIO/β (21) IO require a precise reference, a simple voltage divider suffices to ⎜ ⎟ R ⎝ G ⎠ develop the input voltage to the buffer. where VIO is the input offset voltage. The input offset voltage of the 5V AD8139 is laser trimmed and guaranteed to be less than 500 μV. 0.1µF 324Ω The second error is calculated as 3 200Ω 8 5 ⎛ ⎞⎛ ⎞ R + R R R + F G G F ⎜ ⎟⎜ ⎟ Vo_e2= I = I() R (22) V IO IO F OCM 2 ⎜ ⎟⎜ ⎟ V IN R R + R AD8139 G F G ⎝ ⎠⎝ ⎠ 0V TO 5V 1 – 4 where I is defined as the offset between the two input bias IO 6 currents. 200Ω 324Ω 5V TO AD7674 REFBUFIN The third error voltage is calculated as 0.1µF Vo_e3 = Δenr × (V − V) (23) ICM OCM 0.1µF + ADR431 + 10µF where Δenr is the fractional mismatch between the two 2.5V REFERENCE AD8031 feedback resistors. – The total differential offset error is the sum of these three error sources. Figure 62. Low-Z 2.5 V Buffer Other Impact of Mismatches in the Feedback Networks Another way to avoid the input common-mode swing limitation is The internal common-mode feedback network still forces the to use dual power supplies on the AD8139. In this case, the output voltages to remain balanced, even when the RF/RG feedback biasing circuitry is not required. networks are mismatched. However, the mismatch will cause a gain error proportional to the feedback network mismatch. Bandwidth vs. Closed-Loop Gain The 3 dB bandwidth of the AD8139 decreases proportionally Ratio-matching errors in the external resistors degrade the ability to reject common-mode signals at the V and V input to increasing closed-loop gain in the same way as a traditional AN IN terminals, much the same as with a four-resistor difference voltage feedback operational amplifier. For closed-loop gains amplifier made from a conventional op amp. Ratio-matching greater than 4, the bandwidth obtained for a specific gain can be estimated as errors also produce a differential output component that is equal to the VOCM input voltage times the difference between the R G f− 3 dB,V = ×(300 MHz) (20) feedback factors (βs). In most applications using 1% resistors, OUT ,dm R + R F G this component amounts to a differential dc offset at the output or equivalently, β(300 MHz). that is small enough to be ignored. This estimate assumes a minimum 90° phase margin for the amplifier loop, which is a condition approached for gains greater than 4. Lower gains show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin. Rev. B | Page 21 of 24 04679-053 AD8139 Driving a Capacitive Load The input resistance presented by the AD8139 input circuitry is seen in parallel with the termination resistor, and its loading A purely capacitive load reacts with the bondwire and pin effect must be taken into account. The Thevenin equivalent inductance of the AD8139, resulting in high frequency ringing circuit of the driver, its source resistance, and the termination in the transient response and loss of phase margin. One way to resistance must all be included in the calculation as well. An minimize this effect is to place a small resistor in series with exact solution to the problem requires the solution of several each output to buffer the load capacitance (see Figure 58 and simultaneous algebraic equations and is beyond the scope of Figure 63). The resistor and load capacitance form a first-order, this data sheet. An iterative solution is also possible and simpler, low-pass filter; therefore, the resistor value should be as small as especially considering the fact that standard 1% resistor values possible. In some cases, the ADCs require small series resistors are generally used. to be added on their inputs. 5 Figure 64 shows the AD8139 in a unity-gain configuration R = 30.1Ω S 4 R = 30.1Ω S C = 5pF L driving the AD6645, which is a 14-bit, high speed ADC, and C = 15pF 3 L 2 with the following discussion, provides a good example of how 1 to provide a proper termination in a 50 Ω environment. 0 R = 0Ω S –1 C = 0pF L, dm The termination resistor, RT, in parallel with the 268 Ω input –2 R = 60.4Ω S –3 resistance of the AD8139 circuit (calculated using Equation 19), C = 15pF L –4 yields an overall input resistance of 50 Ω that is seen by the –5 –6 signal source. To have matched feedback loops, each loop must –7 R = 60.4Ω S have the same RG if they have the same RF. In the input (upper) –8 C = 5pF L –9 loop, RG is equal to the 200 Ω resistor in series with the (+) V = ±5V S –10 V = 0.1V p-p O, dm input plus the parallel combination of RT and the source –11 G = 1 (R = R = 200Ω) F G –12 R = 1kΩ resistance of 50 Ω. In the upper loop, RG is therefore equal to L, dm –13 10M 100M 1G 228 Ω. The closest standard 1% value to 228 Ω is 226 Ω and is FREQUENCY (Hz) used for R in the lower loop. Greater accuracy could be G Figure 63. Frequency Response for achieved by using two resistors in series to obtain a resistance Various Capacitive Load and Series Resistance closer to 228 Ω. The Typical Performance Characteristics that illustrate transient Things get more complicated when it comes to determining response vs. the capacitive load were generated using series the feedback resistor values. The amplitude of the signal source resistors in each output and a differential capacitive load. generator VS is two times the amplitude of its output signal Layout Considerations when terminated in 50 Ω. Therefore, a 2 V p-p terminated amplitude is produced by a 4 V p-p amplitude from V . The S Standard high speed PCB layout practices should be adhered to Thevenin equivalent circuit of the signal source and R must T when designing with the AD8139. A solid ground plane is be used when calculating the closed-loop gain, because in recommended, and good wideband power supply decoupling the upper loop, R is split between the 200 Ω resistor and G networks should be placed as close as possible to the supply pins. the Thevenin resistance looking back toward the source. The To minimize stray capacitance at the summing nodes, the Thevenin voltage of the signal source is greater than the signal copper in all layers under all traces and pads that connect to source output voltage when terminated in 50 Ω because RT the summing nodes should be removed. Small amounts of stray must always be greater than 50 Ω. In this case, RT is 61.9 Ω and summing-node capacitance cause peaking in the frequency the Thevenin voltage and resistance are 2.2 V p-p and 28 Ω, response, and large amounts can cause instability. If some stray respectively. Now the upper input branch can be viewed as a summing-node capacitance is unavoidable, its effects can be 2.2 V p-p source in series with 228 Ω. Because this is a unity- compensated for by placing small capacitors across the feedback gain application, a 2 V p-p differential output is required, and resistors. RF must therefore be 228 × (2/2.2) = 206 Ω. The closest Terminating a Single-Ended Input standard value to this is 205 Ω. Controlled impedance interconnections are used in most When generating the Typical Performance Characteristics data, high speed signal applications, and they require at least one the measurements were calibrated to take the effects of the line termination. In analog applications, a matched resistive terminations on the closed-loop gain into account. termination is generally placed at the load end of the line. This section deals with how to properly terminate a single-ended input to the AD8139. Rev. B | Page 22 of 24 CLOSED LOOP GAIN (dB) 04679-076 AD8139 Because this is a single-ended-to-differential application on a Exposed Paddle (EP) single supply, the input common-mode voltage swing must be The 8-lead SOIC and the 8-lead LFCSP have an exposed paddle checked. From Figure 64, β = 0.52, V = 2.4 V, and V is OCM ICM on the bottom of the package. To achieve the specified thermal 1.1 V p-p swinging about ground. Using Equation 16, VACM is resistance, the exposed paddle must be soldered to one of the calculated to be 0.53 V p-p swinging about a baseline of 1.25 V, PCB planes. The exposed paddle mounting pad should contain and the minimum negative excursion is approximately 1 V. several thermal vias within it to ensure a low thermal path to the plane. 5V 3.3V 0.01µF 0.01µF 0.01µF 205Ω 25Ω AV DV CC CC AIN 3 2V p-p 50Ω 200Ω 8 5 + R T V V OCM 2 S AD8139 61.9Ω SIGNAL AD6645 1 SOURCE – 4 226Ω 6 AIN GND C1 C2 VREF 205Ω 25Ω 0.1µF 0.1µF 2.4V Figure 64. AD8139 Driving AD6645, 14-Bit, 80 MSPS/105 MSPS ADC Rev. B | Page 23 of 24 04679-054 AD8139 OUTLINE DIMENSIONS 5.00 (0.197) 4.90 (0.193) 2.29 (0.090) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 2.29 (0.090) 3.80 (0.150) 85 6.20 (0.244) TOP VIEW 6.00 (0.236) 1 4 5.80 (0.228) BOTTOM VIEW 1.27 (0.05) (PINS UP) BSC 0.50 (0.020) 45° 1.65 (0.065) 1.75 (0.069) 0.25 (0.010) 1.25 (0.049) 1.35 (0.053) 1.27 (0.050) 0.10 (0.004) SEATING 8° MAX PLANE 0.40 (0.016) 0° 0.25 (0.0098) 0.51 (0.020) COPLANARITY 0.17 (0.0067) 0.10 0.31 (0.012) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 65. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1)—Dimensions shown in millimeters and (inches) 3.25 0.60 MAX 3.00 SQ 0.50 2.75 BSC 0.60 MAX 5 8 2.95 1.60 2.75 SQ EXPOSED TOP 1.45 PIN 1 PAD VIEW 2.55 INDICATOR (BOTTOM VIEW) 1.30 4 1 PIN 1 0.50 INDICATOR 1.89 0.40 1.74 12° MAX 0.30 0.70 MAX 1.59 0.90 MAX 0.65 TYP 0.85 NOM 0.05 MAX 0.01 NOM 0.30 SEATING PLANE 0.23 0.20 REF 0.18 Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2)—Dimensions shown in millimeters ORDERING GUIDE Package Model Temperature Range Package Description Option Branding AD8139ARD –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) RD-8-1 AD8139ARD-REEL –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) RD-8-1 AD8139ARD-REEL7 –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) RD-8-1 1 AD8139ARDZ –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) RD-8-1 1 AD8139ARDZ-REEL –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) RD-8-1 1 AD8139ARDZ-REEL7 –40°C to +125°C 8-Lead Small Outline Package with Exposed Pad (SOIC_N_EP) RD-8-1 AD8139ACP-R2 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HEB AD8139ACP-REEL –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HEB AD8139ACP-REEL7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HEB 1 AD8139ACPZ-R2 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HEB# 1 AD8139ACPZ-REEL –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HEB# 1 AD8139ACPZ-REEL7 –40°C to +125°C 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) CP-8-2 HEB# 1 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04679-0-10/07(B) Rev. B | Page 24 of 24 060506- A 061507-B