ANALOG DEVICES AD8138

Low Distortion Differential ADC Driver AD8138 FEATURES PIN CONFIGURATION Easy to use, single-ended-to-differential conversion –IN 1 8 +IN Adjustable output common-mode voltage V 7 NC 2 OCM Externally adjustable gain V+ 3 6 V– +OUT 4 5 –OUT Low harmonic distortion AD8138 −94 dBc SFDR @ 5 MHz NC = NO CONNECT −85 dBc SFDR @ 20 MHz Figure 1. −3 dB bandwidth of 320 MHz, G = +1 TYPICAL APPLICATION CIRCUIT Fast settling to 0.01% of 16 ns 5V Slew rate 1150 V/μs 5V 499Ω Fast overdrive recovery of 4 ns 499Ω Low input voltage noise of 5 nV/√Hz AVDD DVDD V + IN AIN V OCM 1 mV typical offset voltage DIGITAL ADC AD8138 OUTPUTS 499Ω Wide supply range +3 V to ±5 V AIN – V AVSS REF Low power 90 mW on 5 V 499Ω 0.1 dB gain flatness to 40 MHz Available in 8-Lead SOIC and MSOP packages Figure 2. APPLICATIONS ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers GENERAL DESCRIPTION The AD8138 is a major advancement over op amps for The AD8138 eliminates the need for a transformer with high differential signal processing. The AD8138 can be used as a performance ADCs, preserving the low frequency and dc infor- single-ended-to-differential amplifier or as a differential-to- mation. The common-mode level of the differential output is differential amplifier. The AD8138 is as easy to use as an op adjustable by a voltage on the V pin, easily level-shifting the OCM amp and greatly simplifies differential signal amplification and input signals for driving single-supply ADCs. Fast overload driving. Manufactured on ADI’s proprietary XFCB bipolar recovery preserves sampling accuracy. process, the AD8138 has a −3 dB bandwidth of 320 MHz and The AD8138 distortion performance makes it an ideal ADC delivers a differential signal with the lowest harmonic distortion driver for communication systems, with distortion performance available in a differential amplifier. The AD8138 has a unique good enough to drive state-of-the-art 10-bit to 16-bit converters internal feedback feature that provides balanced output gain at high frequencies. The AD8138’s high bandwidth and IP3 also and phase matching, suppressing even order harmonics. The make it appropriate for use as a gain block in IF and baseband internal feed-back circuit also minimizes any gain error that signal chains. The AD8138 offset and dynamic performance would be associated with the mismatches in the external gain makes it well suited for a wide variety of signal processing and setting resistors. data acquisition applications. The AD8138’s differential output helps balance the input to The AD8138 is available in both SOIC and MSOP packages for differential ADCs, maximizing the performance of the ADC. operation over −40°C to +85°C temperatures. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 01073-001 01073-002 AD8138 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications....................................................................................... 1 Analyzing an Application Circuit ............................................ 17 Pin Configuration............................................................................. 1 Setting the Closed-Loop Gain .................................................. 17 Typical Application Circuit ............................................................. 1 Estimating the Output Noise Voltage...................................... 17 General Description ......................................................................... 1 The Impact of Mismatches in the Feedback Networks......... 18 Revision History ............................................................................... 2 Calculating an Application Circuit’s Input Impedance......... 18 Specifications..................................................................................... 3 Input Common-Mode Voltage Range in Single-Supply Applications ................................................................................ 18 ±D to ±OUT Specifications...................................................... 3 IN Setting the Output Common-Mode Voltage .......................... 18 VOCM to ±OUT Specifications ..................................................... 4 Driving a Capacitive Load......................................................... 18 ±DIN to ±OUT Specifications...................................................... 5 Layout, Grounding, and Bypassing.............................................. 19 VOCM to ±OUT Specifications ..................................................... 6 Balanced Transformer Driver ....................................................... 20 Absolute Maximum Ratings............................................................ 7 High Performance ADC Driving ................................................. 21 Thermal Resistance ...................................................................... 7 3 V Operation ................................................................................. 22 ESD Caution.................................................................................. 7 Outline Dimensions....................................................................... 23 Pin Configuration and Function Descriptions............................. 8 Ordering Guide .......................................................................... 23 Typical Performance Characteristics ............................................. 9 Test Circuits..................................................................................... 15 Operational Description................................................................ 16 Definition of Terms.................................................................... 16 REVISION HISTORY 7/02—Rev. C to Rev. D Addition of TPC 35 and TPC 36 .....................................................8 1/06—Rev. E to Rev. F Changes to Features.......................................................................... 1 6/01—Rev. B to Rev. C Added Thermal Resistance Section and Maximum Power Edits to Specifications ......................................................................2 Dissipation Section........................................................................... 7 Edits to Ordering Guide ...................................................................4 Changes to Balanced Transformer Driver Section..................... 20 Changes to Ordering Guide .......................................................... 23 12/00—Rev. A to Rev. B 9/99—Rev. 0 to Rev. A 3/03—Rev. D to Rev. E 3/99—Rev. 0: Initial Version Changes to Specifications................................................................ 2 Changes to Ordering Guide ............................................................ 4 Changes to TPC 16........................................................................... 6 Changes to Table I ............................................................................ 9 Added New Paragraph after Table I ............................................. 10 Updated Outline Dimensions ....................................................... 14 Rev. F | Page 2 of 24 AD8138 SPECIFICATIONS ±D to ±OUT SPECIFICATIONS IN At 25°C, V = ±5 V, V = 0, G = +1, R = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All S OCM L, dm specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth V = 0.5 V p-p, C = 0 pF 290 320 MHz OUT F V = 0.5 V p-p, C = 1 pF 225 MHz OUT F Bandwidth for 0.1 dB Flatness VOUT = 0.5 V p-p, CF = 0 pF 30 MHz Large Signal Bandwidth VOUT = 2 V p-p, CF = 0 pF 265 MHz Slew Rate VOUT = 2 V p-p, CF = 0 pF 1150 V/μs Settling Time 0.01%, V = 2 V p-p, C = 1 pF 16 ns OUT F Overdrive Recovery Time V = 5 V to 0 V step, G = +2 4 ns IN 1 NOISE/HARMONIC PERFORMANCE Second Harmonic V = 2 V p-p, 5 MHz, R = 800 Ω −94 dBc OUT L, dm V = 2 V p-p, 20 MHz, R = 800 Ω −87 dBc OUT L, dm V = 2 V p-p, 70 MHz, R = 800 Ω −62 dBc OUT L, dm Third Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −114 dBc VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −85 dBc VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω −57 dBc IMD 20 MHz −77 dBc IP3 20 MHz 37 dBm Voltage Noise (RTI) f = 100 kHz to 40 MHz 5 nV/√Hz Input Current Noise f = 100 kHz to 40 MHz 2 pA/√Hz INPUT CHARACTERISTICS Offset Voltage VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V −2.5 ±1 +2.5 mV TMIN to TMAX variation ±4 μV/°C Input Bias Current 3.5 7 μA T to T variation −0.01 μA/°C MIN MAX Input Resistance Differential 6 MΩ Common mode 3 MΩ Input Capacitance 1 pF Input Common-Mode Voltage −4.7 to +3.4 V CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V −77 −70 dB OUTPUT CHARACTERISTICS Output Voltage Swing Maximum ∆VOUT; single-ended output 7.75 V p-p Output Current 95 mA Output Balance Error ∆V /∆V ; ∆V = 1 V −66 dB OUT, cm OUT, dm OUT, dm 1 Harmonic distortion performance is equal or slightly worse with higher values of R . See Figure 17 and Figure 18 for more information. L, dm Rev. F | Page 3 of 24 AD8138 V to ±OUT SPECIFICATIONS OCM At 25°C, VS = ±5 V, VOCM = 0, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 250 MHz Slew Rate 330 V/μs INPUT VOLTAGE NOISE (RTI) f = 0.1 MHz to 100 MHz 17 nV/√Hz DC PERFORMANCE Input Voltage Range ±3.8 V Input Resistance 200 kΩ Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 0 V –3.5 ±1 +3.5 mV Input Bias Current 0.5 μA V CMRR ∆V /∆V ; ∆V = ±1 V −75 dB OCM OUT, dm OCM OCM Gain ∆V /∆V ; ∆V = ±1 V 0.9955 1 1.0045 V/V OUT, cm OCM OCM POWER SUPPLY Operating Range ±1.4 ±5.5 V Quiescent Current 18 20 23 mA TMIN to TMAX variation 40 μA/°C Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ±1 V −90 −70 dB OPERATING TEMPERATURE RANGE −40 +85 °C Rev. F | Page 4 of 24 AD8138 ±D to ±OUT SPECIFICATIONS IN At 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential output, unless otherwise noted. Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth VOUT = 0.5 V p-p, CF = 0 pF 280 310 MHz VOUT = 0.5 V p-p, CF = 1 pF 225 MHz Bandwidth for 0.1 dB Flatness V = 0.5 V p-p, C = 0 pF 29 MHz OUT F Large Signal Bandwidth V = 2 V p-p, C = 0 pF 265 MHz OUT F Slew Rate V = 2 V p-p, C = 0 pF 950 V/μs OUT F Settling Time 0.01%, VOUT = 2 V p-p, CF = 1 pF 16 ns Overdrive Recovery Time VIN = 2.5 V to 0 V step, G = +2 4 ns 1 NOISE/HARMONIC PERFORMANCE Second Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −90 dBc VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −79 dBc V = 2 V p-p, 70 MHz, R = 800 Ω −60 dBc OUT L, dm Third Harmonic V = 2 V p-p, 5 MHz, R = 800 Ω −100 dBc OUT L, dm V = 2 V p-p, 20 MHz, R = 800 Ω −82 dBc OUT L, dm VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω −53 dBc IMD 20 MHz −74 dBc IP3 20 MHz 35 dBm Voltage Noise (RTI) f = 100 kHz to 40 MHz 5 nV/√Hz Input Current Noise f = 100 kHz to 40 MHz 2 pA/√Hz INPUT CHARACTERISTICS Offset Voltage V = V /2; V = V = V = 0 V −2.5 ±1 +2.5 mV OS, dm OUT, dm DIN+ DIN– OCM T to T variation ±4 μV/°C MIN MAX Input Bias Current 3.5 7 μA TMIN to TMAX variation −0.01 μA/°C Input Resistance Differential 6 MΩ Common mode 3 MΩ Input Capacitance 1 pF Input Common-Mode Voltage −0.3 to +3.2 V CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = 1 V −77 −70 dB OUTPUT CHARACTERISTICS Output Voltage Swing Maximum ∆V ; single-ended output 2.9 V p-p OUT Output Current 95 mA Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V −65 dB 1 Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information. Rev. F | Page 5 of 24 AD8138 V TO ±OUT SPECIFICATIONS OCM At 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All specifications refer to single-ended input and differential output, unless otherwise noted. Table 4. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 220 MHz Slew Rate 250 V/μs INPUT VOLTAGE NOISE (RTI) f = 0.1 MHz to 100 MHz 17 nV/√Hz DC PERFORMANCE Input Voltage Range 1.0 to 3.8 V Input Resistance 100 kΩ Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 0 V −5 ±1 +5 mV Input Bias Current 0.5 μA V CMRR ∆V /∆V ; ∆V = 2.5 V ±1 V −70 dB OCM OUT, dm OCM OCM Gain ∆V /∆V ; ∆V = 2.5 V ±1 V 0.9968 1 1.0032 V/V OUT, cm OCM OCM POWER SUPPLY Operating Range 2.7 11 V Quiescent Current 15 20 21 mA TMIN to TMAX variation 40 μA/°C Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ± 1 V −90 −70 dB OPERATING TEMPERATURE RANGE −40 +85 °C Rev. F | Page 6 of 24 AD8138 ABSOLUTE MAXIMUM RATINGS Table 5. The power dissipated in the package (PD) is the sum of the Parameter Ratings quiescent power dissipation and the power dissipated in the Supply Voltage ±5.5 V package due to the load drive for all outputs. The quiescent V ±V OCM S power is the voltage between the supply pins (V ) times the S Internal Power Dissipation 550 mW quiescent current (I ). The load current consists of the differential S Operating Temperature Range −40°C to +85°C and common-mode currents flowing to the load, as well as Storage Temperature Range −65°C to +150°C currents flowing through the external feedback networks and Lead Temperature (Soldering 10 sec) 300°C internal common-mode feedback loop. The internal resistor tap Junction Temperature 150°C used in the common-mode feedback loop places a negligible differential load on the output. RMS voltages and currents Stresses above those listed under Absolute Maximum Ratings should be considered when dealing with ac signals. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Airflow reduces θ . In addition, more metal directly in contact JA other conditions above those indicated in the operational with the package leads from metal traces through holes, ground, section of this specification is not implied. Exposure to absolute and power planes reduces the θ . JA maximum rating conditions for extended periods may affect device reliability. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC THERMAL RESISTANCE (121°C/W) and 8-lead MSOP (θJA = 145°C/W) packages on a θ is specified for the worst-case conditions, that is, θ is JA JA JEDEC standard 4-layer board. θJA values are approximations. specified for the device soldered in a circuit board in still air. 1.75 Table 6. 1.50 Package Type θJA Unit 8-Lead SOIC/4-Layer 121 °C/W 1.25 8-Lead MSOP/4-Layer 145 °C/W 1.00 SOIC Maximum Power Dissipation 0.75 The maximum safe power dissipation in the AD8138 packages MSOP is limited by the associated rise in junction temperature (TJ) on 0.50 the die. At approximately 150°C, which is the glass transition 0.25 temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 package exerts on the die, permanently shifting the parametric AMBIENT TEMPERATURE (°C) performance of the AD8138. Exceeding a junction temperature Figure 3. Maximum Power Dissipation vs. Temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 7 of 24 MAXIMUM POWER DISSIPATION (W) 01073-049 AD8138 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS –IN 1 8 +IN V 2 7 NC OCM V+ 3 6 V– 4 5 +OUT –OUT AD8138 NC = NO CONNECT Figure 4. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input Summing Node. 2 VOCM Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on VOCM sets the dc bias level on +OUT and −OUT to 1 V. 3 V+ Positive Supply Voltage. 4 +OUT Positive Output. Note that the voltage at −D is inverted at +OUT (see Figure 42). IN 5 −OUT Negative Output. Note that the voltage at +D is inverted at −OUT (see Figure 42). IN 6 V− Negative Supply Voltage. 7 NC No Connect. 8 +IN Positive Input Summing Node. Rev. F | Page 8 of 24 01073-004 AD8138 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, Gain = 1, RG = RF = RL, dm = 499 V, TA = 25°C; refer to Figure 39 for test setup. 6 6 V =2Vp-p V =0.2Vp-p IN IN C =0pF C =0pF F F 3 3 V =+5V S V =+5V S 0 0 V =±5V S V =±5V S –3 –3 –6 –6 –9 –9 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response Figure 8. Large Signal Frequency Response 6 6 V =±5V V =2Vp-p S IN V =0.2Vp-p V =±5V IN S 3 3 C =0pF F C =0pF F 0 0 C =1pF F C =1pF F –3 –3 –6 –6 –9 –9 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response Figure 9. Large Signal Frequency Response 0.5 30 V =±5V S V =±5V S C =0pF F V =0.2Vp-p IN V =0.2V p-p OUT, dm R = 499Ω G 0.3 G = 10, R = 4.99kΩ F C =0pF F 20 G= 5,R = 2.49kΩ F 0.1 10 G=2, R =1kΩ F –0.1 C =1pF F G=1,R =499Ω F 0 –0.3 –0.5 –10 1 10 100 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. 0.1 dB Flatness vs. Frequency Figure 10. Small Signal Frequency Response for Various Gains Rev. F | Page 9 of 24 GAIN (dB) GAIN (dB) GAIN (dB) 01073-007 01073-006 01073-005 GAIN (dB) GAIN (dB) GAIN (dB) 01073-009 01073-008 01073-010 AD8138 –50 –60 V =2Vp-p OUT, dm V =±5V S R = 800Ω L R = 800Ω L HD3 (F = 20MHz) –60 –70 HD2 (F = 20MHz) –70 –80 HD2 (V =+5V) S –80 HD2 (V =±5V) S –90 –90 HD2 (F = 5MHz) –100 –100 HD3 (V =+5V) S HD3 (F = 5MHz) –110 –110 HD3 (V =±5V) S –120 –120 0 1020 30 40 5060 70 0 1 2 3 4 5 6 FUNDAMENTAL FREQUENCY (MHz) DIFFERENTIAL OUTPUT VOLTAGE (V p-p) Figure 11. Harmonic Distortion vs. Frequency Figure 14. Harmonic Distortion vs. Differential Output Voltage –40 –60 V =4Vp-p OUT, dm V =5V S R = 800Ω L R = 800Ω L –50 –70 HD3 (V =+5V) HD2 (F = 20MHz) S –60 –80 HD3 (F = 20MHz) –70 –90 HD2 (V =+5V) S HD2 (F = 5MHz) –80 HD2 (V =±5V) S –100 –90 HD3 (F = 5MHz) –110 –100 HD3 (V =±5V) S –120 –110 0 1020 30 40 5060 70 01 23 4 FUNDAMENTAL FREQUENCY (MHz) DIFFERENTIAL OUTPUT VOLTAGE (V p-p) Figure 12. Harmonic Distortion vs. Frequency Figure 15. Harmonic Distortion vs. Differential Output Voltage –30 –60 V =2V p-p V =3V S OUT, dm R =800Ω R = 800Ω L L F = 20MHz –40 O –70 HD3 (F = 20MHz) –50 HD2 (F = 20MHz) HD2 (V =+5V) S –80 –60 HD3 (V =+5V) S –70 –90 HD2 (F = 5MHz) –80 HD3 (V =±5V) S –100 HD3 (F = 5MHz) –90 HD2 (V =±5V) S –110 –100 0.25 0.50 0.75 1.00 1.25 1.50 1.75 –4 –3 –2 –1 012 34 DIFFERENTIAL OUTPUT VOLTAGE (V p-p) V DC OUTPUT (V) OCM Figure 16. Harmonic Distortion vs. Differential Output Voltage Figure 13. Harmonic Distortion vs. VOCM Rev. F | Page 10 of 24 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01073-013 01073-012 01073-011 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01073-015 01073-014 01073-016 AD8138 –60 45 R =800Ω L V =5V S V =2V p-p OUT, dm –70 40 HD2 (F = 20MHz) –80 V =±5V S HD3 (F = 20MHz) 35 –90 V =+5V S HD2 (F = 5MHz) 30 –100 HD3 (F = 5MHz) 25 –110 020 40 60 80 200 600 1000 1400 1800 FREQUENCY (MHz) R (Ω) LOAD Figure 17. Harmonic Distortion vs. RLOAD Figure 20. Third-Order Intercept vs. Frequency –60 V =±5V S V =±5V S V =2V p-p OUT, dm –70 V OUT, dm HD2 (F = 20MHz) HD3 (F = 20MHz) V –80 OUT– –90 V OUT+ HD2 (F = 5MHz) –100 V +DIN HD3 (F = 5MHz) –110 1V 5ns –120 200 600 1000 1400 1800 R (Ω) LOAD Figure 18. Harmonic Distortion vs. RLOAD Figure 21. Large Signal Transient Response 10 V =0.2Vp-p OUT, dm F =50MHz C V =±5V C =0pF S F V =±5V S –10 C =1pF –30 F –50 –70 –90 40mV 5ns –110 49.5 49.7 49.9 50.1 50.3 50.5 FREQUENCY (MHz) Figure 19. Intermodulation Distortion Figure 22. Small Signal Transient Response Rev. F | Page 11 of 24 P (dBm) OUT DISTORTION (dBc) DISTORTION (dBc) 01073-018 01073-017 01073-019 INTERCEPT (dBm) 01073-022 01073-021 01073-020 AD8138 V =2V p-p V =±5V OUT, dm S C =0pF F V OUT, dm V =+5V S V =±5V S F=20MHz V =8Vp-p +DIN G= 3(R = 1500) F V +DIN 400mV 5ns 4V 30ns Figure 23. Large Signal Transient Response Figure 26. Output Overdrive C =0pF V =2V p-p OUT, dm V =±5V F S V =±5V S C =0pF F C =10pF L C =5pF L C =1pF C = 20pF F L 400mV 5ns 400mV 2.5ns Figure 24. Large Signal Transient Response Figure 27. Large Signal Transient Response for Various Cap Loads (See Figure 40) –20 V =±5V S ΔV /ΔV 200µV V =±5V OUT, dm IN, cm S C =1pF –30 F V OUT, dm –40 –50 –60 –70 V +DIN –80 1V 4ns 110 100 1k FREQUENCY (MHz) Figure 28. CMRR vs. Frequency Figure 25. Settling Time Rev. F | Page 12 of 24 01073-023 01073-025 01073-024 CMRR (dB) 01073-028 01073-026 01073-029 AD8138 –20 5.0 V =2Vp-p IN –30 2.5 V =±5V S –40 V =+5V S 0 V =±5V S –50 V =+3V S –2.5 –60 V =+5V S –70 –5.0 1 10 100 1k –40 –20 0 20 40 60 80 100 FREQUENCY (MHz) TEMPERATURE (°C) Figure 29. Output Balance Error vs. Frequency (See Figure 41) Figure 32. Output Referred Differential Offset Voltage vs. Temperature –10 5 ΔV /ΔV OUT, dm S –20 –30 4 –PSRR (V =±5V) S V =±5V, +5V S –40 –50 3 –60 +PSRR V =+3V S (V = +5V, 0V AND ±5V) S –70 2 –80 –90 1 1 10 100 1k –40 –20 0 20 40 60 80 100 FREQUENCY (MHz) TEMPERATURE (°C) Figure 30. PSRR vs. Frequency Figure 33. Input Bias Current vs. Temperature 100 30 SINGLE-ENDED OUTPUT 25 10 V =±5V S 20 V =+5V S V =+5V S 15 1 V =+3V S 10 V =±5V S 0.1 5 1 10 100 –40 –20 0 20 40 60 80 100 FREQUENCY (MHz) TEMPERATURE (°C) Figure 31. Output Impedance vs. Frequency Figure 34. Supply Current vs. Temperature Rev. F | Page 13 of 24 IMPEDANCE (Ω) PSRR (dB) BALANCE ERROR (dB) 01073-032 01073-031 01073-033 SUPPLY CURRENT (mA) BIAS CURRENT (µA) DIFFERENTIAL OUTPUT OFFSET (mV) 01073-035 01073-036 01073-034 AD8138 100 6 V =+5V S V =±5V S 3 0 10 –3 1.1pA/ Hz –6 –9 1 10 100 1k 10k 100k 1M 1 10 100 1k FREQUENCY (MHz) FREQUENCY (Hz) Figure 35. V Frequency Response Figure 37. Current Noise (RTI) OCM 1000 V =±5V S V =–1V TO +1V OCM V OUT, cm 100 10 5.7nV/ Hz 1 400mV 5ns 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 36. V Transient Response OCM Figure 38. Voltage Noise (RTI) Rev. F | Page 14 of 24 GAIN (dB) 01073-038 01073-037 INPUT CURRENT NOISE (pA/ Hz) INPUT VOLTAGE NOISE (nV/ Hz) 01073-040 01073-039 AD8138 TEST CIRCUITS R = 499Ω 499Ω F R = 499Ω G 499Ω 249Ω 49.9Ω 49.9Ω AD8138 R =499Ω L, dm AD8138 R = 499Ω 249Ω G 499Ω 24.9Ω 24.9Ω 499Ω R = 499Ω F Figure 41. Test Circuit for Output Balance Figure 39. Basic Test Circuit 499Ω 499Ω 24.9Ω 49.9Ω C 453Ω AD8138 L 499Ω 24.9Ω 24.9Ω 499Ω Figure 40. Test Circuit for Cap Load Drive Rev. F | Page 15 of 24 01073-003 01073-027 01073-030 AD8138 OPERATIONAL DESCRIPTION DEFINITION OF TERMS Common-mode voltage refers to the average of two node C F voltages. The output common-mode voltage is defined as VOUT, cm = (V+OUT + V−OUT)/2 R F R Balance is a measure of how well differential signals are G +IN –OUT +D IN matched in amplitude and exactly 180° apart in phase. Balance V OCM AD8138 R V L, dm OUT, dm is most easily determined by placing a well-matched resistor –D IN –IN +OUT R divider between the differential voltage nodes and comparing G R F the magnitude of the signal at the divider’s midpoint with the C F magnitude of the differential signal (see Figure 41). By this definition, output balance is the magnitude of the output Figure 42. Circuit Definitions common-mode voltage divided by the magnitude of the output differential mode voltage: Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or V OUT , cm equivalently output differential-mode voltage) is defined as Output Balance Error= V OUT , dm V = (V − V ) OUT, dm +OUT −OUT where V and V refer to the voltages at the +OUT and +OUT −OUT −OUT terminals with respect to a common reference. Rev. F | Page 16 of 24 01073-041 AD8138 THEORY OF OPERATION The AD8138 differs from conventional op amps in that it has ANALYZING AN APPLICATION CIRCUIT two outputs whose voltages move in opposite directions. Like The AD8138 uses high open-loop gain and negative feedback to an op amp, it relies on high open-loop gain and negative force its differential and common-mode output voltages in such feedback to force these outputs to the desired voltages. The a way as to minimize the differential and common-mode error AD8138 behaves much like a standard voltage feedback op voltages. The differential error voltage is defined as the voltage amp and makes it easy to perform single-ended-to-differential between the differential inputs labeled +IN and −IN in Figure 42. conversion, common-mode level-shifting, and amplification of For most purposes, this voltage can be assumed to be zero. differential signals. Also like an op amp, the AD8138 has high Similarly, the difference between the actual output common- input impedance and low output impedance. mode voltage and the voltage applied to V can also be OCM assumed to be zero. Starting from these two assumptions, any Previous differential drivers, both discrete and integrated application circuit can be analyzed. designs, have been based on using two independent amplifiers and two independent feedback loops, one to control each of the SETTING THE CLOSED-LOOP GAIN outputs. When these circuits are driven from a single-ended Neglecting the capacitors C , the differential-mode gain of the F source, the resulting outputs are typically not well balanced. circuit in Figure 42 can be determined to be described by Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. S V OUT , dm R F = S V R DC common-mode level-shifting has also been difficult with OUT , dm G previous differential drivers. Level-shifting has required the use S S This assumes the input resistors, R , and feedback resistors, R , of a third amplifier and feedback loop to control the output G F on each side are equal. common-mode level. Sometimes the third amplifier has also been used to attempt to correct an inherently unbalanced ESTIMATING THE OUTPUT NOISE VOLTAGE circuit. Excellent performance over a wide frequency range Similar to the case of a conventional op amp, the differential has proven difficult with this approach. output errors (noise and offset voltages) can be estimated by The AD8138 uses two feedback loops to separately control the multiplying the input referred terms, at +IN and −IN, by the differential and common-mode output voltages. The differential circuit noise gain. The noise gain is defined as feedback, set with external resistors, controls only the differential ⎛ ⎞ R output voltage. The common-mode feedback controls only the F ⎜ ⎟ G = 1+ N ⎜ ⎟ common-mode output voltage. This architecture makes it easy R G ⎝ ⎠ to arbitrarily set the output common-mode level. It is forced, by To compute the total output referred noise for the circuit of internal common-mode feedback, to be equal to the voltage Figure 42, consideration must also be given to the contribution applied to the V input, without affecting the differential OCM of the Resistors R and R . Refer to Table 8 for the estimated F G output voltage. output noise voltage densities at various closed-loop gains. The AD8138 architecture results in outputs that are very highly Table 8. balanced over a wide frequency range without requiring tightly Output Output matched external components. The common-mode feedback Noise Noise loop forces the signal component of the output common-mode RG RF Bandwidth AD8138 AD8138 + voltage to be zeroed. The result is nearly perfectly balanced Gain (Ω) (Ω) −3 dB Only R , R G F differential outputs of identical amplitude and exactly 1 499 499 320 MHz 10 nV/√Hz 11.6 nV/√Hz 180° apart in phase. 2 499 1.0 k 180 MHz 15 nV/√Hz 18.2 nV/√Hz 5 499 2.49 k 70 MHz 30 nV/√Hz 37.9 nV/√Hz 10 499 4.99 k 30 MHz 55 nV/√Hz 70.8 nV/√Hz Rev. F | Page 17 of 24 AD8138 CALCULATING AN APPLICATION CIRCUIT’S INPUT When using the AD8138 in gain configurations where IMPEDANCE R F The effective input impedance of a circuit such as the one in R G Figure 42, at +DIN and –DIN, depends on whether the amplifier is being driven by a single-ended or differential signal source. For of one feedback network is unequal to balanced differential input signals, the input impedance (RIN, dm) R F between the inputs (+DIN and −DIN) is simply R G R =2 × R IN, dm G of the other network, there is a differential output noise due to In the case of a single-ended input signal (for example if −D is IN input-referred voltage in the VOCM circuitry. The output noise is grounded and the input signal is applied to +D ), the input IN defined in terms of the following feedback terms (refer to impedance becomes Figure 42): ⎛ ⎞ R ⎜ ⎟ G β = R 1 G ⎜ ⎟ R + R R = F G IN , dm R ⎜ ⎟ F 1− ⎜ ⎟ 2×() R + R ⎝ G F ⎠ for −OUT to +IN loop, and R G The circuit’s input impedance is effectively higher than it would β = 2 R + R be for a conventional op amp connected as an inverter because F G a fraction of the differential output voltage appears at the inputs for +OUT to −IN loop. With these defined, as a common-mode signal, partially bootstrapping the voltage across the input resistor R . G ⎡ ⎤ β−β 1 2 V = 2V ⎢ ⎥ nOUT , dm nIN ,V OCM β+β INPUT COMMON-MODE VOLTAGE RANGE IN ⎢ 1 2⎥ ⎣ ⎦ SINGLE-SUPPLY APPLICATIONS where V is the output differential noise, and is nOUT, dm V nIN ,V COM The AD8138 is optimized for level-shifting, ground-referenced the input-referred voltage noise in V . OCM input signals. For a single-ended input, this would imply, for example, that the voltage at −DIN in Figure 42 would be 0 V THE IMPACT OF MISMATCHES IN THE FEEDBACK when the amplifier’s negative power supply voltage (at V−) is NETWORKS also set to 0 V. As previously mentioned, even if the external feedback SETTING THE OUTPUT COMMON-MODE VOLTAGE networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The The AD8138’s VOCM pin is internally biased at a voltage amplitudes of the signals at each output remains equal and 180° approximately equal to the midsupply point (average value of out of phase. The input-to-output differential-mode gain varies the voltages on V+ and V−). Relying on this internal bias results proportionately to the feedback mismatch, but the output in an output common-mode voltage that is within about balance is unaffected. 100 mV of the expected value. Ratio matching errors in the external resistors result in a In cases where more accurate control of the output common- degradation of the circuit’s ability to reject input common- mode level is required, it is recommended that an external mode signals, much the same as for a four-resistor difference source, or resistor divider (made up of 10 kΩ resistors), be used. amplifier made from a conventional op amp. The output common-mode offset listed in the Specifications section assumes the VOCM input is driven by a low impedance In addition, if the dc levels of the input and output common- voltage source. mode voltages are different, matching errors result in a small differential-mode output offset voltage. For the G = 1 case, with DRIVING A CAPACITIVE LOAD a ground referenced input signal and the output common-mode A purely capacitive load can react with the pin and bondwire level set for 2.5 V, an output offset of as much as 25 mV (1% of inductance of the AD8138, resulting in high frequency ringing the difference in common-mode levels) can result if 1% tolerance in the pulse response. One way to minimize this effect is to resistors are used. Resistors of 1% tolerance result in a worst- place a small capacitor across each of the feedback resistors. The case input CMRR of about 40 dB, worst-case differential mode added capacitance should be small to avoid destabilizing the output offset of 25 mV due to 2.5 V level-shift, and no significant amplifier. An alternative technique is to place a small resistor in degradation in output balance error. series with the amplifier’s outputs, as shown in Figure 40. Rev. F | Page 18 of 24 AD8138 LAYOUT, GROUNDING, AND BYPASSING As a high speed part, the AD8138 is sensitive to the PCB The power supply pins should be bypassed as close as possible environment in which it has to operate. Realizing its superior to the device to the nearby ground plane. Good high frequency specifications requires attention to various details of good high ceramic chip capacitors should be used. This bypassing should speed PCB design. be done with a capacitance value of 0.01 μF to 0.1 μF for each supply. Further away, low frequency bypassing should be provided The first requirement is for a good solid ground plane that with 10 μF tantalum capacitors from each supply to ground. covers as much of the board area around the AD8138 as possible. The only exception to this is that the two input pins The signal routing should be short and direct to avoid parasitic (Pin 1 and Pin 8) should be kept a few millimeters from the effects. Wherever there are complementary signals, a symmetrical ground plane, and ground should be removed from inner layers layout should be provided to the extent possible to maximize and the opposite side of the board under the input pins. This the balance performance. When running differential signals minimizes the stray capacitance on these nodes and helps over a long distance, the traces on the PCB should be close preserve the gain flatness vs. frequency. together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This reduces the radiated energy and makes the circuit less susceptible to interference. Rev. F | Page 19 of 24 AD8138 BALANCED TRANSFORMER DRIVER Transformers are among the oldest devices used to perform a The well-balanced outputs of the AD8138 provide a drive signal single-ended-to-differential conversion (and vice versa). Trans- to each of the transformer’s primary inputs that are of equal formers can also perform the additional functions of galvanic amplitude and 180° out of phase. Therefore, depending on how isolation, step-up or step-down of voltages, and impedance the polarity of the secondary is connected, the signals that transformation. For these reasons, transformers always find conduct across the interwinding capacitance either both assist uses in certain applications. the transformer’s secondary signal equally, or both buck the secondary signals. In either case, the parasitic effect is However, when driving the transformer in a single-ended symmetrical and provides a well-balanced transformer output manner, there is an imbalance at the output due to the parasitics (see Figure 45). inherent in the transformer. The primary (or driven) side of the SIGNALIS COUPLED transformer has one side at dc potential (usually ground), while ON THIS SIDE VIA C STRAY the other side is driven. This can cause problems in systems that C STRAY require good balance of the transformer’s differential output 500Ω V UNBAL signals. 0.005% PRIMARY 52.3Ω SECONDARY V DIFF 500Ω 0.005% If the interwinding capacitance (C ) is assumed to be STRAY C STRAY uniformly distributed, a signal from the driving source couples to the secondary output terminal that is closest to the primary’s NO SIGNAL IS COUPLED ON THIS SIDE driven side. On the other hand, no signal is coupled to the Figure 43. Transformer Single-Ended-to-Differential Converter Is Inherently opposite terminal of the secondary because its nearest primary Imbalanced terminal is not driven (see Figure 43). The exact amount of this 499Ω imbalance depends on the particular parasitics of the trans- former, but is mostly a problem at higher frequencies. C STRAY 49.9Ω The balance of a differential circuit can be measured by 499Ω +IN 500Ω OUT– V 0.005% UNBAL connecting an equal-valued resistive voltage divider across the AD8138 V DIFF 499Ω differential outputs and then measuring the center point of the 500Ω OUT+ 0.005% –IN circuit with respect to ground. Since the two differential outputs 49.9Ω are supposed to be of equal amplitude, but 180° opposite phase, C STRAY 499Ω there should be no signal present for perfectly balanced outputs. Figure 44. AD8138 Forms a Balanced Transformer Driver The circuit in Figure 43 shows a Mini-Circuits® T1-6T 0 transformer connected with its primary driven single-endedly and the secondary connected with a precision voltage divider across its terminals. The voltage divider is made up of two –20 500 Ω, 0.005% precision resistors. The voltage VUNBAL, which is also equal to the ac common-mode voltage, is a measure of how V , FOR TRANSFORMER UNBAL –40 WITH SINGLE-ENDED DRIVE closely the outputs are balanced. Figure 45 compares the transformer being driven single- –60 endedly by a signal generator and being driven differentially using an AD8138. The top signal trace of Figure 45 shows the –80 balance of the single-ended configuration, while the bottom V , DIFFERENTIAL DRIVE UNBAL shows the differentially driven balance response. The 100 MHz balance is 35 dB better when using the AD8138. –100 0.3 1 10 100 500 FREQUENCY (MHz) Figure 45. Output Balance Error for Circuits of Figure 43 and Figure 44 Rev. F | Page 20 of 24 OUTPUT BALANCE ERROR (dB) 01073-042 01073-044 01073-043 AD8138 HIGH PERFORMANCE ADC DRIVING The circuit in Figure 46 shows a simplified front-end The signal generator has a ground-referenced, bipolar output, connection for an AD8138 driving an AD9224, a 12-bit, that is, it drives symmetrically above and below ground. 40 MSPS ADC. The ADC works best when driven differentially, Connecting VOCM to the CML pin of the AD9224 sets the output which minimizes its distortion. The AD8138 eliminates the common-mode of the AD8138 at 2.5 V, which is the midsupply need for a transformer to drive the ADC and performs single- level for the AD9224. This voltage is bypassed by a 0.1 μF ended-to-differential conversion, common-mode level-shifting, capacitor. and buffering of the driving signal. The full-scale analog input range of the AD9224 is set to The positive and negative outputs of the AD8138 are connected 4 V p-p, by shorting the SENSE terminal to AVSS. This has to the respective differential inputs of the AD9224 via a pair of been determined to be the scaling to provide minimum 49.9 Ω resistors to minimize the effects of the switched-capacitor harmonic distortion. front end of the AD9224. For best distortion performance, it For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p runs from supplies of ±5 V. while providing signals that are 180° out of phase. With a The AD8138 is configured with unity gain for a single-ended, common-mode voltage at the output of 2.5 V, each AD8138 input-to-differential output. The additional 23 Ω, 523 Ω total, at output swings between 1.5 V and 3.5 V. the input to −IN is to balance the parallel impedance of the A ground-referenced 4 V p-p, 5 MHz signal at D + was used to IN 50 Ω source and its 50 Ω termination that drives the Figure 46. When the combined-device circuit test the circuit in noninverting input. was run with a sampling rate of 20 MSPS, the spurious-free dynamic range (SFDR) was measured at −85 dBc. +5V +5V 0.1pF 0.1pF 499Ω 15 26 28 3 49.9Ω 499Ω AVDD DRVDD 8 5 + 24 VINB DIGITAL V OCM 50Ω 2 AD9224 OUTPUTS SOURCE 49.9Ω AD8138 523Ω 49.9Ω 1 4 23 VINA AVSS SENSE CML DRVSS 6 16 25 17 22 27 0.1pF 499Ω –5V Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC Rev. F | Page 21 of 24 01073-045 AD8138 3 V OPERATION The circuit in Figure 47 shows a simplified front-end The circuit was tested with a −0.5 dBFS signal at various connection for an AD8138 driving an AD9203, a 10-bit, frequencies. Figure 48 shows a plot of the total harmonic 40 MSPS ADC that is specified to work on a single 3 V supply. distortion (THD) vs. frequency at signal amplitudes of 1 V and The ADC works best when driven differentially to make the 2 V differential drive levels. best use of the signal swing available within the 3 V supply. –40 The appropriate outputs of the AD8138 are connected to the –45 appropriate differential inputs of the AD9203 via a low-pass filter. –50 The AD8138 is configured for unity gain for a single-ended input to differential output. The additional 23 Ω at the input to –55 AD8138–2V −IN is to balance the impedance of the 50 Ω source and its 50 Ω –60 termination that drives the noninverting input. –65 The signal generator has ground-referenced, bipolar output, AD8138–1V –70 that is, it can drive symmetrically above and below ground. Even though the AD8138 has ground as its negative supply, it –75 can still function as a level-shifter with such an input signal. –80 0 5 10 15 20 25 The output common mode is raised up to midsupply by the FREQUENCY (MHz) voltage divider that biases VOCM. In this way, the AD8138 Figure 48. AD9203 THD @ −0.5 dBFS AD8138 provides dc coupling and level-shifting of a bipolar signal, without inverting the input signal. Figure 49 shows the signal-to-noise-plus distortion (SINAD) under the same conditions as above. For the smaller signal The low-pass filter between the AD8138 and the AD9203 swing, the AD8138 performance is quite good, but its provides filtering that helps to improve the signal-to-noise ratio performance degrades when trying to swing too close to the (SNR). Lower noise can be realized by lowering the pole supply rails. frequency, but the bandwidth of the circuit is lowered. 65 3V 3V 63 499Ω 0.1µF 0.1µF 0.1µF 61 10kΩ 28 2 3 59 499Ω 49.9Ω AVDD DRVDD + 5 8 25 AINN 20pF 57 DIGITAL AD8138–1V 49.9Ω 2 AD9203 AD8138 OUTPUTS AINP 523Ω 49.9Ω 55 26 1 4 AVSS DRVSS 6 20pF AD8138–2V 27 1 0.1µF 53 499Ω 51 10kΩ 49 Figure 47. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter 47 45 0 5 10 15 20 25 FREQUENCY (MHz) Figure 49. AD9203 SINAD @ −0.5 dBFS AD8138 Rev. F | Page 22 of 24 01073-046 SINAD (dBc) THD (dBc) 01073-048 01073-047 AD8138 OUTLINE DIMENSIONS 3.20 3.00 5.00 (0.1968) 2.80 4.80 (0.1890) 85 8 5 5.15 6.20 (0.2440) 4.00 (0.1574) 3.20 4.90 5.80 (0.2284) 3.80 (0.1497) 1 4 3.00 4.65 1 2.80 4 1.27 (0.0500) 0.50 (0.0196) PIN 1 × 45° BSC 1.75 (0.0688) 0.25 (0.0099) 0.65 BSC 1.35 (0.0532) 0.25 (0.0098) 0.95 0.10 (0.0040) 0.85 1.10 MAX 8° 0.51 (0.0201) 0.75 0° 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) 0.80 SEATING 0.10 0.40 (0.0157) 8° 0.17 (0.0067) 0.15 PLANE 0.60 0.38 0.23 0° 0.00 0.40 0.22 0.08 COMPLIANT TO JEDEC STANDARDS MS-012-AA COPLANARITY SEATING CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.10 PLANE (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 51. 8-Lead Mini Small Outline Package [MSOP] Figure 50. 8-Lead Standard Small Outline Package [SOIC] (RM-8) (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8138AR −40°C to +85°C 8-Lead SOIC R-8 AD8138AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 AD8138AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 1 AD8138ARZ −40°C to +85°C 8-Lead SOIC R-8 1 AD8138ARZ-RL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8 1 AD8138ARZ-R7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8 AD8138ARM −40°C to +85°C 8-Lead MSOP RM-8 HBA AD8138ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HBA AD8138ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HBA 1 AD8138ARMZ −40°C to +85°C 8-Lead MSOP RM-8 HBA# 1 AD8138ARMZ-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HBA# 1 AD8138ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HBA# 1 Z = Pb-free part, # denotes lead-free product may be top or bottom marked. Rev. F | Page 23 of 24 AD8138 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01073-0-1/06(F) Rev. F | Page 24 of 24