ANALOG DEVICES AD8133

Triple Differential Driver With Output Pull-Down AD8133 FEATURES FUNCTIONAL BLOCK DIAGRAM Triple high speed fully differential driver 225 MHz −3 dB large signal bandwidth Easily drives 1.4 V p-p video signal into source-terminated 24 23 22 21 20 19 100 Ω UTP cable OPD 1 18 V C OCM AD8133 1600 V/µs slew rate V 2 17 V S– S+ Fixed internal gain of 2 –IN A 3 16 –IN C Internal common-mode feedback network +IN A 4 15 +IN C Output balance error −60 dB @ 50 MHz B V 5 14 V Differential input and output S– A C S– Differential-to-differential or single-ended-to-differential –OUT A 6 13 –OUT C operation 7 8 9 10 11 12 Adjustable output common-mode voltage Output pull-down feature for line isolation Low distortion: 64 dB SFDR @ 10 MHz on 5 V supply, Figure 1. R = 200 Ω L, dm 0 Low offset: 4 mV typical output referred on 5 V supply ∆V = 2V p-p OUT, dm Low power: 26 mA @ 5 V for three drivers –10 ∆V /∆V OUT, cm OUT, dm Wide supply voltage range: +5 V to ±5 V –20 V = ±5V Available in space-saving packaging: 4 mm × 4 mm LFCSP S –30 –40 APPLICATIONS –50 V = +5V KVM (keyboard-video-mouse) networking S –60 UTP (unshielded twisted pair) driving –70 Differential signal multiplexing –80 –90 GENERAL DESCRIPTION –100 1 10 100 500 The AD8133 is a major advancement beyond using discrete FREQUENCY (MHz) op amps for driving differential RGB signals over twisted pair Figure 2. Output Balance vs. Frequency cable. The AD8133 is a triple, low cost differential or single- ended input to differential output driver, and each amplifier has Manufactured on Analog Devices’ next generation XFCB bipo- a fixed gain of 2 to compensate for the attenuation of line ter- lar process, the AD8133 has a large signal bandwidth of mination resistors. The AD8133 is specifically designed for RGB 225 MHz and a slew rate of 1600 V/µs. The AD8133 has an signals but can be used for any type of analog signals or high speed internal common-mode feedback feature that provides output data transmission. The AD8133 is capable of driving either Cate- amplitude and phase matching that is balanced to −60 dB at gory 5 unshielded twisted pair (UTP) cable or differential printed 50 MHz, suppressing harmonics and minimizing radiated elec- circuit board transmission lines with minimal signal degradation. tromagnetic interference (EMI). The outputs of the AD8133 can be set to a low voltage state to The output common-mode level is easily adjustable by applying be used with series diodes for line isolation, allowing easy dif- a voltage to the V input pin. The V input can also be used OCM OCM ferential multiplexing over the same twisted pair cable. The to transmit signals on the output common-mode voltages. AD8133 driver can be used in conjunction with the AD8129 The AD8133 is available in a 24-lead LFCSP package and can and AD8130 differential receivers. operate over the temperature range of −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. OUTPUT BALANCE ERROR (dB) +OUT A V S+ V –IN B S+ +OUT B +IN B –OUT B V S– V V A S+ OCM +OUT C V B OCM 04769-0-001 04769-0-034 AD8133 TABLE OF CONTENTS Specifications..................................................................................... 3 Driving a Capacitive Load......................................................... 13 Absolute Maximum Ratings............................................................ 5 Output Pull-Down (OPD) ........................................................ 13 Thermal Resistance ...................................................................... 5 Output Common-Mode Control ............................................. 13 ESD Caution.................................................................................. 5 Applications..................................................................................... 14 Pin Configuration and Function Descriptions............................. 6 Driving RGB Video Signals Over Category-5 UTP Cable.... 14 Typical Performance Characteristics ............................................. 7 Output Pull-Down ..................................................................... 15 Theory of Operation ...................................................................... 12 KVM Networks........................................................................... 15 Definition of Terms.................................................................... 12 Layout and Power Supply Decoupling Considerations .... 15 Analyzing an Application Circuit............................................. 12 Amplifier-to-Amplifier Isolation ............................................. 15 Closed-Loop Gain ...................................................................... 12 Exposed Paddle (EP).................................................................. 15 Calculating an Application Circuit’s Input Impedance ......... 13 Outline Dimensions ....................................................................... 16 Input Common-Mode Voltage Range in Single-Supply Ordering Guide .......................................................................... 16 Applications .................................................................................. 13 REVISION HISTORY 7/04—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8133 SPECIFICATIONS VS = ±5V, VOCM = 0 V @ 25°C, RL, dm = 200 Ω, unless otherwise noted. TMIN to TMAX = −40°C to +85°C. Table 1. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth V = 0.2 V p-p 450 MHz O −3 dB Large Signal Bandwidth V = 2 V p-p 225 MHz O Bandwidth for 0.1 dB Flatness V = 0.2 V p-p 60 MHz O VO = 2 V p-p 55 MHz Slew Rate VO = 2 V p-p, 25% to 75% 1600 V/µs Settling Time to 0.1% VO = 2 V Step 15 ns Isolation between Amplifiers f = 10 MHz, between Amplifiers A and B 81 dB DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range −5 to +5 V Input Resistance Differential 1.5 kΩ Single-Ended Input 1.13 kΩ Input Capacitance Differential 1 pF DC CMRR ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V −50 dB DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain ∆VOUT, dm/∆VIN, dm; ∆VIN, dm = ±1 V 1.925 1.960 2.000 V/V Output Voltage Swing Each Single-Ended Output VS− + 1.9 VS+ – 1.6 V Output Offset Voltage −24 +4 +24 mV Output Offset Drift T to T ±30 µV/°C MIN MAX Output Balance Error ∆V /∆V , ∆V = 2 V p-p, f = 50 MHz −60 dB OUT, cm IN, dm OUT, dm DC −70 −58 dB Output Voltage Noise (RTO) f = 1 MHz 25 nV/√Hz Output Short-Circuit Current 90 mA VOCM to VO, cm PERFORMANCE V DYNAMIC PERFORMANCE OCM −3 dB Bandwidth ∆V = 100 mV p-p 330 MHz OCM Slew Rate VOCM = −1 V to +1 V, 25% to 75% 1000 V/µs DC Gain ∆VOCM = ±1 V 0.980 0.995 1.005 V/V V INPUT CHARACTERISTICS OCM Input Voltage Range ±3.1 V Input Resistance 70 kΩ Input Offset Voltage −15 −6 +15 mV Input Offset Voltage Drift T to T ±50 µV/°C MIN MAX DC CMRR ∆V /∆V , ∆V = ±1 V −42 dB OUT, dm OCM OCM POWER SUPPLY Operating Range +4.5 ±6 V Quiescent Current 28 29 mA PSRR ∆V /∆V ; ∆V = ±1 V −84 −76 dB OUT, dm S S OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage V to V − 4.15 V S− S+ OPD Input High Voltage VS+ − 3.15 to VS+ V OPD Input Bias Current 67 90 µA OPD Assert Time 100 ns OPD De-Assert Time 100 ns Output Voltage When OPD Asserted Each Output, OPD Input @ V+ V + 0.86 V + 0.90 V S S− S− Rev. 0 | Page 3 of 16 AD8133 V = 5 V, V = 2.5 V @ 25°C, R = 200 Ω, unless otherwise noted. T to T = −40°C to +85°C. S OCM L, dm MIN MAX Table 2. Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth VO = 0.2 V p-p 400 MHz −3 dB Large Signal Bandwidth V = 2 V p-p 200 MHz O Bandwidth for 0.1 dB Flatness V = 0.2 V p-p 50 MHz O Slew Rate V = 2 V p-p, 25% to 75% 1400 V/µs O Settling Time to 0.1% VO = 2 V Step 14 ns Isolation Between Amplifiers f = 10 MHz, between Amplifiers A and B 75 dB DIFFERENTIAL INPUT CHARACTERISTICS Input Common-Mode Voltage Range 0 to 5 V Input Resistance Differential 1.5 kΩ Single-Ended Input 1.13 kΩ Input Capacitance Differential 1 pF DC CMRR ∆V /∆V , ∆V = ±1 V −50 dB OUT, dm IN, cm IN, cm DIFFERENTIAL OUTPUT CHARACTERISTICS Differential Signal Gain ∆V /∆V ; ∆V = ±1 V 1.925 1.960 2.000 OUT, dm IN, dm IN, dm Output Voltage Swing Each Single-Ended Output V − + 1.25 V − 1.15 V S S+ Output Offset Voltage −24 +4 +24 mV Output Offset Drift TMIN to TMAX ±30 µV/°C Output Balance Error ∆VOUT, cm/∆VIN, dm, ∆VOUT, dm = 2 V p-p, f = 50 MHz −60 dB DC −70 −58 dB Output Voltage Noise (RTO) f = 1 MHz 25 nV/√Hz Output Short-Circuit Current 90 mA V PERFORMANCE OCM VOCM DYNAMIC PERFORMANCE −3 dB Bandwidth ∆VOCM = 100 mV p-p 290 MHz Slew Rate V = −1 V to +1 V, 25% to 75% 700 V/µs OCM DC Gain ∆V = ±1 V, T to T 0.980 0.995 1.005 V/V OCM MIN MAX VOCM INPUT CHARACTERISTICS Input Voltage Range 1.25 to 3.85 V Input Resistance 70 kΩ Input Offset Voltage −15 +2 +15 mV Input Offset Voltage Drift TMIN to TMAX ±50 µV/°C DC CMRR ∆VO, dm/∆VOCM; ∆VOCM = ±1 V −42 dB POWER SUPPLY Operating Range +4.5 ±6 V Quiescent Current 26 27 mA PSRR ∆VOUT, dm/∆VS; ∆VS = ±1 V −84 −76 dB OUTPUT PULL-DOWN PERFORMANCE OPD Input Low Voltage VS− to VS+ − 3.85 V OPD Input High Voltage V − 2.85 to V V S+ S+ OPD Input Bias Current 63 80 µA OPD Assert Time 100 ns OPD De-Assert Time 100 ns Output Voltage When OPD Asserted Each Output, OPD Input @ VS+ VS− + 0.79 VS− + 0.82 V Rev. 0 | Page 4 of 16 AD8133 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (PD) is the sum of the Table 3. quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage 12 V power is the voltage between the supply pins (VS) times the All V ±V OCM S quiescent current (I ). The load current consists of differential S Power Dissipation See Figure 3 and common-mode currents flowing to the loads, as well as Input Common-Mode Voltage ±VS currents flowing through the internal differential and common- Storage Temperature −65°C to +125°C mode feedback loops. The internal resistor tap used in the Operating Temperature Range −40°C to +85°C common-mode feedback loop places a 4 kΩ differential load on Lead Temperature Range 300°C the output. RMS output voltages should be considered when (Soldering 10 sec) dealing with ac signals. Junction Temperature 150°C Airflow reduces θJA. Also, more metal directly in contact with Stresses above those listed under Absolute Maximum Ratings the package leads from metal traces, through holes, ground, may cause permanent damage to the device. This is a stress rat- and power planes reduces the θ . The exposed paddle on the JA ing only and functional operation of the device at these or any underside of the package must be soldered to a pad on the PCB other conditions above those indicated in the operational sec- surface that is thermally connected to a copper plane in order to tion of this specification is not implied. Exposure to absolute achieve the specified θJA. maximum rating conditions for extended periods may affect device reliability. Figure 3 shows the maximum safe power dissipation in the package versus ambient temperature for the 24-lead LFCSP THERMAL RESISTANCE (70°C/W) package on a JEDEC standard 4-layer board with the θ is specified for the worst-case conditions, i.e., θ is specified JA JA underside paddle soldered to a pad that is thermally connected for the device soldered in a circuit board in still air. to a PCB plane. θ values are approximations. JA Table 4. Thermal Resistance with the Underside Pad 4.0 Connected to the Plane 3.5 Package Type/PCB Type θJA Unit 24-Lead LFCSP/4-Layer 70 °C/W 3.0 2.5 Maximum Power Dissipation 2.0 The maximum safe power dissipation in the AD8133 package is 1.5 limited by the associated rise in junction temperature (TJ) on LFCSP the die. At approximately 150°C, which is the glass transition 1.0 temperature, the plastic changes its properties. Even temporarily 0.5 exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the para- 0 –40 –20 0 20 40 60 80 metric performance of the AD8133. Exceeding a junction tem- AMBIENT TEMPERATURE (°C) perature of 175°C for an extended period of time can result in Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board changes in the silicon devices potentially causing failure. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprie- tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 MAXIMUM POWER DISSIPATION (W) 04769-0-024 AD8133 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 OPD 1 18 V C OCM AD8133 V 2 17 V S– S+ –IN A 3 16 –IN C +IN A 4 15 +IN C B V 5 14 V S– A C S– –OUT A 6 13 –OUT C 7 8 9 10 11 12 Figure 4. 24-Lead LFCSP Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 OPD Output Pull-Down 2, 5, 14, 21 VS− Negative Power Supply Voltage 3 −IN A Inverting Input, Amplifier A 4 +IN A Noninverting Input, Amplifier A 6 −OUT A Negative Output, Amplifier A 7 +OUT A Positive Output, Amplifier A 8, 11, 17, 24 VS+ Positive Power Supply Voltage 9 +OUT B Positive Output, Amplifier B 10 −OUT B Negative Output, Amplifier B 12 +OUT C Positive Output, Amplifier C 13 −OUT C Negative Output, Amplifier C 15 +IN C Noninverting Input, Amplifier C 16 −IN C Inverting Input, Amplifier C 18 VOCMC Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C 19 VOCMB Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B 20 V A Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A OCM 22 +IN B Noninverting Input, Amplifier B 23 −IN B Inverting Input, Amplifier B +5V V S+ 0.1µF ON ALL V PINS S+ AD8133 1.5kΩ 50Ω 750Ω 53.6Ω + – V V R 200Ω V TEST L, dm OUT, dm OCM – + 53.6Ω 50Ω TEST SIGNAL 750Ω 1.5kΩ SOURCE MIDSUPPLY V S– 0.1µF ON ALL V PINS S– –5V Figure 5. Basic Test Circuit Rev. 0 | Page 6 of 16 +OUT A V S+ V –IN B S+ +OUT B +IN B –OUT B V S– V V A S+ OCM +OUT C V B OCM 04769-0-001 04769-0-035 AD8133 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, RL, dm = 200 Ω, VS = ±5 V, TA = 25°C, VOCMA = VOCMB = VOCMC = 0 V. Refer to the basic test circuit in Figure 5 for the definition of terms. 9 9 –40°C 85°C 25°C 25°C 6 6 –40°C 85°C 3 3 0 0 V = 2V p-p V = 200mV p-p OUT, dm OUT, dm –3 –3 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response at Various Temperatures Figure 9. Large Signal Frequency Response at Various Temperatures 9 6.9 V = ±5V S 6.8 6 6.7 V = 2V p-p OUT, dm 6.6 V = +5V S 3 6.5 V = 200mV p-p OUT, dm 6.4 0 6.3 6.2 –3 6.1 6.0 V = 2V p-p OUT, dm –6 5.9 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Large Signal Frequency Response for Various Power Supplies Figure 10. 0.1 dB Flatness Response –30 –30 V = +5V S V = +5V S V = 2V p-p OUT, dm V = 2V p-p –40 OUT, dm –40 –50 –50 –60 –70 –60 R = 200Ω L, dm R = 200Ω L, dm –80 –70 –90 –100 –80 R = 1000Ω L, dm R = 1000Ω L, dm –110 –90 –120 –130 –100 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Second Harmonic Distortion at V = 5 V at Various Loads Figure 11. Third Harmonic Distortion at V = 5 V at Various Loads S S Rev. 0 | Page 7 of 16 DISTORTION (dBc) GAIN (dB) GAIN (dB) 04769-0-027 04769-0-008 04769-0-010 DISTORTION (dBc) GAIN (dB) GAIN (dB) 04769-0-028 04769-0-009 04769-0-011 AD8133 –30 –30 V = 2V p-p OUT, dm V = 2V p-p OUT, dm –40 –40 –50 –50 R = 200Ω L, dm –60 –60 R = 200Ω L, dm –70 –70 –80 –80 –90 –90 R = 1000Ω L, dm –100 R = 1000Ω L, dm –100 –110 –110 –120 –130 –120 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Second Harmonic Distortion at V = ±5 V at Various Loads Figure 15. Third Harmonic Distortion at V = ±5 V at Various Loads S S 200 V = 2V p-p OUT, dm V = 200mV p-p V = +5V V = +5V OUT, dm S S 1.0 100 V = ±5V S V = ±5V S 0.5 50 0 0 –0.5 –50 –1.0 –100 5ns/DIV 5ns/DIV –200 Figure 16. Large Signal Transient Response Figure 13. Small Signal Transient Response for Various Power Supply Voltages for Various Power Supply Voltages 10 2× V IN, dm 8 V IN, dm 250mV/DIV 6 V OUT, dm 4 +0.1% 2 0 –0.1% SETTLING TIME ERROR –2 2mV/DIV –4 –6 –8 10ns/DIV 100ns/DIV –10 t = 0 Figure 14. Overdrive Recovery Figure 17. Settling Time (0.1%) Rev. 0 | Page 8 of 16 VOLTAGE (V) V (mV) DISTORTION (dBc) O, dm 04769-0-018 04769-0-007 04769-0-029 V (V) DISTORTION (dBc) O, dm 04769-0-016 04769-0-006 04769-0-030 AD8133 –30 2 R =∞ V /V L, dm OUT, dm IN, dm WITH SINGLE-ENDED OUTPUT –32 OUTPUT PULL-DOWN 1 –34 0 –36 –38 V 2V p-p I, dm = –1 –40 OUTPUT PULL-DOWN –2 –42 –44 –3 +5 –46 –4 –5 –48 100ns/DIV V ON –50 –5 0.1 1 10 100 1000 t = 0 FREQUENCY (MHz) Figure 18. Output Pull-Down Response Figure 21. Output Pull-Down Isolation vs. Frequency 1000 0 ∆V = 2V p-p OUT, dm –10 ∆V /∆V OUT, cm OUT, dm –20 V = ±5V S –30 –40 100 –50 V = +5V S –60 –70 –80 –90 10 –100 10 100 1k 10k 100k 1M 10M 100M 1 10 100 500 FREQUENCY (Hz) FREQUENCY (MHz) Figure 19. Output-Referred Voltage Noise vs. Frequency Figure 22. Output Balance vs. Frequency –30 10 ∆V = 200mV p-p ∆V /∆V OUT, dm S IN, cm 0 –35 –10 –20 PSRR– –40 –30 –45 –40 PSRR– ∆V /∆V OUT, dm IN, cm –50 –50 –60 –55 –70 –80 –60 –90 –65 –100 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Common-Mode Rejection Ratio vs. Frequency Figure 23. Power Supply Rejection Ratio vs. Frequency Rev. 0 | Page 9 of 16 SINGLE-ENDED OUTPUT VOLTAGE (V) NOISE (nV√Hz) COMMON-MODE REJECTION (dB) 04769-0-023 04769-0-020 OPD INPUT VOLTAGE (V) 04769-0-017 PSRR (dB) OUTPUT BALANCE ERROR (dB) OUTPUT PULL-DOWN ISOLATION (dB) 04769-0-022 04769-0-034 04769-0-021 AD8133 –40 30 AMPLIFIER A TO V = 200mV p-p AMPLIFIER B IN, dm V = ±5V 29 S ∆V B/∆V A –50 OUT, dm IN, dm 28 –60 27 26 –70 V = 2V p-p IN, dm V = +5V S 25 –80 24 23 –90 22 –100 21 –110 20 1 10 100 1000 –40–30 –10 10305070 85 FREQUENCY (MHz) TEMPERATURE (°C) Figure 24. Amplifier-to-Amplifier Isolation vs. Frequency Figure 27. Power Supply Current vs. Temperature 1.5 –20 V = 2V p-p ∆V = 200mV p-p V = +5V OUT, cm OCM S –30 1.0 V = ±5V S –40 0.5 –50 0 ∆V /∆V OUT, dm OCM –60 –0.5 –70 –1.0 5ns/DIV –80 –1.5 1 10 100 1000 FREQUENCY (MHz) Figure 28. VOCM Large Signal Transient Response for Various Power Supply Voltages Figure 25 V CMRR vs. Frequency OCM 2 1.0 ∆V /∆V 1 OUT, cm OCM 0.8 V = ±5V S 0 0.6 –1 0.4 –2 V = +5V S 0.2 –3 0 –4 –5 –0.2 –6 –0.4 –7 –0.6 –8 V = 100mV p-p OUT, cm –0.8 –9 V TAKEN SINGLE ENDED OUT, cm –10 –1.0 1 10 100 1000 –5 –4 –3 –2 –1 015 2 3 4 FREQUENCY (MHz) V INPUT VOLTAGE OCM Figure 26. V Frequency Response for OCM Figure 29. VOCM Bias Current vs. VOCM Input Voltage Various Power Supply Voltages Rev. 0 | Page 10 of 16 GAIN (dB) ISOLATION (dB) V CMRR (dB) OCM 04769-0-013 04769-0-019 04769-0-015 V BIAS CURRENT (mA) OCM V (V) POWER SUPPLY CURRENT (mA) OCM 04769-0-005 04769-0-025 04769-0-012 AD8133 4.5 100 3.5 2.5 5 10 1.5 4 0.5 3 V = +5V V = ±5V S S –0.5 2 –1.5 1 1 V = ±5V S –2.5 0 –3.5 V = +5V S –4.5 0.1 100 1000 10000 0.01 0.1 1 10 100 1000 LOAD (Ω) FREQUENCY (MHz) Figure 30. Output Saturation Voltage vs. Single-Ended Output Load Figure 32. Single-Ended Output Impedance Magnitude vs. Frequency –1.0 1.5 4.0 3.5 –1.5 1.0 V = +5V S V = ±5V S 3.0 0.5 –2.0 5.0 2.5 0 –2.5 2.0 4.5 V = +5V S V = ±5V –3.0 S 1.5 4.0 –3.5 1.0 3.5 –40 –25 –5 15 35 55 75 85 –40 –25 –5 15 35 55 75 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. Positive Output Saturation Voltage vs. Temperature Figure 33. Negative Output Saturation Voltage vs. Temperature Rev. 0 | Page 11 of 16 ±5V SINGLE-ENDED OUTPUT VOLTAGE (V) ±5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) +5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) +5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) 04769-0-031 04769-0-032 ±5V SINGLE-ENDED OUTPUT VOLTAGE (V) OUTPUT IMPEDANCE (Ω) 04769-0-026 +5V SINGLE-ENDED OUTPUT VOLTAGE SWING (V) 04769-0-033 AD8133 THEORY OF OPERATION Each differential driver in the AD8133 differs from a conven- Common-mode voltage refers to the average of two node volt- tional op amp in that it has two outputs whose voltages move in ages with respect to a common reference. The output common- opposite directions. Like an op amp, it relies on high open-loop mode voltage is defined as gain and negative feedback to force these outputs to the desired (V +V ) OP ON voltages. The AD8133 drivers make it easy to perform single- V = OUT,cm 2 ended-to-differential conversion, common-mode level shifting, and amplification of differential signals. Output Balance Output balance is a measure of how well the differential output Previous differential drivers, both discrete and integrated signals are matched in amplitude and how close they are to designs, have been based on using two independent amplifiers exactly 180° apart in phase. Balance is most easily determined and two independent feedback loops, one to control each of the by placing a well-matched resistor divider between the differen- outputs. When these circuits are driven from a single-ended tial output voltage nodes and comparing the magnitude of the source, the resulting outputs are typically not well balanced. signal at the divider’s midpoint with the magnitude of the dif- Achieving a balanced output has typically required exceptional ferential signal. By this definition, output balance error is the matching of the amplifiers and feedback networks. magnitude of the change in output common-mode voltage DC common-mode level shifting has also been difficult with divided by the magnitude of the change in output differential- previous differential drivers. Level shifting has required the use mode voltage in response to a differential input signal. of a third amplifier and feedback loop to control the output ∆V common-mode level. Sometimes, the third amplifier has also OUT,cm Output Balance Error= been used to attempt to correct an inherently unbalanced ∆V OUT,dm circuit. Excellent performance over a wide frequency range has proven difficult with this approach. ANALYZING AN APPLICATION CIRCUIT The AD8133 uses high open-loop gain and negative feedback to Each of the AD8133 drivers uses two feedback loops to force its differential and common-mode output voltages to separately control the differential and common-mode output minimize the differential and common-mode input error voltages. The differential feedback, set by the internal resistors, voltages. The differential input error voltage is defined as the controls only the differential output voltage. The internal voltage between the differential inputs labeled VAP and VAN in common-mode feedback loop controls only the common-mode Figure 34. For most purposes, this voltage can be assumed to be output voltage. This architecture makes it easy to arbitrarily set zero. Similarly, the difference between the actual output the output common-mode level by simply applying a voltage to common-mode voltage and the voltage applied to VOCM can also the V input. The output common-mode voltage is forced, by OCM be assumed to be zero. Starting from these two assumptions, any internal common-mode feedback, to equal the voltage applied to application circuit can be analyzed. the V input, without affecting the differential output voltage. OCM CLOSED-LOOP GAIN The AD8133 architecture results in outputs that are highly The differential mode gain of the circuit in Figure 34 can be balanced over a wide frequency range without requiring exter- described by the following equation. nal components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode V R OUT,dm F voltage to be zeroed. The result is nearly perfectly balanced dif- = = 2 V R ferential outputs of identical amplitude that are exactly 180° IN,dm G apart in phase. where R = 1.5 kΩ and R = 750 Ω nominally. F G DEFINITION OF TERMS R F Differential Voltage R V G AP + V V Differential voltage refers to the difference between two node IP ON V R V V IN, dm OCM L, dm OUT, dm voltages that are balanced with respect to each other. For exam- – V V IN OP V R AN G R ple, in Figure 34 the output differential voltage (or equivalently F output differential mode voltage) is defined as Figure 34. V =(V −V ) OUT,dm OP ON Rev. 0 | Page 12 of 16 04769-0-003 AD8133 CALCULATING AN APPLICATION CIRCUIT’S INPUT DRIVING A CAPACITIVE LOAD IMPEDANCE A purely capacitive load can react with the output The effective input impedance of a circuit such as that in impedance of the AD8133 to reduce phase margin, resulting in Figure 34 at V and V depends on whether the amplifier is IP IN high frequency ringing in the pulse response. The best way to being driven by a single-ended or differential signal source. For minimize this effect is to place a small resistor in series with balanced differential input signals, the differential input imped- each of the amplifier’s outputs to buffer the load capacitance. ance, RIN, dm, between the inputs VIP and VIN is simply OUTPUT PULL-DOWN (OPD) R = 2×R = 1.5kΩ G IN,dm The AD8133 has an OPD pin that when pulled high signifi- cantly reduces the power consumed while simultaneously In the case of a single-ended input signal (for example, if VIN is pulling the outputs to within less than 1 V of V when used S− grounded and the input signal is applied to V ), the input IP with series diodes (see the Applications section). The equivalent impedance becomes: schematic of the output pull-down circuit is shown in Figure 35. (The ESD diodes shown in Figure 35 are for ESD protection and ⎛ ⎞ ⎜ ⎟ are distinct from the series diodes used with the output pull- R G ⎜ ⎟ R = = 1.125kΩ IN,dm down feature.) See Figure 18 and Figure 21 for the output R ⎜ F ⎟ 1− ⎜ ⎟ pull-down transient and isolation performance plots. The 2×() R +R ⎝ G F ⎠ threshold levels for the OPD pin are referenced to the positive power supply voltage and are presented in the Specifications The circuit’s input impedance is effectively higher than it would tables. When the OPD pin is pulled high, the AD8133 enters the be for a conventional op amp connected as an inverter because output low disable state. a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage V S+ V across the input resistor RG. CC ESD DIODE V OUT INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE- SUPPLY APPLICATIONS PULLDOWN The inputs of the AD8133 are designed to facilitate level- (OUTPUT IS shifting of ground referenced input signals on a single power ESD PULLED DOWN DIODE WHEN SWITCH supply. For a single-ended input, this would imply, for example, IS CLOSED) that the voltage at VIN in Figure 34 would be 0 V when the V S– amplifier’s negative power supply voltage was also set to 0 V. Figure 35. Output Pull-Down Equivalent Circuit It is important to ensure that the common-mode voltage at the amplifier inputs, V and V , stays within its specified range. OUTPUT COMMON-MODE CONTROL AP AN Since voltages V and V are driven to be essentially equal by AP AN The AD8133 allows the user to control each of the three negative feedback, the amplifier’s input common-mode voltage common-mode output levels independently through the three . V can be calculated can be expressed as a single term, VACM ACM V input pins. The V pins pass a signal to the common- OCM OCM as follows mode output level of each of their respective amplifiers with 330 MHz of small signal bandwidth and an internally fixed V + 2V OCM ICM V = gain of one. In this way, additional control and communication ACM 3 signals can be embedded on the common-mode levels as the user sees fit. where VICM is the common-mode voltage of the input signal, i.e., V +V IP IN V = . With no external circuitry, the level at the VOCM input of each ICM 2 amplifier defaults to approximately midsupply. An internal resistive divider with an impedance of approximately 100 kΩ sets this level. To limit common-mode noise in dc common- mode applications, external bypass capacitors should be connected from each of the V input pins to ground. OCM Rev. 0 | Page 13 of 16 04769-0-004 AD8133 APPLICATIONS DRIVING RGB VIDEO SIGNALS OVER CATEGORY-5 UTP CABLE The foremost application of the AD8133 is driving RGB video signals over UTP cable in KVM networks. Single-ended video signals are easily converted to differential signals for transmission over the cable, and the internally fixed gain of 2 automatically compensates for the losses incurred by the source and load terminations. The common topologies used in KVM networks, such as daisy-chained, star, and point-to-point, are supported by the AD8133. Figure 36 shows the AD8133 in a triple single-ended-to-differential application when driven from a 75 Ω source, which is typical of how RGB video is driven over an UTP cable. In applications that use the OPD feature, the Schottky diodes are placed in series with each of the 49.9 Ω resistors in the outputs. +5V 0.1µF ON ALL V PINS S+ V S+ AD8133 1.5kΩ 75Ω 750Ω 49.9Ω – 80.6Ω +2.5V V A OUT A OCM 750Ω 49.9Ω VIDEO + SOURCE A 38.3Ω 1.5kΩ 1.5k 75Ω 750Ω 49.9Ω – 80.6Ω +2.5V V B OUT B OCM 750Ω 49.9Ω VIDEO + SOURCE B 38.3Ω 1.5kΩ 1.5kΩ 75Ω 750Ω 49.9Ω – 80.6Ω +2.5V V C OUT C OCM 750Ω 49.9Ω VIDEO + SOURCE C 38.3Ω 1.5kΩ OPD OUTPUT PULLDOWN V S– Figure 36. AD8133 in Single-Ended-to-Differential Application Rev. 0 | Page 14 of 16 04769-0-002 AD8133 OUTPUT PULL-DOWN In the daisy-chained and star networks that use diodes for isola- tion, return paths are required for the common-mode currents The output pull-down feature, when used in conjunction with that flow through the series diodes. A common-mode tap can series Schottky diodes, offers a convenient means to connect a be implemented at each receiver by splitting the100 Ω termina- number of AD8133 outputs together to form a video network. tion resistor into two 50 Ω resistors in series. The diode currents The OPD pin is a binary input that controls the state of the are routed from the tap between the 50 Ω resistors back to the AD8133 outputs. Its binary input level is referenced to the most respective transmitters over one of the wires of the fourth positive power supply (see the Specifications tables for the logic twisted pair in the UTP cable. Series resistors in the common-mode levels). When the OPD input is driven to its low state, the return path are generally required to set the desired diode current. AD8133 output is enabled and operates in its normal fashion. In this state, the VOCM input can be used to provide a positive bias In point-to-point networks, there is one transmitter and one on the series diodes, allowing the AD8133 to transmit signals receiver per cable, and the switching is generally implemented over the network. When the OPD input is driven to its high with a crosspoint switch. In this case, there is no need to use state, the outputs of the AD8133 are forced to a low voltage, diodes or the output pull-down feature. irrespective of the level on the V input, reverse-biasing the OCM series diodes and thus presenting high impedance to the net- Diode and crosspoint switching are by no means the only type work. This feature allows a three-state output to be realized that of switching that can be used with the AD8133. Many other maintains its high impedance state even when the AD8133 is types of mechanical, electromechanical, and electronic switches not powered. This condition can occur in KVM networks where can be used. the AD8133s do not all reside in the same module, and some LAYOUT AND POWER SUPPLY DECOUPLING modules in the network are not powered. CONSIDERATIONS It is recommended that the output pull-down feature only be Standard high speed PCB layout practices should be adhered to used in conjunction with series diodes in such a way as to when designing with the AD8133. A solid ground plane is ensure that the diodes are reverse-biased when the output pull- recommended and good wideband power supply decoupling down feature is asserted, since some loading conditions can networks should be placed as close as possible to the supply prevent the output voltage from being pulled all the way down. pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended KVM NETWORKS for bulk supply decoupling. In daisy-chained KVM networks, the drivers are distributed along one cable and a triple receiver is located at one end. AMPLIFIER-TO-AMPLIFIER ISOLATION Schottky diodes in series with the driver outputs are biased such The least amount of isolation between the three amplifiers that the one driver that is transmitting video signals has its exists between Amplifier A and Amplifier B. This is therefore diodes forward-biased and the disabled drivers have their viewed as the worst-case isolation and is what is reflected in the diodes reverse-biased. The output common-mode voltage, set Specifications tables and Typical Performance Characteristics. by the V input, supplies the forward-biased voltage. When OCM Refer to the Basic Test Circuit shown in Figure 5 for the test the output pull-down feature is asserted, the differential outputs conditions. are pulled to a low voltage, reverse-biasing the diodes. EXPOSED PADDLE (EP) In star networks, all cables radiate out from a central hub, The LFCSP-24 package has an exposed paddle on the underside which contains a triple receiver. The series diodes are all located of its body. In order to achieve the specified thermal resistance, at the receiver in the star network. Only one ray of the star is it must have a good thermal connection to one of the PCB transmitting at a given time, and all others are isolated by the planes. The exposed paddle must be soldered to a pad on the reverse-biased diodes. Diode biasing is controlled in the same top of the board that is connected to an inner plane with several way as in the daisy-chained network. thermal vias. Rev. 0 | Page 15 of 16 AD8133 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 19 24 1 18 0.50 2.25 PIN 1 BSC TOP 3.75 BOTTOM INDICATOR 2.10 SQ VIEW BSC SQ VIEW 1.95 0.50 13 6 0.40 12 7 0.30 0.25 MIN 0.80 MAX 2.50 REF 1.00 12° MAX 0.65TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY 0.30 0.08 0.20 REF 0.23 SEATING 0.18 PLANE COMPLIANT TO JEDECSTANDARDSMO-220-VGGD-2 Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP], 4 mm× 4 mm (CP-24) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Package Package Description Package Outline AD8133ACP-REEL −40°C to +85°C 24-Lead LFCSP CP-24 AD8133ACP-REEL7 −40°C to +85°C 24-Lead LFCSP CP-24 1 AD8133ACPZ-REEL −40°C to +85°C 24-Lead LFCSP CP-24 1 AD8133ACPZ-REEL7 −40°C to +85°C 24-Lead LFCSP CP-24 1 Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis- tered trademarks are the property of their respective owners. D04769–0–7/04(0) Rev. 0 | Page 16 of 16