ANALOG DEVICES AD8132

Low Cost, High Speed Differential Amplifier AD8132 FEATURES CONNECTION DIAGRAM High speed AD8132 –IN 1 8 +IN 350 MHz, −3 dB bandwidth V 2 7 NC OCM 1200 V/μs slew rate V+ 3 6 V– Resistor set gain +OUT 4 5 –OUT Internal common-mode feedback NC = NO CONNECT Improved gain and phase balance: −68 dB @ 10 MHz Figure 1. Separate input to set the common-mode output voltage Low distortion: −99 dBc SFDR @ 5 MHz, 800 Ω load The AD8132 is also used as a differential driver for the trans- Low power: 10.7 mA @ 5 V mission of high speed signals over low cost twisted pair or coaxial cables. The feedback network can be adjusted to boost the high Power supply range: +2.7 V to ±5.5 V frequency components of the signal. The AD8132 is used for either Fully AEC-Q100 qualified (AD8132W) analog or digital video signals or for other high speed data trans- mission. The AD8132 is capable of driving either a Category 3 APPLICATIONS or Category 5 twisted pair or coaxial cable with minimal line Low power differential ADC drivers attenuation. The AD8132 has considerable cost and performance Differential gain and differential filtering improvements over discrete line driver solutions. Video line drivers Differential in/out level shifting Differential signal processing reduces the effects of ground noise Single-ended input to differential output drivers that plagues ground-referenced systems. The AD8132 can be used Active transformers for differential signal processing (gain and filtering) throughout a Automotive driver assistance signal chain, easily simplifying the conversion between differential Automotive infotainment and single-ended components. The AD8132W is the automotive grade version, qualified for GENERAL DESCRIPTION 125°C operation per the AEC-Q100. See the Automotive The AD8132 is a low cost differential or single-ended input to Products section for more details. differential output amplifier with resistor set gain. The AD8132 The AD8132 is available in both 8-lead SOIC and 8-lead MSOP is a major advancement over op amps for driving differential input packages for operation over the extended industrial temperature ADCs or for driving signals over long lines. The AD8132 has a range of −40°C to +125°C. unique internal feedback feature that provides output gain and phase matching balanced to −68 dB at 10 MHz, suppressing 6 harmonics and reducing radiated EMI. V = ±5V S G = +1 3 V = 2V p-p O, dm Manufactured using the next-generation of Analog Devices, Inc., R = 499Ω L, dm XFCB bipolar process, the AD8132 has a −3 dB bandwidth of 0 350 MHz and delivers a differential signal with −99 dBc SFDR at 5 MHz, despite its low cost. The AD8132 eliminates the need for –3 a transformer with high performance ADCs, preserving the low frequency and dc information. The common-mode level of the –6 differential output is adjustable by applying a voltage on the V pin, easily level shifting the input signals for driving single- OCM –9 supply ADCs. Fast overload recovery preserves sampling accuracy. –12 1 10 100 1k FREQUENCY (MHz) Figure 2. Large Signal Frequency Response Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 01035-001 01035-002 AD8132 TABLE OF CONTENTS Features .............................................................................................. 1  Differential Amplifier Without Resistors (High Input Impedance Inverting Amplifier) .............................................. 22  Applications ....................................................................................... 1  Other β2 = 1 Circuits ................................................................. 23  General Description ......................................................................... 1  Varying β2 ................................................................................... 23  Connection Diagram ....................................................................... 1  β1 = 0............................................................................................ 23  Revision History ........................................................................... 3  Estimating the Output Noise Voltage ...................................... 23  Specif ica t ions ..................................................................................... 4  Calculating Input Impedance of the Application Circuit ..... 24  ±D to ±OUT Specifications ...................................................... 4  IN Input Common-Mode Voltage Range in Single-Supply V to ±OUT Specifications ..................................................... 5  OCM Applications ................................................................................ 24  ±DIN to ±OUT Specifications ...................................................... 6  Setting the Output Common-Mode Voltage .......................... 24  VOCM to ±OUT Specifications ..................................................... 7  Driving a Capacitive Load ......................................................... 24  ±DIN to ±OUT Specifications ...................................................... 8  Open-Loop Gain and Phase ..................................................... 24  VOCM to ±OUT Specifications ..................................................... 8  Layout, Grounding, and Bypassing .............................................. 25  Absolute Maximum Ratings ............................................................ 9  Circuits ......................................................................................... 25  Thermal Resistance ...................................................................... 9  Applications Information .............................................................. 26  Maximum Power Dissipation ..................................................... 9  Analog-to-Digital Driver .......................................................... 26  ESD Caution .................................................................................. 9  Balanced Cable Driver ............................................................... 26  Pin Configuration and Function Descriptions ........................... 10  Transmit Equalizer ..................................................................... 27  Typical Performance Characteristics ........................................... 11  Low-Pass Differential Filter ...................................................... 27  Test Circuits ..................................................................................... 20  High Common-Mode Output Impedance Amplifier ........... 28  Operational Description ................................................................ 21  Full-Wave Rectifier .................................................................... 29  Definition of Terms .................................................................... 21  Automotive Products ................................................................. 29  Basic Circuit Operation ............................................................. 21  Outline Dimensions ....................................................................... 30  Theory of Operation ...................................................................... 22  Ordering Guide .......................................................................... 30  General Usage of the AD8132 .................................................. 22  Rev. I | Page 2 of 32 AD8132 REVISION HISTORY 9/09—Rev. H to Rev. I 11/05—Rev. D to Rev. E Changes to Figure 64 Caption ...................................................... 21 Changes to Table 7, Thermal Resistance Section, Maximum Power Dissipation Section, and Figure 3 ...................................... 8 5/09—Rev. G to Rev. H Changes to Ordering Guide .......................................................... 29 Changes to Features Section, Applications Section, and General Description Section .......................................................................... 1 12/04—Rev. C to Rev. D Changes to Table 1 ........................................................................... 4 Changes to General Description .................................................... 1 Changes to Specifications ............................................................... 2 Changes to Table 2 ........................................................................... 5 Changes to Table 3 ........................................................................... 6 Changes to Absolute Maximum Ratings....................................... 8 Changes to Table 4 ........................................................................... 7 Updated Outline Dimensions ....................................................... 29 Added Automotive Products Section .......................................... 29 Changes to Ordering Guide .......................................................... 29 Changes to Ordering Guide .......................................................... 30 2/03—Rev. B to Rev. C 1/09—Rev. F to Rev. G Changes to Specifications ............................................................... 2 Changes to Figure 77 ..................................................................... 26 Addition to Estimating the Output Noise Voltage Section ...... 15 Updated Outline Dimensions ....................................................... 29 Updated Outline Dimensions ....................................................... 21 1/02—Rev. A to Rev. B 11/06—Rev. E to Rev. F Updated Format ................................................................. Universal Edits to Transmitter Equalizer Section ....................................... 18 Changes to Table 1 ........................................................................... 3 Changes to Table 4 ........................................................................... 6 Changes to Table 5 ........................................................................... 7 Changes to Ordering Guide .......................................................... 29 Rev. I | Page 3 of 32 AD8132 SPECIFICATIONS ±D TO ±OUT SPECIFICATIONS IN At T = 25°C, V = ±5 V, V = 0 V, G = +1, R = 499 Ω, R = R = 348 Ω, unless otherwise noted. For G = +2, R = 200 Ω, R = 1000 Ω, A S OCM L, dm F G L, dm F R = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and G differential outputs, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Large Signal Bandwidth V = 2 V p-p 300 350 MHz OUT AD8132W only, T to T 280 MHz MIN MAX VOUT = 2 V p-p, G = +2 190 MHz −3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 360 MHz VOUT = 0.2 V p-p, G = +2 160 MHz Bandwidth for 0.1 dB Flatness V = 0.2 V p-p 90 MHz OUT V = 0.2 V p-p, G = +2 50 MHz OUT Slew Rate VOUT = 2 V p-p 1000 1200 V/μs AD8132W only, TMIN to TMAX 950 V/μs Settling Time 0.1%, VOUT = 2 V p-p 15 ns Overdrive Recovery Time V = 5 V to 0 V step, G = +2 5 ns IN NOISE/HARMONIC PERFORMANCE Second Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −96 dBc V = 2 V p-p, 5 MHz, R = 800 Ω −83 dBc OUT L, dm V = 2 V p-p, 20 MHz, R = 800 Ω −73 dBc OUT L, dm Third Harmonic V = 2 V p-p, 1 MHz, R = 800 Ω −102 dBc OUT L, dm VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −98 dBc VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −67 dBc IMD 20 MHz, RL, dm = 800 Ω −76 dBc IP3 20 MHz, R = 800 Ω 40 dBm L, dm Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz Differential Gain Error NTSC, G = +2, RL, dm = 150 Ω 0.01 % Differential Phase Error NTSC, G = +2, RL, dm = 150 Ω 0.10 Degrees INPUT CHARACTERISTICS Offset Voltage (RTI) VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V ±1.0 ±3.5 mV AD8132W only, TMIN to TMAX ±6 mV T to T variation 10 μV/°C MIN MAX Input Bias Current T = 25°C 3 7 μA A AD8132W only, T to T 8 μA MIN MAX Input Resistance Differential 12 MΩ Common mode 3.5 MΩ Input Capacitance 1 pF Input Common-Mode Voltage −4.7 to +3.0 V CMRR ΔV /ΔV ; ΔV = ±1 V; resistors matched to 0.01% −70 −60 dB OUT, dm IN, cm IN, cm AD8132W only, TMIN to TMAX −60 dB OUTPUT CHARACTERISTICS Output Voltage Swing Maximum ΔV ; single-ended output −3.6 to +3.6 V OUT Output Current +70 mA Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −70 dB Rev. I | Page 4 of 32 AD8132 V TO ±OUT SPECIFICATIONS OCM At TA = 25°C, VS = ±5 V, VOCM = 0 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω, RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth ΔVOCM = 600 mV p-p 210 MHz Slew Rate ΔV = −1 V to +1 V 400 V/μs OCM Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 12 nV/√Hz DC PERFORMANCE Input Voltage Range ±3.6 V Input Resistance 50 kΩ Input Offset Voltage V = V ; V = V = V = 0 V ±1.5 ±7 mV OS, cm OUT, cm DIN+ DIN− OCM AD8132W only, TMIN to TMAX ±9 mV Input Bias Current 0.5 μA VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = ±1 V; resistors matched to 0.01% −68 dB Gain ΔV /ΔV ; ΔV = ±1 V 0.985 1 1.015 V/V OUT, cm OCM OCM AD8132W only, T to T 0.985 1.015 V/V MIN MAX POWER SUPPLY Operating Range ±1.35 ±5.5 V Quiescent Current V = V = V = 0 V 11 12 13 mA DIN+ DIN− OCM AD8132W only, TMIN to TMAX 9 14.5 mA TMIN to TMAX variation 16 μA/°C Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±1 V −70 −60 dB AD8132W only, T to T −60 dB MIN MAX OPERATING TEMPERATURE RANGE −40 +125 °C Rev. I | Page 5 of 32 AD8132 ±D TO ±OUT SPECIFICATIONS IN At TA = 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω, RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Large Signal Bandwidth VOUT = 2 V p-p 250 300 MHz AD8132W only, T to T 240 MHz MIN MAX V = 2 V p-p, G = +2 180 MHz OUT −3 dB Small Signal Bandwidth V = 0.2 V p-p 360 MHz OUT VOUT = 0.2 V p-p, G = +2 155 MHz Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 65 MHz VOUT = 0.2 V p-p, G = +2 50 MHz Slew Rate V = 2 V p-p 800 1000 V/μs OUT AD8132W only, T to T 750 V/μs MIN MAX Settling Time 0.1%, VOUT = 2 V p-p 20 ns Overdrive Recovery Time VIN = 2.5 V to 0 V step, G = +2 5 ns NOISE/HARMONIC PERFORMANCE Second Harmonic VOUT = 2 V p-p, 1 MHz, RL, dm = 800 Ω −97 dBc VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −100 dBc VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −74 dBc Third Harmonic V = 2 V p-p, 1 MHz, R = 800 Ω −100 dBc OUT L, dm V = 2 V p-p, 5 MHz, R = 800 Ω −99 dBc OUT L, dm V = 2 V p-p, 20 MHz, R = 800 Ω −67 dBc OUT L, dm IMD 20 MHz, RL, dm = 800 Ω −76 dBc IP3 20 MHz, RL, dm = 800 Ω 40 dBm Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 8 nV/√Hz Input Current Noise f = 0.1 MHz to 100 MHz 1.8 pA/√Hz Differential Gain Error NTSC, G = +2, R = 150 Ω 0.025 % L, dm Differential Phase Error NTSC, G = +2, RL, dm = 150 Ω 0.15 Degrees INPUT CHARACTERISTICS Offset Voltage (RTI) V = V /2; V = V = V = 2.5 V ±1.0 ±3.5 mV OS, dm OUT, dm DIN+ DIN− OCM AD8132W only, TMIN to TMAX ±6 mV TMIN to TMAX variation 6 μV/°C Input Bias Current TA = 25°C 3 7 μA 8 μA Input Resistance Differential AD8132W only, T to T 10 MΩ MIN MAX Common-mode 3 MΩ Input Capacitance 1 pF Input Common-Mode Voltage 0.3 to 3.0 V CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±1 V; resistors matched to 0.01% −70 −60 dB AD8132W only, T to T −60 dB MIN MAX OUTPUT CHARACTERISTICS AD8132W only, TMIN to TMAX Output Voltage Swing Maximum ΔV ; single-ended output 1.0 to 4.0 V OUT Output Current 50 mA Output Balance Error ΔV /ΔV ; ΔV = 1 V −68 dB OUT, cm OUT, dm OUT, dm Rev. I | Page 6 of 32 AD8132 V TO ±OUT SPECIFICATIONS OCM At TA = 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω, RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 4. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth ΔVOCM = 600 mV p-p 210 MHz Slew Rate ΔV = 1.5 V to 3.5 V 340 V/μs OCM Input Voltage Noise (RTI) f = 0.1 MHz to 100 MHz 12 nV/√Hz DC PERFORMANCE Input Voltage Range 1.0 to 3.7 V Input Resistance 30 kΩ Input Offset Voltage V = V ; V = V = V = 2.5 V ±5 ±11 mV OS, cm OUT, cm DIN+ DIN− OCM AD8132W only, TMIN to TMAX ±13 mV Input Bias Current 0.5 μA VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = 2.5 V ±1 V; resistors matched to 0.01% −66 dB Gain ΔV /ΔV ; ΔV = 2.5 V ±1 V 0.985 1 1.015 V/V OUT, cm OCM OCM AD8132W only, T to T 0.985 1.015 V/V MIN MAX POWER SUPPLY Operating Range 2.7 11 V Quiescent Current V = V = V = 2.5 V 9.4 10.7 12 mA DIN+ DIN− OCM AD8132W only, TMIN to TMAX 6 13 mA TMIN to TMAX variation 10 μA/°C Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±1 V −70 −60 dB AD8132W only, T to T −60 dB MIN MAX OPERATING TEMPERATURE RANGE −40 +125 °C Rev. I | Page 7 of 32 AD8132 ±D TO ±OUT SPECIFICATIONS IN At TA = 25°C, VS = 3 V, VOCM = 1.5 V, G = +1, RL, dm = 499 Ω, RF = RG = 348 Ω, unless otherwise noted. For G = +2, RL, dm = 200 Ω, RF = 1000 Ω, RG = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Table 5. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Large Signal Bandwidth VOUT = 1 V p-p 350 MHz V = 1 V p-p, G = +2 165 MHz OUT −3 dB Small Signal Bandwidth V = 0.2 V p-p 350 MHz OUT V = 0.2 V p-p, G = +2 150 MHz OUT Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 45 MHz VOUT = 0.2 V p-p, G = +2 50 MHz NOISE/HARMONIC PERFORMANCE Second Harmonic VOUT = 1 V p-p, 1 MHz, RL, dm = 800 Ω −100 dBc VOUT = 1 V p-p, 5 MHz, RL, dm = 800 Ω −94 dBc VOUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc Third Harmonic V = 1 V p-p, 1 MHz, R = 800 Ω −90 dBc OUT L, dm V = 1 V p-p, 5 MHz, R = 800 Ω −85 dBc OUT L, dm VOUT = 1 V p-p, 20 MHz, RL, dm = 800 Ω −66 dBc INPUT CHARACTERISTICS Offset Voltage (RTI) V = V /2; V = V = V = 1.5 V ±10 mV OS, dm OUT, dm DIN+ DIN− OCM Input Bias Current 3 μA Input Common-Mode Voltage 0.3 to 1.0 V CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V; resistors matched to 0.01% −60 dB V TO ±OUT SPECIFICATIONS OCM At T = 25°C, V = 3 V, V = 1.5 V, G = +1, R = 499 Ω, R = R = 348 Ω, unless otherwise noted. For G = +2, R = 200 Ω, R = 1000 Ω, A S OCM L, dm F G L, dm F R = 499 Ω. Refer to Figure 56 and Figure 57 for test setup and label descriptions. All specifications refer to single-ended input and G differential outputs, unless otherwise noted. Table 6. Parameter Conditions Min Typ Max Unit DC PERFORMANCE Input Offset Voltage V = V ; V = V = V = 1.5 V ±7 mV OS, cm OUT, cm DIN+ DIN− OCM Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = ±0.5 V 1 V/V POWER SUPPLY Operating Range 2.7 11 V Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 7.25 mA Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±0.5 V −70 dB OPERATING TEMPERATURE RANGE −40 +125 °C Rev. I | Page 8 of 32 AD8132 ABSOLUTE MAXIMUM RATINGS Table 7. The power dissipated in the package (PD) is the sum of the Parameter Rating quiescent power dissipation and the power dissipated in the Supply Voltage ±5.5 V package due to the load drive for all outputs. The quiescent V ±V OCM S power is the voltage between the supply pins (VS) times the Internal Power Dissipation 250 mW quiescent current (I ). The load current consists of the differential S Operating Temperature Range −40°C to +125°C and common-mode currents flowing to the load, as well as Storage Temperature Range −65°C to +150°C currents flowing through the external feedback networks and Lead Temperature (Soldering 10 sec) 300°C the internal common-mode feedback loop. The internal resistor Junction Temperature 150°C tap used in the common-mode feedback loop places a 1 kΩ differential load on the output. Consider rms voltages and Stresses above those listed under Absolute Maximum Ratings currents when dealing with ac signals. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Airflow reduces θJA. In addition, more metal directly in contact other conditions above those indicated in the operational with the package leads from metal traces through holes, ground, section of this specification is not implied. Exposure to absolute and power planes reduces the θ . JA maximum rating conditions for extended periods may affect device reliability. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC THERMAL RESISTANCE (θJA = 121°C/W) and 8-lead MSOP (θJA = 142°C/W) packages θ is specified for the worst-case conditions, that is, θ is JA JA on a JEDEC standard 4-layer board. θJA values are approximations. specified for the device soldered in a circuit board in still air. 1.75 Table 8. 1.50 Package Type θ Unit JA 8-Lead SOIC, 4-Layer 121 °C/W 1.25 8-Lead MSOP, 4-Layer 142 °C/W 1.00 SOIC MAXIMUM POWER DISSIPATION 0.75 The maximum safe power dissipation in the AD8132 packages MSOP is limited by the associated rise in junction temperature (TJ) on 0.50 the die. At approximately 150°C, the glass transition temperature, 0.25 the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 exerts on the die, permanently shifting the parametric performance AMBIENT TEMPERATURE (°C) of the AD8132. Exceeding a junction temperature of 150°C for Figure 3. Maximum Power Dissipation vs. Ambient Temperature an extended period can result in changes in the silicon devices, potentially causing failure. ESD CAUTION Rev. I | Page 9 of 32 MAXIMUM POWER DISSIPATION (W) 01035-082 AD8132 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8132 –IN 1 8 +IN V 2 7 NC OCM V+ 3 6 V– +OUT 4 5 –OUT NC = NO CONNECT Figure 4. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1 −IN Negative Input. 2 V Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on OCM V sets the dc bias level on +OUT and −OUT to 1 V. OCM 3 V+ Positive Supply Voltage. 4 +OUT Positive Output. Note that the voltage at −DIN is inverted at +OUT (see Figure 64). 5 −OUT Negative Output. Note that the voltage at +DIN is inverted at −OUT (see Figure 64). 6 V− Negative Supply Voltage. 7 NC No Connect. 8 +IN Positive Input. Rev. I | Page 10 of 32 01035-004 AD8132 TYPICAL PERFORMANCE CHARACTERISTICS 2 3 V = ±5V S V = +3V S V = +3V 2 S 1 V = +5V S V = +5V S 1 0 0 V = ±5V S –1 –1 –2 –2 G = +1 –3 V = 2V p-p FOR V = ±5V, +5V G = +1 O, dm S –3 V = 1V p-p FOR V = +3V V = 0.2V p-p O, dm S O, dm R = 499Ω R = 499Ω L, dm L, dm –4 –4 –5 –5 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response (See Figure 56) Figure 8. Large Signal Frequency Response; CF = 0 pF (See Figure 56) 0.5 2 G = +1 V = +3V S 0.4 V = 0.2V p-p O, dm R = 499Ω 1 L, dm V = +3V S 0.3 V = +5V S V = +5V S 0 0.2 V = ±5V S 0.1 –1 0 –2 –0.1 V = ±5V S –0.2 –3 G = +1 V = 2V p-p FOR V = ±5V, +5V O, dm S –0.3 V = 1V p-p FOR V = +3V O, dm S –4 R = 499Ω L, dm –0.4 –0.5 –5 1 10 100 1k 110 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. 0.1 dB Flatness vs. Frequency; CF = 0 pF (See Figure 56) Figure 9. Large Signal Frequency Response; C = 0.5 pF (See Figure 56) F 0.2 3 +85°C +25°C V = +3V S 2 0.1 V = +5V S 1 0 0 V = ±5V –0.1 S –40°C –1 –0.2 –2 V = ±5V S –0.3 G = +1 G = +1 –3 V = 2V p-p O, dm V = 0.2V p-p O, dm R = 499Ω L, dm –0.4 R = 499Ω L, dm –4 –0.5 –5 1 10 100 1k 110 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. 0.1 dB Flatness vs. Frequency; CF = 0.5 pF (See Figure 56) Figure 10. Large Signal Frequency Response at Various Temperatures (See Figure 56) Rev. I | Page 11 of 32 GAIN (dB) GAIN (dB) GAIN (dB) 01035-008 01035-007 01035-006 GAIN (dB) GAIN (dB) GAIN (dB) 01035-011 01035-010 01035-009 AD8132 3 6.1 R = 499Ω F 2 R = 348Ω 6.0 F 1 5.9 0 R = 249Ω F 5.8 –1 –2 5.7 V = ±5V S G = +1 V = +3V, +5V, ±5V –3 S V = 2V p-p G = +2 O, dm 5.6 R = 499Ω V = 0.2V p-p L, dm O, dm –4 R = 200Ω L, dm –5 5.5 110 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Large Signal Frequency Response vs. RF (See Figure 56) Figure 14. 0.1 dB Flatness vs. Frequency (See Figure 57) 100 7 V = +5V, ±5V S 6 V = +3V S 5 10 4 G = +2 V = 2V p-p FOR O, dm V = ±5V, +5V S 3 1 V = 1V p-p FOR O, dm V = +3V S R = 200Ω L, dm V = +5V 2 S V = ±5V S 1 0.1 110 100 1k 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Closed-Loop Single-Ended Z vs. Frequency; G = +1 (See Figure 56) Figure 15. Large Signal Frequency Response (See Figure 57) OUT 7 7 R = 1.5kΩ F 6 6 R = 1.0kΩ F 5 5 V = ±5V, +5V S R = 499Ω F 4 4 V = +3V S 3 3 V = ±5V S G = +2 G = +2 V = 0.2V p-p O, dm V = 0.2V p-p O, dm R = 200Ω L, dm R = 200Ω 2 2 L, dm 1 1 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Small Signal Frequency Response (See Figure 57) Figure 16. Small Signal Frequency Response vs. R (See Figure 57) F Rev. I | Page 12 of 32 GAIN (dB) GAIN (dB) IMPEDANCE (Ω) 01035-015 01035-012 01035-013 GAIN (dB) GAIN (dB) GAIN (dB) 01035-018 01035-017 01035-016 AD8132 –30 25 R = 800Ω HD3 (V = +5V) L, dm S G = +10, R = 4.99kΩ F V = 2V p-p O, dm –40 20 G = +5, R = 2.49kΩ F 15 –50 HD2 (V = ±5V) S –60 10 G = +2, R = 1kΩ F HD3 (V = ±5V) S –70 5 HD2 (V = +5V) G = +1, R = 499Ω F S 0 –80 V = ±5V –90 –5 S V = 2V p-p O, dm R = 200Ω L, dm –100 –10 R = 499Ω G –110 –15 05 10 20 30 4006070 110 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Harmonic Distortion vs. Frequency, G = 1 (See Figure 62) Figure 17. Large Signal Frequency Response for Various Gains (See Figure 58) –40 –25 V = 3V S HD3 (f = 20MHz) V = ±5V S R = 800Ω –30 L, dm ΔV = 2V p-p O, dm –50 ΔV /ΔV O, cm O, dm –35 –60 –40 HD2 (f = 20MHz) –45 –70 G = 1 –50 –80 –55 –60 –90 G = 2 –65 –100 HD3 (f = 5MHz) –70 HD2 (f = 5MHz) –110 –75 1 10 100 1k 0.25 0.50 0.75 1.00 1.25 1.50 1.75 DIFFERENTIAL OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz) Figure 21. Harmonic Distortion vs. Figure 18. RTI Output Balance Error vs. Frequency (See Figure 59) Differential Output Voltage, G = 1 (See Figure 62) –40 –40 V = 5V R = 800Ω S L, dm R = 800Ω V = 1V p-p L, dm O, dm –50 –50 HD3 (V = 3V) S HD3 (f = 20MHz) –60 –60 –70 HD2 (V = 3V) –70 S HD2 (f = 20MHz) –80 –80 HD2 (V = 5V) S HD2 (f = 5MHz) –90 –90 –100 HD3 (f = 5MHz) –100 HD3 (V = 5V) S –110 –110 0 1 234 0 10 20 30 40 506070 DIFFERENTIAL OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz) Figure 22. Harmonic Distortion vs. Figure 19. Harmonic Distortion vs. Frequency, G = +1 (See Figure 62) Differential Output Voltage, G = +1 (See Figure 62) Rev. I | Page 13 of 32 DISTORTION (dBc) RTI BALANCE ERROR (dB) GAIN (dB) 01035-024 01035-022 01035-020 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01035-027 01035-025 01035-026 AD8132 –40 –50 V = ±5V S V = ±5V HD3 (f = 20MHz) S V = 2V p-p O, dm R = 800Ω L, dm –50 HD3 (f = 20MHz) –60 HD2 (f = 20MHz) –60 –70 –70 HD2 (f = 20MHz) –80 –80 HD2 (f = 5MHz) –90 HD2 (f = 5MHz) –90 –100 –100 HD3 (f = 5MHz) HD3 (f = 5MHz) –110 –110 200 300 400 500 600 700 800 900 1000 0 1 23 4 5 6 R (Ω) LOAD DIFFERENTIAL OUTPUT VOLTAGE (V p-p) Figure 23. Harmonic Distortion vs. Figure 26. Harmonic Distortion vs. RLOAD, G = +1 (See Figure 62) Differential Output Voltage, G = +1 (See Figure 62) –50 –40 V = 3V R = 800Ω S L, dm V = 1V p-p V = 1V p-p O, dm O, dm HD3 (f = 20MHz) –50 –60 HD3 (V = 3V) S –60 –70 HD2 (f = 20MHz) –70 –80 HD2 (V = 5V) S –80 –90 HD3 (f = 5MHz) –90 HD2 (V = 3V) S –100 –100 HD2 (f = 5MHz) HD3 (V = 5V) S –110 –110 200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 R (Ω) LOAD FREQUENCY (MHz) Figure 24. Harmonic Distortion vs. R , G = +1 (See Figure 62) Figure 27. Harmonic Distortion vs. Frequency, G = +2 (See Figure 63) LOAD –20 –50 HD3 (V = +5V) V = 5V S R = 800Ω S L, dm V = 2V p-p O, dm V = 4V p-p O, dm –30 HD3 (f = 20MHz) –60 HD2 (V = +5V) S –40 –70 –50 HD3 (V = ±5V) S –80 –60 HD2 (f = 20MHz) –70 HD2 (f = 5MHz) –90 –80 HD2 (V = ±5V) S HD3 (f = 5MHz) –100 –90 –100 –110 200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 80 R (Ω) LOAD FREQUENCY (MHz) Figure 25. Harmonic Distortion vs. R , G = +1 (See Figure 62) Figure 28. Harmonic Distortion vs. Frequency, G = +2 (See Figure 63) LOAD Rev. I | Page 14 of 32 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01035-028 01035-029 01035-030 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01035-034 01035-033 01035-031 AD8132 –40 –50 V = ±5V V = 5V S S HD3 (f = 20MHz) HD3 (f = 20MHz) V = 2V p-p R = 800Ω O, dm L, dm –50 –60 –60 HD2 (f = 20MHz) –70 –70 HD2 (f = 20MHz) –80 –80 HD2 (f = 5MHz) –90 –90 HD2 (f = 5MHz) –100 –100 –110 HD3 (f = 5MHz) HD3 (f = 5MHz) –120 –110 03 1 2 4 200 300 400 500 600 700 800 900 1000 DIFFERENTIAL OUTPUT VOLTAGE (V p-p) R (Ω) LOAD Figure 32. Harmonic Distortion vs. R , G = +2 (See Figure 63) Figure 29. Harmonic Distortion vs. LOAD Differential Output Voltage, G = +2 (See Figure 63) –40 10 HD3 (f = 20MHz) V = 5V S f = 20MHz C 0 R = 800Ω L, dm V = ±5V S –50 R = 800Ω L, dm –10 HD2 (f = 20MHz) –60 –20 –30 –70 –40 –80 –50 –60 –90 HD3 (f = 5MHz) –70 –100 HD2 (f = 5MHz) –80 –110 –90 03 1 2 4 56 19.5 20.0 20.5 DIFFERENTIAL OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz) Figure 30. Harmonic Distortion vs. Figure 33. Intermodulation Distortion, G = +1 Differential Output Voltage, G = +2 (See Figure 63) –50 45 V = 5V V = ±5V, +5V S S HD3 (f = 20MHz) V = 2V p-p R = 800Ω O, dm L, dm –60 40 –70 35 HD2 (f = 20MHz) –80 30 HD2 (f = 5MHz) –90 25 –100 20 HD3 (f = 5MHz) –110 15 200 300 400 500 600 700 800 900 1000 010 20 30 40 50 60 70 R (Ω) LOAD FREQUENCY (MHz) Figure 31. Harmonic Distortion vs. R , G = +2 (See Figure 63) Figure 34. Third-Order Intercept vs. Frequency, G = +1 LOAD Rev. I | Page 15 of 32 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01035-036 01035-035 01035-037 P (dBm [Re: 50Ω]) DISTORTION (dBc) INTERCEPT (dBm [Re: 50Ω]) OUT 01035-040 01035-039 01035-038 AD8132 C = 0pF F V = ±5V S V = ±5V, +5V, +3V S V = 2V p-p O, dm C = 0.5pF F 40mV 5ns 400mV 5ns Figure 35. Small Signal Transient Response, G = +1 Figure 38. Large Signal Transient Response, G = +1 V = 3V S C = 0pF F V = 1.5V p-p O, dm V O, dm C = 0.5pF F V –OUT V +OUT V +DIN 300mV 5ns 1V 5ns Figure 36. Large Signal Transient Response, G = +1 Figure 39. Large Signal Transient Response, G = +1 C = 0pF V = 5V V = ±5V, +5V, +3V F S S V = 2V p-p O, dm C = 0.5pF F 40mV 5ns 400mV 5ns Figure 37. Large Signal Transient Response, G = +1 Figure 40. Small Signal Transient Response, G = +2 Rev. I | Page 16 of 32 01035-043 01035-042 01035-041 01035-046 01035-045 01035-044 AD8132 V = ±5V S G = +1 V = 3V S V = 2V p-p O, dm R = 499Ω L, dm 2mV 5ns 300mV 5ns 0 5 10 15 20 25 30 35 40 5ns/DIV Figure 41. Large Signal Transient Response, G = +2 Figure 44. 0.1% Settling Time V = +5V, ±5V C = 0pF L S C = 5pF L C = 20pF L 400mV 5ns 5ns 400mV Figure 42. Large Signal Transient Response, G = +2 Figure 45. Large Signal Transient Response for Various Capacitor Loads (See Figure 60) 0 ΔV O, dm –PSRR V = ±5V S –10 ΔV S –20 +PSRR (V = ±5V, +5V) V S O, dm –30 –PSRR (V = ±5V) S +PSRR V –OUT –40 –50 V +OUT –60 –70 V +DIN –80 –90 1V 5ns 0.1 1 10 100 1k FREQUENCY (MHz) Figure 43. Large Signal Transient Response, G = +2 Figure 46. PSRR vs. Frequency Rev. I | Page 17 of 32 01035-049 01035-048 01035-047 PSRR (dB) 0.1%/DIV 01035-052 01035-050 01035-053 AD8132 –20 –10 V = ±5V ΔV ΔV = 600mV p-p S O, dm OCM V = 2V p-p IN, cm ΔV OCM –20 –30 –30 –40 ΔV O, cm ΔV = 2V p-p OCM ΔV IN, cm –40 –50 –50 –60 –60 ΔV O, dm –70 ΔV IN, cm –70 –80 –80 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 47. CMRR vs. Frequency (See Figure 61) Figure 50. VOCM CMRR vs. Frequency 6 1k ΔV V = ±5V O, cm S ΔV OCM 3 ΔV = 600mV p-p OCM 0 100 ΔV = 2V p-p OCM –3 –6 8nV/√Hz 10 –9 –12 –15 1 1 10 100 1000 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (MHz) FREQUENCY (Hz) Figure 48. V Gain Response OCM Figure 51. Input Voltage Noise vs. Frequency 1k V = ±5V S V = –1V TO +1V OCM 100 V O, cm 10 1.8pA/√Hz 400mV 5ns 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 49. V Transient Response Figure 52. Input Current Noise vs. Frequency OCM Rev. I | Page 18 of 32 CMRR (dB) V GAIN (dB) OCM 01035-057 01035-056 01035-055 INPUT CURRENT NOISE (pA/√Hz) INPUT VOLTAGE NOISE (nV/√Hz) V CMRR (dB) OCM 01035-058 01035-060 01035-059 AD8132 0 V (0.5V/DIV) O, dm V = +5V S –0.5 V (1V/DIV) IN, sm –1.0 V = ±5V S –1.5 V = 5V S V = 2.5V STEP IN G = +2 –2.0 R = 1kΩ F R = 200Ω L, dm 5ns –2.5 –40 –20 020 40 60 80 100 TEMPERATURE (°C) Figure 53. Overdrive Recovery Figure 55. Differential Output Offset Voltage vs. Temperature 15 13 V = ±5V S 11 V = +5V S 9 7 5 –50 –30 –10 103050 70 90 TEMPERATURE (°C) Figure 54. Supply Current vs. Temperature Rev. I | Page 19 of 32 SUPPLY CURRENT (mA) 01035-061 01035-062 DIFFERENTIAL OUTPUT OFFSET (mV) 01035-063 AD8132 TEST CIRCUITS C F 348Ω R F 348Ω R R G L 49.9Ω 49.9Ω 0.1µF 0.1µF 499Ω R L 348Ω R G 24.9Ω 24.9Ω 348Ω R F G = +1: R = R = 348Ω, R = 249Ω (R = 498Ω) F G L L, dm C F G = +2: R = 1000Ω, R = 499Ω, R = 100Ω (R = 200Ω) F G L L, dm Figure 56. Basic Test Circuit, G = +1 Figure 59. Test Circuit for Output Balance 348Ω 1000Ω 348Ω 24.9Ω 499Ω 49.9Ω 49.9Ω 0.1µF C 0.1µF L 453Ω 200Ω 348Ω 24.9Ω 499Ω 24.9Ω 24.9Ω 348Ω 1000Ω Figure 57. Basic Test Circuit, G = +2 Figure 60. Test Circuit for Capacitor Load Drive R F 348Ω 499Ω 348Ω 249Ω 49.9Ω 0.1µF V 200Ω O, dm V O, cm 49.9Ω 348Ω 249Ω 499Ω 24.9Ω 348Ω R F NOTES RESISTORS MATCHED TO 0.01%. Figure 58. Test Circuit for Various Gains Figure 61. CMRR Test Circuit 348Ω 2:1 TRANSFORMER 348Ω 300Ω HPF LPF 49.9Ω Z = 50Ω IN 0.1µF 348Ω 300Ω 24.9Ω 348Ω Figure 62. Harmonic Distortion Test Circuit, G = +1, R = 800 Ω L, dm 1000Ω 2:1 TRANSFORMER 499Ω 300Ω HPF LPF 49.9Ω Z = 50Ω IN 0.1µF 499Ω 300Ω 24.9Ω 1000Ω Figure 63. Harmonic Distortion Test Circuit, G = +2, RL, dm = 800 Ω Rev. I | Page 20 of 32 01035-019 01035-005 01035-014 01035-032 01035-023 01035-054 01035-051 01035-021 AD8132 OPERATIONAL DESCRIPTION Table 10. Differential and Common-Mode Gains DEFINITION OF TERMS Input V V OUT, dm OUT, cm Differential Voltage V R /R 0 (by design) IN, dm F G It is the difference between two node voltages. For example, the V 0 0 (by design) IN, cm output differential voltage (or equivalently output differential V 0 1 (by design) OCM mode voltage) is defined as As listed in Table 10, the differential output (VOUT, dm) is equal to VOUT, dm = (V+OUT − V−OUT) the differential input voltage (V ) times R /R . In this case, it IN, dm F G where V and V refer to the voltages at the +OUT and +OUT −OUT does not matter if both differential inputs are driven, or only one −OUT terminals with respect to a common reference. output is driven and the other is tied to a reference voltage, such as ground. As seen from the two zero entries in the VOUT, dm column, Common-Mode Voltage It is the average of two node voltages. The output common- neither of the common-mode inputs has any effect on this gain. mode voltage is defined as The gain from VIN, dm to VOUT, cm is 0, and first-order, does not V = (V + V )/2 OUT, cm +OUT −OUT depend on the ratio matching of the feedback networks. The C common-mode feedback loop within the AD8132 provides a F corrective action to keep this gain term minimized. The term R F balance error describes the degree that this gain term differs from 0. R G +IN –OUT +D IN V R V AD8132 L, dm OUT, dm OCM The gain from VIN, cm to VOUT, dm directly depends on the matching –D IN of the feedback networks. The analogous term for this transfer R –IN +OUT G R F function (used in conventional op amps) is common-mode C rejection ratio (CMRR). Therefore, if it has a high CMRR, the F feedback ratios must be well matched. Figure 64. Circuit Definitions The gain from V to V is ideally 0 and is first-order IN, cm OUT, cm BASIC CIRCUIT OPERATION independent of the feedback ratio matching. As in the case of One of the more useful and easy to understand ways to use the VIN, dm to VOUT, cm, the common-mode feedback loop keeps this AD8132 is to provide two equal ratio feedback networks. To term minimized. match the effect of parasitics, comprise these networks of two The gain from VOCM to VOUT, dm is ideally 0 when the feedback ratios equal value feedback resistors (RF) and two equal value gain are matched only. The amount of differential output signal that is resistors (RG). This circuit is shown in Figure 64. created by varying V is related to the degree of mismatch in the OCM Like a conventional op amp, the AD8132 has two differential feedback networks. inputs that can be driven with both differential mode input V controls the output common-mode voltage V with a OCM OUT, cm voltage (V ) and common-mode input voltage (V ). IN, dm IN, cm unity-gain transfer function. With equal ratio feedback networks There is another input to consider (VOCM) on the AD8132 that (as previously assumed), its effect on each output is the same, is not present on conventional op amps. VOCM is completely that is the gain from VOCM to VOUT, dm is 0. If not driven, the separate from the previous inputs. output common-mode voltage is set with an internal voltage divider to a level that is nominally midsupply. It is recommended There are two complementary outputs whose response can be that a 0.1 μF bypass capacitor be connected to V . OCM defined by a differential mode output (V ) and a common- OUT, dm mode output (V ). When unequal feedback ratios are used, the two gains associated OUT, cm with V become nonzero. This significantly complicates the OUT, dm Table 10 shows the gain from any type of input to either type mathematical analysis along with any intuitive understanding of of output. how the part operates. Rev. I | Page 21 of 32 01035-064 AD8132 THEORY OF OPERATION The AD8132 differs from conventional op amps by the external For each feedback network, a feedback factor can be defined as presence of an additional input and output. The additional the fraction of the output signal that is fed back to the opposite input, VOCM, controls the output common-mode voltage. The sign input. These terms are additional output is the analog complement of the single output β1 = RG1/(RG1 + RF1) of a conventional op amp. For its operation, the AD8132 uses two β2 = R /(R + R ) G2 G2 F2 feedback loops as compared to the single loop of conventional op amps. Although this provides significant freedom to create The feedback factor, β1, is for the side that is driven, and the various novel circuits, basic op amp theory can still be used to feedback factor, β2, is for the side that is tied to a reference analyze the operation. voltage (ground). Note that each feedback factor can vary anywhere between 0 and 1. One of the feedback loops controls the output common-mode voltage, VOUT, cm. Its input is VOCM (Pin 2) and the output is the A single-ended-to-differential gain equation can be derived common mode, or average voltage, of the two differential outputs (this is true for all values of β1 and β2) from (+OUT and −OUT). The gain of this circuit is internally set to 2(1− β1) unity. When the AD8132 is operating in its linear region, this G= establishes one of the operational constraints: V = V . OUT, cm OCM () β1+ β2 The second feedback loop controls the differential operation. This expression is not very intuitive, but some further examples Similar to an op amp, the gain and gain shaping of the transfer can provide better understanding of its implications. One function can be controlled by adding passive feedback networks. observation that can be made immediately is that a tolerance However, only one feedback network is required to close the error in β1 does not have the same effect on gain as the same loop and fully constrain the operation, but depending on the tolerance error in β2. function desired, two feedback networks can be used. This is possible because there are two outputs that are each inverted DIFFERENTIAL AMPLIFIER WITHOUT RESISTORS with respect to the differential inputs. (HIGH INPUT IMPEDANCE INVERTING AMPLIFIER) The simplest closed-loop circuit that can be made does not GENERAL USAGE OF THE AD8132 require any resistors and is shown in Figure 70. In this circuit, Several assumptions are made here for a first-order analysis; they β1 is equal to 0, and β2 is equal to 1. The gain is equal to 2. are the typical assumptions used for the analysis of op amps. A more intuitive method to figure the gain is by simple inspection. • The input bias currents are sufficiently small so they can be +OUT is connected to −IN, whose voltage is equal to the voltage at neglected. +IN under equilibrium conditions. Therefore, +VOUT is equal to • The output impedances are arbitrarily low. VIN, and there is unity gain in this path. Because −OUT has to swing in the opposite direction from +OUT due to the common- • The open-loop gain is arbitrarily large and drives the mode constraint, its effect doubles the output signal and amplifier to a state where the input differential voltage is produces a gain of 2. effectively 0. One useful function that this circuit provides is a high input • Offset voltages are assumed to be 0. impedance inverter. If +OUT is ignored, there is a unity-gain, Though it is possible to operate the AD8132 with a purely high input impedance amplifier formed from +IN to −OUT. differential input, many of its applications call for a circuit Most traditional op amp inverters have relatively low input that has a single-ended input with a differential output. impedances, unless they are buffered with another amplifier. For a single-ended-to-differential circuit, the R of the input that G VOCM is assumed to be at midsupply. Because there is still the is not driven is tied to a reference voltage or to ground. Additional constraint that +VOUT must equal VIN, changing the VOCM voltage conditions are discussed in the following sections. In addition, does not change +V (equal to V ). Therefore, the effect of OUT IN the voltage at V , and therefore V , is assumed to be ground. OCM OUT, cm changing V must show up at −OUT. OCM Figure 67 shows a generalized schematic of such a circuit using an AD8132 with two feedback paths. For example, if V is raised by 1 V, then −V must increase OCM OUT by 2 V. This makes VOUT, cm also increase by 1 V because it is defined as the average of the two differential output voltages. This means that the gain from VOCM to the differential output is 2. Rev. I | Page 22 of 32 AD8132 With β2 equal to 0 in these circuits, the gain can theoretically be OTHER β2 = 1 CIRCUITS set to any value from close to 0 to infinity, just as it can with a The preceding simple configuration with β2 = 1 and its gain of 2 conventional op amp in the inverting mode. However, practical is the highest gain circuit that can be made under this condition. real-world limitations and parasitics limit the range of acceptable Because β1 was equal to 0, only higher β1 values are possible. gain to more modest values. The circuits with higher values of β1 have gains lower than 2. However, circuits with β1 equal to 1 are not practical because β1 = 0 they have no effective input and result in a gain of 0. There is yet another class of circuits where there is no feedback from −OUT to +IN. This is the case where β1 = 0. The differential To increase β1 from 0, it is necessary to add two resistors in a feed- amplifier without a resistor described in the Differential Amplifier back network. A generalized circuit that has β1 with a value higher Without Resistors (High Input Impedance Inverting Amplifier) than 0 is shown in Figure 69. A couple of different convenient section meets this condition, but it was presented only with the gains that can be created are a gain of 1, when β1 is equal to 1/3, condition that β2 = 1. Recall that this circuit had a gain equal to 2. and a gain of 0.5, when β1 equals 0.6. If β2 decreases in this circuit from unity, a smaller part of +V With β2 equal to 1 in these circuits, V serves as the refer- OUT OCM is fed back to −IN and the gain increases (see Figure 68). This ence voltage that measures the input voltage and the individual circuit is very similar to a noninverting op amp configuration, output voltages. In general, when V is varied in circuits with OCM except for the presence of the additional complementary output. unmatched feedback networks, a differential output signal is Therefore, the overall gain is twice that of a noninverting op generated that is proportional to the applied VOCM voltage. amp or 2 × (1 + RF2/RG2) or 2 × (1/β2). VARYING β2 Once again, varying VOCM does not affect both outputs in the Though the β2 = 1 circuit sets β2 to 1, another class of simple same way; therefore, in addition to varying V with unity OUT, cm circuits can be made that sets β2 equal to 0. This means that gain, there is also an effect on V by changing V . OUT, dm OCM there is no feedback from +OUT to −IN. This class of circuits is very similar to a conventional inverting op amp. However, ESTIMATING THE OUTPUT NOISE VOLTAGE the AD8132 circuits have an additional output and common- Similar to the case of a conventional op amp, the differential mode input that can be analyzed separately (see Figure 71). output errors (noise and offset voltages) can be estimated by multiplying the input-referred terms, at +IN and −IN, by the With −IN connected to ground, +IN becomes a virtual ground circuit noise gain. The noise gain is defined as in the sense that the term is used for conventional op amps. Both inputs must maintain the same voltage for equilibrium operation; ⎛ ⎞ R F ⎜ ⎟ therefore, if one is set to ground, the other is driven to ground. G = 1+ N ⎜ ⎟ R ⎝ G⎠ The input impedance can also be seen to be equal to RG, just as in a conventional op amp. To compute the total output-referred noise for the circuit of Figure 64, consideration must be given to the contribution of In this case, however, the positive input and negative output are resistors, RF and RG. See Table 11 for estimated output noise used for the feedback network. Because a conventional op amp voltage densities at various closed-loop gains. does not have a negative output, only its inverting input can be used for the feedback network. The AD8132 is symmetrical, Table 11. Recommended Resistor Values and Noise therefore, the feedback network on either side can be used to Performance for Specific Gains produce the same results. Output Output Noise Noise Because +IN is a summing junction, by an analogy to conven- AD8132 AD8132 tional op amps, the gain from VIN to −OUT is −RF/RG. This holds Bandwidth Only + R , R G F true regardless of the voltage on V , and because +OUT Gain R (Ω) R (Ω) −3 dB (MHz) (nV/√Hz) (nV/√Hz) OCM G F moves the same amount in the opposite direction from −OUT, 1 499 499 360 16 17 the overall gain is −2(R /R ). F G 2 499 1.0 k 160 24.1 26.1 5 499 2.49 k 65 48.4 53.3 V still governs V ; therefore, +OUT must be the only OCM OUT, cm 10 499 4.99 k 20 88.9 98.6 output that moves when VOCM is varied. Because VOUT, cm is the average of the two outputs, +OUT must move twice as far, and in the same direction as VOCM, to create the proper VOUT, cm. Therefore, the gain from VOCM to +OUT must be 2. Rev. I | Page 23 of 32 AD8132 When using the AD8132 in gain configurations where β1 ≠ β2, In cases where more accurate control of the output common-mode differential output noise appears due to input-referred voltage level is required, it is a best practice that an external source or noise in the V circuitry according to the following formula: OCM resistor divider (with R < 10 kΩ) be used. The output SOURCE common-mode offset values in the Specifications section assume ⎡ ⎤ β1− β2 V =2 V ⎢ ⎥ OND NOCM the VOCM input is driven by a low impedance voltage source. β1+ β2 ⎢ ⎥ ⎣ ⎦ DRIVING A CAPACITIVE LOAD where: A purely capacitive load can react with the pin and bond wire VOND is the output differential noise. inductance of the AD8132, resulting in high frequency ringing VNOCM is the input-referred voltage noise on VOCM. in the pulse response. One way to minimize this effect is to place a small capacitor across each of the feedback resistors. The added CALCULATING INPUT IMPEDANCE OF THE capacitance must be small to avoid destabilizing the amplifier. An APPLICATION CIRCUIT alternative technique is to place a small resistor in series with The effective input impedance of a circuit, such as that in Figure 64, the amplifier outputs, as shown in Figure 60. at +D and −D , depends on whether the amplifier is being IN IN driven by a single-ended or differential signal source. For balanced OPEN-LOOP GAIN AND PHASE differential input signals, the input impedance (RIN, dm) between Open-loop gain and phase plots are shown in Figure 65 and the inputs (+DIN and −DIN) is simply Figure 66. RIN, dm = 2 × RG 60 R = 2kΩ In the case of a single-ended input signal (for example, if −DIN L, dm 50 is grounded and the input signal is applied to +D ), the input IN 40 impedance becomes 30 ⎛ ⎞ ⎜ ⎟ R 20 ⎜ G ⎟ R = IN,dm ⎜ R ⎟ F 1− 10 ⎜ ⎟ 2× ⎝ () R + R ⎠ G F 0 The circuit input impedance is effectively higher than it would –10 be for a conventional op amp connected as an inverter because –20 a fraction of the differential output voltage appears at the inputs 0.1 1 10 100 1000 as a common-mode signal, partially bootstrapping the voltage FREQUENCY (MHz) across the input resistor, RG. Figure 65. Open-Loop Gain vs. Frequency 40 INPUT COMMON-MODE VOLTAGE RANGE IN 20 R = 2kΩ SINGLE-SUPPLY APPLICATIONS L, dm 0 The AD8132 is optimized for level-shifting, ground-referenced –20 input signals. For a single-ended input, this implies that the voltage –40 at −DIN in Figure 64 is 0 V when the negative power supply –60 voltage (at V−) of the amplifier is also set to 0 V. –80 –100 SETTING THE OUTPUT COMMON-MODE VOLTAGE –120 The V pin of the AD8132 is internally biased at a voltage OCM –140 approximately equal to the midsupply point (average value of the –160 voltage on V+ and V−). Relying on this internal bias results in an –180 output common-mode voltage that is within approximately –200 0.1 1 10 100 1000 100 mV of the expected value. FREQUENCY (MHz) Figure 66. Open-Loop Phase vs. Frequency Rev. I | Page 24 of 32 OPEN-LOOP PHASE (Degrees) OPEN-LOOP GAIN (dB) 01035-084 01035-083 AD8132 LAYOUT, GROUNDING, AND BYPASSING CIRCUITS As a high speed part, the AD8132 is sensitive to the printed R F1 circuit board (PCB) environment in which it operates. Realizing R G1 its superior specifications requires attention to various details of + good high speed PCB design. R G2 The first requirement is a good solid ground plane that covers as R much of the board area around the AD8132 as possible. The only F2 exception to this is that the two input pins (Pin 1 and Pin 8) are Figure 67. Typical Four-Resistor Feedback Circuit kept a few millimeters from the ground plane and that ground V + IN be removed from inner layers and the opposite side of the board under the input pins. This minimizes the stray capacitance on these nodes and helps preserve the gain flatness vs. the frequency. R F2 R G2 Bypass the power supply pins as close as possible to the device to the nearby ground plane and use good high frequency ceramic Figure 68. Typical Circuit with β1 = 0 chip capacitors. Do this bypassing with a capacitance value R F1 of 0.01 μF to 0.1 μF for each supply. Farther away, provide low R G1 frequency bypassing with 10 μF tantalum capacitors from each + supply to ground. Keep the signal routing short and direct to avoid parasitic effects. Wherever there are complementary signals, a symmetrical Figure 69. Typical Circuit with β2 = 1 layout with matched lengths must be provided to the extent V + IN possible to maximize the balance performance. When running differential signals over a long distance, place the traces on the PCB close together or twist together any differential wiring to minimize the area of the loop that is formed. This reduces Figure 70. G = +2 Circuit with β1 = 0, Without Resistors the radiated energy and makes the circuit less susceptible to R F1 interference. R G1 V IN + Figure 71. Typical Circuit with β2 = 0 Rev. I | Page 25 of 32 01035-068 01035-067 01035-065 01035-066 01035-069 AD8132 APPLICATIONS INFORMATION 10 ANALOG-TO-DIGITAL DRIVER f = 40MHz FUND S 0 f = 2.5MHz IN Many of the newer high speed ADCs are single supply and have –10 differential inputs. Thus, the driver for these devices is able to –20 convert from a single-ended signal to a differential signal and –30 –40 provide output common-mode level shifting in addition to –50 having low distortion and noise. The AD8132 conveniently –60 performs these functions when driving the AD9203, a 10-bit, –70 2ND 5TH 6TH 8TH 40 MSPS ADC. 9TH –80 7TH 3RD 4TH –90 In Figure 73, a 1 V p-p signal drives the input of an AD8132 –100 configured for unity gain. Both the AD8132 and the AD9203 are –110 powered from a single 3 V supply. A voltage divider biases V OCM –120 at midsupply and in turn drives V to half of the supply OUT, cm 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 INPUT FREQUENCY (MHz) voltage. This is within the common-mode range of the AD9203. Figure 72. FTT Response for AD8132 Driving AD9203 Between the ADC and the driver is a 1-pole, differential filter that BALANCED CABLE DRIVER helps to filter some of the noise and assists the switched-capacitor inputs of the ADC. Each of the ADC inputs is driven by a 0.5 V p-p When driving a twisted pair cable, it is desirable to drive only signal that ranges from 1.25 V dc to 1.75 V dc. Figure 72 is an a pure differential signal onto the line. If the signal is purely FFT plot of the performance of the circuit when running at a differential (that is, fully balanced), and the transmission line is clock rate of 40 MSPS and an input frequency of 2.5 MHz. twisted and balanced, there is minimum radiation of any signal. The complementary electrical fields are confined mostly to the space between the two twisted conductors and does not significantly radiate out from the cable. The current in the cable creates magnetic fields that radiate to some degree. However, the amount of radiation is mitigated by the twists, because for each twist, the two adjacent twists have an opposite polarity magnetic field. If the twist pitch is tight enough, these small magnetic field loops contain most of the magnetic flux, and the magnetic farfield strength is negligible. 3V 3V 3V 10kΩ + 0.1µF 10µF 10kΩ 348Ω 0.1µF 0.1µF 1V p-p 28 2 60.4Ω 348Ω AVDD DRVDD 25 3 8 AINN 5 20pF 49.9Ω DIGITAL AD9203 2 AD8132 OUTPUTS 0.1µF 20pF 4 AINP 348Ω 60.4Ω 1 6 26 AVSS DRVSS 24.9Ω 27 1 348Ω Figure 73. AD8132 Driving AD9203, a 10-Bit, 40 MSPS ADC Rev. I | Page 26 of 32 OUTPUT (dBc) 01035-070 01035-071 AD8132 +5V +5V + 0.1µF 10µF + 1kΩ 0.1µF 10µF 499Ω 49.9Ω 1 49.9Ω 50Ω 100Ω AD8132 SOURCE 0.1µF 2 AD830 TWISTED PAIR 7 523Ω 49.9Ω 3 V OUT 1kΩ 4 10µF 0.1µF 5 + –5V 10µF 0.1µF + –5V Figure 74. Balanced Line Driver and Receiver Using AD8132 and AD830 20 Any imbalance in the differential drive signal appears as a 10 common-mode signal on the cable. This is the equivalent of a single wire that is driven with the common-mode signal. In 0 this case, the wire acts as an antenna and radiates. Therefore, to –10 minimize radiation when driving differential twisted pair cables, –20 make sure the differential drive signal is well balanced. –30 The common-mode feedback loop in the AD8132 helps to –40 minimize the amount of common-mode voltage at the output –50 and can, therefore, be used to create a well-balanced differential –60 line driver. Figure 74 shows an application that uses an AD8132 –70 as a balanced line driver and an AD830 as a differential receiver –80 configured for unity gain. This circuit was operated with 10 meters 1 10 100 1000 of Category 5 cable. FREQUENCY (MHz) Figure 76. Frequency Response for Transmit Boost Circuit TRANSMIT EQUALIZER LOW-PASS DIFFERENTIAL FILTER Any length of transmission line attenuates the signals it carries. This effect is worse at higher frequencies than at lower frequencies. Similar to an op amp, various types of active filters can be One way to compensate for this is to provide an equalizer circuit created with the AD8132. These can have single-ended inputs that boosts the higher frequencies in the transmitter circuit, so and differential outputs that can provide an antialias function that at the receive end of the cable, the attenuation effects are when driving a differential ADC. diminished. 2.15kΩ 549Ω 33pF By lowering the impedance of the RG component of the feedback 2kΩ 953Ω 200pF network at a higher frequency, the gain can be increased at a 100pF V V 49.9Ω IN OUT 100pF 953Ω high frequency. Figure 75 shows the gain of a two-line driver 200pF 2kΩ that has its R resistors shunted by 10 pF capacitors. The effect G 33pF 24.9Ω 549Ω of this is shown in the frequency response plot of Figure 76. 2.15kΩ Figure 77. 1 MHz, 3-Pole Differential Output, 499Ω 10pF Low-Pass, Multiple Feedback Filter 49.9Ω V IN 249Ω Figure 77 is a schematic of a low-pass, multiple feedback filter. 100Ω V 49.9Ω OUT 249Ω The active section contains two poles, and an additional pole 49.9Ω 24.9Ω is added at the output. The filter was designed to have a −3 dB 10pF frequency of 1 MHz. 499Ω Figure 75. Frequency Boost Circuit Rev. I | Page 27 of 32 01035-073 V /V (dB) OUT IN 01035-072 01035-074 01035-075 AD8132 The actual −3 dB frequency was measured to be 1.12 MHz, as If the receive end common-mode voltage is set to ground, it is shown in Figure 78. well defined at the receive end. Any common-mode signal that is picked up over the cable length due to noise appears at the 10 transmit end and must be absorbed by the transmitter. Thus, it is 0 important that the transmitter have adequate common-mode –10 output range to absorb the full amplitude of the common-mode –20 signal coupled onto the cable and therefore prevent clipping. –30 Another way to look at this is that the circuit performs what is –40 sometimes called a transformer action. One main difference is –50 that the AD8132 passes dc while transformers do not. –60 A transformer can also be easily configured to have either a high or –70 low common-mode output impedance. If the transformers center –80 tap is connected to a solid voltage reference, it sets the common- –90 mode voltage on the secondary side of the transformer. In this case, 10k 100k 1M 10M 100M FREQUENCY (Hz) if one of the differential outputs is grounded, the other output has Figure 78. Frequency Response of 1 MHz Low-Pass Filter half of the differential output signal. This keeps the common-mode voltage at ground, where it is required to be due to the center tap HIGH COMMON-MODE OUTPUT IMPEDANCE connection. This is analogous to the AD8132 operating with a low AMPLIFIER output impedance common mode (see Figure 80). Changing the connection to VOCM (Pin 2) can change the common- V V mode from low impedance to high impedance. If VOCM is actively OCM DIFF set to a particular voltage, the AD8132 tries to force V to OUT, cm the same voltage with a relatively low output impedance. All the Figure 80. Transformer with Low Output Impedance Secondary Set at V OCM previous analysis assumed that this output impedance is arbitrarily If the center tap of the secondary of a transformer is allowed to low enough to drive the load condition in the circuit. float as shown in Figure 81 (or if there is no center tap), the However, some applications benefit from high common-mode transformer has high common-mode output impedance. This output impedance. This is accomplished with the circuit shown means that the common mode of the secondary is determined in Figure 79. by what it is connected to and not by anything to do with the transformer itself. R F 348Ω R G 10Ω NC V DIFF 348Ω 49.9Ω 1kΩ Figure 81. Transformer with High Output Impedance Secondary 49.9Ω 1kΩ R G 348Ω 10Ω If one of the differential ends of the transformer is grounded, R F 348Ω the other end swings with the full output voltage. This means that the common mode of the output voltage is one-half of the differential output voltage. However, this shows that the common Figure 79. High Common-Mode, Output Impedance, Differential Amplifier mode is not forced via low impedance to a given voltage. The common-mode output voltage can be easily changed to any voltage V is driven by a resistor divider that measures the output OCM through its other output terminals. common-mode voltage. Thus, the common-mode output voltage takes on the value that is set by the driven circuit. In this case, The AD8132 can exhibit the same performance when one of it comes from the center point of the termination at the receive the outputs in Figure 79 is grounded. The other output swings end of a 10 meter length of Category 5 twisted pair cable. at the full differential output voltage. The common-mode signal is measured by the voltage divider across the outputs and input to VOCM. This, then, drives VOUT, cm to the same level. At higher frequencies, it is important to minimize the capacitance on the VOCM node; otherwise, phase shifts can compromise the performance. The voltage divider resistances can also be lowered for better frequency response. Rev. I | Page 28 of 32 V /V (dB) OUT IN 01035-077 01035-076 01035-078 01035-079 AD8132 FULL-WAVE RECTIFIER If there is not enough forward bias (V too low), the lower OUT, cm sharp cusps of the full-wave rectified output waveform are rounded The balanced outputs of the AD8132, along with a couple of off. In addition, as the frequency increases, there tends to be some Schottky diodes, can create a very high speed, full-wave rectifier. Such circuits are useful for measuring ac voltages and other rounding of the lower cusps. The forward bias can be increased computational tasks. to yield sharper cusps at higher frequencies. Figure 82 shows the configuration of such a circuit. Each of the There is not a reliable, entirely quantifiable, means to measure AD8132 outputs drives the anode of an HP2835 Schottky diode. the performance of a full-wave rectifier. Because the ideal waveform has periodic sharp discontinuities, it has (mostly These Schottky diodes were chosen for their high speed operation. even) harmonics that have no upper bound on the frequency. At lower frequencies (approximately lower than 10 MHz), a silicon However, for a practical circuit, as the frequency increases, the signal diode, such as a 1N4148, can be used. The cathodes of the higher harmonics become attenuated and the sharp cusps that two diodes are connected together, and this output node is connected to ground by a 100 Ω resistor. are present at low frequencies become significantly rounded. +5V When running the circuit at a frequency up to 300 MHz, though it R F1 348Ω stays functional, the major harmonic that remains in the output R G1 348Ω is the second. This looks like a sine wave at 600 MHz. Figure 83 is V IN R an oscilloscope plot of the output when driven by a 100 MHz, T1 49.9Ω 2.5 V p-p input. R R T2 G2 HP2835 24.9Ω 348Ω Sometimes a second harmonic generator is useful for creating a R V F2 OUT 348Ω R L +5V clock to oversample a DAC by a factor of two. If the output of 100Ω –5V this circuit is run through a low-pass filter, it can be used as a 10kΩ CR1 second harmonic generator. Figure 82. Full-Wave Rectifier 1V Operate the diodes such that they are slightly forward-biased when the differential output voltage is zero. For the Schottky diodes, this is approximately 400 mV. The forward biasing is conveniently adjusted by CR1, which, in this circuit, raises and lowers VOUT, cm without creating a differential output voltage. One advantage of this circuit is that the feedback loop is never momentarily opened while the diodes reverse their polarity within the loop. This scheme is sometimes used for full-wave rectifiers 100mV 2ns that use conventional op amps. These conventional circuits do Figure 83. Full-Wave Rectifier Response with 100 MHz Input not work well at frequencies above approximately 1 MHz. AUTOMOTIVE PRODUCTS The AD8132W is qualified per the AEC-Q100 for use in automotive applications. Custom variants of this product may be available to meet stringent automotive performance and quality requirements. Rev. I | Page 29 of 32 01035-080 01035-081 AD8132 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 84. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.70 0.15 0.23 6° 0.55 0.40 0.05 0.13 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 85. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Ordering Quantity AD8132AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8132AR-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 2,500 AD8132AR-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1,000 1 AD8132ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8132ARZ-RL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 2,500 1 AD8132ARZ-R7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1,000 AD8132ARM −40°C to +125°C 8-Lead MSOP RM-8 HMA AD8132ARM-REEL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 HMA 3,000 AD8132ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 HMA 1,000 1 AD8132ARMZ −40°C to +125°C 8-Lead MSOP RM-8 HMA# 1 AD8132ARMZ-REEL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 HMA# 3,000 1 AD8132ARMZ-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 HMA# 1,000 1, 2 AD8132WARMZ-R7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H14 1,000 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. 2 Automotive qualified product. Rev. I | Page 30 of 32 091709-A 012407-A AD8132 NOTES Rev. I | Page 31 of 32 AD8132 NOTES ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01035–0–9/09(I) Rev. I | Page 32 of 32