ANALOG DEVICES AD8123

Triple Differential Receiver with Adjustable Line Equalization AD8123 FEATURES FUNCTIONAL BLOCK DIAGRAM V V V V PEAK POLE OFFSET GAIN Compensates cables to 300 meters for wideband video Fast rise and fall times AD8123 4.9 ns with 2 V step @ 150 meters of UTP cable 8.0 ns with 2 V step @ 300 meters of UTP cable –IN R OUT R 55 dB peak gain at 100 MHz +IN R Two frequency response gain adjustment pins –IN High frequency peaking adjustment (V ) G PEAK OUT G Broadband flat gain adjustment (V ) GAIN +IN G Pole location adjustment pin (V ) POLE –IN B Compensates for variations between cables OUT B +IN Can be optimized for either UTP or coaxial cable B DC output offset adjust (V ) OFFSET –IN CMP1 Low output offset voltage: 24 mV OUT CMP1 +IN CMP1 Compensates both RGB and YPbPr –IN Two on-chip comparators with hysteresis CMP2 OUT CMP2 Can be used for common-mode sync extraction +IN CMP2 Available in 40-lead, 6 mm × 6 mm LFCSP Figure 1. APPLICATIONS Keyboard-video-mouse (KVM) Digital signage RGB video over UTP cables Professional video projection and distribution HD video Security video For added flexibility, an optional pole adjustment pin, VPOLE, GENERAL DESCRIPTION allows movement of the pole locations, allowing for the The AD8123 is a triple, high speed, differential receiver and compensation of different gauges and types of cable as well equalizer that compensates for the transmission losses of UTP as variations between different cables and/or equalizers. The and coaxial cables up to 300 meters in length. Various gain VOFFSET pin allows the dc voltage at the output to be adjusted, stages are summed together to best approximate the inverse adding flexibility for dc-coupled systems. frequency response of the cable. Logic circuitry inside the AD8123 controls the gain functions of the individual stages so that the The AD8123 is available in a 6 mm × 6 mm, 40-lead LFCSP lowest noise can be achieved at short-to-medium cable lengths. and is rated to operate over the extended temperature range of This technique optimizes its performance for low noise, short- −40°C to +85°C. to-medium range applications, while at the same time provides UXGA RESOLUTION IMAGE UXGA RESOLUTION IMAGE AFTER 300 METER CAT-5 CABLE AFTER 300 METER CAT-5 CABLE the high gain bandwidth required for long cable equalization BEFORE AD8123. AFTER AD8123. (up to 300 meters). Each channel features a high impedance differential input that is ideal for interfacing directly with the cable. The AD8123 has three control pins for optimal cable compensation, as well as an output offset adjust pin. Two voltage-controlled pins are used to compensate for different cable lengths; the VPEAK pin controls the amount of high frequency Figure 2. peaking and the VGAIN pin adjusts the broadband flat gain, which compensates for the low frequency flat cable loss. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 06814-001 06814-019 AD8123 TABLE OF CONTENTS Features .............................................................................................. 1 Comparators ............................................................................... 11 Applications....................................................................................... 1 Sync Pulse Extraction Using Comparators............................. 12 Functional Block Diagram .............................................................. 1 Using the VPEAK, VPOLE, VGAIN, and VOFFSET Inputs................... 12 General Description ......................................................................... 1 Using the AD8123 with Coaxial Cable.................................... 13 Revision History ............................................................................... 2 Driving 75 Ω Video Cable With the AD8123 ........................ 13 Specifications..................................................................................... 3 Driving a Capacitive Load......................................................... 13 Absolute Maximum Ratings............................................................ 5 Filtering the RGB Outputs ........................................................ 13 Thermal Resistance ...................................................................... 5 Power Supply Filtering............................................................... 14 ESD Caution.................................................................................. 5 Layout and Power Supply Decoupling Considerations......... 14 Pin Configuration and Function Description .............................. 6 Input Common-Mode Range ................................................... 15 Typical Performance Characteristics ............................................. 7 Small Signal Frequency Response............................................ 15 Theory of Operation ...................................................................... 10 Power-Down ............................................................................... 15 Input Common-Mode Voltage Range Considerations ......... 10 Outline Dimensions ....................................................................... 16 Applications Information .............................................................. 11 Ordering Guide .......................................................................... 16 Basic Operation .......................................................................... 11 REVISION HISTORY 11/07—Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Ordering Guide .......................................................... 16 8/07—Revision 0: Initial Version Rev. A | Page 2 of 16 AD8123 SPECIFICATIONS TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), VOFFSET = 0 V, VPEAK, VGAIN, and VPOLE are set to recommended settings shown in Figure 17, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit PEAKING PERFORMANCE (NO CABLE) Peak Frequency VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 1 V 100 MHz VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 2 V 105 MHz Peak Gain VPEAK = 2 V, VGAIN = 0.6 V, VPOLE = 1 V 45 dB V = 2 V, V = 0.6 V, V = 2 V 55 dB PEAK GAIN POLE DYNAMIC PERFORMANCE 10% to 90% Rise/Fall Time VOUT = 2 V step, 150 meters Cat-5 4.9 ns V = 2 V step, 300 meters Cat-5 8.0 ns OUT Settling Time to 2% V = 2 V step, 150 meters Cat-5 36 ns OUT VOUT = 2 V step, 300 meters Cat-5 106 ns –3 dB Large Signal Bandwidth VOUT = 1 V p-p, <10 meters Cat-5 120 MHz VOUT = 2 V p-p, <10 meters Cat-5 110 MHz V = 2 V p-p, 150 meters Cat-5 78 MHz OUT V = 2 V p-p, 300 meters Cat-5 43 MHz OUT Integrated Output Voltage Noise 150 meter setting, integrated to 160 MHz 2.5 mV rms 300 meter setting, integrated to 160 MHz 24 mV rms INPUT DC PERFORMANCE Input Voltage Range −IN and +IN ±3.0 V Maximum Differential Voltage Swing 4 V p-p Voltage Gain ΔVO/ΔVI, VGAIN set for 0 meters of cable 1 V/V Common-Mode Rejection Ratio (CMRR) At dc, VPEAK = VGAIN = VPOLE = 0 V −86 dB At dc, V = V = V = 2 V −67 dB PEAK GAIN POLE At 1 MHz, V = V = V = 2 V −52 dB PEAK GAIN POLE Input Resistance Common mode 4.4 MΩ Differential 3.7 MΩ Input Capacitance Common mode 1.0 pF Differential 0.5 pF Input Bias Current 2.4 μA V Pin Current 28.9 μA OFFSET VGAIN Pin Current 0.5 μA VPEAK Pin Current 0.4 μA VPOLE Pin Current 0.4 μA ADJUSTMENT PINS VPEAK Input Voltage Range Relative to GND 0 to 2 V VPOLE Input Voltage Range Relative to GND 0 to 2 V V Input Voltage Range Relative to GND 0 to 2 V GAIN V to OUT Gain OUT/V , range limited by output swing 1 V/V OFFSET OFFSET Maximum Flat Gain VGAIN = 2 V 2 dB OUTPUT CHARACTERISTICS Output Voltage Swing 150 Ω load −3.75 to +3.69 V 1 kΩ load −3.66 to +3.69 V Output Offset Voltage Referred to output, VPEAK = VGAIN = VPOLE = 0 V 24 mV Referred to output, VPEAK = VGAIN = VPOLE = 2 V 32 mV Output Offset Voltage Drift Referred to output 33 μV/°C Rev. A | Page 3 of 16 AD8123 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Voltage Range ±4.5 ±5.5 V Positive Quiescent Supply Current 132 mA Negative Quiescent Supply Current 126 mA Supply Current Drift, I /I 80 μA/°C CC EE Positive Power Supply Rejection Ratio DC, referred to output −51 dB Negative Power Supply Rejection Ratio DC, referred to output −63 dB Power Down, VIH (Minimum) Minimum Logic 1 voltage 1.1 V Power Down, V (Maximum) Maximum Logic 0 voltage 0.8 V IL Positive Supply Current, Powered Down V = V = V = 0 V 1.1 μA PEAK GAIN POLE Negative Supply Current, Powered Down V = V = V = 0 V 0.7 μA PEAK GAIN POLE COMPARATORS Output Voltage Levels V /V 3.33/0.043 V OH OL Hysteresis V 70 mV HYST Propagation Delay tPD, LH/tPD, HL 17.5/10.0 ns Rise/Fall Times tRISE/tFALL 9.3/9.3 ns Output Resistance 0.03 Ω OPERATING TEMPERATURE RANGE −40 +85 °C Rev. A | Page 4 of 16 AD8123 ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (PD) is the sum of the Table 2. quiescent power dissipation and the power dissipated in the Parameter Rating package due to the load drive for all outputs. The quiescent Supply Voltage 11 V power is the voltage between the supply pins (V ) times the S Power Dissipation See Figure 3 quiescent current (I ). The power dissipation due to each load S Input Voltage (Any Input) VS− − 0.3 V to VS+ + 0.3 V current is calculated by multiplying the load current by the Storage Temperature Range −65°C to +125°C voltage difference between the associated power supply and the Operating Temperature Range −40°C to +85°C output voltage. The total power dissipation due to load currents Lead Temperature (Soldering, 10 sec) 300°C is then obtained by taking the sum of the individual power Junction Temperature 150°C dissipations. RMS output voltages must be used when dealing with ac signals. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Airflow reduces θ . In addition, more metal directly in contact JA rating only; functional operation of the device at these or any with the package leads from metal traces, through holes, ground, other conditions above those indicated in the operational section of and power planes reduces the θ . The exposed paddle on the JA this specification is not implied. Exposure to absolute maximum underside of the package must be soldered to a pad on the PCB rating conditions for extended periods may affect device reliability. surface that is thermally connected to a solid plane (usually the ground plane) to achieve the specified θJA. THERMAL RESISTANCE Figure 3 shows the maximum safe power dissipation in the θ is specified for the worst-case conditions, that is, θ is JA JA package vs. the ambient temperature for the 40-lead LFCSP specified for the device soldered in a circuit board in still air. (29°C/W) on a JEDEC standard 4-layer board with the underside Table 3. Thermal Resistance with the Underside Pad paddle soldered to a pad that is thermally connected to a PCB Connected to the Plane plane. θ values are approximations. JA Package Type/PCB Type θJA Unit 7 40-Lead LFCSP/4-Layer 29 °C/W 6 Maximum Power Dissipation 5 The maximum safe power dissipation in the AD8123 package 4 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition 3 temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the 2 package exerts on the die, permanently shifting the parametric 1 performance of the AD8123. Exceeding a junction temperature of 175°C for an extended time can result in changes in the 0 silicon devices, potentially causing failure. –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION Rev. A | Page 5 of 16 MAXIMUM POWER DISSIPATION (W) 06814-025 AD8123 PIN CONFIGURATION AND FUNCTION DESCRIPTION AD8123 TOP VIEW (Not to Scale) NC 1 30 NC +IN V CMP1 2 29 S+ 1 –IN 3 28 CMP1 PD OUT 27 CMP1 4 V POLE V _CMP 5 26 V S+ PEAK OUT 6 25 V CMP2 GAIN –IN GND 7 24 CMP2 2 V +IN 8 23 OFFSET CMP2 V V _CMP 9 22 S– S– NC NC 10 21 NC = NO CONNECT NOTES 1. EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO A PCB PLANE TO ACHIEVE SPECIFIED THERMAL RESISTANCE. Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1, 10, 20, 21, 30, 40 NC No Internal Connection. 2 +INCMP1 Positive Input, Comparator 1. 3 −IN Negative Input, Comparator 1. CMP1 4 OUT Output, Comparator 1. CMP1 5 VS+_CMP Positive Power Supply, Comparator. Must be connected to VS+. 6 OUTCMP2 Output, Comparator 2. 7 −INCMP2 Negative Input, Comparator 2. 8 +IN Positive Input, Comparator 2. CMP2 9 V _CMP Negative Power Supply, Comparator. Must be connected to V . S− S− 11, 14, 17, 22, 33 V Negative Power Supply, Equalizer Sections. S− 12 OUTB Output, Blue Channel. 13, 16, 19, 29, 36 VS+ Positive Power Supply, Equalizer Sections. 15 OUTG Output, Green Channel. 18 OUT Output, Red Channel. R 23 V Output Offset Control Voltage. OFFSET 24, 39 GND Signal Ground Reference. 25 VGAIN Broadband Flat Gain Control Voltage. 26 VPEAK Equalizer High Frequency Boost Control Voltage. 27 V Equalizer Pole Location Adjustment Control Voltage. POLE 28 PD Power Down. 31 +IN Positive Input, Red Channel. R 32 −INR Negative Input, Red Channel. 34 +ING Positive Input, Green Channel. 35 −ING Negative Input, Green Channel. 37 +IN Positive Input, Blue Channel. B 38 −IN Negative Input, Blue Channel. B Exposed Underside Pad Thermal Plane Connection. Connect to any PCB plane with voltage between VS+ and VS−. Rev. A | Page 6 of 16 V NC S– OUT GND B V –IN S+ B V +IN S– B OUT V G S+ V –IN S+ G V +IN S– G OUT V R S– V –IN S+ R NC +IN R 06814-002 11 40 12 39 13 38 14 37 15 36 16 35 17 34 18 33 19 32 20 31 AD8123 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), VOFFSET = 0 V, VPEAK, VGAIN, and VPOLE are set to recommended settings shown in Figure 17, unless otherwise noted. 4 3 V = 0V V = 2V p-p GAIN O 2 V = 0V POLE 3 V = 1V p-p 1 O 2 0 –1 1 –2 0 –3 –4 –1 –5 –2 –6 –7 –3 –8 50m –4 –9 100m V = 0V GAIN 150m –10 V = 1V –5 GAIN 200m V = 2V –11 GAIN 300m –6 –12 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 8. Equalized Frequency Response for Various Cable Lengths Figure 5. Frequency Response for Various V Without Cable GAIN 120 60 V = 0.6V V = 2V p-p GAIN O V = 2V POLE V = 1V p-p O 100 40 80 20 60 0 40 –20 20 –40 V = 0V PEAK V = 1V PEAK V = 2V PEAK 0 –60 0 50 100 150 200 250 300 100k 1M 10M 100M CABLE LENGTH (meters) FREQUENCY (Hz) Figure 9. Equalized −3 dB Bandwidth vs. Cable Length Figure 6. Frequency Response for Various VPEAK Without Cable 6 40 V = 0.6V V = 0.6V GAIN GAIN V = 0V PEAK V = 1V 30 PEAK V = 0V POLE V = 1V p-p O 4 20 10 2 0 0 –10 –20 –2 –30 –40 –4 V = 0V POLE INPUT –50 V = 1V POLE OUTPUT V = 2V POLE –6 –60 0 50 100 150 200 250 300 350 400 450 500 100k 1M 10M 100M TIME (ns) FREQUENCY (Hz) Figure 10. Overdrive Recovery Figure 7. Frequency Response for Various VPOLE Without Cable Rev. A | Page 7 of 16 GAIN (dB) GAIN (dB) GAIN (dB) 06814-005 06814-004 06814-003 VOLTAGE (V) BANDWIDTH (MHz) GAIN (dB) 06814-006 06814-008 06814-007 AD8123 1.5 1.5 50m 50m 150m 150m 300m 300m 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 50 100 150 200 250 300 350 400 450 500 012345678 9 10 TIME (ns) TIME (µs) Figure 11. Pulse Response for Various Cable Lengths (2 MHz) Figure 14. Pulse Response for Various Cable Lengths (100 kHz) 10000 30 0m 150m 300m 25 1000 20 15 100 10 5 10 0 100k 1M 10M 100M 25 50 75 100 125 150 175 200 225 250 275 300 FREQUENCY (Hz) CABLE LENGTH (meters) Figure 12. Output Voltage Noise vs. Frequency for Various Cable Length Figure 15. Integrated Output Voltage Noise vs. Cable Length 20 20 V = 0V, V = 0V, V = 0V GAIN PEAK POLE V = 0V, V = 0V, V = 0V GAIN PEAK POLE 10 10 V = 1.85V, V = 1.65V, V = 1.75V GAIN PEAK POLE V = 1.85V, V = 1.65V, V = 1.75V GAIN PEAK POLE 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. CMRR vs. Frequency Figure 16. Crosstalk vs. Frequency Rev. A | Page 8 of 16 OUTPUT VOLTAGE NOISE (nV/ Hz) CMRR (dB) OUTPUT VOLTAGE (V) 06814-011 06814-009 06814-010 INTEGRATED OUTPUT VOLTAGE NOISE FROM CROSSTALK (dB) OUTPUT VOLTAGE (V) 100kHz TO 160MHz (mV rms) 06814-014 06814-012 06814-013 AD8123 2.0 2.0 V V PEAK PEAK V V POLE POLE 1.8 1.8 V V GAIN GAIN 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 0 25 50 75 100 125 150 175 200 225 250 275 300 25 50 75 100 125 150 175 200 225 250 275 300 CABLE LENGTH (meters) CABLE LENGTH (meters) Figure 17. Recommended Settings for UTP Cable Figure 18. Recommended Settings for Coaxial Cable Rev. A | Page 9 of 16 CONTROL VOLTAGE (V) 06814-015 CONTROL VOLTAGE (V) 06814-016 AD8123 THEORY OF OPERATION The AD8123 is a unity-gain, triple, wideband, low noise analog The AD8123 is designed such that systems that use short-to- line equalizer that compensates for losses in UTP and coaxial medium-length cables do not pay a noise penalty for excess gain cables up to 300 meters in length. The 3-channel architecture is that they do not require. The high gain is only available for targeted at high resolution RGB applications but can be used in longer length systems where it is required. This feature is built HD YPbPr applications as well. into the V control and is transparent to the user. PEAK Three continuously adjustable control voltages, common Two comparators are provided on-chip that can be used for to the RGB channels, are available to the designer to provide sync pulse extraction in systems that use sync-on-common compensation for various cable lengths as well as for variations mode encoding. Each comparator has very low output impedance in the cable itself. The VPEAK input is used to control the amount and can therefore be used in a source-only cable termination of high frequency peaking. VPEAK is the primary control that is scheme by placing a series resistor equal to the cable characteristic used to compensate for frequency and cable-length dependent, impedance directly on the comparator output. Additional high frequency losses that are present due to the skin effect of details are provided in the Applications Information section. the cable. A second control pin, V , is used to adjust broadband GAIN INPUT COMMON-MODE VOLTAGE RANGE gain to compensate for low frequency flat losses present in the CONSIDERATIONS cable. A third control, V , is used to move the positions of the POLE When using the AD8123 as a receiver, it is important to ensure equalizer poles and can be linearly derived from V , as illustrated PEAK that its input common-mode voltage stays within the specified in the Typical Performance Characteristics and Applications range. The received common-mode level is calculated by adding Information sections, for UTP and coaxial cables. Finally, an the common-mode level of the driver, the single-ended peak output offset adjust control, VOFFSET, allows the designer to shift amplitude of the received signal, the amplitude of any sync the output dc level. pulses, and the other induced common-mode signals, such as The AD8123 has a high impedance differential input that makes ground shifts between the driver and the AD8123 and pickup termination simple and allows dc-coupled signals to be received from external sources, such as power lines and fluorescent directly from the cable. The AD8123 input can also be used in a lights. See the Applications Information section for more details. single-ended fashion in coaxial cable applications. For differential systems that require very high CMRR, a triple differential receiver, such as the AD8143 or AD8145, can be placed in front of the AD8123. The AD8123 has a low impedance output that is capable of driving a 150 Ω load. For systems where the AD8123 has to drive a high impedance capacitive load, it is recommended that a small series resistor be placed between the output and load to buffer the capacitance. The resistor should not be so large as to reduce the overall bandwidth to an unacceptable level. Rev. A | Page 10 of 16 AD8123 APPLICATIONS INFORMATION The comparator outputs have nearly 0 Ω output impedance and BASIC OPERATION are designed to drive source-terminated transmission lines. The The AD8123 is easy to apply because it contains everything source termination technique uses a resistor in series with each on-chip needed for cable loss compensation. Figure 20 shows a comparator output such that the sum of the comparator source basic application circuit (power supplies not shown) with resistance (≈0 Ω) and the series resistor equals the transmission common-mode sync pulse extraction that is compatible with line characteristic impedance. The load end of the transmission the common-mode sync pulse encoding technique used in the line is high impedance. When the signal is launched into the source AD8134, AD8147, and AD8148 triple differential drivers. If termination, its initial value is one-half of its source value because sync extraction is not required, the terminations can be single its amplitude is divided by two in the voltage divider formed by 100 Ω resistors, and the comparator inputs can be left floating. the source termination and the transmission line. At the load, In Figure 20, the AD8123 is feeding a high impedance input, the signal experiences nearly 100% positive reflection due to the such as a delay line or crosspoint switch, and the additional gain high impedance load and is restored to nearly its full value. This of two that makes up for double termination loss is not required. technique is commonly used in PCB layouts that involve high COMPARATORS speed digital logic. In addition to general-purpose applications, the two on-chip Figure 19 shows how to apply the comparators with source comparators can be used to extract video sync pulses from the termination when driving a 50 Ω transmission line that is high received common-mode voltages or to receive differential digital impedance at its receive end. information. Built-in hysteresis helps to eliminate false triggers HIGH-Z from noise. The Sync Pulse Extraction Using Comparators 49.9Ω Z = 50Ω 0 section describes the sync extraction details. Figure 19. Using Comparator with Source Termination 26 V PEAK 27 ANALOG V AD8123 POLE CONTROL 25 V GAIN INPUTS 23 V OFFSET POWER DOWN 28 PD CONTROL RED 31 49.9Ω 18 RECEIVED RED VIDEO OUT RED VIDEO 32 49.9Ω GREEN 34 49.9Ω 15 RECEIVED GREEN VIDEO OUT 35 GREEN VIDEO 49.9Ω BLUE 37 49.9Ω 12 RECEIVED BLUE VIDEO OUT BLUE VIDEO 38 49.9Ω 1kΩ BLUE CMV 2 4 1kΩ 1 HSYNC OUT 3 RED CMV 8 6 2 VSYNC OUT GREEN 475Ω 7 CMV GND REFERENCE 24, 39 47pF 47pF Figure 20. Basic Application Circuit with Common-Mode Sync Extraction Rev. A | Page 11 of 16 06814-020 06814-021 AD8123 In some cases, as would likely be with automatic control, the SYNC PULSE EXTRACTION USING COMPARATORS V control is derived from a low impedance source, such as PEAK The AD8123 is useful in many systems that transport computer an op amp. Figure 21 shows how to derive V from V in a POLE PEAK video signals, which are typically comprised of red, green, and UTP application according to the recommended curves shown blue (RGB) video signals and separate horizontal and vertical in Figure 17, when VPEAK originates from a low impedance sync signals. Because the sync signals are separate and not source. Clearly, the 5 V supply must be clean to provide a clean embedded in the color signals, it is advantageous to transmit VPOLE voltage. them using a simple scheme that encodes them among the three 20Ω common-mode voltages of the RGB signals. The AD8134, V PEAK 5V AD8147, and AD8148 triple differential drivers are natural complements to the AD8123 because they perform the sync 14kΩ V 5.11kΩ PEAK V PEAK V ≈ + 0.9V POLE pulse encoding with the necessary circuitry on-chip. 2 8.25kΩ The sync encoding equations follow: Figure 21. Deriving VPOLE from VPEAK with Low-Z Source for UTP Cable K Red V =[V− H] (1) CM 2 The 20 Ω series resistor in the VPEAK path provides capacitive load buffering for the op amp. This value can be modified, K Green V =[− 2 V] (2) CM depending on the actual capacitive load. 2 In automatic equalization circuits that place the control voltages K Blue V =[V+ H] (3) CM inside feedback loops, attention must be paid to the poles 2 produced by the summing resistors and load capacitances. where: The peaking can also be adjusted by a mechanical or digitally Red VCM, Green VCM, and Blue VCM are the transmitted common- controlled potentiometer. In these cases, if the resistance of the mode voltages of the respective color signals. potentiometer is a couple of orders of magnitude lower than the K is an adjustable gain constant that is set by the driver. values of the resistors used to develop VPOLE, its resistance can be V and H are the vertical and horizontal sync pulses, defined ignored. Figure 22 shows how to use a 500 Ω potentiometer with with a weight of −1 when the pulses are in their low states, and a the resistor values shown in Figure 21 scaled up by a factor of 10. weight of +1 when they are in their high states. V PEAK 5V The AD8134 and AD8146/AD8147/AD8148 data sheets contain 5V 750Ω further details regarding the encoding scheme. Figure 20 illustrates 140kΩ 51.1kΩ V PEAK V ≈ how the AD8123 comparators can be used to extract the horizontal 500Ω + 0.9V POLE 2 82.5kΩ and vertical sync pulses that are encoded on the RGB common- mode voltages by the aforementioned drivers. Figure 22. Deriving V from V with Potentiometer for UTP Cable POLE PEAK USING THE V , V , V , AND V INPUTS PEAK POLE GAIN OFFSET Many potentiometers have wide tolerances. If a wide tolerance The VPEAK input is the main peaking control and is used to potentiometer is used, it may be necessary to change the value compensate for the low-pass roll-off in the cable response. The of the 750 Ω resistor to obtain a full swing for V . PEAK VPOLE input is a secondary frequency response shaping control The VGAIN input is essentially a contrast control and can be set that shifts the positions of the equalizer poles. The V input GAIN by adjusting it to produce the correct amplitude of a known test controls the wideband flat gain and is used to compensate for signal (such as a white screen) at the AD8123 output. the low frequency cable loss that is nominally flat. The V OFFSET VGAIN can also be derived from VPEAK according to the linear input is used to produce an offset at the AD8123 output. The relationships shown in Figure 17 and Figure 18. Figure 23 shows output offset is equal to the voltage applied to the VOFFSET input, how to derive V and V from V in a UTP application POLE GAIN PEAK limited by the output swing limits. that originates from a low-Z source. The VPEAK and VPOLE controls can be used independently or they 20Ω can be coupled to form a single peaking control. While Figure 17 V PEAK 5V and Figure 18 show recommended settings vs. cable length, 14kΩ designers may find other combinations that they prefer. These V 5.11kΩ V PEAK PEAK V ≈ POLE + 0.9V two controls give designers extra freedom, as well as the ability 2 8.25kΩ to compensate for different cable types (such as UTP and coaxial cable), as opposed to having only a single frequency shaping 5V control. 60.4kΩ 5.11kΩ V ≈ 0.89 × V + 0.38V GAIN PEAK 133kΩ Figure 23. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for UTP Cable Rev. A | Page 12 of 16 06814-027 06814-026 06814-028 AD8123 The other option is to include a triple gain-of-2 buffer, such as the USING THE AD8123 WITH COAXIAL CABLE ADA4862-3, on the AD8123 RGB outputs, as shown in Figure 26 The VPOLE control allows the AD8123 to be used with other for one channel (power supplies not shown). The ADA4862-3 types of cable, including coaxial cable. Figure 18 presents the provides the gain of 2 that compensates for the double- recommended settings for VPEAK, VPOLE, and VGAIN when the termination loss. AD8123 is used with good quality 75 Ω video cable. Figure 24 ONE CHANNEL OF ADA4862-3 shows how to derive V and V from V in a coaxial POLE GAIN PEAK ONE VIDEO OUTPUT cable application where V originates from a low-Z source. PEAK 75Ω Z = 75Ω 0 FROM AD8123 500Ω 20Ω 500Ω 75Ω V PEAK 24.3kΩ V 5.11kΩ PEAK Figure 26. Using ADA4862-3 on AD8123 Outputs V ≈ 0.76 × V – 0.41V POLE PEAK 47.5kΩ DRIVING A CAPACITIVE LOAD 1.16kΩ –5V 20kΩ When driving a high impedance capacitive input, it is necessary to place a small series resistor between each of the three AD8123 V ≈ 1.06 × V – 0.62V 10kΩ GAIN PEAK +5V video outputs and the load to buffer the input capacitance of the 1.24kΩ device being driven. Clearly, the resistor value must be small enough to preserve the required bandwidth. Figure 24. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for Coaxial Cable FILTERING THE RGB OUTPUTS The op amp in the circuit that develops VGAIN is required to In some cases, it is desirable to place low-pass filters on the insert the offset of −0.62 V with a gain from VPEAK to VGAIN that AD8123 video outputs to reduce high frequency noise. A 3-pole is close to unity. A passive offset circuit would require an offset Butterworth filter with cutoff frequency in the neighborhood of injection voltage that is much larger in magnitude than the 140 MHz is sufficient in most applications. Figure 27 and Figure 28 available −5 V supply. Clearly, the V control voltage can GAIN present filters for the high impedance load case (driving a delay also be developed independently. line, crosspoint switch, ADA4862-3) and the double-termination The AD8123 differential input can accept signals carried over case (75 Ω source and load resistances), respectively. In the high unbalanced cable, as shown in Figure 25, for an unbalanced impedance load case, the load capacitance must be absorbed in 75 Ω coaxial cable termination. the capacitor that is placed across the load. For example, in AD8123 INPUT STAGE Figure 27, if the high-Z load were the input to an ADA4862-3, INPUT FROM 75Ω CABLE which has an input capacitance of 2 pF, the filter capacitor value 75Ω in parallel with the input would be 15 pF to obtain 17 pF. HIGH-Z Figure 25. Terminating a 75 Ω Cable 150nH 100Ω AD8123 OUTPUT DRIVING 75 Ω VIDEO CABLE WITH THE AD8123 5.6pF 17pF* When the RGB outputs must drive a 75 Ω line rather than a *INPUT CAPACITANCE OF LOAD MUST BE ABSORBED INTO THIS VALUE. high impedance load, an additional gain of two is required to Figure 27. 140 MHz Low-Pass Filter on AD8123 Output Feeding High-Z Load make up for the double termination loss (75 Ω source and load terminations). There are two options available for this. 180nH One option is to place the additional gain of 2 at the drive end 75Ω Z = 75Ω 0 AD8123 by using the AD8148 triple differential driver to drive the cable. OUTPUT 15pF 15pF 75Ω The AD8148 has a fixed gain of 4 instead of the usual gain of 2 and thereby provides the required additional gain of 2 without Figure 28. 135 MHz Low-Pass Filter on AD8123 Output Feeding having to add additional amplifiers to the signal chain. The Doubly Terminated Load AD8148 also contains sync-on-common-mode encoding. If These filters are by no means the only choices but are presented sync-on-common-mode is not required, it can be deactivated here as examples. In the high-Z load case, it is important to on the AD8148 by connecting its SYNC LEVEL input to ground. keep the filter source resistance large enough to buffer the capacitive loading presented by the first capacitor in the filter. Rev. A | Page 13 of 16 06814-030 06814-029 06814-023 06814-024 06814-022 AD8123 0 POWER SUPPLY FILTERING External power supply filtering between the system power –20 supplies and the AD8123 is required in most applications to prevent supply noise from contaminating the received signal as –40 well as to prevent unwanted feedback through the supplies that could cause instability. Figure 29 shows that the AD8123 power –60 supply rejection decreases with increasing frequency. These –80 plots are for the lowest control settings and shift upward as the peaking is increased. –100 10 V = 0V GAIN V = 0V PEAK V = 0V POLE –120 0 10k 100k 1M 10M 100M FREQUENCY (Hz) –10 Figure 31. Power Supply Filter Frequency Response in a 50 Ω System –20 LAYOUT AND POWER SUPPLY DECOUPLING CONSIDERATIONS –30 Standard high speed PCB layout practices should be adhered –40 to when designing with the AD8123. A solid ground plane is –50 required and controlled impedance traces should be used when +PSRR interconnecting the high speed signals. Source termination –PSRR –60 resistors on all of the outputs must be placed as close as possible 100k 1M 10M 100M FREQUENCY (Hz) to the output pins. Figure 29. AD8123 PSRR vs. Frequency The exposed paddle on the underside of the AD8123 must be connected to a pad that connects to at least one PCB plane. A suitable filter that uses a surface-mount ferrite bead is shown Several thermal vias should be used to make the connection in Figure 30, and its frequency response is shown in Figure 31. Because the frequency response was taken using a 50 Ω network between the pad and the plane(s). analyzer and with only one 0.1 μF capacitor on the AD8123 High quality 0.1 μF power supply decoupling capacitors should side, the actual amount of rejection provided by the filter in a be placed as close as possible to all of the supply pins. Small real-world application will be different from that shown in surface-mount ceramic capacitors should be used for these, and Figure 31. The general shape of the rejection curve, however, tantalum capacitors are recommended for bulk supply decoupling. matches Figure 31, providing substantially increased overall PSRR from approximately 5 MHz to 500 MHz, where it is most needed. One filter is required on each of the two supplies (not one filter per supply pin). FAIR-RITE 2743021447 SYSTEM TO AD8123* SUPPLY 0.1µF 4700pF 4700pF *ALL AD8123 SUPPLY PINS ARE INDIVIDUALLY DECOUPLED WITH A 0.1µF CAPACITOR. Figure 30. Power Supply Filter Rev. A | Page 14 of 16 PSRR (dB) 06814-031 06814-017 OUTPUT RESPONSE (dB) 06814-018 AD8123 When used, common-mode sync signals are generally applied INPUT COMMON-MODE RANGE with a peak deviation of 500 mV and thereby increase the Most applications that use the AD8123 as a receiver use a driver common-mode level from 2.675 V to 3.175 V. This common- (such as one from the AD8146/AD8147/AD8148 family, the mode level exceeds the specified input voltage swing limits of AD8133, or the AD8134) powered from ±5 V supplies. This ±3.0 V; therefore, the AD8123 cannot be used with a system places the common-mode voltage on the line nominally at 0 V that uses common-mode sync encoding with 500 mV sync peak relative to the ground potential at the driver and provides optimum deviation and 2.5 V common-mode line level. While it is possible immunity from any common-mode anomalies picked up along to operate a driver powered from a single 5 V supply at a common- the cable (including ground shifts between the driver and receiver mode voltage of <2.5 V to obtain a received voltage swing that is ends). In many of these applications, the AD8123 input voltage within the specified limits, there is not much margin for other range of typically ±3.0 V is sufficient. If wider input range is shifts in the common-mode level due to interference pickup and required, the AD8143 triple receiver (input common-mode differing ground potentials. There are two ways to increase the range equals ±10.5 V on ±12 V supplies) may be placed in front of common-mode range of the overall system. One is to power the the AD8123. Figure 32 illustrates how this is done for one channel. driver from ±5 V supplies, and the other is to place an AD8143 ONE AD8143 CHANNEL ONE AD8123 POWER SUPPLIES = ±12V INPUT in front of the AD8123, as shown in Figure 32. These techniques +5V may be combined or applied separately. RECEIVED 100Ω 2 SIGNAL SMALL SIGNAL FREQUENCY RESPONSE 49.9Ω 3 Though the AD8123 large signal frequency response (VO = 1 V p-p) is of most concern, occasionally designers are 1 HBAT-540C interested in the small signal frequency response. The AD8123 –5V frequency response for V = 300 m V p-p is shown in Figure 33 O Figure 32. Optional Use of AD8143 in Front of AD8123 for for 200 meter and 300 meter cable lengths. Wide Input Common-Mode Range 3 V = 300mV p-p O 2 The Schottky diodes are required to protect the AD8123 from 1 200 METERS any AD8143 outputs that may exceed the AD8123 input limits. 0 The 49.9 Ω resistor limits the fault current and produces a pole –1 at approximately 800 MHz with the effective diode capacitance of 300 METERS –2 –3 3 pF and the AD8123 input capacitance of 1 pF. The pole drops –4 the response by only 0.07 dB at 100 MHz and therefore has a –5 negligible effect on the signal. –6 –7 When using a single 5 V supply on the driver side, the common- –8 mode voltage at the driver is typically midsupply, or V = 2.5 V. CM –9 The largest received differential video signal is approximately –10 –11 700 mV p-p, and this therefore adds 175 mV to the common- PEAK –12 mode voltage, resulting in a worst-case peak voltage of 2.675 V 0.01 0.1 1 10 100 FREQUENCY (MHz) on an AD8123 input (presuming there is no ground shift between Figure 33. Small Signal Frequency Response for Various Cable Lengths driver and receiver). This is within the AD8123 input voltage swing limits, and such a system works well as long as the difference POWER-DOWN in ground potential between driver and receiver does not cause The power-down feature is intended to be used to reduce power the input voltage swing to exceed its specified limits. consumption when a particular device is not in use and does not place the output in a high-Z state when asserted. The input logic levels and supply current in power-down mode are presented in the Power Supply section of Table 1. Rev. A | Page 15 of 16 06814-033 GAIN (dB) 06814-032 AD8123 OUTLINE DIMENSIONS 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 29 40 INDICATOR 1 28 0.50 PIN 1 BSC TOP 4.45 INDICATOR 5.75 EXPOSED VIEW BCS SQ 4.30 SQ PAD (BOT TOM VIEW) 4.15 0.50 20 0.40 10 19 11 0.30 0.25 MIN 4.50 0.80 MAX REF 12° MAX 1.00 0.65 TYP 0.85 0.05 MAX 0.80 0.02 NOM COPLANARITY 0.30 SEATING 0.08 0.20 REF PLANE 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 34. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm, Very Thin Quad (CP-40-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option 1 AD8123ACPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-4 1 AD8123ACPZ-R7 −40°C to +85°C 40-Lead LFCSP_VQ CP-40-4 1 AD8123ACPZ-RL −40°C to +85°C 40-Lead LFCSP_VQ CP-40-4 1 Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06814-0-11/07(A) Rev. A | Page 16 of 16 080107-A