ANALOG DEVICES AD812

Dual, Current Feedback a Low Power Op Amp AD812 FEATURES PIN CONFIGURATION 8-Lead Plastic Two Video Amplifiers in One 8-Lead SOIC Package Mini-DIP and SOIC Optimized for Driving Cables in Video Systems Excellent Video Specifications (R = 150 V): L Gain Flatness 0.1 dB to 40 MHz OUT1 1 8 V+ 0.02% Differential Gain Error –IN1 2 + 7 OUT2 0.028 Differential Phase Error Low Power +IN1 3 6 –IN2 Operates on Single +3 V Supply V– 4 5 +IN2 AD812 5.5 mA/Amplifier Max Power Supply Current High Speed 145 MHz Unity Gain Bandwidth (3 dB) 1600 V/ms Slew Rate Easy to Use 50 mA Output Current Output Swing to 1 V of Rails (150 V Load) APPLICATIONS The AD812 offers low power of 4.0 mA per amplifier max (V = S Video Line Driver +5 V) and can run on a single +3 V power supply. The outputs Professional Cameras of each amplifier swing to within one volt of either supply rail to Video Switchers easily accommodate video signals of 1 V p-p. Also, at gains of Special Effects +2 the AD812 can swing 3 V p-p on a single +5 V power sup- ply. All this is offered in a small 8-lead plastic DIP or 8-lead PRODUCT DESCRIPTION SOIC package. These features make this dual amplifier ideal The AD812 is a low power, single supply, dual video amplifier. for portable and battery powered applications where size and Each of the amplifiers have 50 mA of output current and are power is critical. optimized for driving one back-terminated video load (150 W) The outstanding bandwidth of 145 MHz along with 1600 V/ms each. Each amplifier is a current feedback amplifier and fea- of slew rate make the AD812 useful in many general purpose tures gain flatness of 0.1 dB to 40 MHz while offering differen- high speed applications where a single +5 V or dual power sup- tial gain and phase error of 0.02% and 0.02°. This makes the plies up to –15 V are available. The AD812 is available in the AD812 ideal for professional video electronics such as cameras industrial temperature range of –40°C to +85°C. and video switchers. 0.4 0.06 G = +2 0.3 R = 150V L 0.04 0.2 DIFFERENTIAL GAIN 0.1 0.08 0.02 0 –0.1 0.06 DIFFERENTIAL PHASE –0.2 V = 615V S 0.04 –0.3 65V –0.4 0.02 5V –0.5 3V 0 –0.6 100k 1M 10M 100M 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE – 6Volts FREQUENCY – Hz Figure 1. Fine-Scale Gain Flatness vs. Frequency, Gain Figure 2. Differential Gain and Phase vs. Supply Voltage, = +2, R = 150 WGain = +2, R = 150 WL L REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: http://www.analog.com which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1998 NORMALIZED GAIN – dB DIFFERENTIAL PHASE – Degrees DIFFERENTIAL GAIN – % + AD812–SPECIFICATIONS Dual Supply (@ T = +258C, R = 150 V, unless otherwise noted) A L Model AD812A Conditions V Min Typ Max Units S DYNAMIC PERFORMANCE –3 dB Bandwidth G = +2, No Peaking–5 V 50 65 MHz –15 V 75 100 MHz Gain = +1–15 V 100 145 MHz Bandwidth for 0.1 dB Flatness G = +2–5 V 20 30 MHz –15 V 25 40 MHz 1 Slew Rate G = +2, R = 1 kW– 5 V 275 425 V/ms L 20 V Step–15 V 1400 1600 V/ms G = –1, R = 1 kW– 5 V 250 V/ms L –15 V 600 V/ms Settling Time to 0.1% G = –1, R = 1 kWL V = 3 V Step–5 V 50 ns O V = 10 V Step–15 V 40 ns O NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion f = 1 MHz, R = 1 kW– 15 V –90 dBc C L Input Voltage Noise f = 10 kHz–5 V, –15 V 3.5 nV/√Hz Input Current Noise f = 10 kHz, +In–5 V, –15 V 1.5 pA/√Hz f = 10 kHz, –In–5 V, –15 V 18 pA/√Hz Differential Gain Error NTSC, G = +2, R = 150 W– 5 V 0.05 0.1 % L –15 V 0.02 0.06 % Differential Phase Error–5 V 0.07 0.15 Degrees –15 V 0.02 0.06 Degrees DC PERFORMANCE Input Offset Voltage–5 V, –15 V 2 5 mV T –T 12 mV MIN MAX Offset Drift–5 V, –15 V 15mV/°C –Input Bias Current–5 V, –15 V 7 25mA T –T 38mA MIN MAX +Input Bias Current–5 V, –15 V 0.3 1.5mA T –T 2.0mA MIN MAX Open-Loop Voltage Gain V = –2.5 V, R = 150 W– 5 V 68 76 dB O L T –T 69 dB MIN MAX V = –10 V, R = 1 kW– 15 V 76 82 dB O L T –T 75 dB MIN MAX Open-Loop Transresistance V = –2.5 V, R = 150 W– 5 V 350 550 kWO L T –T 270 kWMIN MAX V = –10 V, R = 1 kW– 15 V 450 800 kWO L T –T 370 kWMIN MAX INPUT CHARACTERISTICS Input Resistance +Input–15 V 15 MW –Input 65W Input Capacitance +Input 1.7 pF Input Common Mode–5 V 4.0–V Voltage Range–15 V 13.5–V Common-Mode Rejection Ratio Input Offset Voltage V = –2.5 V–5 V 51 58 dB CM –Input Current 23.0mA/V +Input Current 0.07 0.15mA/V Input Offset Voltage V = –12 V–15 V 55 60 dB CM –Input Current 1.5 3.3mA/V +Input Current 0.05 0.15mA/V –2– REV. B AD812 Model AD812A Conditions V Min Typ Max Units S OUTPUT CHARACTERISTICS Output Voltage Swing R = 150 W, T –T–5 V 3.5 3.8–V L MIN MAX = 1 kW, T –T–15 V 13.6 14.0–V R L MIN MAX Output Current–5 V 30 40 mA –15 V 40 50 mA = 715 W– 15 V 100 mA Short Circuit Current G = +2, R F V = 2 V IN Output Resistance Open-Loop–15 V 15W MATCHING CHARACTERISTICS Dynamic Crosstalk G = +2, f = 5 MHz–5 V, –15 V –75 dB Gain Flatness Match G = +2, f = 40 MHz–15 V 0.1 dB DC Input offset Voltage T –T–5 V, –15 V 0.5 3.6 mV MIN MAX –Input Bias Current T –T–5 V, –15 V 2 25mA MIN MAX POWER SUPPLY Operating Range–1.2–18 V Quiescent Current Per Amplifier–5 V 3.5 4.0 mA –15 V 4.5 5.5 mA T –T–15 V 6.0 mA MIN MAX Power Supply Rejection Ratio Input Offset Voltage V = –1.5 V to –15 V 70 80 dB S –Input Current 0.3 0.6mA/V +Input Current 0.005 0.05mA/V NOTES 1 Slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain. Specifications subject to change without notice. Single Supply (@ T = +258C, R = 150 V, unless otherwise noted) A L Model AD812A Conditions V Min Typ Max Units S DYNAMIC PERFORMANCE –3 dB Bandwidth G = +2, No Peaking +5 V 35 50 MHz +3 V 30 40 MHz Bandwidth for 0.1 dB Flatness G = +2 +5 V 13 20 MHz +3 V 10 18 MHz 1 G = +2, R = 1 kW+5 V 125 V/ms Slew Rate L +3 V 60 V/ms NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 10 kHz +5 V, +3 V 3.5 nV/√Hz Input Current Noise f = 10 kHz, +In +5 V, +3 V 1.5 pA/√Hz f = 10 kHz, –In +5 V, +3 V 18 pA/√Hz 2 Differential Gain Error NTSC, G = +2, R = 150 W+5 V 0.07 % L G = +1 +3 V 0.15 % 2 Differential Phase Error G = +2 +5 V 0.06 Degrees G = +1 +3 V 0.15 Degrees REV. B –3– AD812–SPECIFICATIONS Single Supply (Continued) AD812A Model Conditions V Min Typ Max Units S DC PERFORMANCE Input Offset Voltage +5 V, +3 V 1.5 4.5 mV T –T 7.0 mV MIN MAX Offset Drift +5 V, +3 V 7mV/°C –Input Bias Current +5 V, +3 V 2 20mA T –T 30mA MIN MAX +Input Bias Current +5 V, +3 V 0.2 1.5mA T –T 2.0mA MIN MAX Open-Loop Voltage Gain V = +2.5 V p-p +5 V 67 73 dB O V = +0.7 V p-p +3 V 70 dB O Open-Loop Transresistance V = +2.5 V p-p +5 V 250 400 kWO V = +0.7 V p-p +3 V 300 kWO INPUT CHARACTERISTICS Input Resistance +Input +5 V 15 MW –Input +5 V 90W Input Capacitance +Input 2 pF Input Common Mode +5 V 1.0 4.0 V Voltage Range +3 V 1.0 2.0 V Common-Mode Rejection Ratio Input Offset Voltage V = 1.25 V to 3.75 V +5 V 52 55 dB CM –Input Current 35.5mA/V +Input Current 0.1 0.2mA/V Input Offset Voltage V = 1 V to 2 V +3 V 52 dB CM –Input Current 3.5mA/V +Input Current 0.1mA/V OUTPUT CHARACTERISTICS Output Voltage Swing p-p R = 1 kW, T –T +5 V 3.0 3.2 V p-p L MIN MAX R = 150 W, T –T +5 V 2.8 3.1 V p-p L MIN MAX +3 V 1.0 1.3 V p-p Output Current +5 V 20 30 mA +3 V 15 25 mA Short Circuit Current G = +2, R = 715 W+5 V 40 mA F V = 1 V IN MATCHING CHARACTERISTICS Dynamic Crosstalk G = +2, f = 5 MHz +5 V, +3 V –72 dB Gain Flatness Match G = +2, f = 20 MHz +5 V, +3 V 0.1 dB DC Input offset Voltage T –T +5 V, +3 V 0.5 3.5 mV MIN MAX –Input Bias Current T –T +5 V, +3 V 2 25mA MIN MAX POWER SUPPLY Operating Range 2.4 36 V Quiescent Current Per Amplifier +5 V 3.2 4.0 mA +3 V 3.0 3.5 mA T –T +5 V 4.5 mA MIN MAX Power Supply Rejection Ratio Input Offset Voltage V = +3 V to +30 V 70 80 dB S –Input Current 0.3 0.6mA/V +Input Current 0.005 0.05mA/V TRANSISTOR COUNT 56 NOTES 1 Slew rate measurement is based on 10% to 90% rise time in the specified closed-loop gain. 2 Single supply differential gain and phase are measured with the ac coupled circuit of Figure 53. Specifications subject to change without notice. –4– REV. B AD812 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–18 V The maximum power that can be safely dissipated by the 2 Internal Power Dissipation AD812 is limited by the associated rise in junction temperature. Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Watts The maximum safe junction temperature for the plastic encap- Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts sulated parts is determined by the glass transition temperature Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .–V of the plastic, about 150°C. Exceeding this limit temporarily S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .–1.2 V may cause a shift in parametric performance due to a change in Output Short Circuit Duration the stresses exerted on the die by the package. Exceeding a . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves junction temperature of 175°C for an extended period can result Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C in device failure. Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C While the AD812 is internally short circuit protected, this may Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C not be sufficient to guarantee that the maximum junction tem- NOTES perature (150 degrees) is not exceeded under all conditions. To 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- ensure proper operation, it is important to observe the derating nent damage to the device. This is a stress rating only; functional operation of the curves. device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating It must also be noted that in high (noninverting) gain configura- conditions for extended periods may affect device reliability. tions (with low values of gain resistor), a high level of input 2 Specification is for device in free air: 8-lead plastic package: q = 90°C/Watt; JA overdrive can result in a large input error current, which may 8-lead SOIC package: q = 150°C/Watt. JA result in a significant power dissipation in the input stage. This ORDERING GUIDE power must be included when computing the junction tempera- ture rise due to total internal power. Temperature Package Package Model Range Description Option 2.0 T = +1508C J AD812AN –40°C to +85°C 8-Lead Plastic DIP N-8 8-LEAD MINI-DIP PACKAGE AD812AR –40°C to +85°C 8-Lead Plastic SOIC SO-8 AD812AR-REEL 13" Reel 1.5 AD812AR-REEL7 7" Reel METALIZATION PHOTO 1.0 Dimensions shown in inches and (mm). 8-LEAD SOIC PACKAGE 0.0783 0.5 (1.99) V+ OUT2 –IN2 8 7 6 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 5 +IN2 AMBIENT TEMPERATURE – 8C Figure 3. Plot of Maximum Power Dissipation vs. Temperature 0.0539 (1.37) 4 V– 1 2 3 4 OUT1 –IN1 +IN1 V– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– MAXIMUM POWER DISSIPATION – Watts AD812–Typical Performance Characteristics 16 20 14 15 V = 615V S 12 10 10 V = 65V S 8 5 6 4 0 02 5 10 150 –60 –40 –20 0 20 40 60 80 100 120 140 SUPPLY VOLTAGE – 6Volts JUNCTION TEMPERATURE – 8C Figure 4. Input Common-Mode Voltage Range vs. Supply Figure 7. Total Supply Current vs. Junction Temperature Voltage 10 20 T = +25 C A NO LOAD 9 15 8 10 7 R = 150V L 6 5 5 0 2 4 6 8 10 12 14 16 0 SUPPLY VOLTAGE – 6Volts 02 5 10 150 SUPPLY VOLTAGE – 6Volts Figure 5. Output Voltage Swing vs. Supply Voltage Figure 8. Total Supply Current vs. Supply Voltage 30 25 615V SUPPLY 20 25 15 –I , V = 65V 10 B S 20 5 15 0 –5 +I , V = 65V, 615V B S 10 –10 65V SUPPLY –I , V = 615V B S –15 5 –20 0 –25 10 100 1k 10k –40 –20 0 20 40 60 80 100 120 140 –60 LOAD RESISTANCE – V JUNCTION TEMPERATURE – 8C Figure 6. Output Voltage Swing vs. Load Resistance Figure 9. Input Bias Current vs. Junction Temperature –6– REV. B OUTPUT VOLTAGE – Volts p-p OUTPUT VOLTAGE – V p-p COMMON-MODE VOLTAGE RANGE – 6Volts INPUT BIAS CURRENT – mA TOTAL SUPPLY CURRENT – mA TOTAL SUPPLY CURRENT – mA AD812 4 70 2 V = 65V S 60 0 –2 50 –4 V = 615V S –6 40 –8 –10 30 –12 –14 –16 20 0 5 10 15 20 –60 –40 –20 0 20 40 60 80 100 120 140 SUPPLY VOLTAGE – 6Volts JUNCTION TEMPERATURE – 8C Figure 10. Input Offset Voltage vs. Junction Temperature Figure 13. Linear Output Current vs. Supply Voltage 1k 160 G = +2 140 100 SINK V = 615V S 120 10 100 SOURCE 1 80 65V S 0.1 60 615V S 0.01 40 10k 100k 1M 10M 100M –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE – 8C FREQUENCY – Hz Figure 11. Short Circuit Current vs. Junction Temperature Figure 14. Closed-Loop Output Resistance vs. Frequency 80 30 V = 615V S 70 25 60 20 R = 1kV L 50 15 V = 65V S 40 10 V = 65V S V = 615V S 30 5 0 20 –60 –40 –20 0 20 40 60 80 100 120 140 100k 1M 10M 100M FREQUENCY – Hz JUNCTION TEMPERATURE – 8C Figure 12. Linear Output Current vs. Junction Temperature Figure 15. Large Signal Frequency Response REV. B –7– INPUT OFFSET VOLTAGE – mV SHORT CIRCUIT CURRENT – mA OUTPUT CURRENT – mA OUTPUT CURRENT – mA CLOSED-LOOP OUTPUT RESISTANCE – V OUTPUT VOLTAGE – V p-p AD812 100 100 0 –45 120 V = 615V PHASE S INVERTING INPUT –90 CURRENT NOISE –135 100 GAIN –180 V = 3V S 10 10 80 VOLTAGE NOISE V = 3V V = 615V S S NONINVERTING INPUT 60 CURRENT NOISE 1 1 40 10 100 1k 10k 100k 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz Figure 16. Input Current and Voltage Noise vs. Frequency Figure 19. Open-Loop Transimpedance vs. Frequency (Relative to 1 W) –30 90 681V G = +2 V = 2V p-p 80 681V S V V IN OUT V = 615V ; R = 1kV S L –50 681V V = 65V ; R = 150V 70 S L 681V 60 –70 50 V = 65V S V = 615V V = 615V S ND S –90 2 HARMONIC 40 V = 3V S RD 3 HARMONIC 30 –110 20 ND 2 RD 3 10 –130 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz Figure 17. Common-Mode Rejection vs. Frequency Figure 20. Harmonic Distortion vs. Frequency 80 10 GAIN = –1 8 70 V = 615V S 615V 6 60 4 50 2 61.5V 40 0 0.025% 1% 0.1% –2 30 –4 20 –6 10 –8 0 –10 10k 100k 1M 10M 100M 20 30 40 50 60 FREQUENCY – Hz SETTLING TIME – ns Figure 18. Power Supply Rejection vs. Frequency Figure 21. Output Swing and Error vs. Settling Time –8– REV. B POWER SUPPLY REJECTION – dB COMMON-MODE REJECTION – dB VOLTAGE NOISE – nV/ Hz CURRENT NOISE – pA/ Hz HARMONIC DISTORTION – dBc OUTPUT SWING FROM 6V TO 0 TRANSIMPEDANCE – dB PHASE – Degrees AD812 1400 1400 G = +1 G = +1 V = 615V S 1200 1200 R = 500V L 1000 1000 G = +2 G = +2 800 800 G = +10 G = +10 600 600 400 400 G = –1 G = –1 200 200 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1.5 3.0 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 OUTPUT STEP SIZE – Vp-p SUPPLY VOLTAGE – 6Volts Figure 22. Slew Rate vs. Output Step Size Figure 25. Maximum Slew Rate vs. Supply Voltage 500mV 20ns 2V 50ns 100 100 V V IN 90 IN 90 V V 10 10 OUT OUT 0% 0% 500mV 2V Figure 26. Small Signal Pulse Response, Gain = +1, Figure 23. Large Signal Pulse Response, Gain = +1, (R = 750 W, R = 150 W, V = –5 V) (R = 750 W, R = 150 W, V = –5 V) F L S F L S 200 PHASE G = +1 G = +1 180 R = 150V 0 L R = 150V L V = 615V S 160 –90 R = 750V F 65V 140 1 –180 R = 866V F GAIN 5V 120 0 –270 PEAKING 1dB 3V 100 –1 V = 615V PEAKING 0.2dB S 80 –2 65V 60 –3 5V 40 –4 3V 20 –5 –6 0 0 2 4 6 8 10 12 14 16 18 20 1 10 100 1000 FREQUENCY – MHz SUPPLY VOLTAGE – 6Volts Figure 24. Closed-Loop Gain and Phase vs. Frequency, Figure 27. –3 dB Bandwidth vs. Supply Voltage, G = +1 G = +1 REV. B –9– SLEW RATE – V/ms CLOSED-LOOP GAIN – dB PHASE SHIFT – Degrees SLEW RATE – V/ms –3dB BANDWIDTH – MHz AD812 50mV 20ns 500mV 50ns 100 100 V V IN 90 90 IN 10 V 10 V OUT OUT 0% 0% 500mV 5V Figure 28. Large Signal Pulse Response, Gain = +10, Figure 31. Small Signal Pulse Response, Gain = +10, (R = 357 W, R = 500 W, V = –15 V) F L S (R = 357 W, R = 150 W, V = –5 V) F L S PHASE G = +10 PHASE G = +10 0 V = 615V V = 615V S 0 S R = 150V R = 1kV L L –90 65V –90 65V 5V 3V 5V 1 –180 1 –180 3V GAIN GAIN –270 0 0 –270 V = 615V S –1 –1 –360 5V 5V –2 –2 V = 615V S 3V 3V –3 –3 65V –4 –4 65V –5 –5 –6 –6 1 10 100 1000 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz Figure 29. Closed-Loop Gain and Phase vs. Frequency, Figure 32. Closed-Loop Gain and Phase vs. Frequency, Gain = +10, R = 150 WL Gain = +10, R = 1 kWL 100 110 G = +10 90 G = +10 100 R = 150V L R = 1kV L 80 90 R = 357V F 70 80 PEAKING 1dB R = 357V F 60 70 R = 154V F R = 154V F 50 60 R = 649V F R = 649V F 40 50 30 40 20 30 10 20 0 10 01 21 4 6 8 10 12 146820 01 21 4 6 8 10 12 146820 SUPPLY VOLTAGE – 6Volts SUPPLY VOLTAGE – 6Volts Figure 30. –3 dB Bandwidth vs. Supply Voltage, Figure 33. –3 dB Bandwidth vs. Supply Voltage, Gain = +10, R = 150 WL Gain = +10, R = 1 kWL –10– REV. B –3dB BANDWIDTH – MHz CLOSED-LOOP GAIN (NORMALIZED) – dB PHASE SHIFT – Degrees –3dB BANDWIDTH – MHz CLOSED-LOOP GAIN (NORMALIZED) – dB PHASE SHIFT – Degrees AD812 50ns 500mV 2V 20ns 100 100 V 90 V 90 IN IN 10 V 10 V OUT OUT 0% 0% 500mV 2V Figure 34. Large Signal Pulse Response, Gain = –1, Figure 37. Small Signal Pulse Response, Gain = –1, (R = 750 W, R = 150 W, V = –5 V) (R = 750 W, R = 150 W, V = –5 V) F L S F L S PHASE G = –1 V = 615V S V = 615V PHASE S G = –10 R = 150V 0 L 0 R = 1kV 65V L 65V 5V –90 –90 3V 1 –180 5V –180 1 GAIN GAIN 3V 0 –270 –270 0 –1 –1 V = 615V S –2 –2 V = 615V S 65V –3 –3 65V –4 5V 5V –4 –5 3V 3V –5 –6 –6 1 10 100 1000 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz Figure 35. Closed-Loop Gain and Phase vs. Frequency, Figure 38. Closed-Loop Gain and Phase vs. Frequency, Gain = –1, R = 150 WL Gain = –10, R = 1 kWL 130 100 G = –1 120 G = –10 90 R = 150V L R = 1kV L R = 681V 110 F 80 PEAKING # 1.0dB R = 357V F 100 70 R = 715V F 90 60 R = 154V R = 649V F F 80 50 PEAKING # 0.2dB 70 40 60 30 50 20 40 10 30 0 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE – 6Volts SUPPLY VOLTAGE – 6Volts Figure 36. –3 dB Bandwidth vs. Supply Voltage, Figure 39. –3 dB Bandwidth vs. Supply Voltage, Gain = –1, R = 150 WL Gain = –10, R = 1 kWL REV. B –11– –3dB BANDWIDTH – MHz CLOSED-LOOP GAIN (NORMALIZED) – dB PHASE SHIFT – Degrees –3dB BANDWIDTH – MHz CLOSED-LOOP GAIN (NORMALIZED) – dB PHASE SHIFT – Degrees AD812 General Considerations To estimate the –3 dB bandwidth for closed-loop gains or feed- The AD812 is a wide bandwidth, dual video amplifier which back resistors not listed in the above table, the following two offers a high level of performance on less than 5.5 mA per am- pole model for the AD812 many be used: plifier of quiescent supply current. It is designed to offer out- standing performance at closed-loop inverting or noninverting G gains of one or greater. A = CL ØøRG + rC () FIN T Built on a low cost, complementary bipolar process, and achiev- 2 ŒœS ++ S R Gr C +1 () FIN T 2pf ing bandwidth in excess of 100 MHz, differential gain and phaseŒ2œ ºß errors of better than 0.1% and 0.1° (into 150 W), and output where: A = closed-loop gain CL current greater than 40 mA, the AD812 is an exceptionally G = 1 + R /R F G efficient video amplifier. Using a conventional current feedback r = input resistance of the inverting input IN architecture, its high performance is achieved through careful C = “transcapacitance,” which forms the open-loop T attention to design details. dominant pole with the tranresistance Choice of Feedback and Gain Resistors R = feedback resistor F Because it is a current feedback amplifier, the closed-loop band- R = gain resistor G width of the AD812 depends on the value of the feedback resis- f = frequency of second (nondominant) pole 2 tor. The bandwidth also depends on the supply voltage. In S = 2 pj f addition, attenuation of the open-loop response when driving Appropriate values for the model parameters at different supply load resistors less than about 250 W will affect the bandwidth. voltages are listed in Table II. Reasonable approximations for Table I contains data showing typical bandwidths at different these values at supply voltages not found in the table can be supply voltages for some useful closed-loop gains when driving a obtained by a simple linear interpolation between those tabu- load of 150 W. (Bandwidths will be about 20% greater for load lated values which “bracket” the desired condition. resistances above a few hundred ohms.) Table II. Two-Pole Model Parameters at Various The choice of feedback resistor is not critical unless it is impor- Supply Voltages tant to maintain the widest, flattest frequency response. The resistors recommended in the table are those (metal film values) V r (V)C (pF) f (MHz) S IN T 2 that will result in the widest 0.1 dB bandwidth. In those appli- cations where the best control of the bandwidth is desired, 1% –15 85 2.5 150 metal film resistors are adequate. Wider bandwidths can be –5 90 3.8 125 attained by reducing the magnitude of the feedback resistor (at +5 105 4.8 105 the expense of increased peaking), while peaking can be reduced +3 115 5.5 95 by increasing the magnitude of the feedback resistor. As discussed in many amplifier and electronics textbooks (such Table I. –3 dB Bandwidth vs. Closed-Loop Gain and as Roberge’s Operational Amplifiers: Theory and Practice), the Feedback Resistor (R = 150 W) L –3 dB bandwidth for the 2-pole model can be obtained as: 2 2 4 1/2 1/2 V (V) Gain R (V) BW (MHz) S F f = f [1 – 2d + (2 – 4d + 4d ) ] 3 N –15 +1 866 145 where: +2 715 100 12 / +10 357 65Øø f 2Œœ–1 715 100 f = N Œœ –10 357 60 RG + r C () FIN T ºß –5 +1 750 90 and: +2 681 65 1/2 d = (1/2) [f (R + Gr ) C ] 2 F IN T +10 154 45 –1 715 70 This model will predict –3 dB bandwidth within about 10 to –10 154 45 15% of the correct value when the load is 150 W. However, it is not an accurate enough to predict either the phase behavior or +5 +1 750 60 the frequency response peaking of the AD812. +2 681 50 +10 154 35 Printed Circuit Board Layout Guidelines –1 715 50 As with all wideband amplifiers, printed circuit board parasitics –10 154 35 can affect the overall closed-loop performance. Most important for controlling the 0.1 dB bandwidth are stray capacitances at +3 +1 750 50 the output and inverting input nodes. Increasing the space between +2 681 40 signal lines and ground plane will minimize the coupling. Also, +10 154 30 signal lines connecting the feedback and gain resistors should be –1 715 40 kept short enough that their associated inductance does not –10 154 25 cause high frequency gain errors. –12– REV. B AD812 Power Supply Bypassing The input and output signal return paths must also be kept from Adequate power supply bypassing can be very important when overlapping. Since ground connections are not of perfectly zero optimizing the performance of high speed circuits. Inductance impedance, current in one ground return path can produce a in the supply leads can (for example) contribute to resonant voltage drop in another ground return path if they are allowed circuits that produce peaking in the amplifier’s response. In to overlap. addition, if large current transients must be delivered to a load, Electric field coupling external to (and across) the package can then large (greater than 1 mF) bypass capacitors are required to be reduced by arranging for a narrow strip of ground plane to be produce the best settling time and lowest distortion. Although run between the pins (parallel to the pin rows). Doing this on 0.1 mF capacitors may be adequate in some applications, more both sides of the board can reduce the high frequency crosstalk elaborate bypassing is required in other cases. by about 5 dB or 6 dB. When multiple bypass capacitors are connected in parallel, it is Driving Capacitive Loads important to be sure that the capacitors themselves do not form When used with the appropriate output series resistor, any load resonant circuits. A small (say 5 W) resistor may be required in capacitance can be driven without peaking or oscillation. In series with one of the capacitors to minimize this possibility. most cases, less than 50 W is all that is needed to achieve an As discussed below, power supply bypassing can have a signifi- extremely flat frequency response. As illustrated in Figure 44, cant impact on crosstalk performance. the AD812 can be very attractive for driving largely capacitive loads. In this case, the AD812’s high output short circuit Achieving Low Crosstalk current allows for a 150 V/ms slew rate when driving a 510 pF Measured crosstalk from the output of amplifier 2 to the input capacitor. of amplifier 1 of the AD812 is shown in Figure 40. The crosstalk from the output of amplifier 1 to the input of amplifier 2 is a few R F dB better than this due to the additional distance between criti- cal signal nodes. +V S 0.1mF A carefully laid-out PC board should be able to achieve the level of crosstalk shown in the figure. The most significant contribu- 1.0mF tors to difficulty in achieving low crosstalk are inadequate power R G supply bypassing, overlapped input and/or output signal paths, 8 R S and capacitive coupling between critical nodes. V AD812 O The bypass capacitors must be connected to the ground plane at V C R IN 4 L L 1.0mF a point close to and between the ground reference points for the R T two loads. (The bypass of the negative power supply is particu- 0.1mF larly important in this regard.) There are two amplifiers in the package, and low impedance signal return paths must be pro- –V S vided for each load. (Using a parallel combination of 1 mF, Figure 41. Circuit for Driving a Capacitive Load 0.1mF, and 0.01 mF bypass capacitors will help to achieve opti- mal crosstalk.) –10 V = 65V S –20 G = +2 R = 150V R = 750V L F –30 R = 1kV L C = 10pF 12 L –40 9 –50 R = 0 S 6 –60 R = 30V S 3 –70 R = 50V 0 S –80 –3 –90 –6 –100 –110 1 10 100 1000 100k 1M 10M 100M FREQUENCY – MHz FREQUENCY – Hz Figure 42. Response to a Small Load Capacitor at –5 V Figure 40. Crosstalk vs. Frequency REV. B –13– CROSSTALK – dB CLOSED-LOOP GAIN – dB AD812 V = 615V S 50ns 1V G = +2 R = 750V F 100 R = 1kV L 90 V IN 12 9 6 C = 150pF, R = 30V L S 3 0 10 V OUT –3 0% C = 510pF, R = 15V L S –6 2V –9 1 10 100 1000 FREQUENCY – MHz Figure 45. 6 dB Overload Recovery; G = 10, R = 500 W, L V = –5 V S Figure 43. Response to Large Load Capacitor, V = –15 V S In the case of high gains with very high levels of input overdrive, 5V 100ns a longer recovery time may occur. For example, if the input common-mode voltage range is exceeded in a gain of +10, the 100 V IN recovery time will be on the order of 100 ns. This is primarily 90 due to current overloading of the input stage. As noted in the warning under “Maximum Power Dissipation,” a high level of input overdrive in a high noninverting gain circuit can result in a large current flow in the input stage. For differ- ential input voltages of less than about 1.25 V, this will be inter- V 10 OUT nally limited to less than 20 mA (decreasing with supply voltage). 0% For input overdrives which result in higher differential input voltages, power dissipation in the input stage must be consid- 5V ered. It is recommended that external diode clamps be used in cases where the differential input voltage is expected to exceed Figure 44. Pulse Response of Circuit of Figure 41 with 1.25 V. C = 510 pF, R = 1 kW, R = R = 715 W, R = 15 WL L F G S High Performance Video Line Driver At a gain of +2, the AD812 makes an excellent driver for a back- Overload Recovery terminated 75 W video line. Low differential gain and phase There are three important overload conditions to consider. errors and wide 0.1 dB bandwidth can be realized over a wide They are due to input common mode voltage overdrive, input range of power supply voltage. Outstanding gain and group current overdrive, and output voltage overdrive. When the delay matching are also attainable over the full operating supply amplifier is configured for low closed-loop gains, and its input voltage range. common-mode voltage range is exceeded, the recovery time will R R be very fast, typically under 10 ns. When configured for a higher G F gain, and overloaded at the output, the recovery time will also +V S be short. For example, in a gain of +10, with 6 dB of input 0.1mF overdrive, the recovery time of the AD812 is about 10 ns. 75V 8 CABLE 75V 75V V AD812 OUT CABLE V 75V 4 IN 75V 0.1mF –V S Figure 46. Gain of +2 Video Line Driver (R = R from F G Table I) –14– REV. B CLOSED-LOOP GAIN – dB AD812 90 0.4 PHASE G = +2 G = +2 0 0.3 R = 150V L R = 150V L –90 0.2 3V V = 615V S 5V –180 1 0.1 65V GAIN –270 0 0 5V –1 –0.1 3V –2 V = 615V S –0.2 V = 615V S –3 –0.3 65V 65V –4 –0.4 5V –5 –0.5 3V –6 –0.6 1 10 100 1000 100k 1M 10M 100M FREQUENCY –MHz FREQUENCY – Hz Figure 47. Closed-Loop Gain and Phase vs. Frequency for Figure 50. Fine-Scale Gain Flatness vs. Frequency, the Line Driver Gain = +2, R = 150 WL 120 1.0 R = 590V G = +2 F G = +2 110 0.8 R = 150V L R = 715V F R = 150V L V = 3V 100 S 0.6 R = 750V F PEAKING # 1dB R = 681V F 90 0.4 80 0.2 NO PEAKING 70 0 V = 615V S 60 –0.2 R = 715V F 50 –0.4 40 –0.6 30 –0.8 20 –1.0 0 2 4 6 8 10 12 14 16 18 20 1 10 100 1000 SUPPLY VOLTAGE – 6Volts FREQUENCY – MHz Figure 48. –3 dB Bandwidth vs. Supply Voltage, Figure 51. Closed-Loop Gain Matching vs. Frequency, Gain = +2, R = 150 WL Gain = +2, R = 150 WL DELAY 0.06 8 3V 6 5V 0.04 65V 4 DIFFERENTIAL GAIN 615V 2 0.08 0.02 0 0.06 DELAY MATCHING 0.4 DIFFERENTIAL PHASE 0.2 0.04 V = 3V TO 615V S 0 0.02 –0.2 –0.4 0 100k 1M 10M 100M 5 6 7 8 9 10 11 12 13 14 15 FREQUENCY – Hz SUPPLY VOLTAGE – 6Volts Figure 52. Group Delay and Group Delay Matching vs. Figure 49. Differential Gain and Phase vs. Supply Voltage, Frequency, G = +2, R = 150 WL Gain = +2, R = 150 WL REV. B –15– DIFFERENTIAL PHASE – Degrees –3dB BANDWIDTH – MHz CLOSED-LOOP GAIN – dB PHASE SHIFT – Degrees DIFFERENTIAL GAIN – % NORMALIZED GAIN – dB GAIN MATCH – dB GROUP DELAY – ns AD812 Operation Using a Single Supply 90 PHASE The AD812 will operate with total supply voltages from 36 V 0 down to 2.4 V. With proper biasing (see Figure 53), it can be an V = 5V S 0.5 –90 outstanding single supply video amplifier. Since the input and GAIN output voltage ranges extend to within 1 volt of the supply rails, 0 –180 it will handle a 1.3 V p-p signal on a single 3.3 V supply, or a –0.5 –270 3 V p-p signal on a single 5 V supply. The small signal, 0.1 dB –1.0 bandwidths will exceed 10 MHz in either case, and the large signal bandwidths will exceed 6 MHz. –1.5 The capacitively coupled cable driver in Figure 53 will achieve –2.0 outstanding differential gain and phase errors of 0.07% and 0.06 –2.5 degrees respectively on a single 5 V supply. Resistor R2, in this –3.0 circuit, is selected to optimize the differential gain and phase by –3.5 operating the amplifier in its most linear region. To optimize the 1 10 100 1000 circuit for a 3 V supply, a value of 8 kW is recommended for R2. FREQUENCY – MHz Figure 54. Closed-Loop Gain and Phase vs. Frequency, 649V 649V Circuit of Figure 53 C3 R3 30mF 1kV +V S C2 1V 50ns 1mF R1 C OUT 75V 9kV 100 8 CABLE 47mF 75V V 90 IN C1 V OUT AD812 2mF V IN 75V 4 R2 11.8kV V OUT Figure 53. Biasing for Single Supply Operation 10 0% 500mV Figure 55. Pulse Response of the Circuit of Figure 53 with V = 5 V S OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP 8-Lead Plastic SOIC (N-8) (SO-8) 0.39 (9.91) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.25 85 (6.35) 0.1574 (4.00) 0.2440 (6.20) 14 0.325 (8.25) 1 4 0.1497 (3.80) 0.2284 (5.80) 0.300 (7.62) 0.060 (1.52) PIN 1 0.015 (0.38) 0.195 (4.95) 0.165 60.01 PIN 1 0.0688 (1.75) 0.0196 (0.50) (4.19 60.25) 0.115 (2.93) 3 458 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.125 (3.18) 0.0040 (0.10) MIN 0.015 (0.381) SEATING 0.018 60.003 0.033 (0.84) 0.10 88 0.008 (0.204) PLANE (0.46 +0.08) (2.54) NOM 0.0500 0.0192 (0.49) 08 SEATING 0.0098 (0.25) 0.0500 (1.27) BSC (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) 0.0160 (0.41) –16– REV. B CLOSED-LOOP GAIN – dB PHASE SHIFT – Degrees PRINTED IN U.S.A. C1859b–0–9/98