ANALOG DEVICES AD8074

500 MHz, G = +1 and +2 Triple a Video Buffers with Disable AD8074/AD8075 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual Supply �5 V High-Speed Fully Buffered Inputs and Outputs AD8074 /AD8075 600 MHz Bandwidth (–3 dB) 200 mV p-p 1 16 V OE CC 500 MHz Bandwidth (–3 dB) 2 V p-p 2 DGND 15 V CC 1600 V/�s Slew Rate, G = +1 G = 1350 V/�s Slew Rate, G = +2 IN2 3 14 OUT2 +1/+2 Fast Settling Time: 4 ns 4 AGND 13 V EE Low Supply Current: <30 mA G = Excellent Video Specifications (R = 150 �): IN1 5 12 OUT1 L +1/+2 Gain Flatness of 0.1 dB to 50 MHz 6 AGND 11 V CC 0.01% Differential Gain Error G = 0.01� Differential Phase Error IN0 7 10 OUT0 +1/+2 “All Hostile“ Crosstalk V 8 V 9 EE EE –80 dB @ 10 MHz –50 dB @ 100 MHz High “OFF” Isolation of 90 dB @ 10 MHz Low Cost Fast Output Disable Feature APPLICATIONS RGB Buffer in LCD and Plasma Displays RGB Driver Video Routers Table I. Truth Table PRODUCT DESCRIPTION The AD8074/AD8075 are high-speed triple video buffers with OE OUT0, 1, 2 G = +1 and +2 respectively. They have a –3 dB full signal band- width in excess of 450 MHz, along with slew rates in excess of 0 IN0, IN1, IN2 1400 V/µs. With better than –80 dB of all hostile crosstalk and 1 High Z 90 dB isolation, they are useful in many high-speed applica- tions. The differential gain and differential phase error are 0.01% and 0.01°. Gain flatness of 0.1 dB up to 50 MHz makes the AD8074/AD8075 ideal for RGB buffering or driving. They consume less than 30 mA on a ±5 V supply. Both devices offer a high-speed disable feature that allows the outputs to be put into a high impedance state. This allows the building of larger input arrays while minimizing “OFF” chan- nel output loading. The AD8074/AD8075 are offered in a 16-lead TSSOP package. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (T = 25�C, V = �5 V, unless otherwise noted.) AD8074/AD8075–SPECIFICATIONS A S Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth (Small Signal) V = 200 mV p-p, C = 5 pF 330/310 600/550 MHz IN L V = 200 mV p-p, R = 150 Ω 250/230 400/400 MHz IN L –3 dB Bandwidth (Large Signal) V = 2 V p-p, C = 5 pF 330/300 500/500 MHz IN L V = 2 V p-p, R = 150 Ω 250/230 350/350 MHz IN L 0.1 dB Bandwidth V = 200 mV p-p, C = 5 pF 70/65 MHz IN L V = 200 mV p-p, R = 150 Ω 70/65 MHz IN L Slew Rate 2 V Step, R = 1 kΩ/150 Ω 1600/1350 V/µs L Settling Time to 0.1% 2 V Step, R = 1 kΩ/150 Ω 4/7.5 ns L NOISE/DISTORTION PERFORMANCE Differential Gain V = 3.58 MHz, 150 Ω 0.01 % Differential Phase V = 3.58 MHz, 150 Ω 0.01 Degrees All Hostile Crosstalk V = 10 MHz, R = 1 kΩ –80/–74 dB L V = 100 MHz, R = 1 kΩ –50/–44 dB L OFF Isolation V = 10 MHz, R = 150 Ω 90 dB L Voltage Noise V = 10 kHz to 100 MHz 19.5/22 nV/√Hz DC PERFORMANCE Voltage Gain Error No Load ±0.1/±0.2 ±0.15/±0.65 % Input Offset Voltage 2.5 27/40 mV T to T 3mV MIN MAX Input Offset Drift 10 µV/°C Input Bias Current 5 9.5/10 µA INPUT CHARACTERISTICS Input Resistance 10 MΩ Input Capacitance Channel Enabled 1.5 pF Channel Disabled 1.5 pF Input Voltage Range ±2.8/±1.4 V OUTPUT CHARACTERISTICS Output Voltage Swing R = 1 kΩ +V – 1.95 +V – 1.8 V L S S –V + 2.1 –V + 1.8 V S S R = 150 Ω +V – 2.35 +V – 2.2 V L S S –V + 2.30 –V + 2.2 V S S Short Circuit Current (Protected) 70 mA Output Resistance Enabled 0.5 Ω Disabled 3.5 7.5 MΩ Output Capacitance Disabled 2.2 pF POWER SUPPLY Operating Range ±4.5 ±5.5 V Power Supply Rejection Ratio +PSRR: +V = +4.5 V to +5.5 V, –V = –5 V 60 74 dB S S –PSRR: –V = –4.5 V to –5.5 V, +V = +5 V 56 64 dB S S Quiescent Current All Channels “ON” 21.5/24 30 mA All Channels “OFF” 3/4 5.5 mA T to T 23/26 mA MIN MAX DIGITAL INPUT Logic “1” Voltage OE Input 2.0 V Logic “0” Voltage OE Input 0.8 V Logic “1” Input Current OE = 4 V 100 nA Logic “0” Input Current OE = 0.4 V 1 µA OPERATING TEMPERATURE RANGE Temperature Range Operating (Still Air) –40 +85 °C θ Operating (Still Air) 150.4 °C/W JA θ Operating 27.6 °C/W JC Specifications subject to change without notice. –2– Rev. B AD8074/AD8075 1 ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V 2, 3 Internal Power Dissipation AD8074/AD8075 16-Lead TSSOP (RU) . . . . . . . . . . . . . 1 W Input Voltage IN0, IN1, IN2 . . . . . . . . . . . . . . . . . . . . . . . . . V ≤ V ≤ V EE IN CC OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND ≤ V ≤ V IN CC 3 Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C PIN CONFIGURATION Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . 300°C NOTES 1 AD8074 /AD8075 Stresses above those listed under Absolute Maximum Ratings may cause perma- OE 1 16 V nent damage to the device. This is a stress rating only; functional operation of the CC device at these or any other conditions above those indicated in the operational DGND 2 15 V section of this specification is not implied. Exposure to absolute maximum rating CC conditions for extended periods may affect device reliability. G = 2 IN2 3 14 OUT2 Specification is for device in free air (T = 25°C). +1/+2 A 3 16-lead plastic TSSOP; θ = 150.4°C/W. Maximum internal power dissipa- JA 4 13 AGND V EE tion (P ) should be derated for ambient temperature (T ) such that D A P < (150°C – T )/θ . D A JA G = IN1 5 12 OUT1 +1/+2 AGND 6 11 V CC G = IN0 7 10 OUT0 +1/+2 V 8 9 V EE EE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8074/AD8075 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions ESD SENSITIVE DEVICE are recommended to avoid performance degradation or loss of functionality. 1.5 MAXIMUM POWER DISSIPATION T = 150�C J The maximum power that can be safely dissipated by the AD8074/ AD8075 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the 1.0 plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junc- tion temperature of 175°C for an extended period can result in 0.5 device failure. While the AD8074/AD8075 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To 0 010 30 50 90 ensure proper operation, it is necessary to observe the maximum –50 –30 –10 70 power derating curves shown in Figure 1. AMBIENT TEMPERA TURE – �C Figure 1. Maximum Power Dissipation vs. Temperature Rev. B –3– MAXIMUM POWER DISSIPATION – Watts AD8074/AD8075–Typical Performance Characteristics 1 0.4 1 0.4 GAIN GAIN 0 0.3 0 0.3 –1 0.2 –1 0.2 2V p-p –2 0.1 –2 0.1 200mV p-p FLATNESS FLATNESS –3 0 200mV p-p –3 0 –4 –0.1 –4 –0.1 –5 –0.2 –5 –0.2 2V p-p –6 –0.3 –6 –0.3 2V p-p –0.4 –7 –7 –0.4 –8 –0.5 –8 –0.5 –9 –0.6 –9 –0.6 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 1. AD8074 Frequency Response; R = 150 Ω L TPC 4. AD8075 Frequency Response; R = 150 Ω L 2 0.6 2 0.6 1 0.5 1 0.5 GAIN GAIN 0 0.4 0 0.4 –1 0.3 –1 0.3 2V p-p –2 0.2 0.2 –2 2V p-p 2V p-p –3 0.1 –3 0.1 FLATNESS FLATNESS –4 0 –4 0 –5 –0.1 –5 –0.1 200mV p-p –6 –0.2 –6 –0.2 2V p-p 200mV p-p –0.3 –7 –7 200mV p-p –0.3 –0.4 –8 –8 –0.4 –0.5 –9 –9 –0.5 –0.6 –10 –0.6 –10 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 2. AD8074 Frequency Response; R = 1 kΩ, C = 5 pF TPC 5. AD8075 Frequency Response; R = 1 kΩ, C = 5 pF L L L L 3 3 C = 10pF C = 10pF 2 L 2 L 1 1 0 0 –1 –1 C = 0pF C = 0pF L L –2 –2 C = 5pF C = 5pF L L –3 –3 –4 –4 –5 V V IN –5 OUT V V IN OUT C 1k� L –6 75� C –6 L 150k� 75� –7 –7 –8 –8 V = 2V p-p OUT –9 –9 V = 2V p-p OUT –10 –10 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 3. AD8074 Frequency Response vs. Capacitive Load TPC 6. AD8075 Frequency Response vs. Capacitive Load –4– Rev. B GAIN – dB GAIN – dB GAIN – dB FLATNESS – dB FLATNESS – dB NORMALIZED GAIN – dB NORMALIZED GAIN – dB NORMALIZED GAIN – dB NORMALIZED FLATNESS – dB NORMALIZED FLATNESS – dB AD8074/AD8075 0 0 V = 2V p-p (ACTIVE CHANNEL(s)) V = 2V p-p (ACTIVE CHANNEL(s)) OUT OUT –10 –10 R = 1k� R = 150� L L R = 37.5� R = 37.5� T T –20 –20 –30 –30 –40 –40 –50 –50 ALL-HOSTILE –60 –60 ALL-HOSTILE –70 –70 –80 –80 ADJACENT ADJACENT –90 –90 –100 –100 –110 –110 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 7. AD8074 Crosstalk vs. Frequency (All Hostile and TPC 9. AD8075 Crosstalk vs. Frequency (All Hostile and Adjacent R = 1 kΩ) L Adjacent R = 150 Ω) L 0 0 V = 2V p-p V = 2V p-p OUT OUT –10 –10 R = 150� R = 150� L L R = 37.5� R = 37.5� T T –20 –20 –30 –30 –40 –40 SECOND HARMONIC –50 –50 SECOND –60 –60 HARMONIC –70 –70 THIRD HARMONIC –80 –80 THIRD HARMONIC –90 –90 –100 –100 1 10 100 1000 1 10 100 1000 FUNDAMENTAL FREQUENCY – MHz FUNDAMENTAL FREQUENCY – MHz TPC 8. AD8074 Distortion vs. Frequency TPC 10. AD8075 Distortion vs. Frequency Rev. B –5– DISTORTION – dBc CROSSTALK – dB CROSSTALK – dB DISTORTION – dBc AD8074/AD8075 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 R = 1k� L –70 –70 R = 1k� L –80 –80 R = 150� L –90 –90 R = 150� L –100 –100 –110 –110 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 14. AD8075 Off Isolation vs. Frequency TPC 11. AD8074 Off Isolation vs. Frequency 20 10 0 10 –10 0 –PSRR –20 –10 +PSRR –30 –20 +PSRR –PSRR –40 –30 –50 –40 –60 –50 –70 –60 –80 –70 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 15. AD8075 PSRR vs. Frequency TPC 12. AD8074 PSRR vs. Frequency 350 400 350 300 300 250 250 200 200 150 150 100 100 50 50 0 0 10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 16. AD8075 Voltage Noise vs. Frequency TPC 13. AD8074 Voltage Noise vs. Frequency –6– Rev. B VOLTAGE NOISE – nV/ Hz OFF ISOLATION – dB PSRR – dB VOLTAGE NOISE – nV/ Hz OFF ISOLATION – dB PSRR – dB AD8074/AD8075 10000 10000 1000 1000 100 100 10 10 1 1 0.1 0.1 0.01 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 17. AD8074 Input Impedance vs. Frequency TPC 20. AD8075 Input Impedance vs. Frequency 1000 1000 100 100 10 10 1 1 0.1 0.1 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 21. AD8075 Output Impedance vs. Frequency; TPC 18. AD8074 Output Impedance vs. Frequency; Enabled Enabled 1000 1000 100 100 10 10 1 1 0.1 0.1 0.01 0.01 0.001 0.001 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY – MHz FREQUENCY – MHz TPC 19. AD8074 Output Impedance vs. Frequency; TPC 22. AD8075 Output Impedance vs. Frequency; Disabled Disabled Rev. B –7– INPUT IMPEDANCE – k� OUTPUT IMPEDANCE – k� OUTPUT IMPEDANCE – � INPUT IMPEDANCE – k� OUTPUT IMPEDANCE – k� OUTPUT IMPEDANCE – � AD8074/AD8075 0.15 0.15 V = 200mV STEP O V = 200mV STEP O 0.10 0.10 0.05 0.05 0 0 –0.05 –0.05 –0.10 –0.10 2ns 2ns –0.15 –0.15 TPC 23. AD8074 Small Signal Pulse Response (R = 1 kΩ, TPC 26. AD8075 Small Signal Pulse Response (R = 150 kΩ) L L C = 5 pF) L 0.8 0.8 0.7 0.7 0.6 V = 700mV STEP O V = 700mV STEP 0.6 O 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 2ns 0 –0.1 2ns –0.1 –0.2 TPC 24. AD8074 Video Amplitude Pulse Response TPC 27. AD8075 Video Amplitude Pulse Response (R = 1 kΩ, C = 5 pF) (R = 150 Ω) L L L 1.5 1.5 V = 2V STEP O V = 2V STEP O 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 2ns 2ns –1.5 –1.5 TPC 25. AD8074 Large Signal Pulse Response TPC 28. AD8075 Large Signal Pulse Response (R = 150 Ω) L (R = 1 kΩ, C = 5 pF) L L –8– Rev. B AD8074/AD8075 THEORY OF OPERATION APPLICATIONS Response Tuning The AD8074 (G = +1) and AD8075 (G = +2) are triple-channel, high-speed buffers with TTL-compatible output enable control. It has been mentioned in passing that the primary cause of over- shoot for the AD8074 and AD8075 is the presence of large Optimized for buffering RGB (red, green, blue) video sources, reactive loads at the output. If the system exhibits excessive the devices have high peak slew rates, maintaining their band- ringing while settling, a 10 Ω–50 Ω series resistor may be used width for large signals. Additionally, the buffers are compensated at the output to isolate the emitter-follower output buffer from for high phase margin, minimizing overshoot for good pixel the reactive load. If the output exhibits an overdamped response, resolution. The buffers also have video specifications that are the system designer may add a few pF shunt capacitance at the suitable for buffering NTSC or PAL composite signals. output to tune for a faster edge transition. A system with a small The buffers are organized as three independent channels, each degree of overshoot will settle faster than an overdamped system. with an input transconductance stage and an output trans- impedance stage. Each channel is characterized by low input 2.0 capacitance and high input impedance. The transconductance R = 10� S 1.5 C = 10pF stages, NPN differential pairs, source signal current into the folded L R = 0� cascode output stages. Each output stage contains a compensat- S 1.0 C = 5pF L ing network and emitter follower output buffer. Internal voltage 0.5 feedback sets the gain, the AD8074 being configured as a unity gain follower, and the AD8075 as a gain-of-two amplifier with a R = 20� S 0 C = 15pF feedback network. The architecture provides drive for a reverse- L terminated video load (150 Ω) with low differential gain and –0.5 phase error for relatively low power consumption. Careful chip –1.0 design and layout allow excellent crosstalk isolation between R S V V IN OUT channels. C L 1k� –1.5 75� 2ns One logic pin, OE, controls whether the three outputs are –2.0 enabled, or disabled to a high-impedance state. The high imped- ance disable allows larger matrices to be built when busing the Figure 2. Driving Capacitive Loads outputs together. When disabled, the AD8074 and AD8075 con- Single Supply Operation sume a fifth the power as when enabled. In the case of the The AD8074 and AD8075 may be operated from a single 10 V AD8075 (G = +2), a feedback isolation scheme is used so that supply. In this configuration, the AD8075’s AGND pins must the impedance of the gain-of-two feedback network does not be tied near midsupply, as AGND provides the reference for the load the output. ground buffer, to which the internal gain network is terminated. Full power bandwidth for an undistorted sinusoid is often calcu- Logic is referenced to DGND. The buffers are disabled in single lated using peak slew rate from the equation: supply operation for V > V + ~2.0 V and enabled for OE DGND V < V + 0.8 V. TTL logic levels are expected. The fol- Peak Slew Rate OE DGND Full Power Bandwidth = lowing restrictions are placed upon the digital ground potential: 2×× π Sinusoidal Amplitude 35 .VV≤≤ –V 12V AVCC DGND Peak slew rate is not the same as average slew rate (25% to V ≥ V DGND AVEE 75%) which is typically specified. For a natural response, peak slew rate may be 2.7 times larger than average slew rate. There- The architecture of the output buffer is such that the output fore, calculating a full power bandwidth with a specified average voltage can swing to within ~2.3 V of either rail. For example, if slew rate will give a pessimistic result. the output need swing only 2 V, then the buffers could be oper- ated on dual 3.5 V or single 7 V supplies. It is cautioned that The primary cause of overshoot in these amplifiers is the pres- saturation effects may become noticeable when the output swings ence of large reactive loads at the output and insufficient series within 2.6 V of either rail. The system designer may opt to isolation of the load. However, it is possible to overdrive these use this characteristic to his or her advantage by using the amplifiers with 1 V, subnanosecond input-pulse edges. The soft-saturation regime, (2.2 V–2.6 V from the supply rails), to ensuing dynamics may give rise to subnanosecond overshoot. To tame excessive overshoot. The designer is cautioned that a reduce these effects, an edge-rate limiting network at the input charge storage associated time delay of several nanoseconds is should be considered for input transition times less than 0.5 ns. incurred when recovering from soft-saturation. This effect results in longer settling tails. Rev. B –9– AD8074/AD8075 RGB Buffer for Second Monitor can be connected to the same signal, as is done in some studio- The RGB signals for PC monitors are driven through coax type TV monitors. cables whose characteristic impedance is 75 Ω. The graphics A way around this problem is to connect the first monitor to the chip will generally have current-source output drivers that should RGB channels in the standard fashion, and then to provide a be double terminated with a 75 Ω shunt termination at each end. triple gain-of-two buffer to drive the second monitor. The AD8075 On the transmit end, the shunt terminations are provided to is designed to provide this function and also provide excellent ground close to the graphics IC, while the monitor terminates high-frequency performance for high-resolution graphics signals. its end via internal termination resistors. While this scheme works Figure 3 shows a schematic of this circuit. well and is virtually foolproof for a single monitor, it leaves no The outputs of the AD8075 are low impedance voltage sources means for passively connecting a second monitor to the same source. and are therefore series-terminated with 75 Ω resistors. The A second monitor that is connected simply in parallel will pro- internal resistors in Monitor #2 provide the terminations at its vide an extra set of terminations that will upset the signal levels. end. The overall effect of this type of termination scheme is to To keep costs low, most computer monitors do not have the ability divide the signal amplitude by two. This is compensated by the to open-circuit the terminations in order that an additional monitor gain of two provided by the AD8075. MONITOR #1 PC GRAPHICS IC R 75� 75� CURRENT SOURCE G OUTPUT DRIVERS INTERNAL 75� 75� TERMINATIONS B 75� 75� +5V +5V +5V + 25�F 0.1�F 0.1�F 0.1�F MONITOR #2 75� 75� AD8075 75� INTERNAL 75� TERMINATIONS 75� 75� 25�F 0.1�F 0.1�F 0.1�F + –5V –5V –5V Figure 3. Buffer –10– Rev. B AD8074/AD8075 Triple Video Multiplexer and the amplifier output are disabled to a high impedance to The AD8074 and AD8075 each have an output-enable function provide a high-impedance disabled state. that can be used to disable the outputs and put them in a high- To construct a multiplexer, the outputs from one or more devices impedance state. Usually, for a unity-gain device, it is relatively are connected in parallel and only one device is enabled at a easy to provide high disabled impedance, because the feedback time while all of the others are disabled. The two sets of inputs path is from the output to a high-impedance input. However, for a are applied individually to each of the separate device inputs. non-unity-gain part, the feedback provides a resistive path to Figure 4 shows the circuit details for this function. The first RGB ground. This will usually dominate the disabled output imped- Source 1 is input to the first AD8075. Each of the individual ance, and make it a much lower value than the unity-gain device. signals is terminated to ground with 75 Ω to provide proper The AD8075 has an internal buffer that provides a low-impedance, termination for the input cables. In a similar fashion, the Source ground level output that terminates the feedback path during 2 signals are input to the second AD8075. enabled operation. In the disabled state, both this buffer output +5V +5V +5V + 25�F 0.1�F 0.1�F 0.1�F 75� R R 75� AD8075 75� SOURCE 1 G G OUTPUT 75� 75� B B 75� OE 25�F 0.1�F 0.1�F 0.1�F + –5V –5V –5V SEL1/SEL2 +5V +5V +5V + 25�F 0.1�F 0.1�F 0.1�F OE 75� R 75� AD8075 75� SOURCE 2 G 75� 75� B 75� 25�F 0.1�F 0.1�F 0.1�F + –5V –5V –5V Figure 4. Mux Rev. B –11– AD8074/AD8075 Each of the six outputs has a 75 Ω series resistor that is used to A major area of focus should be the power distribution system. reverse-terminate the output transmission line. The correspond- There should be a full ground plane that provides the reference ing outputs are then wired in parallel and delivered to the output and return paths for both the inputs and outputs. The ground cable. The termination resistors in this position help to isolate also provides isolation between the input signals to minimize the the off capacitance of the disabled device’s outputs from loading crosstalk. This ground plane should cover as wide an area as the enabled device’s outputs. The gain-of-two of the AD8075 possible and be minimally interrupted in order to keep its compensates for the signal halving that occurs as a result of the impedance to a minimum. output terminations. The power planes should also be as broad as possible to provide A select signal is provided directly to the OE of the second minimal inductance, which is required for high-slew-rate sig- AD8075 and an inverted version is used to drive the other device’s nals. These power planes layers should be spaced closely to the OE. This will ensure that only one device is active at a time. Since ground plane to increase the interplane capacitance between the there is a total of 150 Ω in series between any two outputs, it is supplies and ground. not essential to be overly concerned about the exact timing of Each supply pin should be bypassed with a low inductance the making and breaking of the enable signals. 0.1 µF ceramic capacitance with minimal excess circuit length Additional inputs can easily be added to the circuit shown to to minimize the series impedance. A 25 µF tantalum electro- make wider multiplexers. The outputs of all of the devices will lytic capacitor will supply a charge reservoir for lower frequency, be wired in parallel, and the logic must allow that only one output high-amplitude transitions. be enabled at a time. The input and output signals should be run as directly as pos- If it is desired to make a triple 3:1 multiplexer, a triple 2:1 mul- sible in order to minimize the effects of parasitics. If they must tiplexer, like the AD8185 can be used along with the AD8075. run over a longer distance of more than a few centimeters, con- The same general guidelines for input and output treatment trolled impedance PCB traces should be used to minimize the should be followed and the logic must perform the proper function. effect of reflections due to mismatches in impedance and the proper termination should be provided. If it is desired to design such a multiplexer at unity gain, the AD8074 should be used. For a triple 3:1 multiplexer, an To avoid excess crosstalk, the above recommendations should AD8183 (triple 2:1 mux) can be combined with an AD8074 to be followed carefully. The power system and signal routing are provide this function. the most important aspects of preventing excess crosstalk. Beyond these techniques, shielding can be provided by ground Layout and Grounding traces between adjacent signals, especially those that travel The AD8074 and AD8075 are extreme bandwidth, high-slew-rate parallel over long distances. devices that are designed to drive up to the highest resolution monitors and provide excellent resolution. To realize their full performance potential, it is essential to adhere to the best prac- tices of high-speed PCB layout. –12– Rev. B AD8074/AD8075 TP2 DO NOT INSTALL V EE V P1 1 V EE EE C2 50� IMPEDANCE LINE 10�F + TP3 TP4 AGND V AGND CC AGND P1 2 AGND R16 AGND AGND 20k� TP1 DO NOT INSTALL V CC W2 V V P1 3 CC CC + 50� IMPEDANCE LINE C1 TP5 AGND 10�F 50� IMPEDANCE LINE DISOUT AGND DISOUT R11 50� V CC DO NOT INSTALL C15 C14 AGND 0.01�F 0.01�F IN2 75� IMPEDANCE LINE IN2 AGND AGND DO NOT INSTALL C3 R7 75� IMPEDANCE LINE 0.1�F 75� OUT2 OUT2 R1 C7 AGND 75� R6 0.1�F DUT V EE 150� C13 AGND AGND DO NOT INSTALL 0.01�F 1 V 16 OE CC IN1 75� IMPEDANCE LINE AGND AGND IN1 DGND V 2 15 CC AGND 3 IN2 OUT2 14 AGND R2 R8 75� IMPEDANCE LINE 4 AGND V 13 EE 75� 75� OUT1 OUT1 5 IN1 OUT1 12 AGND AGND R10 6 AGND V 11 V CC CC IN0 75� IMPEDANCE LINE 150� C12 IN0 7 IN0 OUT0 10 AGND 0.01�F DO NOT INSTALL V V V 8 V EE EE EE 9 EE AGND C6 C8 C11 R3 AD8074 AGND 0.1�F 0.01�F 0.01�F 75� AGND R9 75� IMPEDANCE LINE AGND AGND AGND 75� OUT0 OUT0 R12 150� AGND DO NOT INSTALL AGND Figure 5. Evaluation Board Schematic Rev. B –13– AD8074/AD8075 Figure 6. Component Side Figure 8. Silkscreen Top Figure 9. Silkscreen Bottom Figure 7. Circuit Side Figure 10. Internal 2 –14– Rev. B AD8074/AD8075 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.75 0.09 8° 0.60 0.30 0° 0.65 0.45 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 1. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8074ARU −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8074ARUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8074ARUZ-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8074ARUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8075ARUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8075ARUZ-REEL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8075ARUZ-REEL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD8074Z-EVAL Evaluation Board AD8075Z-EVAL Evaluation Board 1 Z = RoHS Compliant Part. REVISION HISTORY 10/11—Rev. A to Rev. B Changes to Ordering Guide ........................................................... 15 10/01—Rev. 0 to Rev. A Changes to Single-Supply Operation Section ................................ 9 ©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02391-0-10/11(B) Rev. B