ANALOG DEVICES AD8073

Low Cost, Dual/Triple a Video Amplifiers AD8072/AD8073 FEATURES PIN CONFIGURATIONS Very Low Cost 8-Lead Plastic (N), SOIC (R), and �SOIC (RM) Packages Good Video Specifications (R = 150 �) L Gain Flatness of 0.1 dB to 10 MHz 0.05% Differential Gain Error 1 8 OUT1 +V S 0.1� Differential Phase Error –IN1 2 7 OUT2 Low Power 3 6 +IN1 –IN2 3.5 mA/Amplifier Supply Current –V 4 5 S +IN2 Operates on Single 5 V to 12 V Supply AD8072 High Speed TOP VIEW (Not to Scale) 100 MHz, –3 dB Bandwidth (G = +2) 500 V/�s Slew Rate 14-Lead Plastic (N), and SOIC (R) Packages Fast Settling Time of 25 ns (0.1%) Easy to Use 30 mA Output Current NC 1 14 OUT2 Output Swing to 1.3 V of Rails on Single 5 V Supply 2 13 NC –IN2 APPLICATIONS 3 12 NC +IN2 AD8073 Video Line Driver 4 11 +V TOP VIEW –V S S (Not to Scale) Computer Video Plug-In Boards +IN1 5 10 +IN3 RGB or S-Video Amplifier in Component Systems –IN1 6 9 –IN3 7 8 OUT1 OUT3 PRODUCT DESCRIPTION The AD8072 (dual) and AD8073 (triple) are low cost, current NC = NO CONNECT feedback amplifiers intended for high volume, cost sensitive applications. In addition to being low cost, these amplifiers deliver solid video performance into a 150 Ω load while consuming 6.1 7 only 3.5 mA per amplifier of supply current. Furthermore, the 6.0 6 AD8073 is three amplifiers in a single 14-lead narrow-body SOIC package. This makes it ideal for applications where small 5 5.9 size is essential. Each amplifier’s inputs and output are acces- sible providing added gain setting flexibility. 4 5.8 These devices provide 30 mA of output current per amplifier, 3 5.7 V = �5V S 1 dB and are optimized for driving one back terminated video load V = 2V p-p O DIV (150 Ω) each. These current feedback amplifiers feature gain 2 5.6 R = R = 1k� F G flatness of 0.1 dB to 10 MHz while offering differential gain and R = 150� L 0.1 dB 1 5.5 A = �2 DIV V phase error of 0.05% and 0.1°. This makes the AD8072 and AD8073 ideal for business and consumer video electronics. 0 5.4 Both will operate from a single 5 V to 12 V power supply. The 5.3 –1 outputs of each amplifier swing to within 1.3 volts of either sup- 0.1 110 100 500 ply rail to accommodate video signals on a single 5 V supply. FREQUENCY – MHz The high bandwidth of 100 MHz, 500 V/µs of slew rate, along Figure 1. Large Signal Frequency Response with settling to 0.1% in 25 ns, make the AD8072 and AD8073 useful in many general purpose, high speed applications where a single 5 V or dual power supplies up to ±6 V are needed. The AD8072 is available in 8-lead plastic DIP, SOIC, and µSOIC packages while the AD8073 is available in 14-lead plastic DIP and SOIC packages. Both operate over the commercial temperature range of 0°C to 70°C. Additionally, the AD8072ARM operates over the industrial temperature range of –40°C to +85°C. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002 GAIN FLATNESS – dB CLOSED-LOOP GAIN – dB AD8072/AD8073–SPECIFICATIONS (@ T = 25�C, V = �5 V, R = 150 �, unless otherwise noted.) ELECTRICAL CHARACTERISTICS A S L AD8072/AD8073 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE R = 1 kΩ F –3 dB Bandwidth, Small Signal No Peaking, G = +2 80 100 MHz 0.1 dB Bandwidth, Small Signal No Peaking, G = +2 8 10 MHz Slew Rate V = 4 V Step 500 V/µs O Settling Time to 0.1% V = 2 V Step 25 ns O DISTORTION/NOISE PERFORMANCE R = 1 kΩ F Differential Gain f = 3.58 MHz, G = +2 0.05 0.15 % Differential Phase f = 3.58 MHz, G = +2 0.1 0.3 Degrees Crosstalk f = 5 MHz 60 dB Input Voltage Noise f = 10 kHz 3 nV/√Hz Input Current Noise f = 10 kHz (±I ) 6 pA/√Hz IN DC PERFORMANCE Transimpedance 0.3 MΩ Input Offset Voltage 2 6 mV T to T 8mV MIN MAX Offset Drift 11 µV/°C Input Bias Current (±)412 µA Input Bias Current Drift (±)12nA/°C INPUT CHARACTERISTICS –Input Resistance 120 Ω +Input Resistance 1 MΩ Input Capacitance 1.6 pF Common-Mode Rejection Ratio V = –3.8 V to +3.8 V 56 dB CM Input Common-Mode Voltage Range ±3.8 V OUTPUT CHARACTERISTICS +Output Voltage Swing 3 3.3 V –Output Voltage Swing 2.25 3 V Output Current R = 10 Ω 30 mA L Short Circuit Current 80 mA POWER SUPPLY Operating Range ±2.5 to ±6V Power Supply Rejection Ratio V = ±4 V to ±6 V 70 dB S Quiescent Current per Amplifier 3.5 5 mA OPERATING TEMPERATURE RANGE 0 70 °C Specifications subject to change without notice. –2– REV. D AD8072/AD8073 (@ T = 25�C, V = 5 V, R = 150 � to 2.5 V, unless otherwise noted.) ELECTRICAL CHARACTERISTICS A S L AD8072/AD8073 Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE R = 1 kΩ F –3 dB Bandwidth, Small Signal No Peaking, G = +2 78 100 MHz 0.1 dB Bandwidth, Small Signal No Peaking, G = +2 7.8 10 MHz Slew Rate V = 2 V Step 350 V/µs O Settling Time to 0.1% V = 2 V Step 25 ns O DISTORTION/NOISE PERFORMANCE R = 1 kΩ F Differential Gain f = 3.58 MHz, G = +2, R to 1.5 V 0.1 % L Differential Phase f = 3.58 MHz, G = +2, R to 1.5 V 0.1 Degrees L Crosstalk f = 5 MHz 60 dB Input Voltage Noise f = 10 kHz 3 nV/√Hz Input Current Noise f = 10 kHz (±I ) 6 pA/√Hz IN DC PERFORMANCE Transimpedance 0.25 MΩ Input Offset Voltage 1.5 4 mV T to T 6mV MIN MAX Offset Drift 9 µV/°C Input Bias Current (±) 310 µA Input Bias Current Drift (±)10nA/°C INPUT CHARACTERISTICS –Input Resistance 120 Ω +Input Resistance 1MΩ Input Capacitance 1.6 pF Common-Mode Rejection Ratio V = 1.2 V to 3.8 V 54 dB CM Input Common-Mode Voltage Range 1.2 to 3.8 V OUTPUT CHARACTERISTICS Output Voltage Swing R = 150 Ω 1.5 to 3.5 1.3 to 3.7 V L Output Voltage Swing R = 1 kΩ T to T 1.3 to 3.7 1.1 to 3.9 V L MIN MAX Output Current R = 10 Ω 20 mA L Short Circuit Current 60 mA POWER SUPPLY Operating Range ±2.5 to ±6V Power Supply Rejection Ratio V = 4 V to 6 V 64 dB S Quiescent Current per Amplifier 3 4.5 mA OPERATING TEMPERATURE RANGE 0 70 °C Specifications subject to change without notice. REV. D –3– AD8072/AD8073 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.2 V The maximum power that can be safely dissipated by the AD8072 2 Internal Power Dissipation and AD8073 is limited by the associated rise in junction tem- AD8072 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . . 1.3 Watts perature. The maximum safe junction temperature for plastic AD8072 8-Lead Small Outline (SO-8) . . . . . . . . . 0.9 Watts encapsulated devices is determined by the glass transition tem- AD8072 8-Lead µSOIC (RM) . . . . . . . . . . . . . . . . 0.6 Watts perature of the plastic, approximately 150°C. Exceeding this AD8073 14-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.6 Watts limit temporarily may cause a shift in parametric performance AD8073 14-Lead Small Outline (R) . . . . . . . . . . . 1.0 Watts due to a change in the stresses exerted on the die by the package. Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .±V Exceeding a junction temperature of 175°C for an extended S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ±1.25 V period can result in device failure. Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . While the AD8072 and AD8073 are internally short circuit pro- . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves tected, this may not be sufficient to guarantee that the maximum Storage Temperature Range junction temperature (150°C) is not exceeded under all condi- N, R, RM Packages . . . . . . . . . . . . . . . . . . –65°C to +125°C tions. To ensure proper operation, it is necessary to observe the Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C maximum power derating curves shown in Figures 2 and 3. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- 2.0 nent damage to the device. This is a stress rating only; functional operation of the 8-LEAD MINI-DIP PACKAGE T = 150�C J device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating 1.5 conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic Package: θ = 90°C/W JA 8-LEAD SOIC PACKAGE 8-Lead SOIC Package: θ = 140°C/W JA 1.0 8-Lead µSOIC Package: θ = 214°C/W JA 14-Lead Plastic Package: θ = 75°C/W JA 14-Lead SOIC Package: θ = 120°C/W JA �SOIC 0.5 ORDERING GUIDE Temperature Package Package 0 Model Range Description Option –50 –40 –30 –20 –10 0 10 20 30 40 5060 7080 90 AMBIENT TEMPERATURE – �C *AD8072ARM –40°C to +85°C 8-Lead µSOIC RM-8 *AD8072ARM-REEL –40°C to +85°C 13" Reel 8-Lead µSOIC RM-8 Figure 2. AD8072 Maximum Power Dissipation vs. *AD8072ARM-REEL7 –40°C to +85°C 7" Reel 8-Lead µSOIC RM-8 Temperature AD8072JN 0°C to 70°C 8-Lead Plastic DIP N-8 AD8072JR 0°C to 70°C 8-Lead SOIC SO-8 2.5 AD8072JR-REEL 0°C to 70°C 13" Reel 8-Lead SOIC SO-8 T = 150�C J AD8072JR-REEL7 0°C to 70°C 7" Reel 8-Lead SOIC SO-8 AD8073JN 0°C to 70°C 14-Lead Plastic DIP N-14 2.0 AD8073JR 0°C to 70°C 14-Lead Narrow SOIC R-14 AD8073JR-REEL 0°C to 70°C 13" Reel 14-Lead SOIC R-14 14-LEAD DIP PACKAGE AD8073JR-REEL7 0°C to 70°C 7" Reel 14-Lead SOIC R-14 1.5 *Brand Code: HLA 14-LEAD SOIC 1.0 0.5 –50 –40 –30 –20 –10 0 1020 3040 50 60 70 80 90 AMBIENT TEMPERATURE – �C Figure 3. AD8073 Maximum Power Dissipation vs. Temperature CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. WARNING! Although the AD8072/AD8073 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. D MAXIMUM POWER DISSIPATION – W MAXIMUM POWER DISSIPATION – W Typical Performance Characteristics– AD8072/AD8073 7 6.1 6 6.0 5 5.9 4 5.8 0�C, 25�C V = �5V 3 5.7 70�C S R = 1k� F V = 5V S R = 150� 2 5.6 L R = 1k� F A = 2 V 0�C R = 150� TO 2.5V L V = 100mV p-p 1 5.5 IN A = 2 V V = 100mV p-p IN 70�C 0 5.4 25�C 0.1 5.3 0.1 1.0 10 100 1000 0.1 1.0 10 100 500 FREQUENCY – MHz FREQUENCY – MHz TPC 1. Frequency Response Over Temperature; V = 5 V TPC 4. 0.1 dB Flatness vs. Frequency Over Temperature; S V = ±5 V S MIN = 0.00 MAX = 0.09 p-p/MAX = 0.09 7 0.00 0.03 0.07 0.08 0.08 0.08 0.09 0.08 0.08 0.07 0.06 0.12 V = 5V, R = 1k�, R = 150� TO 1.5V, A = 2 6 S F L V 0.10 0.08 0.06 5 0.04 0.02 4 0.00 –0.02 3 MIN = 0.00 MAX = 0.10 p-p = 0.10 V = �5V 0.00 0.05 0.09 0.10 0.09 0.08 0.06 0.06 0.05 0.04 0.02 S 0�C 2 R = 1k� F 0.12 V = 5V, R = 1k�, R = 150� TO 1.5V, A = 2 S F L V R = 150� 0.10 L 70�C 1 0.08 A = 2 V 25�C 0.06 V = 100mV p-p IN 0.04 0 0.02 0.00 0.1 –0.02 0.1 1.0 10 100 1000 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH FREQUENCY – MHz MODULATING RAMP LEVEL – IRE TPC 2. Frequency Response Over Temperature; V = ±5 V TPC 5. Differential Gain and Phase, V = 5 V S S MIN = –0.03 MAX = 0.00 p-p/MAX = 0.03 6.1 0.00 0.00 0.00 –0.00 0.00 –0.01 –0.01 –0.02 –0.03 –0.03 –0.03 6.0 0.00 V = �5V S –0.01 5.9 R = 1k� F –0.02 R = 150� L 5.8 –0.03 A = 2 V 5.7 V = 5V S MIN = –0.10 MAX = 0.00 p-p = 0.10 R = 1k� F 0.00 0.00 –0.00 –0.02 –0.03 –0.05 –0.07 –0.08 –0.10 –0.10 –0.10 R = 150� TO 2.5V 5.6 L 0.02 A = 2 V 0.00 0�C, 25�C V = 100mV p-p IN 5.5 –0.02 V = �5V S –0.04 70�C R = 1k� F –0.06 5.4 –0.08 R = 150� L –0.10 A = 2 V –0.12 5.3 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 0.1 1.0 10 100 500 FREQUENCY – MHz MODULATING RAMP LEVEL – IRE TPC 3. 0.1 dB Flatness vs. Frequency Over Temperature; TPC 6. Differential Gain and Phase, V = ±5 V S V = 5 V S REV. D –5– GAIN FLATNESS – dB CLOSED-LOOP GAIN – dB CLOSED-LOOP GAIN – dB DIFFERENTIAL PHASE – deg DIFFERENTIAL GAIN – % DIFFERENTIAL PHASE – deg DIFFERENTIAL GAIN – % GAIN FLATNESS – dB AD8072/AD8073 0 1M 0 AMP 2 OUTPUT –10 –20 SOIC PACKAGE OHMS (�) DRIVE AMP 2 –20 100k –40 RECEIVE AMPS 1, 3 AD8073 RECEIVE AMP 1 AD8072 –30 –60 V = 5V, �5V S DEGREES R = 1k�, R = 150� F 10k –40 L A = 2 V –80 V = 1V p-p IN –50 –100 –60 1k –120 –70 –140 –80 100 –160 –90 –180 –100 10 0.1 1.0 10 100 500 1k 10k 100k 1M 10M 100M 1G FREQUENCY – MHz FREQUENCY – Hz TPC 7. Crosstalk vs. Frequency TPC 10. Open-Loop Transimpedance vs. Frequency –40 3 V = �5V S 2 R = 1k� F –50 A = 1 V R = 150� L 1 A = 2 V V = 2V p-p OUT 3RD –60 0 HARMONIC –1 –70 –2 V = �5V S A = 2 A = 10 V R = 1k� V 2ND F –80 –3 HARMONIC R = 150� L V = 200mV p-p OUT –4 –90 A = 5 V –5 –100 –6 0.1 1 10 0.1 1 10 100 1k FREQUENCY – MHz FREQUENCY – MHz TPC 8. Distortion vs. Frequency; V = ±5 V TPC 11. Normalized Frequency Response; V = ±5 V S S –40 6.1 7 V = 5V S 6 6.0 R = 1k� F –50 3RD R = 150� TO 2.5V L HARMONIC A = 2 5 5.9 V V = 2V p-p OUT –60 4 5.8 3 –70 5.7 V = 5V S 1 dB V = 2V p-p O DIV 2 5.6 2ND R = R = 1k� F G –80 HARMONIC R = 150� TO 2.5V 0.1 dB L 1 5.5 DIV A = 2 V –90 0 5.4 –100 5.3 –1 0.1 1 10 0.1 1 10 100 500 FREQUENCY – MHz FREQUENCY – MHz TPC 9. Distortion vs. Frequency; V = 5 V TPC 12. Large Signal Frequency Response S –6– REV. D CROSSTALK – dB DISTORTION – dBc DISTORTION – dBc T – � Z GAIN FLATNESS – dB NORMALIZED CLOSED-LOOP GAIN – dB CLOSED-LOOP GAIN – dB DEGREES AD8072/AD8073 100 V = �5V S 100 R = 1k� F 80 A = 2 V 60 10 40 1 20 0 0.1 1 10 100 1k 10k 100k 0.1 1 10 100 500 FREQUENCY – Hz FREQUENCY – MHz TPC 13. Output Resistance vs. Frequency; V = ±5 V TPC 15. Noise vs. Frequency; V = ±5 V S S 50 10 V = �5V S 0 R = 1k� F R = 150� 40 L –10 A = 2 V –PSRR 100mV p-p ON TOP OF V –20 S 30 –30 20 –40 �PSRR –50 10 –60 0 –70 1 10 100 1k 10k 100k 0.02 0.1 1 10 100 500 FREQUENCY – Hz FREQUENCY – MHz TPC 14. Noise vs. Frequency; V = ±5 V TPC 16. PSRR vs. Frequency S –5 1k� 1k� V IN –10 2V p-p V 154� OUT –15 60.4� 150� 154� –20 –25 –30 –35 –40 –45 –50 –55 0.1 1 10 100 500 0.02 FREQUENCY – MHz TPC 17. CMRR vs. Frequency; V = ±5 V S REV. D –7– INPUT VOLTAGE NOISE – nV/ Hz OUTPUT RESISTANCE – � CMRR – dB INPUT CURRENT NOISE – pA/ Hz PSRR – dB AD8072/AD8073 1k� 1k� V OUT R L 150� V IN �V S + 50� 0.1�F 0.001�F 10�F + 0.1�F 0.001�F 10�F –V S TPC 18. Test Circuit; Gain = +2 250mV 20ns 250mV 10ns TPC 19. 2 V Step Response; G = +2, V = ±5 V TPC 22. 2 V Step Response; G = +2, V = ±2.5 V* S S 50mV 20ns 50mV 20ns TPC 20. 200 mV Step Response; G = +2, V = ±5 V TPC 23. 200 mV Step Response; G = +2, V = ±2.5 V* S S 1V 20ns 250mV 20ns TPC 21. Sine Response; G = +2, V = ±5 V TPC 24. Sine Response; G = +2, V = ±2.5 V* S S *V = ±2.5 V operation is identical to V = 5 V single supply operation. S S –8– REV. D AD8072/AD8073 APPLICATIONS On the other hand, the bandwidth of a current feedback ampli- Overdrive Recovery fier can be decreased by increasing the feedback resistance. This Overdrive of an amplifier occurs when the output and/or input can sometimes be useful where it is desired to reduce the noise range are exceeded. The amplifier must recover from this overdrive bandwidth of a system. As a practical matter, the maximum condition and resume normal operation. As shown in Figure 4, value of feedback resistor was found to be 2 kΩ. Figure 5 shows the AD8072 and AD8073 recover within 75 ns from positive the frequency response of an AD8072/AD8073 at a gain of two overdrive and 30 ns from negative overdrive. with both feedback and gain resistors equal to 2 kΩ. Capacitive Load Drive When an op amp output drives a capacitive load, extra phase shift V due to the pole formed by the op amp’s output impedance and IN V the capacitor can cause peaking or even oscillation. The top trace OUT of Figure 6, R = 0 Ω, shows the output of one of the amplifiers of S the AD8072/AD8073 when driving a 50 pF capacitor as shown in the schematic of Figure 7. The amount of peaking can be significantly reduced by adding a resistor in series with the capacitor. The lower trace of Figure 6 shows the same capacitor being driven with a 25 Ω resistor in series with it. In general, the resistor value will have to be experimentally determined, but 10 Ω to 50 Ω is a practical range 1V 25ns of values to experiment with for capacitive loads of up to a few hundred pF. Figure 4. Overload Recovery; V = ±5 V, V = 8 V p-p, S IN R = 1 kΩ, R = 150 Ω, G = +2 F L R = 0Ω S Bandwidth vs. Feedback Resistor Value R = 25Ω S The closed-loop frequency response of a current feedback amplifier is a function of the feedback resistor. A smaller feedback resistor will produce a wider bandwidth response. However, if the feed- back resistance becomes too small, the gain flatness can be affected. As a practical consideration, the minimum value of feedback resistance for the AD8072/AD8073 was found to be 649 Ω. For resistances below this value, the gain flatness will be affected and more significant lot-to-lot variations in device per- formance will be noticed. Figure 5 shows a plot of the frequency 50mV 20ns response of an AD8072/AD8073 at a gain of two with both feed- back and gain resistors equal to 649 Ω. Figure 6. Capacitive Low Drive 6.1 7 1k� 1k� 6.0 6 R S 5.9 5 R = 649� F V = 100mV p-p C R IN L L 5.8 4 50pF 1k� 50� 0.1 dB DIV 5.7 3 V = �5V S A = 2 Figure 7. Capacitive Load Drive Circuit V 5.6 1 dB 2 R = 150� L DIV V = 0.2V p-p O 5.5 1 R = 2k� F 0 5.4 0.1 1 10 100 500 FREQUENCY – MHz Figure 5. Frequency Response vs. R F REV. D –9– GAIN FLATNESS – dB CLOSED-LOOP GAIN – dB AD8072/AD8073 Crosstalk Layout Considerations Crosstalk between internal amplifiers may vary depending on The specified high speed performance of the AD8072 and which amplifier is being driven and how many amplifiers are AD8073 require careful attention to board layout and compo- being driven. This variation typically stems from pin location on nent selection. Proper RF design techniques and low parasitic the package and the internal layout of the IC itself. Table I component selection are mandatory. illustrates the typical crosstalk results for a combination of The PCB should have a ground plane covering all unused portions conditions. of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the Table I. AD8073JR Crosstalk Table (dB) area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing. One end Receive Amplifier of the capacitor should be connected to the ground plane and AD8073JR 12 3 the other within 1/8 inches of each power pin. An additional 1 X –60 –56 large (4.7 µF–10 µF) tantalum electrolytic capacitor should be connected in parallel, but not necessarily as close to the supply 2 –60 X –60 Drive pins, to provide current for fast large-signal changes at the Amplifier 3 –54 –60 X device’s output. All Hostile –53 –55 –54 The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the invert- CONDITIONS ing input will affect high speed performance. V = ±5 V S R = 1 kΩ, R = 150 Ω Stripline design techniques should be used for long signal traces F L A = 2 (greater than approximately 1 inch). These should be designed V V = 2 V p-p on Drive Amplifier with a characteristic impedance of 50 Ω or 75 Ω and be properly OUT terminated at each end. –10– REV. D AD8072/AD8073 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP 14-Lead Plastic DIP (N-8) (N-14) 0.430 (10.92) 0.795 (20.19) 0.348 (8.84) 0.725 (18.42) 8 5 14 8 0.280 (7.11) 0.280 (7.11) 0.240 (6.10) 0.240 (6.10) 17 0.325 (8.25) 14 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) 0.300 (7.62) 0.060 (1.52) 0.115 (2.93) PIN 1 PIN 1 0.060 (1.52) 0.015 (0.38) 0.015 (0.38) 0.210 (5.33) 0.195 (4.95) 0.210 (5.33) MAX 0.115 (2.93) 0.130 MAX 0.130 (3.30) 0.160 (4.06) (3.30) 0.160 (4.06) MIN 0.115 (2.93) MIN 0.015 (0.381) 0.115 (2.93) 0.015 (0.381) SEATING 0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.008 (0.204) 0.022 (0.558) 0.100 0.070 (1.77) PLANE 0.008 (0.204) (2.54) PLANE 0.014 (0.356) 0.045 (1.15) (2.54) 0.014 (0.356) 0.045 (1.15) BSC BSC 8-Lead Plastic SOIC 14-Lead SOIC (R-8) (R-14) 0.1968 (5.00) 0.3444 (8.75) 0.1890 (4.80) 0.3367 (8.55) 8 5 14 8 0.1574 (4.00) 0.2440 (6.20) 0.1574 (4.00) 0.2440 (6.20) 1 4 1 7 0.1497 (3.80) 0.2284 (5.80) 0.1497 (3.80) 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0688 (1.75) PIN 1 0.0196 (0.50) 0.0196 (0.50) x 45° x 45° 0.0532 (1.35) 0.0098 (0.25) 0.0532 (1.35) 0.0098 (0.25) 0.0099 (0.25) 0.0099 (0.25) 0.0040 (0.10) 0.0040 (0.10) 8° 8° 0.0500 0.0192 (0.49) 0.0500 0.0192 (0.49) 0° 0° SEATING SEATING 0.0098 (0.25) 0.0500 (1.27) 0.0099 (0.25) 0.0500 (1.27) (1.27) (1.27) 0.0138 (0.35) 0.0138 (0.35) PLANE PLANE BSC 0.0075 (0.19) 0.0160 (0.41) BSC 0.0160 (0.41) 0.0075 (0.19) 8-Lead �SOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 85 0.122 (3.10) 0.199 (5.05) 0.114 (2.90) 0.187 (4.75) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.120 (3.05) 0.112 (2.84) 0.112 (2.84) 0.043 (1.09) 0.006 (0.15) 0.037 (0.94) 0.002 (0.05) 33� 0.018 (0.46) 27� 0.028 (0.71) 0.011 (0.28) SEATING 0.008 (0.20) 0.016 (0.41) PLANE 0.003 (0.08) REV. D –11– AD8072/AD8073 Revision History Location Page 3/02—Data Sheet changed from REV. C to REV. D. Edits to Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 10/01—Data Sheet changed from REV. B to REV. C. Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 –12– REV. D C01066–0–3/02(D) PRINTED IN U.S.A.