ANALOG DEVICES AD8066

High Performance, 145 MHz FastFET Op Amps AD8065/AD8066 FEATURES APPLICATIONS Automotive driver assistance systems Qualified for automotive applications Photodiode preamps FET input amplifier Filters 1 pA input bias current A/D drivers Low cost Level shifting High speed: 145 MHz, −3 dB bandwidth (G = +1) Buffering 180 V/μs slew rate (G = +2) CONNECTION DIAGRAMS Low noise AD8065 7 nV/√Hz (f = 10 kHz) AD8065 V 1 5 +V OUT NC 1 8 NC S 0.6 fA/√Hz (f = 10 kHz) –V 27 S 2 –IN +V S Wide supply voltage range: 5 V to 24 V +IN 3 6 V +IN 3 4 –IN Single-supply and rail-to-rail output OUT TOP VIEW (Not to Scale) –V Low offset voltage 1.5 mV maximum 4 5 NC S TOP VIEW (Not to Scale) High common-mode rejection ratio: −100 dB Excellent distortion specifications AD8066 SFDR −88 dBc @ 1 MHz V 1 8 +V OUT1 S Low power: 6.4 mA/amplifier typical supply current –IN1 2 7 V OUT2 No phase reversal 3 +IN1 6 –IN2 Small packaging: SOIC-8, SOT-23-5, and MSOP-8 –V 4 5 S +IN2 TOP VIEW (Not to Scale) Figure 1. The AD8065/AD8066 are high performance, high speed, FET GENERAL DESCRIPTION input amplifiers available in small packages: SOIC-8, MSOP-8, 1 The AD8065/AD8066 FastFET™ amplifiers are voltage feedback and SOT-23-5. They are rated to work over the industrial amplifiers with FET inputs offering high performance and ease temperature range of −40°C to +85°C. of use. The AD8065 is a single amplifier, and the AD8066 is a The AD8065WARTZ-REEL7 is fully qualified for automotive dual amplifier. These amplifiers are developed in the Analog applications. It is rated to operate over the extended temperature Devices, Inc. proprietary XFCB process and allow exceptionally range (−40°C to +105°C), up to a maximum supply voltage low noise operation (7.0 nV/√Hz and 0.6 fA/√Hz) as well as range of + very high input impedance. 5V only. 24 With a wide supply voltage range from 5 V to 24 V, the ability to 21 operate on single supplies, and a bandwidth of 145 MHz, the G = +10 V = 200mV p-p O AD8065/AD8066 are designed to work in a variety of applications. 18 For added versatility, the amplifiers also contain rail-to-rail outputs. 15 G = +5 Despite the low cost, the amplifiers provide excellent overall 12 performance. The differential gain and phase errors of 0.02% 9 and 0.02°, respectively, along with 0.1 dB flatness out to 7 MHz, G = +2 6 make these amplifiers ideal for video applications. Additionally, 3 they offer a high slew rate of 180 V/μs, excellent distortion (SFDR G = +1 0 of −88 dBc @ 1 MHz), extremely high common-mode rejection of −100 dB, and a low input offset voltage of 1.5 mV maximum –3 under warmed up conditions. The AD8065/AD8066 operate –6 0.1 1 10 100 1000 using only a 6.4 mA/amplifier typical supply current and are FREQUENCY (MHz) capable of delivering up to 30 mA of load current. Figure 2. Small Signal Frequency Response 1 Protected by U. S. Patent No. 6,262,633. Rev. J Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 02916-E-001 02916-E-002 AD8065/AD8066 TABLE OF CONTENTS Features .............................................................................................. 1 Wideband Operation ................................................................. 21 Applications ....................................................................................... 1 Input Protection ......................................................................... 21 Connection Diagrams ...................................................................... 1 Thermal Considerations ............................................................ 22 General Description ......................................................................... 1 Input and Output Overload Behavior ..................................... 22 Revision History ............................................................................... 3 Layout, Grounding, and Bypassing Considerations .................. 23 Specifications ±5 V ........................................................................... 4 Power Supply Bypassing ............................................................ 23 Specifications ±12 V ......................................................................... 6 Grounding ................................................................................... 23 Specifications +5 V ........................................................................... 7 Leakage Currents ........................................................................ 23 Absolute Maximum Ratings ............................................................ 9 Input Capacitance ...................................................................... 23 Maximum Power Dissipation ..................................................... 9 Output Capacitance ................................................................... 23 Output Short Circuit .................................................................... 9 Input-to-Output Coupling ........................................................ 24 ESD Caution .................................................................................. 9 Wideband Photodiode Preamp ................................................ 24 Typical Performance Characteristics ........................................... 10 High Speed JFET Input Instrumentation Amplifier.............. 25 Test Circuits ..................................................................................... 17 Video Buffer ................................................................................ 26 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 27 Closed-Loop Frequency Response ........................................... 20 Ordering Guide .......................................................................... 28 Noninverting Closed-Loop Frequency Response .................. 20 Automotive Products ................................................................. 28 Inverting Closed-Loop Frequency Response ......................... 20 Rev. J | Page 2 of 28 AD8065/AD8066 REVISION HISTORY 8/10—Rev. I to Rev. J 12/05—Rev. E to Rev. F Changes to Features Section, Applications Section, and General Updated Format ................................................................. Universal Description Section ........................................................................... 1 Changes to Features .......................................................................... 1 Change to Table 1 .............................................................................. 4 Changes to General Description ..................................................... 1 Change to Table 3 .............................................................................. 7 Changes to Figure 22 through Figure 27 ...................................... 11 Changes to Table 4 ............................................................................ 9 Updated Outline Dimensions ........................................................ 25 Changes to Figure 9 ......................................................................... 10 Changes to Ordering Guide ........................................................... 26 Changes to Inverting Closed-Loop Frequency Response 2/04—Rev. D to Rev. E. Section .............................................................................................. 20 Updated Format ................................................................ Universal Moved Leakage Currents Section, Input Capacitance Section, Updated Figure 56 ......................................................................... 21 and Output Capacitance Section ................................................... 23 Updated Outline Dimensions ...................................................... 25 Moved Input-to-Input Coupling Section, Wideband Updated Ordering Guide ............................................................. 26 Photodiode Preamp Section, and Figure 59 ................................ 24 11/03—Rev. C to Rev. D. Changes to Table 5 .......................................................................... 25 Changes to Features ......................................................................... 1 Moved Figure 60 and High Speed JFET Input Instrumentation Changes to Connection Diagrams ................................................. 1 Amplifier Section ............................................................................ 25 Updated Ordering Guide ................................................................ 5 Updated Outline Dimensions ........................................................ 27 Updated Outline Dimensions ...................................................... 22 Changes to Ordering Guide ........................................................... 28 Added Automotive Products Section ........................................... 28 4/03—Rev. B to Rev. C. 3/09—Rev. H to Rev. I Added SOIC-8 (R) for the AD8065 ............................................... 4 Changes to High Speed JFET Input Instrumentation Amplifier 2/03—Rev. A to Rev. B. Section .............................................................................................. 23 Changes to Absolute Maximum Ratings....................................... 4 Updated Outline Dimensions ........................................................ 24 Changes to Test Circuit 10 ........................................................... 14 9/08—Rev. G to Rev. H Changes to Test Circuit 11 ........................................................... 15 Deleted Usable Range Parameter, Table 1 ...................................... 3 Changes to Noninverting Closed-Loop Frequency Response 16 Deleted Usable Range Parameter, Table 2 ...................................... 4 Changes to Inverting Closed-Loop Frequency Response ....... 16 Deleted Usable Range Parameter, Table 3 ...................................... 5 Updated Figure 6 .......................................................................... 18 Changes to Layout ............................................................................. 6 Changes to Figure 7 ...................................................................... 19 Changes to Input and Output Overload Behavior Section ........ 19 Changes to Figure 10 .................................................................... 21 Changes to Figure 11 .................................................................... 22 Changes to Table 5 Expressions Column ..................................... 22 Changes to High Speed JFET Instrumentation Amplifier ...... 22 1/06—Rev. F to Rev. G Changes to Video Buffer .............................................................. 22 Changes to Ordering Guide ........................................................... 26 8/02—Rev. 0 to Rev. A. Added AD8066 .................................................................. Universal Added SOIC-8 (R) and MSOP-8 (RM) ......................................... 1 Edits to General Description .......................................................... 1 Edits to Specifications ...................................................................... 2 New Figure 2 ..................................................................................... 5 Changes to Ordering Guide ............................................................ 5 Edits to TPCs 18, 25, and 28 ........................................................... 8 New TPC 36 ................................................................................... 11 Added Test Circuits 10 and 11 .................................................... 14 MSOP (RM-8) Added .................................................................. 23 Rev. J | Page 3 of 28 AD8065/AD8066 SPECIFICATIONS ±5 V @ TA = 25°C, VS = ±5 V, RL = 1 kΩ, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p (AD8065) 100 145 MHz O AD8065WARTZ only: TMIN − TMAX 88 MHz G = +1, VO = 0.2 V p-p (AD8066) 100 120 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, V = 2 V p-p 42 MHz O Bandwidth for 0.1 dB Flatness G = +2, V = 0.2 V p-p 7 MHz O Input Overdrive Recovery Time G = +1, −5.5 V to +5.5 V 175 ns Output Recovery Time G = −1, −5.5 V to +5.5 V 170 ns Slew Rate G = +2, VO = 4 V step 130 180 V/μs AD8065WARTZ only: T − T 155 V/μs MIN MAX Settling Time to 0.1% G = +2, V = 2 V step 55 ns O G = +2, V = 8 V step 205 ns O NOISE/HARMONIC PERFORMANCE SFDR f = 1 MHz, G = +2, V = 2 V p-p −88 dBc C O f = 5 MHz, G = +2, V = 2 V p-p −67 dBc C O fC = 1 MHz, G = +2, VO = 8 V p-p −73 dBc Third-Order Intercept fC = 10 MHz, RL = 100 Ω 24 dBm Input Voltage Noise f = 10 kHz 7 nV/√Hz Input Current Noise f = 10 kHz 0.6 fA/√Hz Differential Gain Error NTSC, G = +2, R = 150 Ω 0.02 % L Differential Phase Error NTSC, G = +2, R = 150 Ω 0.02 Degrees L DC PERFORMANCE Input Offset Voltage V = 0 V, SOIC package 0.4 1.5 mV CM AD8065WARTZ only: TMIN − TMAX 2.6 mV Input Offset Voltage Drift 1 17 μV/°C AD8065WARTZ only: TMIN − TMAX 17 μV/°C Input Bias Current SOIC package 2 6 pA T to T 25 125 pA MIN MAX Input Offset Current 1 10 pA TMIN to TMAX 1 125 pA Open-Loop Gain VO = ±3 V, RL = 1 kΩ 100 113 dB AD8065WARTZ only: TMIN − TMAX 100 dB INPUT CHARACTERISTICS Common-Mode Input Impedance 1000 || 2.1 GΩ || pF Differential Input Impedance 1000 || 4.5 GΩ || pF Input Common-Mode Voltage Range FET Input Range −5 to +1.7 −5.0 to +2.4 V AD8065WARTZ only: TMIN − TMAX −5 to +1.7 V Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB VCM = −1 V to +1 V (SOT-23) −82 −91 dB AD8065WARTZ only: T − T −82 dB MIN MAX Rev. J | Page 4 of 28 AD8065/AD8066 Parameter Conditions Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ −4.88 to +4.90 −4.94 to +4.95 V AD8065WARTZ only: TMIN − TMAX −4.88 to +4.90 V R = 150 Ω −4.8 to +4.7 V L Output Current V = 9 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA O Short-Circuit Current 90 mA Capacitive Load Drive 30% overshoot G = +1 20 pF POWER SUPPLY Operating Range 5 24 V AD8065WARTZ only: TMIN − TMAX 5 10 V Quiescent Current per Amplifier 6.4 7.2 mA AD8065WARTZ only: T − T 7.2 mA MIN MAX Power Supply Rejection Ratio ±PSRR −85 −100 dB AD8065WARTZ only: T − T −85 dB MIN MAX Rev. J | Page 5 of 28 AD8065/AD8066 SPECIFICATIONS ±12 V @ TA = 25°C, VS = ±12 V, RL = 1 kΩ, unless otherwise noted. Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p (AD8065) 100 145 MHz O G = +1, VO = 0.2 V p-p (AD8066) 100 115 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, VO = 2 V p-p 40 MHz Bandwidth for 0.1 dB Flatness G = +2, V = 0.2 V p-p 7 MHz O Input Overdrive Recovery G = +1, −12.5 V to +12.5 V 175 ns Output Overdrive Recovery G = −1, −12.5 V to +12.5 V 170 ns Slew Rate G = +2, VO = 4 V step 130 180 V/μs Settling Time to 0.1% G = +2, VO = 2 V step 55 ns G = +2, V = 10 V step 250 ns O NOISE/HARMONIC PERFORMANCE SFDR fC = 1 MHz, G = +2, VO = 2 V p-p −100 dBc f = 5 MHz, G = +2, V = 2 V p-p −67 dBc C O f = 1 MHz, G = +2, V = 10 V p-p −85 dBc C O Third-Order Intercept f = 10 MHz, R = 100 Ω 24 dBm C L Input Voltage Noise f = 10 kHz 7 nV/√Hz Input Current Noise f = 10 kHz 1 fA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.04 % Differential Phase Error NTSC, G = +2, R = 150 Ω 0.03 Degrees L DC PERFORMANCE Input Offset Voltage V = 0 V, SOIC package 0.4 1.5 mV CM Input Offset Voltage Drift 1 17 μV/°C Input Bias Current SOIC package 3 7 pA TMIN to TMAX 25 pA Input Offset Current 2 10 pA TMIN to TMAX 2 pA Open-Loop Gain V = ±10 V, R = 1 kΩ 103 114 dB O L INPUT CHARACTERISTICS Common-Mode Input Impedance 1000 || 2.1 GΩ || pF Differential Input Impedance 1000 || 4.5 GΩ || pF Input Common-Mode Voltage Range FET Input Range −12 to +8.5 −12.0 to +9.5 V Common-Mode Rejection Ratio VCM = −1 V to +1 V −85 −100 dB VCM = −1 V to +1 V (SOT-23) −82 −91 dB OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ −11.8 to +11.8 −11.9 to +11.9 V RL = 350 Ω −11.25 to +11.5 V Output Current V = 22 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 30 mA O Short-Circuit Current 120 mA Capacitive Load Drive 30% overshoot G = +1 25 pF POWER SUPPLY Operating Range 5 24 V Quiescent Current per Amplifier 6.6 7.4 mA Power Supply Rejection Ratio ±PSRR −84 −93 dB Rev. J | Page 6 of 28 AD8065/AD8066 SPECIFICATIONS +5 V @ TA = 25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted. Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p (AD8065) 125 155 MHz O AD8065WARTZ only: TMIN − TMAX 90 MHz G = +1, VO = 0.2 V p-p (AD8066) 110 130 MHz G = +2, VO = 0.2 V p-p 50 MHz G = +2, V = 2 V p-p 43 MHz O Bandwidth for 0.1 dB Flatness G = +2, V = 0.2 V p-p 6 MHz O Input Overdrive Recovery Time G = +1, −0.5 V to +5.5 V 175 ns Output Recovery Time G = −1, −0.5 V to +5.5 V 170 ns Slew Rate G = +2, VO = 2 V step 105 160 V/μs AD8065WARTZ only: T − T 123 V/μs MIN MAX Settling Time to 0.1% G = +2, V = 2 V step 60 ns O NOISE/HARMONIC PERFORMANCE SFDR f = 1 MHz, G = +2, V = 2 V p-p −65 dBc C O f = 5 MHz, G = +2, V = 2 V p-p −50 dBc C O Third-Order Intercept f = 10 MHz, R = 100 Ω 22 dBm C L Input Voltage Noise f = 10 kHz 7 nV/√Hz Input Current Noise f = 10 kHz 0.6 fA/√Hz Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.13 % Differential Phase Error NTSC, G = +2, R = 150 Ω 0.16 Degrees L DC PERFORMANCE Input Offset Voltage V = 1.0 V, SOIC package 0.4 1.5 mV CM AD8065WARTZ only: T − T 2.6 mV MIN MAX Input Offset Voltage Drift 1 17 μV/ºC AD8065WARTZ only: TMIN − TMAX 17 μV/ºC Input Bias Current SOIC package 1 5 pA TMIN to TMAX 25 125 pA Input Offset Current 1 5 pA T to T 1 125 pA MIN MAX Open-Loop Gain V = 1 V to 4 V (AD8065) 100 113 dB O AD8065WARTZ only: TMIN − TMAX 100 dB VO = 1 V to 4 V (AD8066) 90 103 dB INPUT CHARACTERISTICS Common-Mode Input Impedance 1000 || 2.1 GΩ || pF Differential Input Impedance 1000 || 4.5 GΩ || pF Input Common-Mode Voltage Range FET Input Range 0 to 1.7 0 to 2.4 V AD8065WARTZ only: TMIN − TMAX 0 to 1.7 V Common-Mode Rejection Ratio VCM = 0.5 V to 1.5 V −74 −100 dB VCM = 1 V to 2 V (SOT-23) −78 −91 dB AD8065WARTZ only: T -T −76 dB MIN MAX OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ 0.1 to 4.85 0.03 to 4.95 V AD8065WARTZ only: T − T 0.1 to 4.85 V MIN MAX R = 150 Ω 0.07 to 4.83 V L Output Current V = 4 V p-p, SFDR ≥ −60 dBc, f = 500 kHz 35 mA O Short-Circuit Current 75 mA Capacitive Load Drive 30% overshoot G = +1 5 pF Rev. J | Page 7 of 28 AD8065/AD8066 Parameter Conditions Min Typ Max Unit POWER SUPPLY Operating Range 5 24 V AD8065WARTZ only: TMIN − TMAX 5 10 V Quiescent Current per Amplifier 5.8 6.4 7.0 mA AD8065WARTZ only: T − T 7.0 mA MIN MAX Power Supply Rejection Ratio ±PSRR −78 −100 dB AD8065WARTZ only: TMIN − TMAX −78 dB Rev. J | Page 8 of 28 AD8065/AD8066 ABSOLUTE MAXIMUM RATINGS RMS output voltages should be considered. If RL is referenced to Table 4. VS−, as in single-supply operation, then the total drive power is Parameter Rating VS × IOUT. Supply Voltage 26.4 V Power Dissipation See Figure 3 If the rms signal levels are indeterminate, then consider the Common-Mode Input Voltage V − 0.5 V to V + 0.5 V EE CC worst case, when VOUT = VS/4 for RL to midsupply. Differential Input Voltage 1.8 V 2 () V /4 S Storage Temperature Range −65°C to +125°C P =() V ×I + D S S R L Operating Temperature Range −40°C to +85°C AD8065WARTZ Only −40°C to +105°C In single-supply operation with R referenced to V −, worst case L S Lead Temperature 300°C is V = V /2. OUT S (Soldering, 10 sec) 2.0 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress 1.5 rating only; functional operation of the device at these or any MSOP-8 other conditions above those indicated in the operational SOIC-8 section of this specification is not implied. Exposure to absolute 1.0 maximum rating conditions for extended periods may affect SOT-23-5 device reliability. MAXIMUM POWER DISSIPATION 0.5 The maximum safe power dissipation in the AD8065/AD8066 packages is limited by the associated rise in junction temperature 0 (TJ) on the die. The plastic encapsulating the die locally reaches –60 –40 –20 0 20 40 60 80 100 the junction temperature. At approximately 150°C, which is the AMBIENT TEMPERATURE (°C) glass transition temperature, the plastic changes its properties. Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board Even temporarily exceeding this temperature limit can change Airflow increases heat dissipation, effectively reducing θJA. Also, the stresses that the package exerts on the die, permanently more metal directly in contact with the package leads from shifting the parametric performance of the AD8065/AD8066. metal traces, through holes, ground, and power planes reduce Exceeding a junction temperature of 175°C for an extended the θ . Care must be taken to minimize parasitic capacitances JA time can result in changes in the silicon devices, potentially at the input leads of high speed op amps as discussed in the causing failure. Layout, Grounding, and Bypassing Considerations section. The still air thermal properties of the package and PCB (θ ), JA Figure 3 shows the maximum safe power dissipation in the ambient temperature (T ), and total power dissipated in the A package vs. the ambient temperature for the SOIC (125°C/W), package (P ) determine the junction temperature of the die. D SOT-23 (180°C/W), and MSOP (150°C/W) packages on a The junction temperature can be calculated by JEDEC standard 4-layer board. θJA values are approximations. TJ = TA + (PD × θJA) OUTPUT SHORT CIRCUIT The power dissipated in the package (PD) is the sum of the Shorting the output to ground or drawing excessive current for quiescent power dissipation and the power dissipated in the the AD8065/AD8066 will likely cause catastrophic failure. package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V ) times the S quiescent current (I ). Assuming the load (R ) is referenced to S L ESD CAUTION midsupply, then the total drive power is V /2 × I , some of S OUT which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. P =QuiescentPower + (TotalDrivePower −LoadPower) D 2 V V VOUT ⎛ ⎞ S OUT P =() V ×I + × − ⎜ ⎟ D S S 2 R R ⎝ L ⎠ L Rev. J | Page 9 of 28 MAXIMUM POWER DISSIPATION (W) 02916-E-003 AD8065/AD8066 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ±5 V, CL = 5 pF, RL = 1 kΩ, VOUT = 2 V p-p, Temperature = 25°C. 24 6.9 R = 150Ω L 21 G = +10 6.8 G = +2 V = 200mV p-p V = 0.2V p-p O OUT 18 6.7 V = 0.7V p-p OUT G = +5 15 6.6 V = 1.4V p-p OUT 12 6.5 9 6.4 G = +2 6 6.3 3 6.2 G = +1 0 6.1 –3 6.0 –6 5.9 0.1 1 10 100 1000 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response for Various Gains Figure 7. 0.1 dB Flatness Frequency Response (See Figure 43) 6 9 V = 200mV p-p V = 200mV p-p O O G = +1 G = +2 4 8 V = +5V S V = +5V S 2 7 V = ±5V S V = ±5V S 0 6 V = ±12V S V = ±12V S –2 5 –4 4 –6 3 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response for Various Supplies Figure 8. Small Signal Frequency Response for Various Supplies (See Figure 42) (See Figure 43) 8 2 V = 2V p-p O V = 2V p-p O G = +2 G = +1 7 V = +5V 1 S V = ±5V S 6 0 V = ±12V S V = ±5V S 5 –1 4 V = ±12V –2 S 3 –3 2 –4 1 0 –5 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Large Signal Frequency Response for Various Supplies Figure 6. Large Signal Frequency Response for Various Supplies (See Figure 43) (See Figure 42) Rev. J | Page 10 of 28 GAIN (dB) GAIN (dB) GAIN (dB) 02916-E-006 02916-E-005 02916-E-004 GAIN (dB) GAIN (dB) GAIN (dB) 02916-009 02916-E-008 02916-E-007 AD8065/AD8066 9 8 V = 200mV p-p O C = 25pF L G = +1 R = 20Ω 6 SNUB 6 C = 25pF C = 55pF L L C = 5pF L 4 C = 20pF C = 25pF L L 3 2 0 0 C = 5pF L –2 –3 –4 –6 V = 200mV p-p O –6 G = +2 –9 –8 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Small Signal Frequency Response for Various CLOAD (See Figure 42) Figure 13. Small Signal Frequency Response for Various CLOAD (See Figure 43) 8 8 V = 0.2V p-p OUT R = 100Ω 6 7 L V = 2V p-p G = +2 OUT 4 6 R = 1kΩ L 2 5 V = 4V p-p OUT 0 4 –2 3 –4 2 V = 200mV p-p O –6 1 G = +2 –8 0 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 11. Frequency Response for Various Output Amplitudes Figure 14. Small Signal Frequency Response for Various R (See Figure 43) LOAD (See Figure 43) 80 120 14 V = 200mV p-p O 12 G = +2 PHASE 60 60 R = R = 1kΩ, 10 F G R = 500Ω S 8 R = R = 500Ω, F G 40 0 R = 250Ω S 6 GAIN = R = 500Ω, R F G 4 R = 250Ω, S –60 20 R = R = 1kΩ, F G C = 2.2pF F R = 500Ω, S 2 C = 3.3pF F 0 0 –120 –2 –20 –180 –4 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Small Signal Frequency Response for Various R /C (See Figure 43) Figure 15. Open-Loop Response F F Rev. J | Page 11 of 28 GAIN (dB) GAIN (dB) GAIN (dB) 02916-E-012 02916-E-011 02916-E-010 OPEN-LOOP GAIN (dB) GAIN (dB) GAIN (dB) PHASE (DEGREES) 02916-E-015 02916-E-014 02916-E-013 AD8065/AD8066 –40 –30 –40 G = +2 –50 –50 –60 HD2 G = +2 –60 HD3 G = +2 –70 –70 HD2 R = 150Ω L HD2 R = 1kΩ HD2 G = +1 L –80 –80 HD3 R = 1kΩ L –90 –90 HD3 R = 150Ω L HD3 G = +1 –100 –100 –110 –110 –120 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Harmonic Distortion vs. Frequency for Various Loads Figure 19. Harmonic Distortion vs. Frequency for Various Gains (See Figure 42 and Figure 43) (See Figure 43) –20 –30 V = ±12V S –30 –40 G = +2 G = +2 HD2 V = 20V p-p V = ±12V O S –40 F = 1MHz –50 HD3 V = 20V p-p –50 O –60 –60 HD2 V = 10V p-p HD2 R = 150Ω –70 L O –70 HD3 R = 150Ω L –80 HD3 V = 10V p-p –80 O –90 HD2 R = 300Ω –90 L –100 –100 HD2 V = 2V p-p O HD3 R = 300Ω L –110 HD3 V = 2V p-p –110 O –120 –120 0.1 1.0 10.0 01234 5 6 789 10 11 12 13 14 15 OUTPUT AMPLITUDE (V p-p) FREQUENCY (MHz) Figure 17. Harmonic Distortion vs. Amplitude for Various Loads VS = ±12 V Figure 20. Harmonic Distortion vs. Frequency for Various Amplitudes (See Figure 43) (See Figure 43) 50 100 R = 100Ω L V = ±12V 45 S 40 V = ±5V S 35 10 30 V = +5V S 25 20 1 15 10 100 1k 10k 100k 1M 10M 100M 1G 110 FREQUENCY (Hz) FREQUENCY (MHz) Figure 21. Voltage Noise Figure 18. Third-Order Intercept vs. Frequency and Supply Voltage Rev. J | Page 12 of 28 INTERCEPT POINT (dBm) DISTORTION (dBc) DISTORTION (dBc) 02916-E-018 02916-E-017 02916-E-016 NOISE (nV/ Hz) DISTORTION (dBc) DISTORTION (dBc) 02916-E-020 02916-E-019 02916-E-021 AD8065/AD8066 G = +1 C = 20pF G = +1 L C = 5pF L 25ns/DIV 50mV/DIV 50mV/DIV 25ns/DIV Figure 22. Small Signal Transient Response 5 V Supply (See Figure 42) Figure 25. Small Signal Transient Response ±5 V (See Figure 42) G = +1 G = +2 5µs V = 10V p-p V = ±12V OUT S V = ±12V S V = 10V p-p OUT V = 4V p-p OUT V = 2V p-p OUT V = 2V p-p OUT 50ns/DIV 2V/DIV 50ns/DIV 2V/DIV Figure 23. Large Signal Transient Response (See Figure 42) Figure 26. Large Signal Transient Response (See Figure 43) G = –1 G = +1 V = ±5V S V = ±5V S 2.0V/DIV 100ns/DIV 2.0V/DIV 100ns/DIV Figure 24. Output Overdrive Recovery (See Figure 44) Figure 27. Input Overdrive Recovery (See Figure 42) Rev. J | Page 13 of 28 02916-024 02916-023 02916-022 02916-027 02916-026 02916-025 AD8065/AD8066 V = 140mV/DIV IN V = 500mV/DIV IN V – 2V OUT IN +0.1% +0.1% –0.1% –0.1% t = 0 t = 0 V – 2V OUT IN 2mV/DIV 10ns/DIV 2mV/DIV 64μs/DIV Figure 28. Long-Term Settling Time (See Figure 49) Figure 31. 0.1% Short-Term Settling Time (See Figure 49) 0 42 +I 36 b 30 24 –5 –I b –I 18 b 12 6 –10 0 10 –15 5 –I b +I 0 b –5 –20 +I b –10 –15 –25 –20 –25 –30 –30 25 35 45 55 65 75 85 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 TEMPERATURE (°C) COMMON-MODE VOLTAGE (V) Figure 29. Input Bias Current vs. Temperature Figure 32. Input Bias Current vs. Common-Mode Voltage Range (See the Input and Output Overload Behavior Section) 0.3 40 N = 299 SD = 0.388 35 0.2 MEAN = –0.069 30 0.1 25 V = +5V S V = ±5V 0 S 20 15 –0.1 V = ±12V S 10 –0.2 5 –0.3 0 –14–12 –10 –8–6–4 –2 0 2 4 6 8 10 12 14 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 COMMON-MODE VOLTAGE (V) INPUT OFFSET VOLTAGE (mV) Figure 30. Input Offset Voltage vs. Common-Mode Voltage Figure 33. Input Offset Voltage Rev. J | Page 14 of 28 OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (pA) 02916-E-030 02916-E-029 02916-E-028 I (pA) I (μA) b b FET INPUT STAGE BJT INPUT STAGE 02916-E-033 02916-E-032 02916-E-031 AD8065/AD8066 –30 100 –40 10 –50 1 G = +1 –60 G = +2 –70 V = ±12V S 0.1 –80 0.01 –90 V = ±5V S –100 0 100 1k 10k 100k 1M 10M 100M 0.1 1 10 100 FREQUENCY (Hz) FREQUENCY (MHz) Figure 34. CMRR vs. Frequency (See Figure 46) Figure 37. Output Impedance vs. Frequency (See Figure 45 and Figure 47) 0.30 80 0.25 70 V – V CC OH V – V CC OH 0.20 60 0.15 50 V – V OL EE 0.10 V – V OL EE 40 0.05 30 0 02 1003040 25 35 45 55 65 75 85 TEMPERATURE (°C) I (mA) LOAD Figure 38. Output Saturation Voltage vs. Temperature Figure 35. Output Saturation Voltage vs. Output Load Current 0 0 V = 2V p-p IN –10 –10 G = +1 –20 –20 –PSRR –30 –30 –40 +PSRR –40 –50 –50 –60 –60 B TO A –70 –70 –80 A TO B –80 –90 –100 –90 0.01 0.1 1 10 100 1000 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 36. PSRR vs. Frequency (See Figure 48 and Figure 50) Figure 39. Crosstalk vs. Frequency (See Figure 51) Rev. J | Page 15 of 28 PSRR (dB) OUTPUT SATURATION VOLTAGE (V) CMRR (dB) 02916-E-036 02916-E-035 02916-E-034 CROSSTALK (dB) OUTPUT SATURATION VOLTAGE (mV) OUTPUT IMPEDANCE (Ω) 02916-E-039 02916-E-038 02916-E-037 AD8065/AD8066 6.60 125 V = ±12V S 120 6.55 V = ±5V S 115 V = ±12V S 6.50 110 6.45 105 V = +5V S 100 6.40 V = +5V S 95 6.35 V = ±5V S 90 6.30 85 6.25 80 –40 –20 020 40 60 80 02 1003040 TEMPERATURE (°C) I (mA) LOAD Figure 40. Quiescent Supply Current vs. Temperature for Various Figure 41. Open-Loop Gain vs. Load Current for Various Supply Voltages Supply Voltages Rev. J | Page 16 of 28 SUPPLY CURRENT (mA) 02916-E-040 OPEN-LOOP GAIN (dB) 02916-E-041 AD8065/AD8066 TEST CIRCUITS SOIC-8 Pinout +V +V CC CC 4.7μF 4.7μF 0.1μF 0.1μF 2.2pF 24.9Ω 499Ω 499Ω V IN 49.9Ω FET PROBE FET PROBE R SNUB AD8065 AD8065 V IN 249Ω 1kΩ C LOAD 1kΩ 49.9Ω 0.1μF 0.1μF 4.7μF 4.7μF –V –V EE EE Figure 44. G = −1 Figure 42. G = +1 +V +V CC CC 4.7μF 4.7μF 0.1μF 0.1μF 2.2pF 24.9Ω 499Ω 499Ω FET PROBE R SNUB AD8065 AD8065 V NETWORK ANALYZER S22 IN 249Ω C 1kΩ LOAD 0.1μF 49.9Ω 0.1μF 4.7μF 4.7μF –V EE –V EE Figure 43. G = +2 Figure 45. Output Impedance G = +1 Rev. J | Page 17 of 28 02916-E-042 02916-E-043 02916-E-045 02916-E-044 AD8065/AD8066 +V CC V IN 4.7μF 1V p-p +V CC 49.9Ω 0.1μF 24.9Ω 499Ω 499Ω V IN FET PROBE FET PROBE AD8065 AD8065 49.9Ω 499Ω 1kΩ 1kΩ 0.1μF 499Ω 0.1μF 4.7μF 4.7μF –V EE –V EE Figure 46. CMRR Figure 48. Positive PSRR +V +V CC CC 4.7μF 4.7μF 0.1μF 0.1μF 2.2pF 499Ω 499Ω 499Ω 499Ω AD8065 249Ω NETWORK ANALYZER 976Ω TO SCOPE S22 AD8065 249Ω V 0.1μF IN 49.9Ω 0.1μF 49.9Ω 4.7μF 4.7μF –V EE –V EE Figure 49. Settling Time Figure 47. Output Impedance G = +2 Rev. J | Page 18 of 28 02916-E-047 02916-E-046 02916-E-048 02916-E-049 AD8065/AD8066 2.2pF +V CC 4.7μF 499Ω 499Ω 0.1μF 5V 4.7μF 1.5V 24.9Ω 0.1μF FET PROBE AD8065 FET PROBE 249Ω V IN AD8065 1kΩ 49.9Ω 1kΩ 49.9Ω 1.5V 1.5V V IN 1V p-p –V EE Figure 50. Negative PSRR Figure 52. Single Supply 24.9Ω FET PROBE 24.9Ω AD8066 +5V 4.7μF 1kΩ 0.1μF RECEIVE SIDE AD8066 V IN 0.1μF 1kΩ 49.9Ω 4.7μF –5V DRIVE SIDE Figure 51. Crosstalk—AD8066 Rev. J | Page 19 of 28 02916-E-050 02916-E-051 02916-E-052 AD8065/AD8066 THEORY OF OPERATION The AD8065/AD8066 are voltage feedback operational amplifiers NONINVERTING CLOSED-LOOP FREQUENCY that combine a laser-trimmed JFET input stage with the Analog RESPONSE Devices eXtra Fast Complementary Bipolar (XFCB) process, Solving for the transfer function resulting in an outstanding combination of precision and speed. 2π × f () R +R V crossover G F The supply voltage range is from 5 V to 24 V. The amplifiers feature O = () V R +R s + 2π × f ×R a patented rail-to-rail output stage capable of driving within 0.5 V crossover I F G G of either power supply while sourcing or sinking up to 30 mA. where fcrossover is the frequency where the amplifier’s open-loop Also featured is a single-supply input stage that handles common- gain equals 0 db mode signals from below the negative supply to within 3 V of the V R +R O F G positive rail. Operation beyond the JFET input range is possible At dc = V R I G because of an auxiliary bipolar input stage that functions with input voltages up to the positive supply. The amplifiers operate as Closed-loop −3 dB frequency if they have a rail-to-rail input and exhibit no phase reversal R G behavior for common-mode voltages within the power supply. f = f × −3dB crossover R +R F G With voltage noise of 7 nV/√Hz and −88 dBc distortion for INVERTING CLOSED-LOOP FREQUENCY 1 MHz, 2 V p-p signals, the AD8065/AD8066 are a great choice RESPONSE for high resolution data acquisition systems. Their low noise, sub-pA input current, precision offset, and high speed make −2π × f ×R V crossover F O = them superb preamps for fast photodiode applications. The V s() R +R + 2π × f ×R I F G crossover G speed and output drive capability of the AD8065/AD8066 also V R O F make them useful in video applications. At dc = − V R I G CLOSED-LOOP FREQUENCY RESPONSE Closed-loop −3 dB frequency The AD8065/AD8066 are classic voltage feedback amplifiers R with an open-loop frequency response that can be approximated as G f = f × −3dB crossover R +R the integrator response shown in Figure 53. Basic closed-loop F G frequency response for inverting and noninverting configurations can be derived from the schematics shown. R R F F R R G V G I V V O O V V A A E E V I 80 A = (2π× f )/s crossover 60 40 f = 65MHz crossover 20 0 0.01 0.1 1 10 100 FREQUENCY (MHz) Figure 53. Open-Loop Gain vs. Frequency and Basic Connections Rev. J | Page 20 of 28 OPEN-LOOP GAIN (A) (dB) 02916-E-053 AD8065/AD8066 The closed-loop bandwidth is inversely proportional to the noise Actual distortion performance depends on a number of gain of the op amp circuit, (R + R )/R . This simple model is variables: F G G accurate for noise gains above 2. The actual bandwidth of circuits • The closed-loop gain of the application with noise gains at or below 2 is higher than those predicted • Whether it is inverting or noninverting with this model due to the influence of other poles in the • Amplifier loading frequency response of the real op amp. • Signal frequency and amplitude R F • Board layout +V – Also see Figure 16 to Figure 20. The lowest distortion is obtained OS R G with the AD8065 used in low gain inverting applications, V O I A b– because this eliminates common-mode effects. Higher closed- R S V I loop gains result in worse distortion performance. I b+ INPUT PROTECTION The inputs of the AD8065/AD8066 are protected with back-to- Figure 54. Voltage Feedback Amplifier DC Errors back diodes between the input terminals as well as ESD diodes Figure 54 shows a voltage feedback amplifier’s dc errors. For to either power supply. This results in an input stage with picoamps both inverting and noninverting configurations of input current that can withstand up to 1500 V ESD events (human body model) with no degradation. R +R R +R ⎛ ⎞ ⎛ ⎞ G F G F V() error =I ×R −I ×R +V ⎜ ⎟ ⎜ ⎟ O b+ S b− F OS Excessive power dissipation through the protection devices R R G G ⎝ ⎠ ⎝ ⎠ destroys or degrades the performance of the amplifier. Differ- The voltage error due to Ib+ and Ib– is minimized if RS = RF || RG ential voltages greater than 0.7 V result in an input current of (though with the AD8065 input currents at typically less than approximately (|V − V | 0.7 V)/R , where R is the resistance in + − I I 20 pA over temperature, this is likely not a concern). To include series with the inputs. common-mode and power supply rejection effects, total V can be OS For input voltages beyond the positive supply, the input current modeled is approximately (VI − VCC − 0.7)/RI. Beyond the negative supply, ΔV ΔV S CM the input current is about (VI − VEE + 0.7)/RI. If the inputs of the V =V + + OS OS nom PSR CMR amplifier are to be subjected to sustained differential voltages greater than 0.7 V, or to input voltages beyond the amplifier V is the offset voltage specified at nominal conditions, OSnom power supply, input current should be limited to 30 mA by an ΔVS is the change in power supply from nominal conditions, appropriately sized input resistor (R ), as shown in Figure 55. I PSR is the power supply rejection, ΔVCM is the change in common- (V –V – 0.7V) mode voltage from nominal conditions, and CMR is the common- (| V –V | – 0.7V) I EE + – R > R > I I 30mA 30mA mode rejection. (V –V + 0.7V) I EE FOR LARGE | V –V | + – R > I WIDEBAND OPERATION 30mA FOR V BEYOND AD8065 I R Figure 42 through Figure 44 show the circuits used for wideband SUPPLY VOLTAGES I V I V O characterization for gains of +1, +2, and −1. Source impedance at the summing junction (R || R ) forms a pole in the amplifier’s loop F G response with the amplifier’s input capacitance of 6.6 pF. This can cause peaking and ringing if the time constant formed is too Figure 55. Current-Limiting Resistor low. Feedback resistances of 300 Ω to 1 kΩ are recommended, because they do not unduly load down the amplifier, and the time constant formed will not be too low. Peaking in the frequency response can be compensated for with a small capacitor (C ) in parallel with the feedback resistor, as F illustrated in Figure 12. This shows the effect of different feedback capacitances on the peaking and bandwidth for a noninverting G = +2 amplifier. For the best settling times and the best distortion, the impedances at the AD8065/AD8066 input terminals should be matched. This minimizes nonlinear common-mode capacitive effects that can degrade ac performance. Rev. J | Page 21 of 28 02916-E-054 02916-E-055 AD8065/AD8066 THERMAL CONSIDERATIONS INPUT AND OUTPUT OVERLOAD BEHAVIOR With 24 V power supplies and 6.5 mA quiescent current, the A simplified schematic of the AD8065/AD8066 input stage is AD8065 dissipates 156 mW with no load. The AD8066 dissipates shown in Figure 56. This shows the cascoded N-channel JFET 312 mW. This can lead to noticeable thermal effects, especially input pair, the ESD and other protection diodes, and the in the small SOT-23-5 (thermal resistance of 160°C/W). V auxiliary NPN input stage that eliminates any phase inversion OS temperature drift is trimmed to guarantee a maximum drift of behavior. When the common-mode input voltage to the amplifier 17 μV/°C, so it can change up to 0.425 mV due to warm-up is driven to within approximately 3 V of the positive power supply, effects for an AD8065/AD8066 in a SOT-23-5 package on 24 V. the input JFET’s bias current turns off and the bias of the NPN pair turns on, taking over control of the amplifier. The NPN Ib increases by a factor of 1.7 for every 10°C rise in temperature. differential pair now sets the amplifier’s offset, and the input Ib is close to five times higher at 24 V supplies as opposed to a bias current is now in the range of several tens of microamps. single 5 V supply. This behavior is shown in Figure 32. Normal operation resumes Heavy loads increase power dissipation and raise the chip when the common-mode voltage goes below the 3 V from the junction temperature as described in the Maximum Power positive supply threshold. Dissipation section. Care should be taken not to exceed the The output transistors of the rail-to-rail output stage have rated power dissipation of the package. circuitry to limit the extent of their saturation when the output is overdriven. This helps output recovery time. Output recovery from a 0.5 V output overdrive on a ±5 V supply is shown in Figure 24. V CC R1 R5 TO REST OF AMP Q2 Q5 V THRESHOLD VBIAS D1 R6 R3 Q1 Q6 D2 V N V D3 D4 P Q3 Q4 S S R4 R7 R2 R8 Q7 I I T1 T2 –V EE Figure 56. Simplified Input Stage Rev. J | Page 22 of 28 02916-E-056 AD8065/AD8066 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS inputs and surrounding area to set up any leakage currents. POWER SUPPLY BYPASSING For the guard ring to be completely effective, it must be driven Power supply pins are actually inputs and care must be taken so by a relatively low impedance source and should completely that a noise-free stable dc voltage is applied. The purpose of bypass surround the input leads on all sides, above and below, using capacitors is to create low impedances from the supply to ground at a multilayer board. all frequencies, thereby shunting or filtering most of the noise. Another effect that can cause leakage currents is the charge Decoupling schemes are designed to minimize the bypassing absorption of the insulator material itself. Minimizing the impedance at all frequencies with a parallel combination of amount of material between the input leads and the guard ring capacitors. 0.1 μF (X7R or NPO) chip capacitors are critical helps to reduce the absorption. Also, low absorption materials, and should be as close as possible to the amplifier package. such as Teflon® or ceramic, could be necessary in some instances. The 4.7 μF tantalum capacitor is less critical for high frequency INPUT CAPACITANCE bypassing, and, in most cases, only one is needed per board at the supply inputs. Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. GROUNDING A few pF of capacitance reduces the input impedance at high A ground plane layer is important in densely packed PC boards frequencies, in turn increasing the amplifier’s gain, causing peaking to spread the current minimizing parasitic inductances. However, of the frequency response or even oscillations, if severe enough. an understanding of where the current flows in a circuit is critical It is recommended that the external passive components connected to implementing effective high speed circuit design. The length to the input pins be placed as close as possible to the inputs to of the current path is directly proportional to the magnitude of avoid parasitic capacitance. The ground and power planes must parasitic inductances and, therefore, the high frequency impedance be kept at a small distance from the input pins on all layers of of the path. High speed currents in an inductive ground return the board. create unwanted voltage noise. OUTPUT CAPACITANCE The length of the high frequency bypass capacitor leads is most To a lesser extent, parasitic capacitances on the output can cause critical. A parasitic inductance in the bypass grounding works peaking and ringing of the frequency response. There are two against the low impedance created by the bypass capacitor. Place methods to effectively minimize their effect: the ground leads of the bypass capacitors at the same physical location. Because load currents flow from the supplies as well, • As shown in Figure 57, put a small value resistor (RS) in the ground for the load impedance should be at the same physical series with the output to isolate the load capacitor from the location as the bypass capacitor grounds. For the larger value amp’s output stage. A good value to choose is 20 Ω (see capacitors, which are effective at lower frequencies, the current Figure 10). return path distance is less critical. • Increase the phase margin with higher noise gains or add a pole with a parallel resistor and capacitor from −IN to LEAKAGE CURRENTS the output. Poor PC board layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the AD8065/AD8066. Any voltage differential between the inputs and nearby runs sets up leakage R = 20Ω S V currents through the PC board insulator, for example, 1 V/100 GΩ AD8065 O C = 10 pA. Similarly, any contaminants on the board can create V L I significant leakage (skin oils are a common problem). To reduce leakage significantly, put a guard ring (shield) around the inputs Figure 57. Output Isolation Resistor and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the Rev. J | Page 23 of 28 02916-E-057 AD8065/AD8066 C F R F 11 C I R = 10 Ω PHOTO SH M C S C D C V M O V B C +C F S R F Figure 58. Wideband Photodiode Preamp The frequency response in this case shows about 2 dB of INPUT-TO-OUTPUT COUPLING peaking and 15% overshoot. Doubling C and cutting the F To minimize capacitive coupling between the inputs and output, bandwidth in half results in a flat frequency response with the output signal traces should not be parallel with the inputs. about 5% transient overshoot. WIDEBAND PHOTODIODE PREAMP The preamp’s output noise over frequency is shown in Figure 59. Figure 58 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is 1 f = 1 2πR (C +C +C +2C ) F F S M D I ×R PHOTO F V = OUT 1 1+sC R F F f = 2 2πR C F F f where IPHOTO is the output current of the photodiode, and the CR f = 3 (C +C +2C +C )/C S M D F F parallel combination of RF and CF sets the signal bandwidth. The stable bandwidth attainable with this preamp is a function R NOISE F of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier’s summing junction, including C S f f 2 3 VEN (C +C +C + 2C )/C F S M D F and the amplifier input capacitance. R and the total capacitance F produce a pole in the amplifier’s loop transmission that can f 1 creates a 0 in the result in peaking and instability. Adding CF VEN NOISE DUE TO AMPLIFIER loop transmission that compensates for the pole’s effect and FREQUENCY (Hz) reduces the signal bandwidth. It can be shown that the signal Figure 59. Photodiode Voltage Noise Contributions bandwidth resulting in a 45° phase margin (f(45)) is defined by f The pole in the loop transmission translates to a 0 in the CR f = () 45 amplifier’s noise gain, leading to an amplification of the input 2π ×R ×C F S voltage noise over frequency. The loop transmission 0 where f is the amplifier crossover frequency, R is the feedback CR F introduced by CF limits the amplification. The noise gain resistor, and C is the total capacitance at the amplifier summing S bandwidth extends past the preamp signal bandwidth and is junction (amplifier + photodiode + board parasitics). eventually rolled off by the decreasing loop gain of the The value of CF that produces f(45) can be shown to be amplifier. Keeping the input terminal impedances matched is recommended to eliminate common-mode noise peaking C S effects, which adds to the output noise. C = F 2π ×R × f F CR Integrating the square of the output voltage noise spectral density over frequency and then taking the square root allows users to obtain the total rms output noise of the preamp. Table 5 summarizes approximations for the amplifier and feedback and source resistances. Noise components for an example preamp with R = 50 kΩ, C = 15 pF, and C = 2 pF (bandwidth of about F S F 1.6 MHz) are also listed. Rev. J | Page 24 of 28 VOLTAGE NOISE (nV/ Hz) 02916-E-058 02916-E-059 AD8065/AD8066 Table 5. RMS Noise Contributions of Photodiode Preamp Contributor Expression RMS Noise with R = 50 kΩ, C = 15 pF, C = 2 pF F S F RF (×2) 64.5 μV 2 × 4kT ×R × f ×1.57 F 2 Amp to f1 2.4 μV VEN × f 1 Amp (f2 – f1) 31 μV C +C +C + 2C M F D S VEN × × f − f 2 1 C F Amp to (past f2) 260 μV C +C + 2C +C S M D F VEN × × f ×1.57 3 C F 270 μV (Total) V CC 4.7μF 0.1μF R S1 1 / 2 V N 2.2pF AD8066 4.7μF R2 0.1μF 500Ω V V CC EE 4.7μF 0.1μF R1 500Ω R = 500Ω F V O AD8065 R G 4.7μ F 0.1μ F R3 R = 500Ω V F 500Ω EE V CC 4.7μF 0.1μF R4 500Ω 2.2pF 1 / 2 AD8066 R S2 V P 4.7μF 0.1μ F V EE Figure 60. High Speed Instrumentation Amplifier Common-mode rejection of the in-amp is primarily HIGH SPEED JFET INPUT INSTRUMENTATION determined by the match of the resistor ratios R1:R2 to R3:R4. AMPLIFIER It can be estimated Figure 60 shows an example of a high speed instrumentation V () δ1− δ2 O amplifier with high input impedance using the = V () 1+ δ1 δ2 AD8065/AD8066. The dc transfer function is CM The summing junction impedance for the preamps is equal to ⎛ ⎞ 1000 ⎜ ⎟ () V = V −V 1+ OUT N P R || 0.5(R ). This is the value to be used for matching purposes. F G ⎜ ⎟ R G ⎝ ⎠ For G = +1, it is recommended that the feedback resistors for the two preamps be set to a low value (for instance 50 Ω for 50 Ω source impedance). The bandwidth for G = +1 is 50 MHz. For higher gains, the bandwidth is set by the preamp, equaling Inamp = (f ×R )/ (2 ×R ) −3dB CR G F Rev. J | Page 25 of 28 02916-E-060 AD8065/AD8066 +V S VIDEO BUFFER The output current capability and speed of the AD8065 make it 0.1μ F 4.7μ F 249Ω useful as a video buffer, shown in Figure 61. 75Ω + AD8065 V The G = +2 configuration compensates for the voltage division I + – V 75Ω O of the signal due to the signal termination. This buffer maintains – 0.1μ F 4.7μ F 0.1 dB flatness for signals up to 7 MHz, from low amplitudes up to 2 V p-p (see Figure 7). Differential gain and phase have been –V S 2.2pF measured to be 0.02% and 0.028°, respectively, at ±5 V supplies. 499Ω 499Ω Figure 61. Video Buffer Rev. J | Page 26 of 28 02916-E-061 AD8065/AD8066 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 62. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.00 2.90 2.80 5 4 3.00 1.70 2.80 1.60 2.60 1.50 12 3 0.95 BSC 1.90 BSC 1.30 1.15 0.90 0.20 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.55 0.15 MAX 10° 0.45 SEATING 0.20 0.05 MIN 5° 0.50 MAX 0.35 PLANE BSC 0° 0.35 MIN COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 63. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.80 0.15 0.23 6° 0.55 0.40 0.05 0.09 0° 0.40 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 64. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. J | Page 27 of 28 100709-B 012407-A 121608-A AD8065/AD8066 ORDERING GUIDE 1, 2 Model Temperature Range Package Description Package Option Branding AD8065AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8065AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD8065AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8065ART-R2 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA AD8065ART-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA AD8065ART-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA AD8065ARTZ-R2 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA # AD8065ARTZ-REEL −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA # AD8065ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23 RJ-5 HRA # AD8065WARTZ-REEL7 −40°C to +105°C 5-Lead SOT-23 RJ-5 H2F# AD8065ART-EBZ Evaluation Board (8-Lead SOIC_N) AD8065AR-EBZ Evaluation Board (5-Lead SOT-23) AD8066AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8066AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARZ-RL −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARZ-R7 −40°C to +85°C 8-Lead SOIC_N R-8 AD8066ARM −40°C to +85°C 8-Lead MSOP RM-8 H1B AD8066ARM-REEL −40°C to +85°C 8-Lead MSOP RM-8 H1B AD8066ARM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H1B AD8066ARMZ −40°C to +85°C 8-Lead MSOP RM-8 H7C AD8066ARMZ-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 H7C AD8066AR-EBZ Evaluation Board (8-Lead SOIC_N) AD8066ARM-EBZ Evaluation Board (5-Lead SOT-23) 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8065W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02916-0-8/10(J) Rev. J | Page 28 of 28