ANALOG DEVICES AD8062

Low Cost, 300 MHz Rail-to-Rail Amplifiers AD8061/AD8062/AD8063 FEATURES CONNECTION DIAGRAMS Low cost AD8062 V 1 8 +V OUT1 S Single (AD8061), dual (AD8062) AD8061/ DISABLE 1 AD8063 8 NC Single with disable (AD8063) –IN1 2 7 V (AD8063 ONLY) OUT2 –IN 2 7 +V Rail-to-rail output swing S +IN1 3 6 –IN2 +IN 3 6 V Low offset voltage: 6 mV OUT –V 4 5 NC –V 4 5 +IN2 High speed S S (Not to Scale) (Not to Scale) 300 MHz, −3 dB bandwidth (G = 1) NC = NO CONNECT 650 V/μs slew rate Figure 1. 8-Lead SOIC (R) Figure 2. 8-Lead SOIC (R)/MSOP (RM) 8.5 nV/√Hz at 5 V AD8063 35 ns settling time to 0.1% with 1 V step AD8061 V 1 6 +V OUT S V 1 5 +V OUT S Operates on 2.7 V to 8 V supplies –V 2 5 S DISABLE –V 2 Input voltage range = −0.2 V to +3.2 V with V = 5 V S S Excellent video specifications (R = 150 Ω, G = 2) L 3 +IN 4 –IN 3 +IN 4 –IN (Not to Scale) Gain flatness: 0.1 dB to 30 MHz (Not to Scale) 0.01% differential gain error Figure 3. 6-Lead SOT-23 (RJ) Figure 4. 5-Lead SOT-23 (RJ) 0.04° differential phase error 35 ns overload recovery 3 Low power R = 50Ω F 6.8 mA/amplifier typical supply current AD8063 400 μA when disabled 0 V = 0.2V p-p O R = 1kΩ R = 0Ω L F V = 1V BIAS –3 APPLICATIONS R F Imaging –6 Photodiode preamps OUT Professional video and cameras IN R L 50Ω Handsets –9 DVDs/CDs V BIAS Base stations –12 Filters 1 10 100 1k ADC drivers FREQUENCY (MHz) Clock buffers Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω GENERAL DESCRIPTION The AD8061/AD8062/AD8063 are rail-to-rail output voltage 150 Ω load, along with 0.1 dB flatness out to 30 MHz. Addi- feedback amplifiers offering ease of use and low cost. They have tionally, they offer wide bandwidth to 300 MHz along with a bandwidth and slew rate typically found in current feedback 650 V/μs slew rate. amplifiers. All have a wide input common-mode voltage range The AD8061/AD8062/AD8063 offer a typical low power of and output voltage swing, making them easy to use on single 6.8 mA/amplifier, while being capable of delivering up to supplies as low as 2.7 V. 50 mA of load current. The AD8063 has a power-down disable feature that reduces the supply current to 400 μA. These features Despite being low cost, the AD8061/AD8062/AD8063 provide excellent overall performance. For video applications, their make the AD8063 ideal for portable and battery-powered differential gain and phase errors are 0.01% and 0.04° into a applications where size and power are critical. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©1999–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. NORMALIZED GAIN (dB) 01065-002 01065-001 01065-005 01065-004 01065-003 AD8061/AD8062/AD8063 TABLE OF CONTENTS Features .............................................................................................. 1 Headroom Considerations ........................................................ 14 Applications ....................................................................................... 1 Overload Behavior and Recovery ............................................ 15 Connection Diagrams ...................................................................... 1 Capacitive Load Drive ............................................................... 16 General Description ......................................................................... 1 Disable Operation ...................................................................... 16 Revision History ............................................................................... 2 Board Layout Considerations ................................................... 16 Specif ica t ions ..................................................................................... 3 Applications Information .............................................................. 17 Absolute Maximum Ratings ............................................................ 6 Single-Supply Sync Stripper ...................................................... 17 Maximum Power Dissipation ..................................................... 6 RGB Amplifier ............................................................................ 17 ESD Caution .................................................................................. 6 Multiplexer .................................................................................. 18 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19 Circuit Description ......................................................................... 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 2/10—Rev. F to Rev. G Changes to Table 4 ............................................................................ 6 11/09—Rev. E to Rev. F Changed Input Common-Mode Voltage Range Parameter........ 4 Updated Outline Dimensions ....................................................... 19 10/07—Rev. D to Rev. E Changes to Applications .................................................................. 1 Updated Outline Dimensions ....................................................... 19 12/05—Rev. C to Rev. D Updated Format .................................................................. Universal Change to Features and General Description ............................... 1 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 5/01—Rev. B to Rev. C Replaced TPC 9 with new graph .................................................... 7 11/00—Rev. A to Rev. B 2/00—Rev. 0 to Rev. A 11/99—Revision 0: Initial Version Rev. G | Page 2 of 20 AD8061/AD8062/AD8063 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 320 MHz G = –1, +2, VO = 0.2 V p-p 60 115 MHz −3 dB Large Signal Bandwidth G = 1, V = 1 V p-p 280 MHz O Bandwidth for 0.1 dB Flatness G = 1, VO = 0.2 V p-p 30 MHz Slew Rate G = 1, V = 2 V step, R = 2 kΩ 500 650 V/μs O L G = 2, VO = 2 V step, RL = 2 kΩ 300 500 V/μs Settling Time to 0.1% G = 2, VO = 2 V step 35 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, R = 1 kΩ −77 dBc C O L fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ −50 dBc Crosstalk, Output to Output f = 5 MHz, G = 2, AD8062 −90 dBc Input Voltage Noise f = 100 kHz 8.5 nV/√Hz Input Current Noise f = 100 kHz 1.2 pA/√Hz Differential Gain Error (NTSC) G = 2, R = 150 Ω 0.01 % L Differential Phase Error (NTSC) G = 2, RL = 150 Ω 0.04 Degrees Third-Order Intercept f = 10 MHz 28 dBc SFDR f = 5 MHz 62 dB DC PERFORMANCE Input Offset Voltage 1 6 mV TMIN to TMAX 2 6 mV Input Offset Voltage Drift 3.5 μV/°C Input Bias Current 3.5 9 μA T to T 4 9 μA MIN MAX Input Offset Current ±0.3 ±4.5 μA Open-Loop Gain VO = 0.5 V to 4.5 V, RL = 150 Ω 68 70 dB V = 0.5 V to 4.5 V, R = 2 kΩ 74 90 dB O L INPUT CHARACTERISTICS Input Resistance 13 MΩ Input Capacitance 1 pF Input Common-Mode Voltage Range −0.2 to V +3.2 Common-Mode Rejection Ratio V = –0.2 V to +3.2 V 62 80 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing (Load Resistance Is Terminated at Midsupply) R = 150 Ω 0.3 0.1 to 4.5 4.75 V L RL = 2 kΩ 0.25 0.1 to 4.9 4.85 V Output Current V = 0.5 V to 4.5 V 25 50 mA O Capacitive Load Drive, VOUT = 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF G = 2, RS = 4.7 Ω 300 pF POWER-DOWN DISABLE Turn-On Time 40 ns Turn-Off Time 300 ns DISABLE Voltage (Off) 2.8 V DISABLE Voltage (On) 3.2 V POWER SUPPLY Operating Range 2.7 5 8 V Quiescent Current per Amplifier 6.8 9.5 mA Supply Current when Disabled (AD8063 Only) 0.4 mA Power Supply Rejection Ratio ∆VS = 2.7 V to 5 V 72 80 dB Rev. G | Page 3 of 20 AD8061/AD8062/AD8063 T = 25°C, V = 3 V, R = 1 kΩ, V = 1 V, unless otherwise noted. A S L O Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz G = –1, +2, V = 0.2 V p-p 60 115 MHz O –3 dB Large Signal Bandwidth G = 1, VO = 1 V p-p 250 MHz Bandwidth for 0.1 dB Flatness G = 1, V = 0.2 V p-p 30 MHz O Slew Rate G = 1, VO = 1 V step, RL = 2 kΩ 190 280 V/μs G = 2, VO = 1.5 V step, RL = 2 kΩ 180 230 V/μs Settling Time to 0.1% G = 2, V = 1 V step 40 ns O NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ −60 dBc fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ −44 dBc Crosstalk, Output to Output f = 5 MHz, G = 2 −90 dBc Input Voltage Noise f = 100 kHz 8.5 nV/√Hz Input Current Noise f = 100 kHz 1.2 pA/√Hz DC PERFORMANCE Input Offset Voltage 1 6 mV TMIN to TMAX 2 6 mV Input Offset Voltage Drift 3.5 μV/°C Input Bias Current 3.5 8.5 μA TMIN to TMAX 4 8.5 μA Input Offset Current ±0.3 ±4.5 μA Open-Loop Gain VO = 0.5 V to 2.5 V, RL = 150 Ω 66 70 dB V = 0.5 V to 2.5 V, R = 2 kΩ 74 90 dB O L INPUT CHARACTERISTICS Input Resistance 13 MΩ Input Capacitance 1 pF Input Common-Mode Voltage Range −0.2 to +1.2 V Common-Mode Rejection Ratio VCM = –0.2 V to +1.2 V 80 dB OUTPUT CHARACTERISTICS Output Voltage Swing (Load Resistance Is Terminated at Midsupply) RL = 150 Ω 0.3 0.1 to 2.87 2.85 V R = 2 kΩ 0.3 0.1 to 2.9 2.90 V L Output Current VO = 0.5 V to 2.5 V 25 mA Capacitive Load Drive, VOUT = 0.8 V 30% overshoot, G = 1, RS = 0 Ω 25 pF G = 2, R = 4.7 Ω 300 pF S POWER-DOWN DISABLE Turn-On Time 40 ns Turn-Off Time 300 ns DISABLE Voltage—Off 0.8 V DISABLE Voltage—On 1.2 V POWER SUPPLY Operating Range 2.7 3 V Quiescent Current per Amplifier 6.8 9 mA Supply Current when Disabled (AD8063 Only) 0.4 mA Power Supply Rejection Ratio 72 80 dB Rev. G | Page 4 of 20 AD8061/AD8062/AD8063 T = 25°C, V = 2.7 V, R = 1 kΩ, V = 1 V, unless otherwise noted. A S L O Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = 1, VO = 0.2 V p-p 150 300 MHz G = –1, +2, V = 0.2 V p-p 60 115 MHz O G = 1, VO = 1 V p-p 230 MHz Bandwidth for 0.1 dB Flatness G = 1, V = 0.2 V p-p, V dc = 1 V 30 MHz O O Slew Rate G = 1, VO = 0.7 V step, RL = 2 kΩ 110 150 V/μs G = 2, VO = 1.5 V step, RL = 2 kΩ 95 130 V/μs Settling Time to 0.1% G = 2, V = 1 V step 40 ns O NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ –60 dBc fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ –44 dBc Crosstalk, Output to Output f = 5 MHz, G = 2 –90 dBc Input Voltage Noise f = 100 kHz 8.5 nV/√Hz Input Current Noise f = 100 kHz 1.2 pA/√Hz DC PERFORMANCE Input Offset Voltage 1 6 mV TMIN to TMAX 2 6 mV Input Offset Voltage Drift 3.5 μV/°C Input Bias Current 3.5 μA TMIN to TMAX 4 8.5 μA Input Offset Current ±0.3 ±4.5 μA Open-Loop Gain VO = 0.5 V to 2.2 V, RL = 150 Ω 63 70 dB V = 0.5 V to 2.2 V, R = 2 kΩ 74 90 dB O L INPUT CHARACTERISTICS Input Resistance 13 MΩ Input Capacitance 1 pF Input Common-Mode Voltage Range –0.2 to +0.9 V Common-Mode Rejection Ratio VCM = –0.2 V to +0.9 V 0.8 dB OUTPUT CHARACTERISTICS Output Voltage Swing (Load Resistance Is Terminated at Midsupply) RL = 150 Ω 0.3 0.1 to 2.55 2.55 V R = 2 kΩ 0.25 0.1 to 2.6 2.6 V L Output Current VO = 0.5 V to 2.2 V 25 mA Capacitive Load Drive, VOUT = 0.8 V 30% overshoot: G = 1, RS = 0 Ω 25 pF G = 2, R = 4.7 Ω 300 pF S POWER-DOWN DISABLE Turn-On Time 40 ns Turn-Off Time 300 ns DISABLE 0.5 V Voltage (Off) DISABLE 0.9 V Voltage (On) POWER SUPPLY Operating Range 2.7 8 V Quiescent Current per Amplifier 6.8 8.5 mA Supply Current when Disabled (AD8063 Only) 0.4 mA Power Supply Rejection Ratio 80 dB Rev. G | Page 5 of 20 AD8061/AD8062/AD8063 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Table 4. The maximum power that can be safely dissipated by the Parameter Rating AD8061/AD8062/AD8063 is limited by the associated rise in Supply Voltage 8 V junction temperature. The maximum safe junction temperature 1 Internal Power Dissipation for plastic encapsulated devices is determined by the glass 8-lead SOIC (R) 0.8 W transition temperature of the plastic, approximately 150°C. 5-lead SOT-23 (RJ) 0.5 W Temporarily exceeding this limit may cause a shift in parametric 6-lead SOT-23 (RJ) 0.5 W performance due to a change in the stresses exerted on the die 8-lead MSOP (RM) 0.6 W by the package. Exceeding a junction temperature of 175°C for Input Voltage (Common-Mode) (−V − 0.2 V) to (+V + 0.2 V) S S an extended period can result in device failure. While the Differential Input Voltage ±V S AD8061/AD8062/AD8063 is internally short-circuit protected, Output Short-Circuit Duration Observe power derating curves this may not be sufficient to guarantee that the maximum Storage Temperature Range −65°C to +125°C junction temperature (150°C) is not exceeded under all R-8, RM-8, SOT-23-5, SOT-23-6 conditions. Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering, 300°C To ensure proper operation, it is necessary to observe the 10 sec) maximum power derating curves. 2.0 1 Specification is for device in free air. 8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W. T = 150°C 8-LEAD SOIC J 5-Lead SOT-23: θ = 240°C/W; θ = 92°C/W. JA JC PACKAGE 6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W. 1.5 8-Lead MSOP: θ = 200°C/W; θ = 44°C/W. JA JC Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress 1.0 rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute 0.5 MSOP maximum rating conditions for extended periods may affect SOT-23-5, SOT-23-6 device reliability. 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 6. Maximum Power Dissipation vs. Temperature for AD8061/AD8062/AD8063 ESD CAUTION Rev. G | Page 6 of 20 MAXIMUM POWER DISSIPATION (W) 01065-006 AD8061/AD8062/AD8063 TYPICAL PERFORMANCE CHARACTERISTICS 1.2 3 G = +1 1.0 +V @ +85°C OUT 0 +V @ +25°C OUT 0.8 –3 G = +2 +V @ –40°C OUT 0.6 –6 –V @ –40°C OUT 0.4 G = +5 V = 0.2V p-p O –9 –V @ +85°C R = 1kΩ 0.2 OUT L V = 1V BIAS –V @ +25°C OUT 0 –12 0 10 20 30 40 50 60 70 80 90 1 10 100 1k LOAD CURRENT (mA) FREQUENCY (MHz) Figure 7. Output Saturation Voltage vs. Load Current Figure 10. Small Signal Frequency Response 18 3 V = 1.0V p-p O R = 1kΩ AD8062 L 16 G = +1 V = 1V BIAS 0 14 G = +2 12 –3 10 AD8061 8 G = +5 –6 6 4 –9 2 0 –12 2 346 5 7 8 1 10 100 1k SINGLE POWER SUPPLY (V) FREQUENCY (MHz) Figure 8. I vs. V SUPPLY SUPPLY Figure 11. Large Signal Frequency Response 3 3 R = 50Ω V = 5V F S V = 0.2V p-p O = 1kΩ R L 0 0 V = 1V BIAS V = 0.2V p-p O R = 1kΩ R = 0Ω L F G = –1 V = 1V BIAS –3 G = –5 –3 G = –2 R R F F –6 –6 OUT OUT IN IN R R L L 50Ω 50Ω –9 –9 V V BIAS BIAS –12 –12 1 10 100 1k 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Small Signal Response, R = 0 Ω, 50 Ω F Figure 12. Small Signal Frequency Response Rev. G | Page 7 of 20 NORMALIZED GAIN (dB) POWER SUPPLY CURRENT (mA) VOLTAGE DIFFERENTIAL FROM V (Unit) S 01065-009 01065-008 01065-007 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 01065-012 01065-011 01065-010 AD8061/AD8062/AD8063 0 3 V = 5V V = 5V S S V = 1V p-p –10 R = 1kΩ O L R = 1kΩ G = +1 L –20 0 V = 1V BIAS –30 G = –1 2ND @ 1MHz –3 –40 3RD @ 10MHz –50 G = –2 –60 –6 G = –5 –70 –80 –9 –90 2ND @ 10MHz 3RD @ 1MHz –12 –100 0.5 1.0 3.5 1 10 100 1k 1.5 2.0 2.5 3.0 FREQUENCY (MHz) INPUT SIGNAL DC BIAS (V) Figure 13. Large Signal Frequency Response Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias 0.1 –40 604Ω V = 2.7V V = 0.2V p-p O S 10µF R = 1kΩ L 5V + V = 1V –50 BIAS 0 0.1µF G = +1 1kΩ 50Ω –60 1MΩ INPUT 52.3Ω –0.1 0.1µF + V = 5V 1kΩ S 1.25V dc (R ) –70 – LOAD –0.2 V = 3V S –80 2ND H –0.3 –90 –0.4 –100 3RD H –0.5 –110 1 10 100 1k 0.01 0.1 1 10 50 FREQUENCY (MHz) FREQUENCY (MHz, START = 10kHz, STOP = 30MHz) Figure 14. 0.1 dB Flatness Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs. Input Signal DC Bias 80 –30 200 V = 5V S R = 1kΩ L 150 –40 G = +5 60 V = 1V p-p O SERIES 1 100 –50 2ND 3RD 10MHz 50 –60 40 SERIES 2 0 –70 20 –50 –80 –100 2ND –90 0 –150 3RD 5MHz –100 1MHz –200 –20 –110 –250 2ND 3RD –300 –120 –40 0 1 2 3 4 5 0.01 0.1 1 10 100 1k OUTPUT SIGNAL DC BIAS (V) FREQUENCY (MHz) Figure 18. Harmonic Distortion vs. Output Signal DC Bias Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency, VS = 5 V, RL = 1 kΩ Rev. G | Page 8 of 20 OPEN-LOOP GAIN (dB) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 01065-014 01065-013 01065-015 PHASE (Degrees) DISTORTION (dB) DISTORTION (dB) HARMONIC DISTORTION (dBc) 01065-018 01065-017 01065-016 AD8061/AD8062/AD8063 –40 V = 5V S R = R = 1kΩ F L –50 2ND @ 10MHz G = +2 0.01 0 –60 5V 10µF + –0.01 1MΩ –0.02 0.1µF INPUT 50Ω –70 TO –0.04 50Ω 2ND @ 2MHz 1kΩ 1kΩ 3589A 1kΩ –0.06 –80 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH 2ND @ 500kHz –90 3RD @ 2MHz 0.02 0 –100 –0.02 3RD @ 500kHz –0.04 –110 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 –0.06 RTO OUTPUT (V p-p) 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH Figure 19. Harmonic Distortion vs. Output Signal Amplitude Figure 22. Differential Gain and Phase Error, G = 2, NTSC Input Signal, RL = 1 kΩ, VS = 5 V –30 V = 5V S R = R = 1kΩ I L 0.010 –40 V = 2V p-p O 0.005 G = 2 –50 0 S1 3RD HARMONIC/ –0.005 –60 DUAL ±2.5V SUPPLY –0.010 S1 2ND HARMONIC/ –70 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH DUAL ±2.5V SUPPLY S1 2ND HARMONIC/ –80 SINGLE +5V SUPPLY 0.04 0.03 –90 0.02 0.01 –100 0 S1 3RD HARMONIC/ –0.01 SINGLE +5V SUPPLY –110 –0.02 0.01 0.1 1 10 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH FREQUENCY (MHz, START = 10kHz, STOP = 30MHz) Figure 23. Differential Gain and Phase Error, G = 2, Figure 20. Harmonic Distortion vs. Frequency NTSC Input Signal, R = 150 Ω, V = 5 V L S 1000 1.0 V = 5V S FALLING EDGE 900 R = 1kΩ V = 5V 0.9 S L G = +1 R = 1kΩ L 800 0.8 G = +1 700 0.7 RISING EDGE 600 0.6 500 0.5 400 0.4 300 0.3 200 0.2 100 0.1 0 0 1.0 1.5 2.0 2.5 3.0 0 0.1 0.2 0.3 0.4 0.5 OUTPUT STEP AMPLITUDE (V) TIME (µs) Figure 24. Slew Rate vs. Output Step Amplitude Figure 21. 400 mV Pulse Response Rev. G | Page 9 of 20 OUTPUT VOLTAGE (V) DISTORTION (dB) DISTORTION (dB) 01065-021 01065-020 01065-019 DIFFERENTIAL PHASE DIFFERENTIAL GAIN DIFFERENTIAL PHASE DIFFERENTIAL GAIN (%) (Degrees) (%) SLEW RATE (V/µs) (Degrees) 01065-024 01065-023 01065-022 AD8061/AD8062/AD8063 1400 V = ±2.5V S G = +1 FALLING EDGE V IN R = 1kΩ L 1200 V =±4V S 2.5V 1000 FALLING EDGE V = +5V S V OUT 800 600 RISING EDGE V =±4V S 0V 400 RISING EDGE V = +5V S 200 500mV/DIV 0 0 20 40 60 80 100 120 140 160 180 200 1.0 1.5 04 0.5 2.0 2.5 3.0 3.5.0 TIME (ns) OUTPUT STEP (V) Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, R = 1 kΩ, V = 5 V Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V L S 1k V = ±2.5V S V = 5V G = +5 S R = 1kΩ R = 1kΩ L L V OUT 2.5V 100 V IN 1.0V 10 0V 500mV/DIV 1 0 20 40 60 80 100 120 140 160 180 200 10 100 1k 10k 100k 1M 10M TIME (ns) FREQUENCY (Hz) Figure 26. Voltage Noise vs. Frequency Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V 100 0 V = 0.2V p-p CM V = 5V –10 S R = 100Ω L R = 1kΩ L V = ±2.5V S SIDE 2 –20 –30 10 SIDE 1 –40 –50 –60 604Ω 1 604Ω –70 50Ω V IN 154Ω –80 200mV p-p 57.6Ω 154Ω –90 0 –100 10 100 1k 10k 100k 1M 10M 0.01 0.1 1 10 100 500 FREQUENCY (Hz) FREQUENCY (MHz) Figure 27. Current Noise vs. Frequency Figure 30. CMRR vs. Frequency Rev. G | Page 10 of 20 CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) SLEW RATE (V/µs) 01065-027 01065-025 01065-026 CMRR (dB) VOLTS VOLTS 01065-030 01065-029 01065-028 AD8061/AD8062/AD8063 7 0 ΔV = 0.2V p-p S V = 5V S R = 1kΩ –10 L V = 5V 6 S –20 –PSRR 5 –30 –40 4 –50 +PSRR 3 –60 –70 2 –80 1 –90 –100 0 0.01 0.1 1 10 100 500 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DISABLE VOLTAGE FREQUENCY (MHz) Figure 31. ±PSRR vs. Frequency Delta DISABLE Figure 34. AD8063 Voltage vs. Supply Current –20 6 V = 5V 1kΩ 1kΩ S G = +2 –30 5 V f = 10MHz +2.5V DISABLE IN @ 1.3V –40 BIAS R = 100Ω L OUT 4 –50 IN 1kΩ 50Ω –60 –2.5V 3 –70 INPUT = SIDE 2 INPUT = SIDE 1 2 –80 –90 V = 5V 1 S V = 400mV rms IN –100 R = 1kΩ L G = +2 0 V OUT –110 –120 –1 0.01 0.1 1 10 100 500 02 0.4 0.8 1.2 1.6.0 FREQUENCY (MHz) TIME (µs) Figure 32. AD8062 Crosstalk, V = 2.0 V p-p, R = 1 kΩ, G = 2, V = 5 V DISABLE OUT L S Figure 35. AD8063 Function, Voltage = 0 V to 5 V 0 1k V = 5V S V = 5V S V = 0.2V p-p O –10 V = 0.2V p-p O R = 1kΩ L R = 1kΩ L V = 1V BIAS 100 V = 1V –20 BIAS –30 10 –40 –50 1 –60 –70 0.1 –80 –90 0.01 1 10 100 1k 0.1 1 10 100 1k FREQUENCY (MHz) FREQUENCY (MHz) Figure 33. AD8063 Disabled Output Isolation Frequency Response Figure 36. Output Impedance vs. Frequency, V = 0.2 V p-p, R = 1 kΩ, V = 5 V OUT L S Rev. G | Page 11 of 20 DISABLED ISOLATION (dB) OUTPUT TO OUTPUT CROSSTALK (dB) PSRR (dB) 01065-033 01065-032 01065-031 IMPEDANCE (Ω) OUTPUT VOLTAGE (V) I (mA) SUPPLY 01065-036 01065-035 01065-034 AD8061/AD8062/AD8063 V = 5V V = 5V S S R = 1kΩ G = +2 L R = 1kΩ L V = 1V p-p IN 3.5V +0.1% 2.5V –0.1% 1kΩ 1kΩ 1.5V R = 1kΩ L 50Ω 500mV/DIV t = 0 010 20 30 40 50 60 70 80 90 100 20ns/DIV TIME (ns) Figure 37. Output Settling Time to 0.1% Figure 40. 1 V Step Response 50 V = 5V S 45 FALLING EDGE G = +2 R = 1kΩ L 2.6V 40 V = 100mV IN 35 RISING EDGE 30 2.5V 25 20 2.4V 15 V = 5V 10 S R = 1kΩ L G = +1 5 20mV/DIV 0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) OUTPUT VOLTAGE STEP Figure 38. Settling Time vs. V OUT Figure 41. 100 mV Step Response V = 5V S V = 5V S G = –1 G = +2 R = 1kΩ F R = R = 1kΩ F L R = 1kΩ L V = 4V p-p IN 4.86V 2.43V 0V 0V 1V 2µs 2µs/DIV 1V/DIV Figure 39. Output Swing Figure 42. Output Rail-to-Rail Swing Rev. G | Page 12 of 20 SETTLING TIME TO 0.1% SETTLING TIME (ns) VOLTS 01065-039 01065-038 01065-037 VOLTS VOLTS VOLTS 01065-042 01065-041 01065-040 AD8061/AD8062/AD8063 V = 5V V = 5V S S G = +2 G = +1 R = R = 1kΩ R = 1kΩ L F L V = 2V p-p IN 2.6V 4.5V 2.5V 2.5V 2.4V 0.5V 50mV/DIV 1V/DIV 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) TIME (ns) Figure 43. 200 mV Step Response Figure 44. 2 V Step Response Rev. G | Page 13 of 20 VOLTS 01065-043 VOLTS 01065-044 AD8061/AD8062/AD8063 CIRCUIT DESCRIPTION The AD8061/AD8062/AD8063 family is comprised of high –0.4 speed voltage feedback op amps. The high slew rate input stage –0.8 is a true, single-supply topology, capable of sensing signals at or –1.2 below the minus supply rail. The rail-to-rail output stage can –1.6 pull within 30 mV of either supply rail when driving light loads and within 0.3 V when driving 150 Ω. High speed perform- –2.0 ance is maintained at supply voltages as low as 2.7 V. –2.4 HEADROOM CONSIDERATIONS –2.8 These amplifiers are designed for use in low voltage systems. –3.2 To obtain optimum performance, it is useful to understand the –3.6 behavior of the amplifier as input and output signals approach –4.0 the amplifier’s headroom limits. –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V (V) CM The AD8061/AD8062/AD8063 input common-mode voltage Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V range extends from the negative supply voltage (actually 200 mV below this), or ground for single-supply operation, to within 2 1.8 V of the positive supply voltage. Thus, at a gain of 2, the AD8061/AD8062/AD8063 can provide full rail-to-rail output 0 swing for supply voltage as low as 3.6 V, assuming the input V = 3.0 CM V = 3.1 CM signal swings from −V (or ground) to +V /2. At a gain of 3, S S V = 3.2 CM –2 the AD8061/AD8062/AD8063 can provide a rail-to-rail output V = 3.3 CM range down to 2.7 V total supply voltage. V = 3.4 CM –4 Exceeding the headroom limit is not a concern for any inverting gain on any supply voltage, as long as the reference voltage at the amplifier’s positive input lies within the amplifier’s input –6 common-mode range. The input stage is the headroom limit for signals when the –8 0.1 1 10 100 1k 10k amplifier is used in a gain of 1 for signals approaching the FREQUENCY (MHz) positive rail. Figure 45 shows a typical offset voltage vs. input Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V common-mode voltage for the AD8061/AD8062/AD8063 Higher frequency signals require more headroom than lower amplifier on a 5 V supply. Accurate dc performance is main- frequencies to maintain distortion performance. Figure 47 tained from approximately 200 mV below the minus supply illustrates how the rising edge settling time for the amplifier to within 1.8 V of the positive supply. For high speed signals, however, there are other considerations. Figure 46 shows −3 dB configured as a unity-gain follower stretches out as the top of bandwidth vs. dc input voltage for a unity-gain follower. As a 1 V step input approaches and exceeds the specified input the common-mode voltage approaches the positive supply, common-mode voltage limit. the amplifier holds together well, but the bandwidth begins to For signals approaching the minus supply and inverting gain drop at 1.9 V within +VS. and high positive gain configurations, the headroom limit is the output stage. The AD8061/AD8062/AD8063 amplifiers use This manifests itself in increased distortion or settling time. a common emitter style output stage. This output stage Figure 16 plots the distortion of a 1 V p-p signal with the AD8061/AD8062/AD8063 amplifier used as a follower on maximizes the available output range, limited by the saturation a 5 V supply vs. signal common-mode voltage. Distortion voltage of the output transistors. The saturation voltage performance is maintained until the input signal center voltage increases with the drive current the output transistor is required to supply, due to the output transistors’ collector resistance. The gets beyond 2.5 V, as the peak of the input sine wave begins to saturation voltage is estimated using the equation run into the upper common-mode voltage limit. V = 25 mV + I × 8 Ω SAT O where: IO is the output current. 8 Ω is a typical value for the output transistors’ collector resistance. Rev. G | Page 14 of 20 V (mV) GAIN (dB) OS 01065-046 01065-045 AD8061/AD8062/AD8063 3.6 3.7 3.4 3.5 3.2 3.3 3.0 3.1 VOLTAGE STEP 2V TO 3V STEP FROM 2.4V TO 3.4V 2.8 2.1V TO 3.1V STEP 2.9 VOLTAGE STEP 2.2V TO 3.2V STEP 2.6 FROM 2.4V TO 3.6V 2.7 2.3V TO 3.3V STEP 2.4 VOLTAGE STEP 2.5 2.4V TO 3.4V STEP FROM 2.4V TO 3.8V, 4V AND 5V 2.2 2.3 2.0 2.1 0 100 200 300 400 500 600 0 4 8 12 16 20 24 28 32 TIME (ns) TIME (ns) Figure 48. Pulse Response for G = 1 Follower, Figure 47. Output Rising Edge for 1 V Step at Input Step Overloading the Input Stage Input Headroom Limits, G = 1, V = 5 V, 0 V S Output As the saturation point of the output stage is approached, the output signal shows increasing amounts of compression and Output overload recovery is typically within 40 ns after the clipping. As in the input headroom case, the higher frequency amplifier’s input is brought to a nonoverloading value. Figure 49 signals require a bit more headroom than lower frequency shows output recovery transients for the amplifier recovering signals. Figure 16, Figure 17, and Figure 18 illustrate this point, from a saturated output from the top and bottom supplies to a plotting typical distortion vs. output amplitude and bias for point at midsupply. gains of 2 and 5. 5.0 4.6 OVERLOAD BEHAVIOR AND RECOVERY OUTPUT VOLTAGE 4.2 5V TO 2.5V Input 3.8 OUTPUT VOLTAGE 3.4 The specified input common-mode voltage of the AD8061/ 0V TO 2.5V 3.0 AD8062/AD8063 is −200 mV below the negative supply to 2.6 INPUT VOLTAGE within 1.8 V of the positive supply. Exceeding the top limit EDGES 2.2 results in lower bandwidth and increased settling time as seen R 1.8 in Figure 46 and Figure 47. Pushing the input voltage of a unity- 5V 1.4 R gain follower beyond 1.6 V within the positive supply leads to 1.0 V IN 2.5V the behavior shown in Figure 48—an increasing amount of – V O 0.6 – output error and much increased settling time. Recovery time 0.2 from input voltages 1.6 V or closer to the positive supply is –0.2 0 10 20 30 40 50 60 70 approximately 35 ns, which is limited by the settling artifacts TIME (ns) caused by transistors in the input stage coming out of saturation. Figure 49. Overload Recovery, G = −1, V = 5 V S The AD8061/AD8062/AD8063 family does not exhibit phase reversal, even for input voltages beyond the voltage supply rails. Going more than 0.6 V beyond the power supplies turns on protection diodes at the input stage, which greatly increases the current draw of the device. Rev. G | Page 15 of 20 OUTPUT VOLTAGE (V) 01065-047 INPUT AND OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 01065-049 01065-048 AD8061/AD8062/AD8063 CAPACITIVE LOAD DRIVE DISABLE OPERATION The AD8061/AD8062/AD8063 family is optimized for The internal circuit for the AD8063 disable function is shown bandwidth and speed, not for driving capacitive loads. Output in Figure 52. When the DISABLE node is pulled below 2 V capacitance creates a pole in the amplifier’s feedback path, from the positive supply, the supply current decreases from leading to excessive peaking and potential oscillation. If dealing typically 6.5 mA to under 400 μA, and the AD8063 output with load capacitance is a requirement of the application, the DISABLE enters a high impedance state. If the node is not two strategies to consider are as follows: connected and allowed to float, the AD8063 stays biased at full power. Use a small resistor in series with the amplifier’s output and the VCC load capacitance. Reduce the bandwidth of the amplifier’s feedback loop by increasing the overall noise gain. 2V TO AMPLIFIER Figure 50 shows a unity-gain follower using the series resistor BIAS DISABLE strategy. The resistor isolates the output from the capacitance and, more importantly, creates a zero in the feedback path that compensates for the pole created by the output capacitance. VEE R Figure 52. Disable Circuit of the AD8063 SERIES AD8061 V O C DISABLE Figure 34 shows the AD8063 supply current vs. LOAD V IN voltage. Figure 35 plots the output seen when the AD8063 input Figure 50. Series Resistor Isolating Capacitive Load is driven with a 10 MHz sine wave, and DISABLE is toggled from 0 V to 5 V, illustrating the part’s turn-on and turn-off Voltage feedback amplifiers like those in the AD8061/AD8062/ time. Figure 33 shows the input/output isolation response with AD8063 family are able to drive more capacitive load without the AD8063 shut off. excessive peaking when used in higher gain configurations because the increased noise gain reduces the bandwidth of the BOARD LAYOUT CONSIDERATIONS overall feedback loop. Figure 51 plots the capacitance that Maintaining the high speed performance of the AD8061/AD8062/ produces 30% overshoot vs. noise gain for a typical amplifier. AD8063 family requires the use of high speed board layout 10k techniques and low parasitic components. The PCB should have a ground plane covering unused portions of the component side of the board to provide a low impedance R = 4.7 S path. Remove the ground plane near the package to reduce 1k parasitic capacitance. Proper bypassing is critical. Use a ceramic 0.1 μF chip capacitor R = 0 to bypass both supplies. Locate the chip capacitor within 3 mm S 100 of each power pin. Additionally, connect in parallel a 4.7 μF to 10 μF tantalum electrolytic capacitor to provide charge for fast, large signal changes at the output. Minimizing parasitic capacitance at the amplifier’s inverting 10 1 2 345 input pin is very important. Locate the feedback resistor close to CLOSED-LOOP GAIN the inverting input pin. The value of the feedback resistor may Figure 51. Capacitive Load vs. Closed-Loop Gain come into play—for instance, 1 kΩ interacting with 1 pF of parasitic capacitance creates a pole at 159 MHz. Use stripline design techniques for signal traces longer than 25 mm. Design them with either 50 Ω or 75 Ω characteristic impedance and proper termination at each end. Rev. G | Page 16 of 20 CAPACITIVE LOAD (pF) 01065-050 01065-051 01065-052 AD8061/AD8062/AD8063 APPLICATIONS INFORMATION The circuit can be modified to provide the sync stripping SINGLE-SUPPLY SYNC STRIPPER function for such a waveform. Instead of connecting RG to When a video signal contains synchronization pulses, it is ground, connect it to a dc voltage that is two times the black sometimes desirable to remove them prior to performing level of the input signal. The gain from the noninverting input certain operations. In the case of analog-to-digital conversion, to the output is 2, which means the black level is amplified by 2 the sync pulses consume some of the dynamic range, so to the output. However, the gain through R is −1 to the output. G removing them increases the converter’s available dynamic It takes a dc level of twice the input black level to shift the black range for the video information. level to ground at the output. When this occurs, the sync is Figure 53 shows a basic circuit for creating a sync stripper using stripped, and the active video is passed as in the ground- the AD8061 powered by a single supply. When the negative referenced case. supply is at ground potential, the lowest potential to which the RED DAC output can go is ground. This feature is exploited to create a 75Ω 75Ω waveform whose lowest amplitude is the black level of the video MONITOR GREEN #1 DAC and does not include the sync level. 75Ω 75Ω 3V BLUE DAC 75Ω 75Ω 0.1µF 10µF 7 3 VIDEO IN 1kΩ 75Ω VIDEO OUT 6 75Ω AD8061 3V 2 75Ω 4 R F 1kΩ 0.1µF 10µF 7 R G 1kΩ 2 PIN NUMBERS ARE 1kΩ FOR 8-LEAD PACKAGE 75Ω RED 6 AD8061 3 75Ω Figure 53. Single 3 V Sync Stripper Using AD8061 4 1kΩ In this case, the input video signal has its black level at ground, so it comes out at ground at the input. Because the sync level is 3V MONITOR #2 below the black level, it does not show up at the output. However, 0.1µF 10µF all of the active video portion of the waveform is amplified by a 8 gain of 2 and then normalized to unity gain by the back- 1kΩ 2 terminated transmission line. Figure 54 is an oscilloscope plot 75Ω GREEN 1 AD8062 3 of the input and output waveforms. 75Ω 5 75Ω BLUE 7 1 AD8062 1kΩ 75Ω 6 INPUT 4 1kΩ Figure 55. RGB Cable Driver Using AD8061 and AD8062 2 RGB AMPLIFIER OUTPUT Most RGB graphics signals are created by video DAC outputs that drive a current through a resistor to ground. At the video black level, the current goes to zero, and the voltage of the video is also zero. Before the availability of high speed rail-to-rail op 500mV 10µs amps, it was essential that an amplifier have a negative supply Figure 54. Input and Output Waveforms for a Single-Supply to amplify such a signal. Such an amplifier is necessary if one Video Sync Stripper Using an AD8061 wants to drive a second monitor from the same DAC outputs. Some video signals with sync are derived from single-supply However, high speed, rail-to-rail output amplifiers like the devices, such as video DACs. These signals can contain sync, AD8061 and AD8062 accept ground-level input signals and but the whole waveform is positive, and the black level is not output ground-level signals. They are used as RGB signal at ground but at a positive voltage. amplifiers. A combination of the AD8061 (single) and the AD8062 (dual) amplifies the three video channels of an RGB system. Figure 55 shows a circuit that performs this function. Rev. G | Page 17 of 20 01065-054 01065-053 01065-055 AD8061/AD8062/AD8063 The select signal and the output waveforms for this circuit are MULTIPLEXER shown in Figure 57. For synchronization clarity, two different The AD8063 has a disable pin used to power down the ampli- frequency synthesizers, whose time bases are locked to each fier to save power or to create a mux circuit. If two (or more) other, generate the signals. AD8063 outputs are connected together, and only one is enabled, then only the signal of the enabled amplifier will appear at the 2µs output. This configuration is used to select from various input signal sources. Additionally, the same input signal is applied to OUTPUT different gain stages, or differently tuned filters, to make a gain- step amplifier or a selectable frequency amplifier. Figure 56 shows a schematic of two AD8063 devices used to create a mux that selects between two inputs. One of these is a 1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave. SELECT +4V 0.1µF 10µF 1V 2V 1 TIME 49.9Ω AD8063 Figure 57. AD8063 Mux Output BASE OUT 1V p-p 3MHz 0.1µF 10µF –4V 1kΩ 49.9Ω V OUT 1kΩ +4V 49.9Ω 0.1µF 10µF 1 49.9Ω AD8063 2V p-p 1MHz TIME BASE 10µF 0.1µF IN –4V 1kΩ 1kΩ HCO4 SELECT Figure 56. Two-to-One Multiplexer Using Two AD8063s Rev. G | Page 18 of 20 01065-056 01065-057 AD8061/AD8062/AD8063 OUTLINE DIMENSIONS 3.00 2.90 2.80 5.00 (0.1968) 5 4 3.00 1.70 4.80 (0.1890) 2.80 1.60 2.60 1.50 12 3 85 6.20 (0.2441) 4.00 (0.1574) 1 3.80 (0.1497) 5.80 (0.2284) 4 0.95 BSC 1.90 BSC 1.27 (0.0500) 0.50 (0.0196) 45° 1.30 BSC 1.75 (0.0688) 0.25 (0.0099) 1.15 1.35 (0.0532) 0.25 (0.0098) 8° 0.90 0.10 (0.0040) 0.20 MAX 0° 1.45 MAX 0.08 MIN COPLANARITY 0.51 (0.0201) 0.95 MIN 1.27 (0.0500) 0.10 0.31 (0.0122) 0.55 0.25 (0.0098) SEATING 0.40 (0.0157) 0.15 MAX 10° 0.17 (0.0067) 0.45 PLANE SEATING 0.20 0.05 MIN 5° 0.50 MAX 0.35 PLANE BSC 0° 0.35 MIN COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR COMPLIANT TO JEDEC STANDARDS MO-178-AA REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 58. 5-Lead Small Outline Transistor Package [SOT-23] Figure 59. 8-Lead Standard Small Outline Package [SOIC_N] (RJ-5) Narrow Body (R-8) Dimensions shown in millimeters Dimensions shown in millimeters and (inches) 3.00 2.90 2.80 3.20 3.00 2.80 65 4 3.00 1.70 2.80 1.60 2.60 1.50 8 5 5.15 12 3 3.20 4.90 PIN 1 3.00 4.65 INDICATOR 1 2.80 4 0.95 BSC 1.90 PIN 1 BSC IDENTIFIER 1.30 0.65 BSC 1.15 0.90 0.20 MAX 0.95 15° MAX 1.45 MAX 0.08 MIN 0.85 1.10 MAX 0.95 MIN 0.75 0.55 0.15 MAX 10° 0.80 0.45 SEATING 0.15 0.60 0.23 0.05 MIN 6° 4° 0.55 0.50 MAX 0.35 0.40 PLANE BSC 0.05 0.09 0° 0° 0.40 0.30 MIN 0.25 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-178-AB COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 60. 6-Lead Small Outline Transistor Package [SOT-23] Figure 61. 8-Lead Mini Small Outline Package [MSOP] (RJ-6) (RM-8) Dimensions shown in millimeters Dimensions shown in millimeters Rev. G | Page 19 of 20 121608-A 121608-A 100709-B 012407-A AD8061/AD8062/AD8063 ORDERING GUIDE 1 Model Temperature Range Package Description Package Option Branding AD8061AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8061AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 AD8061AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8 AD8061ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8061ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 AD8061ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8 AD8061ART-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 HGA AD8061ART-REEL −40°C to +85°C 5-Lead SOT-23, 13-Inch Tape and Reel RJ-5 HGA AD8061ART-REEL7 −40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 HGA 2 AD8061ARTZ-R2 −40°C to +85°C 5-Lead SOT-23, 250 Piece Tape and Reel RJ-5 H0D 2 AD8061ARTZ-REEL −40°C to +85°C 5-Lead SOT-23, 13-Inch Tape and Reel RJ-5 H0D 2 AD8061ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23, 7-Inch Tape and Reel RJ-5 H0D AD8062AR −40°C to +85°C 8-Lead SOIC_N R-8 AD8062AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 AD8062AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8 AD8062ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD8062ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 AD8062ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8 AD8062ARM −40°C to +85°C 8-Lead MSOP RM-8 HCA AD8062ARM-REEL −40°C to +85°C 8-Lead MSOP, 13-Inch Tape and Reel RM-8 HCA AD8062ARM-REEL7 –40°C to +85°C 8-Lead MSOP, 7-Inch Tape and Reel RM-8 HCA AD8062ARMZ −40°C to +85°C 8-Lead MSOP RM-8 #HCA AD8062ARMZ-RL −40°C to +85°C 8-Lead MSOP, 13-Inch Tape and Reel RM-8 #HCA AD8062ARMZ-R7 –40°C to +85°C 8-Lead MSOP, 7-Inch Tape and Reel RM-8 #HCA AD8063AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8063AR-REEL –40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 AD8063AR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8 AD8063ARZ 40°C to +85°C 8-Lead SOIC_N R-8 AD8063ARZ-REEL 40°C to +85°C 8-Lead SOIC_N, 13-Inch Tape and Reel R-8 AD8063ARZ-REEL7 40°C to +85°C 8-Lead SOIC_N, 7-Inch Tape and Reel R-8 AD8063ART-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 HHA AD8063ART-REEL –40°C to +85°C 6-Lead SOT-23, 13-Inch Tape and Reel RJ-6 HHA AD8063ART-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 HHA 3 AD8063ARTZ-R2 –40°C to +85°C 6-Lead SOT-23, 250 Piece Tape and Reel RJ-6 H0E 3 AD8063ARTZ-REEL –40°C to +85°C 6-Lead SOT-23, 13-Inch Tape and Reel RJ-6 H0E 3 AD8063ARTZ-REEL7 –40°C to +85°C 6-Lead SOT-23, 7-Inch Tape and Reel RJ-6 H0E 1 Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked. 2 New branding after data code 0542, previously branded HGA. 3 New branding after data code 0542, previously branded HHA. ©1999–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01065-0-2/10(G) Rev. G | Page 20 of 20