ANALOG DEVICES AD8054

Low Cost, High Speed, Rail-to-Rail Amplifiers AD8051/AD8052/AD8054 FEATURES PIN CONNECTIONS (TOP VIEWS) High speed and fast settling on 5 V AD8051 1 8 NC NC AD8051 110 MHz, −3 dB bandwidth (G = +1) (AD8051/AD8052) V 1 5 OUT +V S 2 7 +V –IN S 150 MHz, −3 dB bandwidth (G = +1) (AD8054) –V S 2 +IN 3 6 V +– OUT 145 V/μs slew rate –V S 4 5 NC +IN 3 4 –IN 50 ns settling time to 0.1% NC = NO CONNECT Single-supply operation Figure 1. SOIC-8 (R) Figure 2. SOT-23-5 (RJ) Output swings to within 25 mV of either rail Input voltage range: −0.2 V to +4 V; V = 5 V S Video specifications (G = +2) 1 14 OUT D OUT A 0.1 dB gain flatness: 20 MHz; R = 150 Ω L 2 13 AD8052 –IN A –IN D 1 8 +V OUT1 S Differential gain/phase: 0.03%/0.03° 3 12 +IN D +IN A –IN1 2 – 7 OUT + Low distortion V+ 4 AD8054 11 V– +IN1 3 6 –IN2 – 5 10 +IN C +IN B −80 dBc total harmonic @ 1 MHz, R = 100 Ω L –V + 5 +IN2 S 4 –IN B 6 9 –IN C Outstanding load drive capability 7 8 OUT B OUT C Drives 45 mA, 0.5 V from supply rails (AD8051/AD8052) Drives 50 pF capacitive load (G = +1) (AD8051/AD8052) Figure 3. SOIC (R-8) and MSOP (RM-8) Figure 4. SOIC (R-14) and TSSOP (RU-14) Low power: 2.75 mA/amplifier (AD8054) Low power: 4.4 mA/amplifier (AD8051/AD8052) 5.0 APPLICATIONS 4.5 V = 5V S G = –1 Active filters 4.0 R = 2kΩ F Analog-to-digital drivers R = 2kΩ 3.5 L Clock buffer 3.0 Consumer video 2.5 Professional cameras 2.0 CCD imaging systems 1.5 CD/DVD ROMs 1.0 0.5 0 0.1 1 10 50 FREQUENCY (MHz) Figure 5. Low Distortion Rail-to-Rail Output Swing GENERAL DESCRIPTION The AD8051 (single), AD8052 (dual), and AD8054 (quad) are The AD8051/AD8052/AD8054 are well suited for video low cost, high speed, voltage feedback amplifiers. The amplifiers electronics, cameras, video switchers, or any high speed portable operate on +3 V, +5 V, or ±5 V supplies at low supply current. equipment. Low distortion and fast settling make them ideal for They have true single-supply capability with an input voltage active filter applications. range extending 200 mV below the negative rail and within 1 V The AD8051/AD8052 in the 8-lead SOIC, the AD8052 in the of the positive rail. MSOP, the AD8054 in the 14-lead SOIC, and the 14-lead TSSOP packages are available in the extended temperature range of Despite their low cost, the AD8051/AD8052/AD8054 provide excellent overall performance and versatility. The output voltage −40°C to +125°C. swings to within 25 mV of each rail, providing maximum output dynamic range with excellent overdrive recovery. Rev. J Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PEAK-TO-PEAK OUTPUT VOLTAGE SWING (THD ≤ 0.5%) (V) 01062-001 01062-003 01062-005 01062-002 01062-004 AD8051/AD8052/AD8054 TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Description .................................................................... 16  Applications ....................................................................................... 1  Application Information ................................................................ 17  Pin Connections (Top Views) ......................................................... 1  Overdrive Recovery ................................................................... 17  General Description ......................................................................... 1  Driving Capacitive Loads .......................................................... 17  Revision History ............................................................................... 2  Layout Considerations ............................................................... 18  Specif ica t ions ..................................................................................... 3  Active Filters ............................................................................... 18  Absolute Maximum Ratings ............................................................ 9  Analog-to-Digital and Digital-to-Analog Applications ........ 19  Thermal Resistance ...................................................................... 9  Sync Stripper ............................................................................... 20  Maximum Power Dissipation ..................................................... 9  Single-Supply Composite Video Line Driver ......................... 20  ESD Caution .................................................................................. 9  Outline Dimensions ....................................................................... 21  Typical Performance Characteristics ........................................... 10  Ordering Guide .......................................................................... 23  Theory of Operation ...................................................................... 16  REVISION HISTORY 7/09—Rev. I to Rev. J 2/03—Rev. C to Rev. D Changes to Figure 22 ...................................................................... 12 Changes to General Description ..................................................... 1 Changes to Specifications ................................................................. 3 12/08—Rev. H to Rev. I Changes to Absolute Maximum Ratings ........................................ 6 Change to Settling Time to 0.1% Parameter, Table 1 ................... 3 1/03—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 20 Changes to General Description ..................................................... 1 Changes to Pin Connections ............................................................ 1 12/07—Rev. G to Rev. H Changes to Specifications ................................................................. 2 Changes to Applications .................................................................. 1 Changes to Absolute Maximum Ratings ........................................ 9 Updated Outline Dimensions ....................................................... 21 Changes to Figure 2 ........................................................................... 9 Changes to Ordering Guide .......................................................... 23 Changes to Ordering Guide ............................................................. 9 5/06—Rev. F to Rev. G Updated Outline Dimensions ........................................................ 20 Updated Format .................................................................. Universal Changes to Features, Applications, and General Description ..... 1 Changes to Figure 15 ...................................................................... 12 Changes to the Ordering Guide .................................................... 22 9/04—Rev. E to Rev. F Changes to Ordering Guide ............................................................. 7 Changes to Figure 15 ...................................................................... 15 3/04—Rev. D to Rev. E Changes to General Description ..................................................... 2 Changes to Specifications ................................................................. 3 Changes to Ordering Guide ............................................................. 6 Rev. J | Page 2 of 24 AD8051/AD8052/AD8054 SPECIFICATIONS @ TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted. Table 1. AD8051A/AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, VOUT = 0.2 V p-p 70 110 80 150 MHz G = −1, +2, VOUT = 0.2 V p-p 50 60 MHz Bandwidth for 0.1 dB Flatness G = +2, V = 0.2 V p-p, OUT R = 150 Ω to 2.5 V L 20 MHz RF = 806 Ω (AD8051A/ AD8052A) RF = 200 Ω (AD8054A) 12 MHz Slew Rate G = −1, VOUT = 2 V step 100 145 140 170 V/μs Full Power Response G = +1, V = 2 V p-p 35 45 MHz OUT Settling Time to 0.1% G = −1, V = 2 V step 50 40 ns OUT NOISE/DISTORTION PERFORMANCE 1 Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, −67 −68 dB C OUT G = +2 Input Voltage Noise f = 10 kHz 16 16 nV/√Hz Input Current Noise f = 10 kHz 850 850 fA/√Hz Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.09 0.07 % R = 1 kΩ to 2.5 V 0.03 0.02 % L Differential Phase Error (NTSC) G = +2, R = 150 Ω to 2.5 V 0.19 0.26 Degrees L R = 1 kΩ to 2.5 V 0.03 0.05 Degrees L Crosstalk f = 5 MHz, G = +2 −60 −60 dB DC PERFORMANCE Input Offset Voltage 1.7 10 1.7 12 mV TMIN − TMAX 25 30 mV Offset Drift 10 15 μV/°C Input Bias Current 1.4 2.5 2 4.5 μA T − T 3.25 4.5 μA MIN MAX Input Offset Current 0.1 0.75 0.2 1.2 μA Open-Loop Gain RL = 2 kΩ to 2.5 V 86 98 82 98 dB TMIN − TMAX 96 96 dB RL = 150 Ω to 2.5 V 76 82 74 82 dB T − T 78 78 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 290 300 kΩ Input Capacitance 1.4 1.5 pF Input Common-Mode Voltage Range −0.2 to −0.2 to V +4 +4 Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 72 88 70 86 dB Rev. J | Page 3 of 24 AD8051/AD8052/AD8054 AD8051A/AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kΩ to 2.5 V 0.015 to 0.03 to V L 4.985 4.975 R = 2 kΩ to 2.5 V V L 0.1 to 0.025 to 0.125 to 0.05 to 4.9 4.975 4.875 4.95 RL = 150 Ω to 2.5 V 0.3 to 0.2 to 0.55 to 0.25 to V 4.625 4.8 4.4 4.65 Output Current V = 0.5 V to 4.5 V 45 30 mA OUT T − T 45 30 mA MIN MAX Short-Circuit Current Sourcing 80 45 mA Sinking 130 85 mA Capacitive Load Drive G = +1 (AD8051/AD8052) 50 pF G = +2 (AD8054) 40 pF POWER SUPPLY Operating Range 3 12 3 12 V Quiescent Current/Amplifier 4.4 5 2.75 3.275 mA Power Supply Rejection Ratio ΔV = ±1 V 70 80 68 80 dB S OPERATING TEMPERATURE RANGE RJ-5 −40 +85 °C RM-8, R-8, RU-14, R-14 −40 +125 −40 +125 °C 1 Refer to Figure 19. Rev. J | Page 4 of 24 AD8051/AD8052/AD8054 @ T = 25°C, V = 3 V, R = 2 kΩ to 1.5 V, unless otherwise noted. A S L Table 2. AD8051A/AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, V = 0.2 V p-p 70 110 80 135 MHz OUT G = −1, +2, VOUT = 50 65 MHz 0.2 V p-p Bandwidth for 0.1 dB Flatness G = +2, VOUT = 0.2 V p-p, R = 150 Ω to 2.5 V L R = 402 Ω (AD8051A/ 17 MHz F AD8052A) RF = 200 Ω (AD8054A) 10 MHz Slew Rate G = −1, VOUT = 2 V step 90 135 110 150 V/μs Full Power Response G = +1, VOUT = 1 V p-p 65 85 MHz Settling Time to 0.1% G = −1, V = 2 V step 55 55 ns OUT NOISE/DISTORTION PERFORMANCE 1 Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, −47 −48 dB C OUT G = −1, R = 100 Ω to 1.5 V L Input Voltage Noise f = 10 kHz 16 16 nV/√Hz Input Current Noise f = 10 kHz 600 600 fA/√Hz Differential Gain Error (NTSC) G = +2, VCM = 1 V RL = 150 Ω to 1.5 V 0.11 0.13 % R = 1 kΩ to 1.5 V 0.09 0.09 % L Differential Phase Error (NTSC) G = +2, V = 1 V CM R = 150 Ω to 1.5 V 0.24 0.3 Degrees L RL = 1 kΩ to 1.5 V 0.10 0.1 Degrees Crosstalk f = 5 MHz, G = +2 −60 −60 dB DC PERFORMANCE Input Offset Voltage 1.6 10 1.6 12 mV TMIN − TMAX 25 30 mV Offset Drift 10 15 μV/°C Input Bias Current 1.3 2.6 2 4.5 μA T − T 3.25 4.5 μA MIN MAX Input Offset Current 0.15 0.8 0.2 1.2 μA Open-Loop Gain RL = 2 kΩ 80 96 80 96 dB TMIN − TMAX 94 94 dB R = 150 Ω 74 82 72 80 dB L T − T 76 76 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 290 300 kΩ Input Capacitance 1.4 1.5 pF Input Common-Mode Voltage Range V −0.2 to −0.2 to +2 +2 Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 72 88 70 86 dB Rev. J | Page 5 of 24 AD8051/AD8052/AD8054 AD8051A/AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kΩ to 1.5 V 0.01 to 0.025 to V L 2.99 2.98 R = 2 kΩ to 1.5 V V L 0.0.75 to 0.02 to 0.1 to 0.35 to 2.9 2.98 2.9 2.965 RL = 150 Ω to 1.5 V 0.2 to 0.125 to 0.35 to 0.15 to V 2.75 2.875 2.55 2.75 Output Current V = 0.5 V to 2.5 V 45 25 mA OUT T − T 45 25 mA MIN MAX Short-Circuit Current Sourcing 60 30 mA Sinking 90 50 mA Capacitive Load Drive G = +1 (AD8051/AD8052) 45 pF G = +2 (AD8054) 35 pF POWER SUPPLY Operating Range 3 12 3 12 V Quiescent Current/Amplifier 4.2 4.8 2.625 3.125 mA Power Supply Rejection Ratio ΔV = 0.5 V 68 80 68 80 dB S OPERATING TEMPERATURE RANGE RJ-5 −40 +85 °C RM-8, R-8, RU-14, R-14 −40 +125 −40 +125 °C 1 Refer to Figure 19. Rev. J | Page 6 of 24 AD8051/AD8052/AD8054 @ T = 25°C, V = ±5 V, R = 2 kΩ to ground, unless otherwise noted. A S L Table 3. AD8051A/AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, V = 0.2 V p-p 70 110 85 160 MHz OUT G = −1, +2, VOUT = 0.2 V p-p 50 65 MHz Bandwidth for 0.1 dB Flatness G = +2, VOUT = 0.2 V p-p, RL = 150 Ω, R = 1.1 kΩ (AD8051A/ 20 MHz F AD8052A) R = 200 Ω (AD8054A) 15 MHz F Slew Rate G = −1, VOUT = 2 V step 105 170 150 190 V/μs Full Power Response G = +1, VOUT = 2 V p-p 40 50 MHz Settling Time to 0.1% G = −1, VOUT = 2 V step 50 40 MHz NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion fC = 5 MHz, VOUT = 2 V p-p, −71 −72 dB G = +2 Input Voltage Noise f = 10 kHz 16 16 nV/√Hz Input Current Noise f = 10 kHz 900 900 fA/√Hz Differential Gain Error (NTSC) G = +2, RL = 150 Ω 0.02 0.06 % RL = 1 kΩ 0.02 0.02 % Differential Phase Error (NTSC) G = +2, RL = 150 Ω 0.11 0.15 Degrees R = 1 kΩ 0.02 0.03 Degrees L Crosstalk f = 5 MHz, G = +2 −60 −60 dB DC PERFORMANCE Input Offset Voltage 1.8 11 1.8 13 mV T − T 27 32 mV MIN MAX Offset Drift 10 15 μV/°C Input Bias Current 1.4 2.6 2 4.5 μA TMIN − TMAX 3.5 4.5 μA Input Offset Current 0.1 0.75 0.2 1.2 μA Open-Loop Gain R = 2 kΩ 88 96 84 96 dB L T − T 96 96 dB MIN MAX RL = 150 Ω 78 82 76 82 dB TMIN − TMAX 80 80 dB INPUT CHARACTERISTICS Input Resistance 290 300 kΩ Input Capacitance 1.4 1.5 pF Input Common-Mode Voltage Range −5.2 to −5.2 to V +4 +4 Common-Mode Rejection Ratio V = −5 V to +3.5 V 72 88 70 86 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kΩ −4.98 to −4.97 to V L +4.98 +4.97 RL = 2 kΩ −4.85 to −4.97 to −4.8 to −4.9 to V +4.85 +4.97 +4.8 +4.9 RL = 150 Ω −4.45 to −4.6 to −4.0 to −4.5 to V +4.3 +4.6 +3.8 +4.5 Output Current V = −4.5 V to +4.5 V 45 30 mA OUT T − T 45 30 mA MIN MAX Short-Circuit Current Sourcing 100 60 mA Sinking 160 100 mA Capacitive Load Drive G = +1 (AD8051/AD8052) 50 pF G = +2 (AD8054) 40 pF Rev. J | Page 7 of 24 AD8051/AD8052/AD8054 AD8051A/AD8052A AD8054A Parameter Conditions Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range 3 12 3 12 V Quiescent Current/Amplifier 4.8 5.5 2.875 3.4 mA Power Supply Rejection Ratio ΔV = ±1 68 80 68 80 dB S OPERATING TEMPERATURE RANGE RJ-5 −40 +85 °C RM-8, R-8, RU-14, R-14 −40 +125 −40 +125 °C Rev. J | Page 8 of 24 AD8051/AD8052/AD8054 ABSOLUTE MAXIMUM RATINGS Table 4. MAXIMUM POWER DISSIPATION Parameter Ratings The maximum power that can be safely dissipated by the Supply Voltage 12.6 V AD8051/AD8052/AD8054 is limited by the associated rise in 1 Internal Power Dissipation junction temperature. The maximum safe junction temperature SOIC Packages Observe power for plastic encapsulated devices is determined by the glass derating curves transition temperature of the plastic, approximately 150°C. SOT-23 Package Observe power Temporarily exceeding this limit can cause a shift in parametric derating curves performance due to a change in the stresses exerted on the die MSOP Package Observe power by the package. Exceeding a junction temperature of 175°C for derating curves an extended period can result in device failure. TSSOP Package Observe power derating curves While the AD8051/AD8052/AD8054 are internally short- Input Voltage (Common Mode) ±VS circuit protected, this cannot be sufficient to guarantee that the Differential Input Voltage ±2.5 V maximum junction temperature (150°C) is not exceeded under Output Short-Circuit Duration Observe power all conditions. To ensure proper operation, it is necessary to derating curves observe the maximum power derating curves. Storage Temperature Range (R) −65°C to +150°C 2.5 Operating Temperature Range (A Grade) −40°C to +125°C Lead Temperature (Soldering 10 sec) 300°C SOIC-14 2.0 1 TSSOP-14 See Table 5. Stresses above those listed under Absolute Maximum Ratings SOIC-8 1.5 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any 1.0 other conditions above those indicated in the operational MSOP-8 section of this specification is not implied. Exposure to absolute 0.5 maximum rating conditions for extended periods may affect SOT-23-5 device reliability. 0 THERMAL RESISTANCE –55 –35 –15 5 15 35 55 75 95 115 AMBIENT TEMPERATURE (°C) Specification is for device in free air. Figure 6. Maximum Power Dissipation vs. Temperature for AD8051/AD8052/AD8054 Table 5. Thermal Resistance Package Type θ Unit ESD CAUTION JA 8-Lead SOIC 125 °C/W 5-Lead SOT-23 180 °C/W 8-Lead MSOP 150 °C/W 14-Lead SOIC 90 °C/W 14-Lead TSSOP 120 °C/W Rev. J | Page 9 of 24 MAXIMUM POWER DISSIPATION (W) 01062-006 AD8051/AD8052/AD8054 TYPICAL PERFORMANCE CHARACTERISTICS 3 5 G = +1 V = 5V S 4 G = +2 2 R = 0 G = +2 F GAIN AS SHOWN R = 2kΩ F R = 2kΩ 3 R AS SHOWN F F 1 R = 5kΩ L 2 V = 0.2V p-p OUT 0 1 G = +5 –1 R = 2kΩ F 0 G = +1 G = +10 R = 0 –2 F –1 R = 2kΩ F –2 –3 G = +10 R = 2kΩ F –3 V = 5V –4 S GAIN AS SHOWN –4 R AS SHOWN –5 F –5 R = 2kΩ L G = +5 V = 0.2V p-p –6 OUT –6 R = 2kΩ F –7 –7 0.1 1 10 100 500 100k 1M 10M 100M 500M FREQUENCY (MHz) FREQUENCY (Hz) Figure 7. AD8051/AD8052 Normalized Gain vs. Frequency; VS = 5 V Figure 10. AD8054 Normalized Gain vs. Frequency; VS = 5 V 3 6 V AS SHOWN S G=+1 2 5 G=+1 +3V R =2kΩ V = +3V V = +5V L S S R =2kΩ L C = 5pF L 1 4 +5V V =0.2V p-p OUT =0.2V p-p V OUT 0 3 ±5V –1 2 V = ±5V S –2 1 –3 0 ±5V –4 –1 –5 –2 +3V –6 –3 +5V –7 –4 0.1 1 10 100 500 100k 1M 10M 100M 500M FREQUENCY (MHz) FREQUENCY (Hz) Figure 8. AD8051/AD8052 Gain vs. Frequency vs. Supply Figure 11. AD8054 Gain vs. Frequency vs. Supply 4 3 V = 5V S +85°C 2 R = 2kΩ TO 2.5V 3 L +25°C C = 5pF –40°C L 1 2 G = +1 –40°C V = 0.2V p-p OUT 0 1 +85°C –1 +25°C 0 –2 –1 –3 –2 V = 5V –4 S G= +1 –3 –5 R =2kΩ L V =0.2Vp-p OUT –4 –6 TEMPERATURE AS SHOWN –7 –5 0.1 1 10 100 500 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. AD8054 Gain vs. Frequency vs. Temperature Figure 9. AD8051/AD8052 Gain vs. Frequency vs. Temperature Rev. J | Page 10 of 24 GAIN (dB) NORMALIZED GAIN (dB) GAIN (dB) 01062-008 01062-009 01062-007 NORMALIZED GAIN (dB) GAIN (dB) GAIN (dB) 01062-012 01062-011 01062-010 AD8051/AD8052/AD8054 6.3 6.3 6.2 6.2 6.1 6.1 6.0 6.0 5.9 5.9 5.8 5.8 5.7 5.7 V = 5V V = 5V S S 5.6 5.6 G = +2 R = 200Ω F R = 150Ω R = 150Ω L L 5.5 5.5 R = 806Ω G = +2 F V = 0.2V p-p 5.4 OUT 5.4 V = 0.2V p-p OUT 5.3 5.3 0.1 1 10 100 11 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. AD8051/AD8052 0.1 dB Gain Flatness vs. Frequency; G = +2 Figure 16. AD8054 0.1 dB Gain Flatness vs. Frequency; G = +2 9 9 V = +5V S 8 V = +5V 8 S V = 2V p-p OUT V = 2V p-p OUT 7 7 6 6 5 5 4 4 V = ±5V S V = 4V p-p OUT V = ±5V 3 3 S V = 4V p-p OUT V AS SHOWN V AS SHOWN S S 2 2 G = +2 G = +2 R = 2kΩ R = 2kΩ F F 1 1 R = 2kΩ R = 2kΩ L L V AS SHOWN V AS SHOWN OUT OUT 0 0 –1 –1 0.1 1 10 100 500 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 14. AD8051/AD8052 Large Signal Frequency Response; G = +2 Figure 17. AD8054 Large Signal Frequency Response; G = +2 80 80 V = 5V V = 5V S S 70 70 R = 2kΩ R = 2kΩ L L 60 60 C = 5pF L 50 50 40 40 GAIN GAIN 0 180 30 30 50° PHASE –45 135 20 20 MARGIN PHASE 45° PHASE PHASE MARGIN 90 –90 10 10 0 0 –135 45 0 –10 –180 –10 –20 –20 30k 100k 1M 10M 100M 500M 0.01 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (Hz) Figure 18. AD8054 Open-Loop Gain and Phase Margin vs. Frequency Figure 15. AD8051/AD8052 Open-Loop Gain and Phase vs. Frequency Rev. J | Page 11 of 24 OPEN-LOOP GAIN (dB) GAIN FLATNESS (dB) GAIN (dB) PHASE MARGIN (Degrees) 01062-014 01062-013 01062-015 OPEN-LOOP GAIN (dB) GAIN FLATNESS (dB) GAIN (dB) PHASE MARGIN (Degrees) 01062-017 01062-016 01062-018 AD8051/AD8052/AD8054 1000 –20 V = 2V p-p V = 3V, G = –1 V = 5V OUT S S R = 2kΩ, R = 100Ω –30 F L V = 5V, G = +2 S –40 R = 2kΩ, R = 100Ω F L V = 5V, G = +1 S –50 100 R = 100Ω L –60 –70 V = 5V, G = +1 S –80 10 R = 2kΩ L V = 5V, G = +2 –90 S R = 2kΩ, R = 2kΩ F L –100 1 –110 12 345678910 10 100 1k 10k 100k 1M 10M FUNDAMENTAL FREQUENCY (MHz) FREQUENCY (Hz) Figure 22. Input Voltage Noise vs. Frequency Figure 19. Total Harmonic Distortion 100 –30 V = 5V S –40 10MHz –50 –60 10 –70 –80 5MHz –90 –100 1MHz 1 V = 5V S –110 R = 2kΩ L –120 G = +2 –130 0.1 –140 10 100 1k 10k 100k 1M 10M 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 FREQUENCY (Hz) OUTPUT VOLTAGE (V p-p) Figure 23. Input Current Noise vs. Frequency Figure 20. Worst Harmonic vs. Output Voltage 0.10 0.10 NTSC SUBSCRIBER (3.58MHz) NTSC SUBSCRIBER (3.58MHz) R = 150Ω L 0.08 R = 1kΩ L 0.05 0.06 0.04 0.00 0.02 0.00 R = 1kΩ –0.05 V = 5V, G = +2 –0.02 L V = 5V, G = +2 S S R = 2kΩ, R AS SHOWN –0.04 R = 150Ω R = 2kΩ, R AS SHOWN F L F L L –0.10 –0.06 ST ND RD TH TH TH TH TH TH TH TH 1 2 3 4 5 6 7 8 9 10 11 0 102030 40506070 80 90 100 0.3 0.10 R = 1kΩ L 0.2 0.05 0.00 0.1 R = 1kΩ L –0.05 0.0 R = 150Ω L –0.10 –0.1 R = 150Ω L –0.15 V = 5V, G = +2 V = 5V, G = +2 S S –0.2 R = 2kΩ, R AS SHOWN –0.20 R = 2kΩ, R AS SHOWN F L F L –0.3 –0.25 ST ND RD TH TH TH TH TH TH TH TH 1 2 3 4 5 6 7 8 9 10 11 0 102030 40506070 80 90 100 MODULATING RAMP LEVEL (IRE) MODULATING RAMP LEVEL (IRE) Figure 24. AD8054 Differential Gain and Phase Errors Figure 21. AD8051/AD8052 Differential Gain and Phase Errors Rev. J | Page 12 of 24 DIFFERENTIAL DIFFERENTIAL WORST HARMONIC (dBc) PHASE ERROR (Degrees) GAIN ERROR (%) TOTAL HARMONIC DISTORTION (dBc) 01062-019 01062-020 01062-021 DIFFERENTIAL DIFFERENTIAL VOLTAGE NOISE (nV/√Hz) CURRENT NOISE (pA/√Hz) PHASE ERROR (Degrees) GAIN ERROR (%) 01062-023 01062-022 01062-024 AD8051/AD8052/AD8054 –10 –10 V = ±5V V = 5V S S –20 –20 R = 1kΩ R = 2kΩ F F R =AS SHOWN R = 2kΩ L L –30 V = 2V p-p –30 V = 2V p-p OUT OUT –40 –40 R = 100Ω L –50 –50 –60 –60 –70 R = 1kΩ –70 L –80 –80 –90 –90 –100 –110 –100 0.1 1 10 100 500 0.1 110 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. AD8052 Crosstalk (Output-to-Output) vs. Frequency Figure 28. AD8054 Crosstalk (Output-to-Output) vs. Frequency 0 20 V = 5V V = 5V S S –10 10 –20 0 –30 –10 –PSRR –40 –20 –30 –50 –40 +PSRR –60 –50 –70 –80 –60 –70 –90 –100 –80 0.03 0.1 1 10 100 500 0.01 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. PSRR vs. Frequency Figure 26. CMRR vs. Frequency 100.000 70 V =5V V = 5V S S G = +1 G = –1 31.000 60 R = 2kΩ L 10.000 50 AD8051/AD8052 3.100 40 1.000 AD8054 30 0.310 20 0.100 10 0.031 0.010 0 0.1 1 10 100 500 0.5 1.0 1.5 2.0 FREQUENCY (MHz) INPUT STEP (V p-p) Figure 27. Closed-Loop Output Resistance vs. Frequency Figure 30. Settling Time vs. Input Step Rev. J | Page 13 of 24 OUTPUT RESISTANCE (Ω) CMRR (dB) CROSSTALK (dB) 01062-025 01062-026 01062-027 PSRR (dB) CROSSTALK (dB) SETTLING TIME TO 0.1% (ns) 01062-030 01062-029 01062-028 AD8051/AD8052/AD8054 1.0 1.000 V = 5V S V = +85°C V = 5V OH S 0.9 +5V – V (+125°C) OH 0.875 0.8 V = +25°C OH 0.750 +5V – V (+25°C) 0.7 OH V = –40°C OH V = +85°C OL 0.625 0.6 +5V – V (–40°C) OH 0.5 0.500 0.4 0.375 0.3 V = +25°C OL 0.250 0.2 V (+125°C) OL V = –40°C OL 0.125 V (+25°C) 0.1 OL V (–40°C) OL 0 0 0 3 6 9 12 15 18 21 24 27 30 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 31. AD8051/AD8052 Output Saturation Voltage vs. Load Current Figure 33. AD8054 Output Saturation Voltage vs. Load Current 100 R = 2kΩ L 90 R = 150Ω L 80 70 V = 5V S 60 05 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5.0 OUTPUT VOLTAGE (V) Figure 32. Open-Loop Gain vs. Output Voltage Rev. J | Page 14 of 24 OPEN-LOOP GAIN (dB) OUTPUT SATURATION VOLTAGE (V) 01062-032 01062-031 OUTPUT SATURATION VOLTAGE (V) 01062-033 AD8051/AD8052/AD8054 V = 5V V = 0.1V p-p S IN G = –1 G = +1 R = 2kΩ R = 2kΩ F L 5.0 R = 2kΩ V = 3V L S 1.5 2.5 20ns 2µs 20mV 1V Figure 34. 100 mV Step Response, G = +1 Figure 37. Output Swing; G = −1, R = 2 kΩ L V = 5V S V = 5V S G = +1 G = +1 R = 2kΩ L R = 2kΩ L 2.6 2.55 2.50 2.5 2.4 2.45 50mV 20ns 50mV 40ns Figure 35. AD8051/AD8052 200 mV Step Response; V = 5 V, G = +1 Figure 38. AD8054 100 mV Step Response; V = 5 V, G = +1 S S V = ±5V V = 1V p-p S IN 4.5 4 G = +1 G = +2 R = 2kΩ R = 2kΩ L L 3 V = 5V S 3.5 2 1 2.5 –1 –2 1.5 –3 0.5 –4 1V 20ns 500mV 20ns Figure 36. Large Signal Step Response; V = 5 V, G = +2 S Figure 39. Large Signal Step Response; V = ±5 V, G = +1 S Rev. J | Page 15 of 24 VOLTS VOLTS VOLTS 01062-036 01062-034 01062-035 VOLTS VOLTS VOLTS 01062-037 01062-038 01062-039 AD8051/AD8052/AD8054 THEORY OF OPERATION The inputs of the device can handle voltages from −0.2 V below CIRCUIT DESCRIPTION the negative rail to within 1 V of the positive rail. Exceeding The AD8051/AD8052/AD8054 are fabricated on the Analog these values do not cause phase reversal; however, the input Devices, Inc. proprietary eXtra-Fast Complementary Bipolar ESD devices begin to conduct if the input voltages exceed the (XFCB) process, which enables the construction of PNP and rails by greater than 0.5 V. During this overdrive condition, the NPN transistors with similar fTs in the 2 GHz to 4 GHz region. output stays at the rail. The process is dielectrically isolated to eliminate the parasitic The rail-to-rail output range of the AD8051/AD8052/AD8054 and latch-up problems caused by junction isolation. These is provided by a complementary common emitter output stage. features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential High output drive capability is provided by injecting all output output input stage to maximize bandwidth and headroom (see stage predriver currents directly into the bases of the output Figure 40). The smaller signal swings required on the first stage devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by outputs (nodes SIP, SIN) reduce the effect of nonlinear currents I8 and I5, along with a common-mode feedback loop (not shown). This circuit topology allows the AD8051/AD8052 to due to junction capacitances and improve the distortion per- drive 45 mA of output current and allows the AD8054 to drive formance. This design achieves harmonic distortion of −80 dBc 30 mA of output current with the outputs within 0.5 V of the @ 1 MHz into 100 Ω with VOUT = 2 V p-p (gain = +1) on a supply rails. single 5 V supply. V CC I9 Q25 Q50 R26 R39 I10 I2 I3 Q36 Q4 Q5 Q39 I5 Q51 Q23 V Q40 EE R15 R2 Q22 R23 R27 V EE C3 Q31 Q7 V P IN Q13 Q1 V OUT Q21 Q27 V N IN C9 SIP SIN Q2 Q11 Q8 Q3 Q24 Q47 I8 I11 I7 C7 R21 V R5 R3 CC V EE Figure 40. AD8051/AD8052 Simplified Schematic Rev. J | Page 16 of 24 01062-045 AD8051/AD8052/AD8054 APPLICATION INFORMATION OVERDRIVE RECOVERY V = 5V S Overdrive of an amplifier occurs when the output and/or input G = +1 R = 2kΩ L range is exceeded. The amplifier must recover from this over- C = 50pF L 2.60 drive condition. As shown in Figure 41, the AD8051/AD8052/ 2.55 AD8054 recover within 60 ns from negative overdrive and within 45 ns from positive overdrive. 2.50 2.45 V = ±5V S 2.40 G = +5 INPUT 1V/DIV = 2kΩ R F R = 2kΩ L OUTPUT 2V/DIV 100ns 50mV Figure 43. AD8051/AD8052 200 mV Step Response; CL = 50 pF 10000 V = 5V S ≤ 30% OVERSHOOT R = 3Ω S V/DIV AS SHOWN 100ns 1000 R = 0Ω S Figure 41. Overdrive Recovery DRIVING CAPACITIVE LOADS 100 Consider the AD8051/AD8052 in a closed-loop gain of +1 with R R G F +VS = 5 V and a load of 2 kΩ in parallel with 50 pF. Figure 42 R S V IN 10 V and Figure 43 show their frequency and time domain responses, OUT 100mV C L STEP 50Ω respectively, to a small-signal excitation. The capacitive load drive of the AD8051/AD8052/AD8054 can be increased by 1 adding a low value resistor in series with the load. Figure 44 123 4 56 A (V/V) CL and Figure 45 show the effect of a series resistor on the capaci- Figure 44. AD8051/AD8052 Capacitive Load Drive vs. Closed-Loop Gain tive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less peaking. Adding a series resistor with lower 1000 closed-loop gains accomplishes the same effect. For large V = 5V S ≤ 30% capacitive loads, the frequency response of the amplifier is OVERSHOOT dominated by the roll-off of the series resistor and the load R = 10Ω S capacitance. 8 R = 0Ω S 6 100 4 R R G F 2 R S V IN 0 V OUT 100mV C L STEP 50Ω –2 –4 10 V = 5V S 123 4 56 –6 G = +1 A (V/V) CL R = 2kΩ L –8 Figure 45. AD8054 Capacitive Load Drive vs. Closed-Loop Gain C = 50pF L V = 200mV p-p OUT –10 –12 0.1 110 100 500 FREQUENCY (MHz) Figure 42. AD8051/AD8052 Closed-Loop Frequency Response; CL = 50 pF Rev. J | Page 17 of 24 VOLTS GAIN (dB) 01062-041 01062-040 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) VOLTS 01062-044 01062-042 01062-043 AD8051/AD8052/AD8054 noise bandwidth of the analog signal before analog-to-digital LAYOUT CONSIDERATIONS conversion. The specified high speed performance of the AD8051/AD8052/ Note that the unused amplifier’s inputs should be tied to ground. AD8054 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic R6 1kΩ component selection are necessary. C1 50pF The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low R2 13 R4 2kΩ C2 14 2kΩ impedance path. The ground plane should be removed from the R1 50pF 12 3kΩ R3 2 V area near the input pins to reduce parasitic capacitance. IN 2kΩ R5 1 6 2kΩ 3 7 9 Chip capacitors should be used for supply bypassing. One end 5 8 AD8054 10 should be connected to the ground plane and the other within AD8054 AD8054 3 mm of each power pin. An additional large (4.7 μF to 10 μF) BAND-PASS FILTER OUTPUT tantalum electrolytic capacitor should be connected in parallel, Figure 46. 2 MHz Biquad Band-Pass Filter Using AD8054 but not necessarily so close, to supply current for fast, large signal changes at the output. The frequency response of the circuit is shown in Figure 47. 0 The feedback resistor should be located close to the inverting input pin to keep the parasitic capacitance at this node to a minimum. Parasitic capacitance of less than 1 pF at the inverting –10 input can significantly affect high speed performance. Stripline design techniques should be used for long signal traces –20 (greater than about 25 mm). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end. –30 ACTIVE FILTERS Active filters at higher frequencies require wider bandwidth op –40 amps to work effectively. Excessive phase shift produced by 10k 100k 1M 10M 100M lower frequency op amps can significantly affect active filter FREQUENCY (Hz) performance. Figure 47. Frequency Response of 2 MHz Band-Pass Biquad Filter Figure 46 shows an example of a 2 MHz biquad bandwidth filter that uses three op amps of an AD8054. Such circuits are sometimes used in medical ultrasound systems to lower the Rev. J | Page 18 of 24 GAIN (dB) 01062-047 01062-046 AD8051/AD8052/AD8054 reduced to −60.18 dB and the ADC operated with 8.46 ENOBs ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG as shown in Figure 49. The inclusion of the AD8051 in the APPLICATIONS circuit did not worsen the distortion performance of the AD9201. Figure 50 is a schematic showing the AD8051 used as a driver 10 PART# 0 for an AD9201, a 10-bit, 20 MSPS, dual analog-to-digital FUND 0 FFTSIZE 8192 converter. This converter is designed to convert I and Q signals in FCLK 20.0MHz –10 998.5kHz FUND communications systems. In this application, only the I channel –20 VIN –0.51dB is being driven. The I channel is enabled by applying a logic –68.13 –30 THD SNR 54.97 high to SELECT (Pin 13). –40 SINAD 54.76 –50 ENOB 8.80 The AD8051 is running from a dual supply and is configured SFDR 71.66 –60 2ND –74.53 for a gain of +2. The input signal is terminated in 50 Ω and the –70 2ND 7TH 3RD 4TH 3RD –76.06 9TH 5TH 8TH 6TH output is 2 V p-p, which is the maximum input range of the –80 4TH –76.35 5TH –79.05 AD9201. The 22 Ω series resistor limits the maximum current –90 6TH –80.36 –100 that flows and helps to lower the distortion of the ADC. 7TH –75.08 8TH –88.12 –110 The AD9201 has differential inputs for each channel. These are 9TH –77.87 –120 0 1 2 3 45 67 8 9 10 designated the A and B inputs. The B inputs of each channel are FREQUENCY (MHz) connected to VREF (Pin 22), which supplies a positive reference Figure 48. FFT Plot for AD8051 Driving the AD9201 at 1 MHz of 2.5 V. Each of the B inputs has a small low-pass filter that also helps to reduce distortion. 10 PART# 0 FUND The output of the op amp is ac-coupled into INA-I (Pin 16) via 0 FFTSIZE 8192 FCLK 20.0MHz two parallel capacitors to provide good high frequency and low –10 FUND 9.5MHz frequency coupling. The 1 kΩ resistor references the signal to –20 VIN –0.44dB THD –57.08 –30 VREF that is applied to INB-I. Thus, INA-I swings both positive SNR 54.65 –40 and negative with respect to the bias voltage applied to INB-I. SINAD 52.69 –50 ENOB 8.46 2ND 3RD SFDR 60.18 With the sampling clock running at 20 MSPS, the analog-to- –60 2ND –60.18 –70 digital output was analyzed with a digital analyzer. Two input 7TH 3RD –60.23 4TH 8TH 5TH 6TH 4TH –82.01 –80 frequencies were used, 1 MHz and 9.5 MHz, which is just short 5TH –78.83 –90 of the Nyquist frequency. These signals were well filtered to 6TH –81.28 –100 7TH –77.28 minimize any harmonics. 8TH –84.54 –110 9TH –92.78 –120 Figure 48 shows the FFT response of the ADC for the case of a 0 1 2 3 45 67 8 9 10 FREQUENCY (MHz) 1 MHz analog input. The SFDR is 71.66 dB, and the analog-to- Figure 49. FFT Plot for AD8051 Driving the AD9201 at 9.5 MHz digital is producing 8.8 ENOB (effective number of bits). When the analog frequency was raised to 9.5 MHz, the SFDR was CLOCK 14 15 SLEEP 0.33µF 22Ω SELECT 13 +V DD 16 INA-I +5V 10pF 1kΩ 22Ω 17 INB-I 0.01µF 10pF 0.1µF 10µF AD9201 DATA OUT 18 REFT-I 7 D9 12 22Ω 3 0.1µF 10µF 0.1µF 19 REFB-I D8 11 50Ω 6 AD8051 0.1µF 20 AVSS D7 10 2 1kΩ 4 21 REFSENSE D6 9 22 VREF D5 8 10µF 0.1µF 0.1µF 10µF D4 7 –5V +5V 23 AVDD D3 6 10µF 0.1µF 1kΩ D2 5 24 REFB-Q 0.1µF 10µF 0.1µF D1 4 REFT-Q 25 0.1µF D0 3 22Ω DVDD 2 +5V 26 INB-Q 0.1µF 10µF 10pF DVSS 1 22Ω 27 INA-Q 10pF 28 CHIP–SELECT Figure 50. The AD8051 Driving an AD9201, a 10-Bit, 20 MSPS Analog-to-Digital Converter Rev. J | Page 19 of 24 AMPLITUDE (dB) AMPLITUDE (dB) 01062-048 01062-050 01062-049 AD8051/AD8052/AD8054 dynamic swing requirements are a signal that is mostly low but SYNC STRIPPER goes high with a duty cycle that is a small fraction of a percent, Synchronizing pulses are sometimes carried on video signals so and the other extreme defined by the opposite condition. as not to require a separate channel to carry the synchronizing information. However, for some functions, such as analog-to- The worst case of composite video is not quite this demanding. digital conversion, it is not desirable to have the sync pulses on One bounding condition is a signal that is mostly black for an the video signal. These pulses reduce the dynamic range of the entire frame but has a white (full amplitude) minimum width video signal and do not provide any useful information for such spike at least once in a frame. a function. The other extreme is for a full white video signal. The blanking intervals and sync tips of such a signal have negative-going A sync stripper removes the synchronizing pulses from a video excursions in compliance with the composite video specifications. signal while passing all the useful video information. Figure 51 The combination of horizontal and vertical blanking intervals shows a practical single-supply circuit that uses only a single AD8051. It is capable of directly driving a reverse terminated limit such a signal to being at the highest (white) level for a video line. maximum of about 75% of the time. VIDEO WITH SYNC VIDEO WITHOUT SYNC As a result of the duty cycles between the two extremes previously presented, a 1 V p-p composite video signal that is multiplied by a gain of 2 requires about 3.2 V p-p of dynamic voltage swing at the output for an op amp to pass a composite V GROUND BLANK 0.4V video signal of arbitrarily varying duty cycle without distortion. GROUND 3V OR 5V Some circuits use a sync tip clamp to hold the sync tips at a + relatively constant level to lower the amount of dynamic signal 0.1µF 10µF 7 swing required. However, these circuits can have artifacts, such V 3 IN TO A/D as sync tip compression, unless they are driven by a source with 6 AD8051 100Ω 2 a very low output impedance. The AD8051/AD8052/AD8054 4 R2 have adequate signal swing when running on a single 5 V 1kΩ supply to handle an ac-coupled composite video signal. R1 1kΩ The input to the circuit in Figure 52 is a standard composite 0.8V (1 V p-p) video signal that has the blanking level at ground. The (OR 2 × V ) BLANK input network level shifts the video signal by means of ac coupling. Figure 51. Sync Stripper The noninverting input of the op amp is biased to half of the The video signal plus sync is applied to the noninverting input supply voltage. with the proper termination. The amplifier gain is set to 2 via The feedback circuit provides unity gain for the dc-biasing of the two 1 kΩ resistors in the feedback circuit. A bias voltage the input and provides a gain of 2 for any signals that are in the must be applied to R1 so that the input signal has the sync video bandwidth. The output is ac-coupled and terminated to pulses stripped at the proper level. drive the line. The blanking level of the input video pulse is the desired place to The capacitor values were selected for providing minimum tilt remove the sync information. This level is multiplied by 2 by the or field time distortion of the video signal. These values would amplifier. This level must be at ground at the output for the sync be required for video that is considered to be studio or broadcast stripping action to take place. Since the gain of the amplifier from quality. However, if a lower consumer grade of video, sometimes the input of R1 to the output is −1, a voltage equal to 2 × V BLANK referred to as consumer video, is all that is desired, the values must be applied to make the blanking level come out at ground. and the cost of the capacitors can be reduced by as much as a SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER factor of five with minimum visible degradation in the picture. 5V Many composite video signals have their blanking level at 4.99kΩ ground and have video information that is both positive and + 10µF 4.99kΩ + negative. Such signals require dual-supply amplifiers to pass 0.1µF 10µF COMPOSITE 47µF VIDEO them. However, by ac level shifting, a single-supply amplifier 7 + R BT 3 IN 1000µF 75Ω R can be used to pass these signals. The following complications T + 6 V 10kΩ OUT AD8051 75Ω R L can arise from such techniques. 2 75Ω 4 0.1µF R F Signals of bounded peak-to-peak amplitude that vary in duty 1kΩ cycle require larger dynamic swing capacity than their (bounded) R G 1kΩ peak-to-peak amplitude after they are ac-coupled. As a worst 220µF case, the dynamic signal swing will approach twice the peak-to- peak value. The two conditions that define the maximum Figure 52. Single-Supply Composite Video Line Driver Rev. J | Page 20 of 24 01062-051 01062-052 AD8051/AD8052/AD8054 OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 14 8 4.00 (0.1575) 6.20 (0.2441) 1 3.80 (0.1496) 5.80 (0.2283) 7 1.27 (0.0500) 0.50 (0.0197) 45° BSC 0.25 (0.0098) 1.75 (0.0689) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 1.27 (0.0500) 0.51 (0.0201) 0.10 PLANE 0.25 (0.0098) 0.40 (0.0157) 0.31 (0.0122) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 53. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 2.90 BSC 5 4 2.80 BSC 1.60 BSC 12 3 PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 10° 0.15 MAX 5° 0.50 0.60 SEATING 0° 0.30 0.45 PLANE 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 54. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters Rev. J | Page 21 of 24 060606-A AD8051/AD8052/AD8054 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.38 0.60 0.23 0° 0.00 0.22 0.40 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 55. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° COPLANARITY 0.51 (0.0201) 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 56. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 6.40 4.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 0.20 MAX 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0° 0.05 0.30 0.45 PLANE COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. J | Page 22 of 24 012407-A 061908-A AD8051/AD8052/AD8054 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8051AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8051AR-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8051AR-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8051ARZ −40°C to +85°C 8-Lead SOIC_N R-8 1 AD8051ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8051ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8051ART-R2 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H2A AD8051ART-REEL −40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H2A AD8051ART-REEL7 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H2A 1 AD8051ARTZ-R2 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H06 1 AD8051ARTZ-REEL −40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H06 1 AD8051ARTZ-REEL7 −40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H06 AD8052AR −40°C to +125°C 8-Lead SOIC_N R-8 AD8052AR-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8052AR-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8052ARZ −40°C to +125°C 8-Lead SOIC_N R-8 1 AD8052ARZ-REEL −40°C to +125°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8052ARZ-REEL7 −40°C to +125°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8052ARM −40°C to +125°C 8-Lead MSOP RM-8 H4A AD8052ARM-REEL −40°C to +125°C 8-Lead MSOP, 13" Tape and Reel RM-8 H4A AD8052ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H4A 1 AD8052ARMZ −40°C to +125°C 8-Lead MSOP RM-8 H4A# 1 AD8052ARMZ-REEL7 −40°C to +125°C 8-Lead MSOP, 7" Tape and Reel RM-8 H4A# AD8054AR −40°C to +125°C 14-Lead SOIC_N R-14 AD8054AR-REEL −40°C to +125°C 14-Lead SOIC_N, 13" Tape and Reel R-14 AD8054AR-REEL7 −40°C to +125°C 14-Lead SOIC_N, 7" Tape and Reel R-14 1 AD8054ARZ −40°C to +125°C 14-Lead SOIC_N R-14 1 AD8054ARZ-REEL −40°C to +125°C 14-Lead SOIC_N, 13" Tape and Reel R-14 1 AD8054ARZ-REEL7 −40°C to +125°C 14-Lead SOIC_N, 7" Tape and Reel R-14 AD8054ARU −40°C to +125°C 14-Lead TSSOP RU-14 AD8054ARU-REEL −40°C to +125°C 14-Lead TSSOP, 13" Tape and Reel RU-14 AD8054ARU-REEL7 −40°C to +125°C 14-Lead TSSOP, 7" Tape and Reel RU-14 1 AD8054ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 1 AD8054ARUZ-REEL −40°C to +125°C 14-Lead TSSOP, 13" Tape and Reel RU-14 1 AD8054ARUZ-REEL7 −40°C to +125°C 14-Lead TSSOP, 7" Tape and Reel RU-14 1 Z = RoHS Compliant Part. # denotes lead-free product may be top or bottom marked. Rev. J | Page 23 of 24 AD8051/AD8052/AD8054 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01062-0-7/09(J) Rev. J | Page 24 of 24