ANALOG DEVICES AD8048

250 MHz, General Purpose Voltage Feedback Op Amps AD8047/AD8048 FEATURES FUNCTIONAL BLOCK DIAGRAM Wide Bandwidth AD8047, G = +1 AD8048, G = +2 8-Pin Plastic PDIP (N) Small Signal 250 MHz 260 MHz and SOIC (R) Packages Large Signal (2 V p-p) 130 MHz 160 MHz 5.8 mA Typical Supply Current AD8047/ NC 1 8 NC Low Distortion, (SFDR) Low Noise AD8048 –66 dBc Typ @ 5 MHz 2 7 +V –INPUT S –54 dBc Typ @ 20 MHz +INPUT 3 6 OUTPUT 5.2 nV/√Hz (AD8047), 3.8 nV/√Hz (AD8048) Noise Drives 50 pF Capacitive Load –V 4 5 (TOP VIEW) NC S High Speed NC = NO CONNECT Slew Rate 750 V/�s (AD8047), 1000 V/�s (AD8048) Settling 30 ns to 0.01%, 2 V Step �3 V to �6 V Supply Operation APPLICATIONS Low Power ADC Input Driver The AD8047 and AD8048’s low distortion and cap load drive Differential Amplifiers make the AD8047/AD8048 ideal for buffering high speed ADCs. IF/RF Amplifiers They are suitable for 12-bit/10 MSPS or 8-bit/60 MSPS ADCs. Pulse Amplifiers Additionally, the balanced high impedance inputs of the voltage Professional Video feedback architecture allow maximum flexibility when designing DAC Current to Voltage Conversion active filters. Baseband and Video Communications Pin Diode Receivers The AD8047 and AD8048 are offered in industrial (–40°C to Active Filters/Integrators +85°C) temperature ranges and are available in 8-lead PDIP and SOIC packages. PRODUCT DESCRIPTION The AD8047 and AD8048 are very high speed and wide band- width amplifiers. The AD8047 is unity gain stable. The AD8048 is stable at gains of two or greater. The AD8047 and AD8048, which utilize a voltage feedback architecture, meet the require- ments of many applications that previously depended on current feedback amplifiers. A proprietary circuit has produced an amplifier that combines many of the best characteristics of both current feedback and voltage feedback amplifiers. For the power (6.6 mA max), the AD8047 and AD8048 exhibit fast and accurate pulse response (30 ns to 0.01%) as well as extremely wide small signal and large 1V 5ns signal bandwidth and low distortion. The AD8047 achieves –54 dBc distortion at 20 MHz, 250 MHz small signal, and Figure 1. AD8047 Large Signal Transient Response, 130 MHz large signal bandwidths. V = 4 V p-p, G = +1 O REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. AD8047/AD8048–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (�V = �5 V, R = 100 �, A = 1 (AD8047), A = 2 (AD8048), unless otherwise noted.) S LOAD V V AD8047A AD8048A Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth (–3 dB) Small Signal V ≤ 0.4 V p-p 170 250 180 260 MHz OUT 1 Large Signal V = 2 V p-p 100 130 135 160 MHz OUT Bandwidth for 0.1 dB Flatness V = 300 mV p-p OUT AD8047, R =0 Ω; F AD8048, R = 200 Ω 35 50 MHz F Slew Rate, Average +/– V = 4 V Step 475 750 740 1000 V/µs OUT Rise/Fall Time V = 0.5 V Step 1.1 1.2 ns OUT V = 4 V Step 4.3 3.2 ns OUT Settling Time To 0.1% V = 2 V Step 13 13 ns OUT To 0.01% V = 2 V Step 30 30 ns OUT HARMONIC/NOISE PERFORMANCE Second Harmonic Distortion 2 V p-p; 20 MHz –54 –48 dBc R = 1 kΩ –64 –60 dBc L Third Harmonic Distortion 2 V p-p; 20 MHz –60 –56 dBc R = 1 kΩ –61 –65 dBc L Input Voltage Noise f = 100 kHz 5.2 3.8 nV/√Hz Input Current Noise f = 100 kHz 1.0 1.0 pA/√Hz Average Equivalent Integrated Input Noise Voltage 0.1 MHz to 10 MHz 16 11 µV rms Differential Gain Error (3.58 MHz) R = 150 Ω, G = +2 0.02 0.01 % L Differential Phase Error (3.58 MHz) R = 150 Ω, G = +2 0.03 0.02 Degree L 2 DC PERFORMANCE , R = 150 Ω L 3 Input Offset Voltage 13 13 mV T to T 44mV MIN MAX Offset Voltage Drift ±5 ±5 µV/°C Input Bias Current 1 3.5 1 3.5 µA T to T 6.5 6.5 µA MIN MAX Input Offset Current 0.5 2 0.5 2 µA T to T 33 µA MIN MAX Common-Mode Rejection Ratio V = ±2.5 V 74 80 74 80 dB CM Open-Loop Gain V = ±2.5 V 58 62 65 68 dB OUT T to T 54 56 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 500 500 kΩ Input Capacitance 1.5 1.5 pF Input Common-Mode Voltage Range ±3.4 ±3.4 V OUTPUT CHARACTERISTICS Output Voltage Range, R = 150 Ω±2.8 ±3.0 ±2.8 ±3.0 V L Output Current 50 50 mA Output Resistance 0.2 0.2 Ω Short-Circuit Current 130 130 mA POWER SUPPLY Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V Quiescent Current 5.8 6.6 5.9 6.6 mA T to T 7.5 7.5 mA MIN MAX Power Supply Rejection Ratio 72 78 72 78 dB NOTES 1 See Absolute Maximum Ratings and Theory of Operation sections. 2 Measured at A = 50. V 3 Measured with respect to the inverting input. Specifications subject to change without notice. –2– REV. A AD8047/AD8048 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Supply Voltage, (+V ) – (–V ) . . . . . . . . . . . . . . . . . . . . 12.6 V The maximum power that can be safely dissipated by these devices S S Voltage Swing × Bandwidth Product is limited by the associated rise in junction temperature. The AD8047 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 V-MHz maximum safe junction temperature for plastic encapsulated AD8048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 V-MHz devices is determined by the glass transition temperature of the 2 Internal Power Dissipation plastic, approximately 150°C. Exceeding this limit temporarily Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W may cause a shift in parametric performance due to a change in Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.9 W the stresses exerted on the die by the package. Exceeding a Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V junction temperature of 175°C for an extended period can S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±1.2 V result in device failure. Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . While the AD8047 and AD8048 are internally short circuit . . . . . . . . . . . . . . . . . .Observe Power Derating Curves protected, this may not be sufficient to guarantee that the maxi- Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C mum junction temperature (150°C) is not exceeded under all Operating Temperature Range (A Grade) . . . –40°C to +85°C conditions. To ensure proper operation, it is necessary to observe Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C the maximum power derating curves. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- 2.0 nent damage to the device. This is a stress rating only; functional operation of the T = +150�C J 8-PIN PDIP PACKAGE device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1.5 2 Specification is for device in free air: 8-Lead PDIP Package, � = 90°C/W; 8-Lead JA SOIC Package, � = 140°C/W JA METALLIZATION PHOTOS 1.0 Dimensions shown in inches and (mm) Connect Substrate to –V . S AD8047 8-PIN SOIC PACKAGE 0.5 +V S 0 –50 8 –40 –30 2 –20 –10 0 10 0 30 40 50 60 70 0 90 AMBIENT TEMPERATURE (�C) 0.045 (1.14) V Figure 2. Plot of Maximum Power Dissipation vs. OUT Temperature –IN ORDERING GUIDE –V +IN S 0.044 Temperature Package Package (1.13) Model Range Description Option* AD8048 AD8047AN –40°C to +85°CPDIP N-8 +V S AD8047AR –40°C to +85°C SOIC R-8 AD8047AR-REEL –40°C to +85°C SOIC R-8 AD8047AR-REEL7 –40°C to +85°C SOIC R-8 AD8048AN –40°C to +85°CPDIP N-8 AD8048AR –40°C to +85°C SOIC R-8 0.045 (1.14) AD8048AR-REEL –40°C to +85°C SOIC R-8 V OUT AD8048AR-REEL7 –40°C to +85°C SOIC R-8 *N = PDIP, R= SOIC –IN –V S +IN 0.044 (1.13) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8047/AD8048 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– MAXIMUM POWER DISSIPATION (W) AD8047/AD8048–Typical Performance Characteristics R F 10�F PULSE 10�F +V +V S S GENERATOR T /T = 500ps 0.1�F 0.1�F R F PULSE R IN 7 7 GENERATOR 2 V 2 IN T /T = 500ps V V AD8047 6 AD8047 6 R F OUT OUT R = 66.5� T 0.1�F 0.1�F V 3 3 IN R = 100� R = 100� L L 4 4 R = 49.9� 100� T 10�F 10�F –V –V S S TPC 1. AD8047 Noninverting Configuration, G = +1 TPC 4. AD8047 Inverting Configuration, G = –1 1V 5ns 1V 5ns TPC 2. AD8047 Large Signal Transient Response; TPC 5. AD8047 Large Signal Transient Response; V = 4 V p-p, G = +1 V = 4 V p-p, G = –1, R = R = 200 Ω O O F IN 100mV 100mV 5ns 5ns TPC 3. AD8047 Small Signal Transient Response; TPC 6. AD8047 Small Signal Transient Response; V = 400 mV p-p, G = +1 V = 400 mV p-p, G = –1, R = R = 200 Ω O O F IN –4– REV. A AD8047/AD8048 R F R F PULSE 10�F +V PULSE 10�F S +V GENERATOR S GENERATOR T /T = 500ps R F T /T = 500ps 0.1�F 0.1�F R F R IN R IN 7 7 2 V 2 IN V OUT V AD8048 AD8048 6 6 OUT R = 66.5� T 0.1�F 0.1�F V IN 3 3 R = 100� L 4 4 R = 100� L R = 100� R = 49.9� 10�F T S 10�F –V S –V S TPC 7. AD8048 Noninverting Configuration, G = +2 TPC 10. AD8048 Inverting Configuration, G= –1 1V 5ns 1V 5ns TPC 8. AD8048 Large Signal Transient Response; TPC 11. AD8048 Large Signal Transient Response; V = 4 V p-p, G = +2, R = R = 200 Ω V = 4 V p-p, G = –1, R = R = 200 Ω O F IN O F IN 100mV 5ns 100mV 5ns TPC 9. AD8048 Small Signal Transient Response; TPC 12. AD8048 Small Signal Transient Response; V = 400 mV p-p, G = +2, R = R = 200 Ω V = 400 mV p-p, G = –1, R = R = 200 Ω O F IN O F IN REV. A –5– AD8047/AD8048 1 1 0 0 –1 –1 R = 100� L R = 0� FOR DIP R = 100� F L –2 R = 66.5� FOR SOIC –2 R = 0� FOR DIP F F V = 2V p-p R = 66.5� FOR SOIC OUT F –3 –3 V = 300mV p-p OUT –4 –4 –5 –5 –6 –6 –7 –7 –8 –8 –9 –9 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 13. AD8047 Small Signal Frequency Response, TPC 16. AD8047 Large Signal Frequency Response, G = +1 G = +1 0.1 1 0 0 R = 100� –1 R = 100� –0.1 L L R = 0� FOR DIP R = R = 200� F F F R = 66.5� FOR SOIC V = 300mV p-p –0.2 –2 F OUT V = 300mV p-p OUT –3 –0.3 –4 –0.4 –5 –0.5 –6 –0.6 –7 –0.7 –0.8 –8 –9 –0.9 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 14. AD8047 0.1 dB Flatness, G = +1 TPC 17. AD8047 Small Signal Frequency Response, G = –1 100 70 –20 80 R = 1k� 60 L –30 V = 2V p-p OUT PHASE 60 50 MARGIN –40 40 40 –50 20 30 –60 GAIN 0 20 –70 SECOND HARMONIC –20 10 –80 –40 0 –90 THIRD HARMONIC R = 100� L –60 –10 –100 –80 –20 –110 –100 –30 –120 1k 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) TPC 15. AD8047 Open-Loop Gain and Phase Margin TPC 18. AD8047 Harmonic Distortion vs. Frequency, vs. Frequency G = +1 –6– REV. A GAIN (dB) OUTPUT (dBm) OUTPUT (dBm) PHASE MARGIN (Degrees) OUTPUT (dBm) OUTPUT (dBm) OUTPUT (dBm) AD8047/AD8048 0.5 –20 R = 100� R = 100� –30 L 0.4 L V = 2V p-p OUT R = 0� F V = 2V STEP 0.3 –40 OUT –50 0.2 –60 0.1 –70 0.0 SECOND HARMONIC –0.1 –80 –90 –0.2 THIRD HARMONIC –0.3 –100 –0.4 –110 –0.5 –120 015105 2025 3035 4045 10k 100k 1M 10M 100M SETTLING TIME (ns) FREQUENCY (Hz) TPC 19. AD8047 Harmonic Distortion vs. Frequency, TPC 22. AD8047 Short-Term Settling Time, G = +1 G = +1 –25 0.25 f = 200MHz 0.20 R = 100� –30 L R = 1k� L R = 0� F R = 0� FOR SOIC F V = 2V STEP 0.15 OUT –35 0.10 –40 0.05 –45 0.00 THIRD HARMONIC –0.05 –50 –0.10 –55 –0.15 SECOND HARMONIC –60 –0.20 –65 –0.25 1.5 2.5 3.5 4.5 5.5 6.5 0426810 12 14 16 18 SETTLING TIME (�s) OUTPUT SWING (V p-p) TPC 20. AD8047 Harmonic Distortion vs. Output TPC 23. AD8047 Long-Term Settling Time, G = +1 Swing, G = +1 0.04 17 0.02 15 0.00 13 –0.02 –0.04 11 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.04 9 0.02 7 0.00 5 –0.02 –0.04 3 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 10 100 1k 10k 100k FREQUENCY (Hz) TPC 21. AD8047 Differential Gain and Phase Error, TPC 24. AD8047 Noise vs. Frequency G = +2, R = 150 Ω, R = 200 Ω, R = 200 Ω L F IN REV. A –7– DIFF PHASE (Degrees) DIFF GAIN (%) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) ERROR (%) ERROR (%) INPUT NOISE VOLTAGE (nV/√Hz) AD8047/AD8048 7 7 6 6 5 R = 100� 5 R = 100� L L R = R = 200� IN R = R = 200� F IN F V = 300mV p-p 4 V = 2V p-p 4 OUT OUT 3 3 2 2 1 1 0 0 –1 –1 –2 –2 –3 –3 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 25. AD8048 Small Signal Frequency Response, TPC 28. AD8048 Large Signal Frequency Response, G = +2 G = +2 6.5 1 6.4 0 R = 100� L 6.3 R = R = 200� IN –1 R = 100� F L V = 300mV p-p OUT R = R = 200� IN F V = 300mV p-p 6.2 –2 OUT 6.1 –3 6.0 –4 5.9 –5 5.8 –6 5.7 –7 5.6 –8 5.5 –9 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 26. AD8048 0.1 dB Flatness, G = +2 TPC 29. AD8048 Small Signal Frequency Response, G = –1 100 –20 90 80 80 –30 R = 1k� L 70 60 V = 2V p-p –40 OUT PHASE 60 40 –50 20 50 –60 40 0 –70 SECOND HARMONIC –20 30 R = 100� –80 L –40 20 –90 THIRD HARMONIC 10 –60 –100 –80 0 –110 –100 –10 –20 –120 –120 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 30. AD8048 Harmonic Distortion vs. Frequency, TPC 27. AD8048 Open-Loop Gain and Phase Margin G = +2 vs. Frequency –8– REV. A OUTPUT (dBm) OUTPUT (dBm) GAIN (dB) PHASE (De grees) HARMONIC DISTORTION (dBc) OUTPUT (dBm) OUTPUT (dBm) AD8047/AD8048 –20 0.5 R = 100� –30 L 0.4 V = 2V p-p R = 100� OUT L R = 200� –40 0.3 F V = 2V STEP OUT –50 0.2 –60 0.1 0.0 –70 SECOND HARMONIC –0.1 –80 –90 THIRD HARMONIC –0.2 –0.3 –100 –0.4 –110 –120 –0.5 015105 2025 3035 4045 10k 100k 1M 10M 100M FREQUENCY (Hz) SETTLING TIME (ns) TPC 31. AD8048 Harmonic Distortion vs. Frequency, TPC 34. AD8048 Short-Term Settling Time, G = +2 G = +2 –15 0.25 –20 0.20 f = 20MHz R = 100� L R = 1k� –25 L R = 200� 0.15 F R = 200� THIRD HARMONIC F V = 2V STEP OUT –30 0.10 –35 0.05 –40 0.0 –45 –0.05 –50 SECOND HARMONIC –0.10 –55 –0.15 –60 –0.20 –65 –70 –0.25 1.5 2.5 3.5 4.5 5.5 6.5 0426810 12 14 16 18 SETTLING TIME (�s) OUTPUT SWING (V p-p) TPC 32. AD8048 Harmonic Distortion vs. Output TPC 35. AD8048 Long-Term Settling Time 2 V Swing, G = +2 Step, G = +2 17 0.04 0.02 15 0.00 13 –0.02 11 –0.04 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.04 9 0.02 7 0.00 5 –0.02 –0.04 3 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 10 100 1k 10k 100k FREQUENCY (Hz) TPC 33. AD8048 Differential Gain and Phase Error, TPC 36. AD8048 Noise vs. Frequency G = +2, R = 150 Ω, R = 200 Ω, R = 200 Ω L F IN REV. A –9– HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) DIFF PHASE (Degrees) DIFF GAIN (%) ERROR (%) ERROR (%) INPUT NOISE VOLTAGE (nV/√Hz) AD8047/AD8048 100 100 �V = 1V CM �V = 1V CM 90 90 R = 100� L R = 100� L 80 80 70 70 60 60 50 50 40 40 30 30 20 20 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 37. AD8047 CMRR vs. Frequency TPC 40. AD8048 CMRR vs. Frequency 100 100 10 10 1 1 0.1 0.1 0.01 0.01 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) TPC 38. AD8047 Output Resistance vs. Frequency, TPC 41. AD8048 Output Resistance vs. Frequency, G = +1 G = +2 90 90 80 80 –PSRR +PSRR 70 70 +PSRR –PSRR 60 60 50 50 40 40 30 30 20 20 10 10 0 0 10k 100k 1M 10M 100M 1G 3k 10k 100k 1M 100M 500M FREQUENCY (Hz) FREQUENCY (Hz) TPC 39. AD8047 PSRR vs. Frequency TPC 42. AD8048 PSRR vs. Frequency, G = +2 –10– REV. A R (� ) OUT CMRR (dB) PSRR (dB) PSRR (dB) R (�) OUT CMRR (dB) AD8047/AD8048 4.1 83.0 3.9 R = 1k� +V L 82.0 OUT AD8047 3.7 –V  OUT 81.0 3.5 3.3 80.0 +V OUT R = 150� L AD8048 3.1 79.0 –V  OUT 2.9 78.0 2.7 +V OUT 77.0 R = 50� 2.5 L –V  OUT 2.3 76.0 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (�C) JUNCTION TEMPERATURE (�C) TPC 43. AD8047/AD8048 Output Swing vs. Temperature TPC 46. AD8047/AD8048 CMRR vs. Temperature 8.0 2600 AD8048 2400 7.5 AD8047 AD8048 �6V 2200 7.0 2000 �6V 6.5 AD8048 1800 6.0 AD8047 1600 �5V 5.5 1400 AD8047 �5V 5.0 1200 4.5 1000 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (�C) JUNCTION TEMPERATURE (�C) TPC 44. AD8047/AD8048 Open-Loop Gain vs. TPC 47. AD8047/AD8048 Supply Current vs. Temperature Temperature 900 94 92 800 90 +PSRR 700 AD8048 88 AD8048 600 86 AD8047 500 AD8048 –PSRR 84 400 82 +PSRR AD8047 300 80 200 78 AD8047 –PSRR 100 76 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (�C) JUNCTION TEMPERATURE (�C) TPC 45. AD8047/AD8048 PSRR vs. Temperature TPC 48. AD8047/AD8048 Input Offset Voltage vs. Temperature REV. A –11– OPEN-LOOP GAIN (V/V) OUTPUT SWING (V) PSRR (–dB) INPUT OFFSET VOLTAGE (�V) CMRR (–dB) SUPPLY CURRENT (mA) AD8047/AD8048 THEORY OF OPERATION For general voltage gain applications, the amplifier bandwidth General can be closely estimated as The AD8047 and AD8048 are wide bandwidth, voltage feed- ω O f ≅ 3 dB back amplifiers. Since their open-loop frequency response follows    R  F the conventional 6 dB/octave roll-off, their gain bandwidth 2π 1+     R   G   product is basically constant. Increasing their closed-loop gain results in a corresponding decrease in small signal bandwidth. This estimation loses accuracy for gains of +2/–1 or lower due This can be observed by noting the bandwidth specification to the amplifier’s damping factor. For these low gain cases, the between the AD8047 (gain of 1) and AD8048 (gain of 2). bandwidth will actually extend beyond the calculated value (see Closed-Loop BW plots, TPCs 13 and 25). Feedback Resistor Choice The value of the feedback resistor is critical for optimum perfor- As a general rule, capacitor C will not be required if F mance on the AD8047 and AD8048. For maximum flatness at a NG (R �R )× C ≤ gain of 2, R and R should be set to 200 Ω for the AD8048. F G F G I 4 ω O When the AD8047 is configured as a unity gain follower, R F where NG is the Noise Gain (1 + R /R ) of the circuit. For F G should be set to 0 Ω (no feedback resistor should be used) for most voltage gain applications, this should be the case. the plastic DIP and 66.5 Ω for the SOIC. R +V 10�F F R S F G = 1 + R G 7 C V 3 0.1�F F IN AD8047/ R V 6 TERM OUT AD8048 2 0.1�F V 4 AD8047 OUT C I I I R 10�F –V G S R F Figure 5. Transimpedance Configuration Figure 3. Noninverting Operation Pulse Response +V 10�F Unlike a traditional voltage feedback amplifier, where the slew S speed is dictated by its front end dc quiescent current and gain R F 7 bandwidth product, the AD8047 and AD8048 provide on G = – 3 0.1�F R G demand current that increases proportionally to the input step AD8047/ V 6 OUT AD8048 signal amplitude. This results in slew rates (1000 V/µs) compa- 2 0.1�F 4 R rable to wideband current feedback designs. This, combined G V IN with relatively low input noise current (1.0 pA/√Hz), gives the R TERM 10�F –V S AD8047 and AD8048 the best attributes of both voltage and R F current feedback amplifiers. Large Signal Performance Figure 4. Inverting Operation The outstanding large signal operation of the AD8047 and When the AD8047 is used in the transimpedance (I to V) mode, AD8048 is due to a unique, proprietary design architecture. such as in photodiode detection, the values of R and diode F In order to maintain this level of performance, the maximum capacitance (C ) are usually known. Generally, the value of R I F 180 V-MHz product must be observed (e.g., @ 100 MHz, selected will be in the kΩ range, and a shunt capacitor (C ) F V ≤ 1.8 V p-p) on the AD8047 and the 250 V-MHz product O across R will be required to maintain good amplifier stability. F must be observed on the AD8048. The value of C required to maintain optimal flatness (<1 dB F Power Supply Bypassing peaking) and settling time can be estimated as 1/2 Adequate power supply bypassing can be critical when optimiz- 2 2 C ≅ (2 ω C R –1)/ω R F O I F O F ing the performance of a high frequency circuit. Inductance in [] the power supply leads can form resonant circuits that produce where � is equal to the unity gain bandwidth product of O peaking in the amplifier’s response. In addition, if large current the amplifier in rad/sec, and C is the equivalent total input I transients must be delivered to the load, then bypass capacitors 6 capacitance at the inverting input. Typically, � = 800 × 10 rad/sec O (typically greater than 1 µF) will be required to provide the best (see Open-Loop Frequency Response curve, TPC 15). settling time and lowest distortion. A parallel combination of at As an example, choosing R = 10 kΩ and C = 5 pF requires F I least 4.7 µF, and between 0.1 µF and 0.01 µF, is recommended. C to be 1.1 pF (Note: C includes both source and parasitic F I Some brands of electrolytic capacitors will require a small series circuit capacitance). The bandwidth of the amplifier can be damping resistor ≈4.7 Ω for optimum results. estimated using the C calculated as F Driving Capacitive Loads 1.6 The AD8047/AD8048 have excellent cap load drive capability f ≅ 3 dB for high speed op amps, as shown in Figures 7 and 9. However, 2πR C F F when driving cap loads greater than 25 pF, the best frequency response is obtained by the addition of a small series resistance. –12– REV. A AD8047/AD8048 It is worth noting that the frequency response of the circuit margin (65°), low noise current (1.0 pA/√Hz), and slew rate when driving large capacitive loads will be dominated by the (1000 V/µs) give higher performance capabilities to these appli- passive roll-off of R and C . cations over previous voltage feedback designs. SERIES L With a settling time of 30 ns to 0.01% and 13 ns to 0.1%, the R F devices are an excellent choice for DAC I/V conversion. The same characteristics along with low harmonic distortion make them a good choice for ADC buffering/amplification. With R SERIES AD8047 superb linearity at relatively high signal frequencies, the AD8047 R L C and AD8048 are ideal drivers for ADCs up to 12 bits. L 1k� Operation as a Video Line Driver The AD8047 and AD8048 have been designed to offer out- Figure 6. Driving Capacitive Loads standing performance as video line drivers. The important specifications of differential gain (0.01%) and differential phase (0.02°) meet the most exacting HDTV demands for driving video loads. 200� 200� 10�F +V S 0.1�F 7 75� 2 CABLE 75� AD8047/ 75� V 6 OUT CABLE AD8048 0.1�F V 3 75� IN 4 500mV 5ns 75� 10�F –V S Figure 7. AD8047 Large Signal Transient Response; Figure 10. Video Line Driver V = 2 V p-p, G = +1, R = 0 Ω, R = 0 Ω, C = 27 pF O F SERIES L Active Filters R F The wide bandwidth and low distortion of the AD8047 and AD8048 are ideal for the realization of higher bandwidth active filters. These characteristics, while being more common in many R SERIES R current feedback op amps, are offered in the AD8047 and AD8048 IN AD8048 R L C in a voltage feedback configuration. Many active filter configu- L 1k� rations are not realizable with current feedback amplifiers. A multiple feedback active filter requires a voltage feedback amplifier and is more demanding of op amp performance than Figure 8. Driving Capacitive Loads other active filter configurations such as the Sallen-Key. In general, the amplifier should have a bandwidth that is at least 10 times the bandwidth of the filter if problems due to phase shift of the amplifier are to be avoided. Figure 11 is an example of a 20 MHz low-pass multiple feed- back active filter using an AD8048. C1 10�F +5V R4 50pF 154� 0.1�F 1 R1 R3 154� 78.7� 7 V 2 IN 500mV 5ns V C2 AD8048 6 OUT 100pF 5 0.1�F 3 4 Figure 9. AD8048 Large Signal Transient Response; 100� 10�F V = 2 V p-p, G = +2, R = R = 200 Ω, R = 0 Ω, O F IN SERIES –5V C = 27 pF L Figure 11. Active Filter Circuit APPLICATIONS The AD8047 and AD8048 are voltage feedback amplifiers well suited for such applications as photodetectors, active filters, and log amplifiers. The devices’ wide bandwidth (260 MHz), phase REV. A –13– AD8047/AD8048 Choose Layout Considerations The specified high speed performance of the AD8047 and F = Cutoff Frequency = 20 MHz O AD8048 requires careful attention to board layout and compo- � = Damping Ratio = 1/Q = 2 nent selection. Proper RF design techniques and low-pass –R4 H = Absolute Value of Circuit Gain = = 1 parasitic component selection are mandatory. R1 Then, The PCB should have a ground plane covering all unused por- tions of the component side of the board to provide a low k = 2 π F C1 O impedance path. The ground plane should be removed from the 4 C1(H +1) area near the input pins to reduce stray capacitance. C2 = 2 α Chip capacitors should be used for the supply bypassing (see α Figure 12). One end should be connected to the ground plane R1 = 2 HK and the other within 1/8 inch of each power pin. An additional α large (0.47 µF to 10 µF) tantalum electrolytic capacitor should R3 = be connected in parallel, though not necessarily so close, to the 2 K (H +1) supply current for fast, large signal changes at the output. R4 = H(R1) The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a A/D Converter Driver minimum. Capacitance variations of less than 1 pF at the inverting As A/D converters move toward higher speeds with higher reso- input will significantly affect high speed performance. lutions, there becomes a need for high performance drivers that Stripline design techniques should be used for long signal traces will not degrade the analog signal to the converter. It is desir- (greater than about 1 inch). These should be designed with a able from a system’s standpoint that the A/D be the element in characteristic impedance of 50 Ω or 75 Ω and be properly termi- the signal chain that ultimately limits overall distortion. This nated at each end. places new demands on the amplifiers used to drive fast, high resolution A/Ds. With high bandwidth, low distortion, and fast settling time, the AD8047 and AD8048 make high performance A/D drivers for advanced converters. Figure 12 is an example of an AD8047 used as an input driver for an AD872A, a 12-bit, 10 MSPS A/D converter. +5V DIGITAL +5V ANALOG 10� 7 DV DD 0.1�F 6 DGND +5V DIGITAL 4 AV DD 22 0.1�F +5V ANALOG DRV DD 5 0.1�F AGND 23 DRGND CLOCK INPUT 10�F 21 CLK 20 0.1�F AD872A 49.9� OTR 7 19 MSB 2 18 1 BIT2 V AD8047 6 INA 17 ANALOG IN BIT3 16 0.1�F 3 BIT4 15 4 BIT5 2 14 DIGITAL OUTPUT BIT6 10�F V 13 INB BIT7 27 12 BIT8 REF GND –5V 11 BIT9 ANALOG 10 0.1�F BIT10 9 28 BIT11 8 REF IN BIT12 24 26 AGND REF OUT 1�F AV AV SS SS 3 25 0.1�F 0.1�F –5V ANALOG Figure 12. AD8047 Used as Driver for an AD872A, a 12-Bit, 10 MSPS A/D Converter –14– REV. A AD8047/AD8048 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 0.295 (7.49) 0.285 (7.24) 1 4 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.150 (3.81) 0.300 (7.62) BSC 0.135 (3.43) 0.015 0.120 (3.05) 0.180 (0.38) (4.57) MIN MAX 0.015 (0.38) 0.150 (3.81) 0.010 (0.25) SEATING 0.130 (3.30) PLANE 0.008 (0.20) 0.110 (2.79) 0.060 (1.52) 0.022 (0.56) 0.050 (1.27) 0.018 (0.46) 0.045 (1.14) 0.014 (0.36) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 85 4.00 (0.1574) 6.20 (0.2440) 3.80 (0.1497) 5.80 (0.2284) 1 4 0.50 (0.0196) 1.27 (0.0500) � 45� 1.75 (0.0688) BSC 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 8� 0.51 (0.0201) 0� 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. A –15– AD8047/AD8048 Revision History Location Page 7/03—Data Sheet changed from REV. 0 to REV. A. Renumbered Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Deleted Evaluation Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 –16– REV. A C01061–0–7/03(A)