ANALOG DEVICES AD8044

Quad 150 MHz a Rail-to-Rail Amplifier AD8044 CONNECTION DIAGRAM FEATURES 14-Lead Plastic DIP and SOIC Single AD8041 and Dual AD8042 Also Available Fully Specified at +3 V, +5 V, and �5 V Supplies Output Swings to Within 25 mV of Either Rail OUT A 1 14 OUT D Input Voltage Range Extends 200 mV Below Ground –IN A 2 13 –IN D No Phase Reversal with Inputs 1 V Beyond Supplies 3 +IN D +IN A 12 Low Power of 2.75 mA/Amplifier 4 11 V– V+ AD8044 High Speed and Fast Settling on +5 V 10 +IN B 5 +IN C 150 MHz –3 dB Bandwidth (G = +1) –IN B 6 9 –IN C 170 V/�s Slew Rate OUT B 7 8 OUT C 40 ns Settling Time to 0.1% TOP VIEW Good Video Specifications (R = 150 �, G = +2) L Gain Flatness of 0.1 dB to 12 MHz 0.06% Differential Gain Error 0.15� Differential Phase Error The output voltage swing extends to within 25 mV of each rail, Low Distortion providing the maximum output dynamic range. Additionally, it –68 dBc Total Harmonic @ 5 MHz features gain flatness of 0.1 dB to 12 MHz, while offering differ- Outstanding Load Drive Capability ential gain and phase error of 0.04% and 0.22∞ on a single +5 V Drives 30 mA 0.5 V from Supply Rails supply. This makes the AD8044 useful for video electronics, such as cameras, video switchers, or any high speed portable APPLICATIONS equipment. The AD8044’s low distortion and fast settling make Active Filters it ideal for active filter applications. Video Switchers Distribution Amplifiers The AD8044 offers low power supply current of 13.1 mA max A/D Driver and can run on a single +3.3 V power supply. These features are Professional Cameras ideally suited for portable and battery-powered applications CCD Imaging Systems where size and power are critical. Ultrasound Equipment (Multichannel) The wide bandwidth of 150 MHz, along with 170 V/ms of slew rate on a single +5 V supply, make the AD8044 useful in many general-purpose, high speed applications where dual power PRODUCT DESCRIPTION supplies of up to ±6 V and single supplies from +3 V to +12 V The AD8044 is a quad, low power, voltage feedback, high are needed. The AD8044 is available in 14-lead PDIP and speed amplifier designed to operate on +3 V, +5 V, or ±5 V SOIC. supplies. It has true single-supply capability with an input volt- age range extending 200 mV below the negative rail and within 18 1V of the positive rail. V = +5V S 15 G = +1 12 V = +5V 9 S 6 5V 3 0 2.5V –3 –6 0V –9 1V 2�s –12 100k 1M 10M 100M FREQUENCY (Hz) Figure 1. Output Swing: Gain = –1, R = 2 kW L Figure 2. Frequency Response: Gain = +1, V = +5 V S REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners. NORMALIZED GAIN (dB) AD8044–SPECIFICATIONS (@ T = +25�C, V = +5 V, R = 2 k� to 2.5 V, unless otherwise noted.) A S L AD8044A Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 80 150 MHz O Bandwidth for 0.1 dB Flatness G = +2, R = 150 W 12 MHz L Slew Rate G = –1, V = 4 V Step 140 170 V/ms O Full Power Response V = 2 V p-p 26 MHz O Settling Time to 1% G = –1, V = 2 V Step 30 ns O Settling Time to 0.1% 40 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, G = +2, R = 1 kW –68 dB C O L Input Voltage Noise f = 10 kHz 16 nV/÷Hz Input Current Noise f = 10 kHz 850 fA/÷Hz Differential Gain Error (NTSC) G = +2, R = 150 W to 2.5 V 0.04 % L Differential Phase Error (NTSC) G = +2, R = 150 W to 2.5 V 0.22 Degrees L Crosstalk f = 5 MHz, R = 1 kW, G = +2 –60 dB L DC PERFORMANCE Input Offset Voltage 1.0 6 mV T –T 8mV MIN MAX Offset Drift 8 mV/∞C Input Bias Current 2 4.5 mA T –T 4.5 mA MIN MAX Input Offset Current 0.2 1.2 mA Open-Loop Gain R = 1 kW 82 94 dB L T –T 88 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 225 kW Input Capacitance 1.6 pF Input Common-Mode Voltage Range –0.2 to 4 V Common-Mode Rejection Ratio V = 0 V to 3.5 V 80 90 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kW to 2.5 V 0.03 to 4.975 V L Output Voltage Swing: R = 1 kW to 2.5 V 0.25 to 4.75 0.075 to 4.91 V L Output Voltage Swing: R = 150 W to 2.5 V 0.55 to 4.4 0.25 to 4.65 V L Output Current T –T , V = 0.5 V to 4.5 V 30 mA MIN MAX OUT Short Circuit Current Sourcing 45 mA Sinking 85 mA Capacitive Load Drive G = +2 40 pF POWER SUPPLY Operating Range 312V Quiescent Current 11 13.1 mA Power Supply Rejection Ratio V = 0, +5 V, ±1 V 70 80 dB S OPERATING TEMPERATURE RANGE –40 +85 ∞C Specifications subject to change without notice. REV. B –2– AD8044 SPECIFICATIONS (@ T = +25�C, V = +3 V, R = 2 k� to 1.5 V, unless otherwise noted.) A S L AD8044A Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 80 135 MHz O Bandwidth for 0.1 dB Flatness G = +2, R = 150 W 10 MHz L Slew Rate G = –1, V = 2 V Step 110 150 V/ms O Full Power Response V = 2 V p-p 22 MHz O Settling Time to 1% G = –1, V = 2 V Step 35 ns O Settling Time to 0.1% 55 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, G = –1, R = 100W –48 dB C O L Input Voltage Noise f = 10 kHz 16 nV/÷Hz Input Current Noise f = 10 kHz 600 fA/÷Hz Differential Gain Error (NTSC) G = +2, R = 150 W to 1.5 V, Input V = 0.5 V 0.13 % L CM Differential Phase Error (NTSC) G = +2, R = 150 W to 1.5 V, Input V = 0.5 V 0.3 Degrees L CM Crosstalk f = 5 MHz, R = 1 kW, G = +2 –60 dB L DC PERFORMANCE Input Offset Voltage 1.5 5.5 mV T –T 7.5 mV MIN MAX Offset Drift 8 mV/∞C Input Bias Current 2 4.5 mA T –T 4.5 mA MIN MAX Input Offset Current 0.2 1.2 mA Open-Loop Gain R = 1 kW 80 92 dB L T –T 88 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 225 kW Input Capacitance 1.6 pF Input Common-Mode Voltage Range –0.2 to 2 V Common-Mode Rejection Ratio V = 0 V to 1.5 V 76 90 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kW to 1.5 V 0.025 to 2.98 V L Output Voltage Swing: R = 1 kW to 1.5 V 0.17 to 2.82 0.06 to 2.93 V L Output Voltage Swing: R = 150 W to 1.5 V 0.35 to 2.55 0.15 to 2.75 V L Output Current T –T , V = 0.5 V to 2.5 V 25 mA MIN MAX OUT Short Circuit Current Sourcing 30 mA Sinking 50 mA Capacitive Load Drive G = +2 35 pF POWER SUPPLY Operating Range 312V Quiescent Current 10.5 12.5 mA Power Supply Rejection Ratio V = 0, +3 V, +0.5 V 70 80 dB S OPERATING TEMPERATURE RANGE 0 +70 ∞C Specifications subject to change without notice. REV. B –3– AD8044–SPECIFICATIONS (@ T = +25�C, V = �5 V, R = 2 k� to 0 V, unless otherwise noted.) A S L AD8044A Parameter Conditions Min Typ Max Units DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 85 160 MHz O Bandwidth for 0.1 dB Flatness G = +2, R = 150 W 15 MHz L Slew Rate G = –1, V = 8 V Step 150 190 V/ms O Full Power Response V = 2 V p-p 29 MHz O Settling Time to 0.1% G = –1, V = 2 V Step 30 ns O Settling Time to 0.01% 40 ns NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p, G = +2 –72 dB C O Input Voltage Noise f = 10 kHz 16 nV/÷Hz Input Current Noise f = 10 kHz 900 fA/÷Hz Differential Gain Error (NTSC) G = +2, R = 150 W 0.06 % L Differential Phase Error (NTSC) G = +2, R = 150 W 0.15 Degrees L Crosstalk f = 5 MHz, R = 1 kW, G = +2 –60 dB L DC PERFORMANCE Input Offset Voltage 1.4 6.5 mV T –T 9mV MIN MAX Offset Drift 10 mV/∞C Input Bias Current 2 4.5 mA T –T 4.5 mA MIN MAX Input Offset Current 0.2 1.2 mA Open-Loop Gain R = 1 kW 82 96 dB L T –T 92 dB MIN MAX INPUT CHARACTERISTICS Input Resistance 225 kW Input Capacitance 1.6 pF Input Common-Mode Voltage Range –5.2 to 4 V Common-Mode Rejection Ratio V = –5 V to 3.5 V 76 90 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing R = 10 kW –4.97 to +4.97 V L Output Voltage Swing: R = 1 kW –4.6 to +4.6 –4.85 to +4.85 V L Output Voltage Swing: R = 150 W –4.0 to +3.8 –4.5 to +4.5 V L Output Current T –T , V = –4.5 V to +4.5 V 30 mA MIN MAX OUT Short Circuit Current Sourcing 60 mA Sinking 100 mA Capacitive Load Drive G = +2 40 pF POWER SUPPLY Operating Range 312V Quiescent Current 11.5 13.6 mA Power Supply Rejection Ratio V = –5, +5 V, ±1 V 70 80 dB S OPERATING TEMPERATURE RANGE –40 +85 ∞C Specifications subject to change without notice. –4– REV. B AD8044 1 ABSOLUTE MAXIMUM RATINGS While the AD8044 is internally short-circuit protected, this may Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V not be sufficient to guarantee that the maximum junction tem- 2 Internal Power Dissipation perature (+150∞C) is not exceeded under all conditions. To Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.6 Watts ensure proper operation, it is necessary to observe the maximum Small Outline Package (R) . . . . . . . . . . . . . . . . . . 1.0 Watts power derating curves. Input Voltage (Common-Mode) . . . . . . . . . . . . . . ±V ± 0.5 V S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.4 V 2.5 Output Short Circuit Duration T = +150 C J . . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves Storage Temperature Range (N, R) . . . . . . . –65∞C to +125∞C 2.0 14-LEAD PLASTIC DIP PACKAGE Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300∞C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- 1.5 nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating 14-LEAD SOIC conditions for extended periods may affect device reliability. 2 1.0 Specification is for the device in free air: 14-Lead Plastic Package: q = 75∞C/W JA 14-Lead SOIC Package: q = 120∞C/W JA 0.5 MAXIMUM POWER DISSIPATION –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (�C) The maximum power that can be safely dissipated by the AD8044 is limited by the associated rise in junction tempera- Figure 3. Maximum Power Dissipation vs. Temperature ture. The maximum safe junction temperature for plastic encap- sulated devices is determined by the glass transition temperature of the plastic, approximately +150∞C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175∞C for an extended period can result in device failure. ORDERING GUIDE Temperature Package Package Model Range Description Option AD8044AN –40∞C to +85∞C 14-Lead PDIP N-14 AD8044AR-14 –40∞C to +85∞C 14-Lead SOIC R-14 AD8044AR-14-REEL –40∞C to +85∞C 14-Lead SOIC 13" REEL R-14 AD8044AR-14-REEL7 –40∞C to +85∞C 14-Lead SOIC 7" REEL R-14 AD8044ARZ-14* –40∞C to +85∞C 14-Lead Plastic SOIC R-14 AD8044ARZ-14-REEL* –40∞C to +85∞C 14-Lead SOIC 13" REEL R-14 AD8044ARZ-14-REEL7* –40∞C to +85∞C 14-Lead SOIC 7" REEL R-14 *Z = Pb free part CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8016 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. –5– REV. B MAXIMUM POWER DISSIPATION (W) AD8044–Typical Performance Characteristics 100 11 V = +5V S 10 T = +25�C A 95 9 62 PARTS MEAN = 350�V 8 STD DEVIATION = 560�V 90 7 6 85 5 V = +5V S T = +25�C 4 80 3 2 75 1 70 0 0 250 500 750 1000 1250 1500 1750 2000 –3 –2.5 –2 –1.5 –1 –0.5012 0.5 1.5 2.5 3 LOAD RESISTANCE (�) V (mV) OS Figure 4. Typical Distribution of V Figure 7. Open-Loop Gain vs. R to +2.5 V OS L 100 15 V = +5V S MEAN = 7.9�V/�C R = 1k� TO +2.5V L STD DEV = 2.3�V/�C 97 12 SAMPLE SIZE = 62 V = +5 S 9 94 6 91 3 88 0 85 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 –40 –20 020 40 6080 100 V DRIFT (�V/�C) OS TEMPERATURE (�C) Figure 5. V Drift Over –40∞C to +85∞C OS Figure 8. Open-Loop Gain vs. Temperature 2.4 100 V = +5V S V = +5V 90 R = 500� S L 80 2.2 70 R = 50� L 60 2.0 50 40 30 1.8 20 10 0 0 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 05 0.15 0.35 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.45 4.65 4.85 TEMPERATURE (�C) OUTPUT VOLTAGE (V) Figure 6. I vs. Temperature Figure 9. Open-Loop Gain vs. Output Voltage B REV. B –6– INPUT BIAS CURRENT ( �A) NUMBER OF PARTS IN BIN NUMBER OF PARTS IN BIN OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) AD8044 300 0.03 V = +5V S 0.02 G = +2 0.01 R = 150� 100 L 0.00 –0.01 –0.02 30 –0.03 –0.04 0 10 20 30 40 50 60 70 80 90 100 10 0.20 V = +5V 0.15 S 0.10 G = +2 0.05 R = 150� L 3 0.00 –0.05 –0.10 –0.15 1 –0.20 10 100 1M 10M 1k 10k 100k 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) MODULATING RAMP LEVEL (IRE) Figure 10. Input Voltage Noise vs. Frequency Figure 13. Differential Gain and Phase Errors –30 V = +5V, S V = 2V p-p O 0.3 V = +5V, R = 100� S L –40 R = 100� A = +1 L V V = +3V, S 0.2 A = +2 R = 100� V L –50 A = –1 V 0.1 11.6MHz –60 0.0 –0.1 –70 –0.2 V = +5V –80 S –0.3 R = 200� F R = 150� TO 2.5V L V = +5V, V = +5V, S S –90 –0.4 G = +2 R = 1k� R = 1k� L L V = 0.2V p-p i A = +2 A = +1 V V –0.5 –100 11 23 4 56 7 890 –0.6 FUNDAMENTAL FREQUENCY (MHz) 1M 10M 100M FREQUENCY (Hz) Figure 11. Total Harmonic Distortion Figure 14. 0.1 dB Gain Flatness –30 80 –40 V = +5V 10MHz S –50 70 R = 2k� L –60 60 C = 5pF L –70 50 –80 5MHz 40 GAIN –90 30 180 –100 1MHz 20 135 –110 V = +5V PHASE S 10 R = 2k� TO 2.5V 90 L –120 G = +2 0 45 –130 –10 0 –140 80MHz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –20 OUTPUT VOLTAGE (V p-p) 30k 100k 1M 10M 100M FREQUENCY (Hz) Figure 12. Worst Harmonic vs. Output Voltage Figure 15. Open-Loop Gain and Phase Margin vs. Frequency –7– REV. B WORST HARMONIC (dBc) TOTAL HARMONIC DISTORTION (dBc) INPUT VOLTAGE NOISE (nV/ Hz) OPEN-LOOP GAIN (dB) DIFF PHASE (Degrees) DIFF GAIN (%) NORMALIZED GAIN (dB) PHASE MARGIN (Degrees) AD8044 4 70 +85�C G = –1 V = +5V R = 2k� S +25�C 3 L R = 2k� TO 2.5V L 60 –40�C V = +3V, 0.1% C = 5pF S 2 L G = +1 V = +5V, 0.1% AND S 50 V = 0.2V p-p O V = �5V, 0.1% 1 S 40 0 –1 30 –2 V = +3V, 1% S 20 V = +5V, 1% AND S –3 V = �5V, 1% S 10 –4 –5 0 0.5 1 1.5 2 1M 10M 100M FREQUENCY (Hz) INPUT STEPS (V p-p) Figure 19. Settling Time vs. Input Step Figure 16. Closed-Loop Frequency Response vs. Temperature 6 0 G = +1 5 +3V –10 R = 2k� L V = �5V 4 C = 5pF +5V S L –20 V = 0.2V p-p O 3 �5V –30 2 V = +3V S 1 –40 0 –50 –1 �5V –60 –2 +3V –70 –3 +5V –4 –80 100k 1M 10M 100M 0.03 0.1 110 100 500 FREQUENCY (MHz) FREQUENCY (Hz) Figure 17. Closed-Loop Frequency Response vs. Supply Figure 20. CMRR vs. Frequency 1.00 R = 50� BT 100 V = +5V +5V –V (+125�C) S 0.875 OH G = +1 0.750 V = +5V S +5V –V (+25�C) 10 OH 0.625 R BT V OUT +5V –V (–55�C) 0.500 OH 1 0.375 0.1 R = 0� BT 0.250 V (+125�C) OL 0.125 V (+25�C) OL 0.01 V (–55�C) OL 0.00 0.03 0.1 110 100 500 03 36 9 12 15 1821 24 270 FREQUENCY (MHz) LOAD CURRENT (mA) Figure 18. Output Resistance vs. Frequency Figure 21. Output Saturation Voltage vs. Load Current –8– REV. B OUTPUT RESISTANCE (�) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) OUTPUT SATURATION VOLTAGE (V) CMRR (dB) TIME (ns) AD8044 60 12.0 G = +2, R = 0�, S G = +3, R = 0�, S V = �5V S V = 100mV STEP O V = 150mV STEP O R = R = 750� 50 F G 11.5 G = +1, R = 20�, S V = +5V S V = 100mV STEP O R = 750� F 40 R = 0, R = R = 375� 11.0 G F G G = +1, R = 40�, S V = +3V S V = 100mV STEP O 30 R R G F 10.5 R = 0, R = F G +2.5V V OUT 20 10.0 V IN R S –2.5V 50� 10 9.5 0 0 50 100 150 200 250 9.0 LOAD CAPACITANCE (pF) –40 –20 0 20 40 60 80 100 TEMPERATURE (�C) Figure 22. Supply Current vs. Temperature Figure 25. % Overshoot vs. Capacitive Load 3 20 G = +2 2 10 R = 150� TO 2.5V G = +2 L V = +5V S 1 R = 200� F 0 0 –10 G = +5 –PSRR –1 –20 –2 –30 +PSRR –3 –40 V = +5V S –4 –50 R = 5k� TO 2.5V L –5 R = 2k� –60 F G = +10 –6 –70 –7 –80 100k 1M 10M 100M 500M 0.01 0.1 1 10 100 500 FREQUENCY (Hz) FREQUENCY (MHz) Figure 23. PSRR vs. Frequency Figure 26. Frequency Response vs. Closed-Loop Gain 10 –10 V = �5V S V = �5V 9 S –20 V = 1V p-p IN R = 2k� L G = +2 8 –30 R = 1k� F –40 7 R = 100� –50 6 L 5 –60 –70 4 R = 1k� L –80 3 –90 2 –100 1 –110 0 0.1 110 100 400 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Output Voltage Swing vs. Frequency Figure 27. Crosstalk (Output to Output) vs. Frequency –9– REV. B PSRR (dB) SUPPLY CURRENT (mA) V p-p (V) OUT CROSSTALK (dB) NORMALIZED OUTPUT (dB) % OVERSHOOT AD8044 5V 4.656V 2.6V V = +5V S G = +1 V = +5V S R = 2k� L R = 150� TO +2.5V L 2.55V C = 5pF L C = 5pF L G = –1 2.5V 2.5V 2.45V 2.4V 0.211V 50mV 40ns 500mV 100�s 0V Figure 28a. Output Swing vs. Load Reference Voltage, Figure 30. 100 mV Step Response, V = +5 V, G = +1 S V = +5 V, G = –1 S 5V 3V 4.309V +2.920V V = 3V p-p IN V = +5V S 2.5V R = 2k� L R = 150� TO GND L C = 5pF L C = 5pF L V = +3V 2V S G = –1 G = –1 2.5V 1.5V 1V 0.5V +10mV +22mV 500mV 100�s 500mV 200�s 0V Figure 28b. Output Swing vs. Load Reference Voltage, Figure 31. Output Swing, V = +3 V S V = +5 V, G = –1 S 1.60V 4.5V V = 0.1V p-p IN 1.58V V = +5V R = 2k� S L G = +2 C = 5pF 1.56V L R = 2k� 3.5V L V = +3V S V = 1V p-p 1.54V IN G = +1 C = 5pF L 1.52V 1.50V 2.5V 1.48V 1.46V 1.5V 1.44V 1.42V 20mV 20ns 500mV 20ns 1.40V 0.5V Figure 29. One Volt Step Response, V = +5 V, G = +2 Figure 32. Step Response, G = +1, V = 100 mV S IN –10– REV. B AD8044 Overdrive Recovery Driving Capacitance Loads Overdrive of an amplifier occurs when the output and/or input The capacitive load drive of the AD8044 can be increased by range are exceeded. The amplifier must recover from this over- adding a low valued resistor in series with the load. Figure 35 drive condition. As shown in Figure 33, the AD8044 recovers shows the effects of a series resistor on capacitive drive for vary- within 50 ns from negative overdrive and within 25 ns from ing voltage gains. As the closed-loop gain is increased, the larger positive overdrive. phase margin allows for larger capacitive loads with less over- shoot. Adding a series resistor with lower closed-loop gains accomplishes this same effect. For large capacitive loads, the V = +5V S frequency response of the amplifier will be dominated by the A = +2 V V OUT roll-off of the series resistor and capacitive load. R = 2k� F 1V/DIV R = 2k� L V CC I1 I10 I2 I3 I9 V Q25 Q50 IN R26 R39 2V/DIV Q36 Q4 Q5 Q39 Q51 I5 Q23 Q40 V EE R15 R2 Q22 R23 R27 V EE C3 Q31 Q7 V P Q17 Q13 IN V OUT Q21 Q27 V N IN C9 SIN SIP 2V 1V 50ns Q2 Q11 Q8 Q3 Q24 Q47 I8 Figure 33. Overdrive Recovery, VS + 5 V, V = 4 V Step IN I7 I11 V C7 R5 R21 R3 CC Circuit Description V EE The AD8044 is fabricated on Analog Devices’ proprietary eXtra-Fast Complementary Bipolar (XFCB) process which Figure 34. AD8044 Simplified Schematic enables the construction of PNP and NPN transistors with similar f s in the 2 GHz–4 GHz region. The process is dielectri- T cally isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features allow the construc- tion of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 34). The smaller signal swings required on the first stage outputs (nodes S1P, S1N) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design harmonic distortion of better than –85 dB @ 1 MHz into 100 W with V = 2 V p-p (Gain = +2) on a OUT single 5 volt supply is achieved. The AD8044’s rail-to-rail output range is provided by a comple- mentary common-emitter output stage. High output drive capa- bility is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. Bias- ing of Q8 and Q36 is accomplished by I8 and I5, along with a common-mode feedback loop (not shown). This circuit topol- ogy allows the AD8044 to drive 50 mA of output current with the outputs within 0.5 V of the supply rails. On the input side, the device can handle voltages from –0.2 V below the negative rail to within 1.2 V of the positive rail. Ex- ceeding these values will not cause phase reversal; however, the input ESD devices will begin to conduct if the input voltages exceed the rails by greater than 0.5 V. –11– REV. B AD8044 +5V 1000 GRAPHICS IC V = +5V S R < 30% OVERSHOOT 75� G 75� 100 B 75� 75� 75� R R G F R S V RGB IN 75� +3V OR +5V V OUT 100mV STEP C MONITOR #1 L AD8044 10 0.1�F 10�F 16 2 34 5 A (V/V) CL 75� V+ A Figure 35. Capacitive Load Drive vs. Closed-Loop Gain 1k� APPLICATIONS RGB Buffer 1k� The AD8044 can provide buffering of RGB signals that include 75� AD8044 ground while operating from a single +3 V or +5 V supply. 75� B When driving two monitors from the same RGB video source it 75� is necessary to provide an additional driver for one of the moni- 1k� tors to prevent the double termination situation that the second 1k� monitor presents. This has usually required a dual-supply op 75� amp because the level of the input signal from the video driver AD8044 goes all the way to ground during horizontal blanking. In single- 75� C V– supply systems it can be a major inconvenience and expense to RGB MONITOR #2 add an additional negative supply. 1k� A single AD8044 can provide the necessary drive capability and yet does not require a negative supply in this application. Fig- 1k� ure 36 is a schematic that uses three amplifiers out of a single AD8044 to provide buffering for a second monitor. Figure 36. Single Supply RGB Video Driver The source of the RGB signals is shown to be from a set of three Figure 37 is an oscilloscope photo of the circuit in Figure 36 current output DACs that are within a single-supply graphics operating from a +3 V supply and driven by the Blue signal of a IC. This is typically the situation in most PCs and workstations color bar pattern. Note that the input and output are at ground that may use either a standalone triple DAC or DACs that are during the horizontal blanking interval. The RGB signals are integrated into a larger graphics chip. specified to output a maximum of 700 mV peak. The output of During horizontal blanking, the current output from the DACs the AD8044 is 1.4 V with the termination resistors providing a is turned off and the RGB outputs are pulled to ground by the divide-by-two. termination resistors. If voltage sources were used for the RGB signals, then the termination resistors near the graphics IC would be in series and the rest of the circuit would remain the 500mV 5�s same. This is because a voltage source is an ac short circuit, so a 100 series resistor is required to make the drive end of the line see 90 V IN 75W to ac ground. On the other hand, a current source has a GND very high output impedance, so a shunt resistor is required to make the drive end of the line see 75W to ground. In either case, the monitor terminates its end of the line with 75W. V OUT 10 GND The circuit in Figure 36 shows minimum signal degradation 0% when using a single-supply for the AD8044. The circuit per- 500mV forms equally well on either a +3 V or +5 V supply. Figure 37. +3 V, RGB Buffer –12– REV. B R = 10� S R = 0� S CAPACITIVE LOAD (pF) AD8044 Active Filters Layout Considerations Active filters at higher frequencies require wider bandwidth op The specified high speed performance of the AD8044 requires amps to work effectively. Excessive phase shift produced by careful attention to board layout and component selection. lower frequency op amps can significantly impact active filter Proper RF design techniques and low-pass parasitic component performance. selection are necessary. Figure 38 shows an example of a 2 MHz biquad bandwidth The PCB should have a ground plane covering all unused por- filter that uses three op amps of an AD8044 package. Such tions of the component side of the board to provide a low im- circuits are sometimes used in medical ultrasound systems to pedance path. The ground plane should be removed from the lower the noise bandwidth of the analog signal before A/D area near the input pins to reduce the stray capacitance. conversion. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other R6 1k� within 1/8 inch of each power pin. An additional large (0.47mF C1 – 10 mF) tantalum electrolytic capacitor should be connected in 50pF parallel, but not necessarily so close, to supply current for fast, R2 large signal changes at the output. R4 2k� C2 2k� R1 50pF The feedback resistor should be located close to the inverting 3k� R3 2 V 2k� IN R5 1 6 input pin in order to keep the stray capacitance at this node to a 2k� 3 7 9 minimum. Capacitance variations of less than 1 pF at the invert- 5 8 V OUT AD8044 10 ing input will significantly affect high speed performance. AD8044 AD8044 Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a Figure 38. 2 MHz Biquad Band-pass Filter Using AD8044 characteristic impedance of 50 W or 75 W and properly termi- The frequency response of the circuit is shown in Figure 39. nated at each end. 0 –10 –20 –30 –40 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 39. Frequency Response of 2 MHz Band-pass Biquad Filter –13– REV. B GAIN (dB) AD8044 OUTLINE DIMENSIONS 14-Lead Plastic Dual In-Line Package [PDIP] (N-14) Dimensions shown in inches and (millimeters) 0.685 (17.40) 0.665 (16.89) 0.295 (7.49) 0.645 (16.38) 0.285 (7.24) 0.275 (6.99) 14 8 1 7 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.015 (0.38) 0.300 (7.62) 0.150 (3.81) MIN 0.135 (3.43) 0.180 (4.57) 0.120 (3.05) MAX 0.150 (3.81) SEATING 0.130 (3.30) 0.015 (0.38) PLANE 0.110 (2.79) 0.022 (0.56) 0.060 (1.52) 0.010 (0.25) 0.018 (0.46) 0.050 (1.27) 0.008 (0.20) 0.014 (0.36) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MO-095-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 14-Lead Standard Small Outline Package [SOIC] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 8.75 (0.3445) 8.55 (0.3366) 14 8 4.00 (0.1575) 6.20 (0.2441) 1 7 3.80 (0.1496) 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) 1.75 (0.0689) � 45� BSC 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 0.10 (0.0039) 8� 0.51 (0.0201) 0� SEATING 1.27 (0.0500) 0.25 (0.0098) COPLANARITY PLANE 0.31 (0.0122) 0.10 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –14– REV. B AD8044 Revision History Location Page 8/04—Data Sheet changed from Rev. A to Rev. B Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 –15– –15– REV. B –16– C01060–0–8/04(B)