ANALOG DEVICES AD8040

Low Power, High Speed Rail-to-Rail Input/Output Amplifier AD8029/AD8030/AD8040 CONNECTION DIAGRAMS FEATURES Low power NC 1 8 DISABLE V 1 6 +V OUT S 1.3 mA supply current/amplifier –IN 2 7 +V S High speed +IN 3 6 V OUT –V 2 5 DISABLE S +– –V 4 5 NC 125 MHz, –3 dB bandwidth (G = +1) S 60 V/µs slew rate +IN 3 4 –IN NC = NO CONNECT 80 ns settling time to 0.1% Figure 1. SOIC-8 (R) Figure 2. SC70-6 (KS) Rail-to-rail input and output No phase reversal, inputs 200 mV beyond rails Wide supply range: 2.7 V to 12 V Offset voltage: 6 mV max V 1 1 14 OUT V 4 OUT Low input bias current –IN 1 2 13 –IN 4 +0.7 µA to –1.5 µA +IN 1 3 12 +IN 4 Small packaging V 1 1 8 +V 4 11 –V OUT +V S S S SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14 –IN 1 2 7 +IN 2 5 10 +V 2 +IN 3 OUT –IN 2 6 9 –IN 3 APPLICATIONS +IN 1 3 6 –IN 2 –V 4 5 +IN 2 V 2 7 8 V 3 Battery-powered instrumentation S OUT OUT Filters Figure 3. SOIC-8(R) and Figure 4. SOIC-14 (R) and A-to-D drivers SOT23-8 (RJ) TSSOP-14 (RU) Buffering GENERAL DESCRIPTION The AD8029 (single), AD8030 (dual), and AD8040 (quad) are powered systems with large bandwidth requirements to high rail-to-rail input and output high speed amplifiers with a speed systems where component density requires lower power quiescent current of only 1.3 mA per amplifier. Despite their dissipation. low power consumption, the amplifiers provide excellent The AD8029/AD8030 are the only low power, rail-to-rail input performance with 125 MHz small signal bandwidth and and output high speed amplifiers available in SOT23 and SC70 60 V/µs slew rate. ADI’s proprietary XFCB process enables high micro packages. The amplifiers are rated over the extended speed and high performance on low power. industrial temperature range, –40°C to +125°C. This family of amplifiers exhibits true single-supply operation with rail-to-rail input and output performance for supply 5.0 voltages ranging from 2.7 V to 12 V. The input voltage range INPUT 4.5 extends 200 mV beyond each rail without phase reversal. The OUTPUT 4.0 dynamic range of the output extends to within 40 mV of each rail. 3.5 3.0 The AD8029/AD8030/AD8040 provide excellent signal quality 2.5 with minimal power dissipation. At G = +1, SFDR is –72 dBc at 2.0 1 MHz and settling time to 0.1% is only 80 ns. Low distortion and fast settling performance make these amplifiers suitable 1.5 drivers for single-supply A/D converters. 1.0 G = +1 V = +5V 0.5 S The versatility of the AD8029/AD8030/AD8040 allows the user R = 1kΩ TIED TO MIDSUPPLY 1µs/DIV L 0 to operate the amplifiers on a wide range of supplies while TIME (µs) 03679-A-010 consuming less than 6.5 mW of power. These features extend the operation time in applications ranging from battery- Figure 5. Rail-to-Rail Response Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. VOLTAGE (V) 03679-A-003 03679-A-004 03679-A-002 03679-A-001 AD8029/AD8030/AD8040 TABLE OF CONTENTS Specifications..................................................................................... 3 Applications..................................................................................... 16 Specifications with ±5 V Supply ................................................. 3 Wideband Operation ................................................................. 16 Specifications with +5 V Supply ................................................. 4 Output Loading sensitivity........................................................ 16 Specifications with +3 V Supply ................................................. 5 Disable Pin .................................................................................. 17 Absolute Maximum Ratings............................................................ 6 Circuit Considerations .............................................................. 18 Maximum Power Dissipation ..................................................... 6 Design Tools and Technical Support ....................................... 18 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19 Theory of Operation ...................................................................... 15 Ordering Guide............................................................................... 20 Input Stage................................................................................... 15 ESD Caution................................................................................ 20 Output Stage................................................................................ 15 REVISION HISTORY Revision A 11/03—Data Sheet Changed from Rev. 0 to Rev. A Change Page Added AD8040 part .......................................................Universal Change to Figure 5 ....................................................................... 1 Changes to Specifications............................................................ 3 Changes to Figures 10–12............................................................ 7 Change to Figure 14 ..................................................................... 8 Changes to Figures 20 and 21 ..................................................... 9 Inserted new Figure 36............................................................... 11 Change to Figure 40 ................................................................... 12 Inserted new Figure 41............................................................... 12 Added Output Loading Sensitivity section ............................. 16 Changes to Table 5...................................................................... 17 Changes to Power Supply Bypassing section .......................... 18 Changes to Ordering Guide ...................................................... 20 Rev. A | Page 2 of 20 AD8029/AD8030/AD8040 SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY Table 1. V = ±5 V @ T = 25°C, G = +1, R = 1 kΩ to ground, unless otherwise noted. All specifications are per amplifier. S A L Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, V = 0.1 V p-p 80 125 MHz O G = +1, V = 2 V p-p 14 19 MHz O Bandwidth for 0.1 dB Flatness G = +2, V = 0.1 V p-p 6 MHz O Slew Rate G = +1, VO = 2 V Step 62 V/µs G = –1, VO = 2 V Step 63 V/µs Settling Time to 0.1% G = +2, VO = 2 V Step 80 ns NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) f = 1 MHz, V = 2 V p-p –74 dBc C O f = 5 MHz, V = 2 V p-p –56 dBc C O Input Voltage Noise f = 100 kHz 16.5 Hz nV/√ Input Current Noise f = 100 kHz 1.1 Hz pA/√ Crosstalk (AD8030/AD8040) f = 5 MHz, V = 2 V p-p dB IN –79 DC PERFORMANCE Input Offset Voltage PNP Active, VCM = 0 V 1.6 5 mV NPN Active, VCM = 4.5 V 2 6 mV Input Offset Voltage Drift TMIN to TMAX 30 µV/°C 1 Input Bias Current NPN Active, VCM = 4.5 V 0.7 1.3 µA TMIN to TMAX 1 µA PNP Active, VCM = 0 V –1.7 –2.8 µA TMIN to TMAX 2 µA Input Offset Current ±0.1 ±0.9 µA Open-Loop Gain Vo = ±4.0 V 65 74 dB INPUT CHARACTERISTICS Input Resistance 6 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range –5.2 to +5.2 V Common-Mode Rejection Ratio VCM = –4.5 V to +3 V, RL = 10 kΩ 80 90 dB DISABLE PIN (AD8029) DISABLE –V + 0.8 V Low Voltage S DISABLE –6.5 µA Low Current DISABLE –V + 1.2 V High Voltage S DISABLE 0.2 µA High Current Turn-Off Time 150 ns 50% of DISABLE to <10% of Final VO, V = –1 V, G = –1 IN Turn-On Time 50% of DISABLE to <10% of Final VO, 85 ns VIN = –1 V, G = –1 OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) V = +6 V to –6 V, G = –1 55/45 ns IN Output Voltage Swing R = 1 kΩ –V + 0.22 +V – 0.22 V L S S R = 10 kΩ –V + 0.05 +V – 0.05 V L S S Short-Circuit Current Sinking and Sourcing 170/160 mA Off Isolation (AD8029) DISABLE –55 dB VIN = 0.1 V p-p, f = 1 MHz, = Low Capacitive Load Drive 30% Overshoot 20 pF POWER SUPPLY Operating Range 2.7 12 V Quiescent Current/Amplifier 1.4 1.5 mA Quiescent Current (Disabled) DISABLE 150 200 µA = Low Power Supply Rejection Ratio V ± 1 V 73 80 dB s 1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin. Rev. A | Page 3 of 20 AD8029/AD8030/AD8040 SPECIFICATIONS WITH +5 V SUPPLY Table 2. VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, VO = 0.1 V p-p 80 120 MHz G = +1, VO = 2 V p-p 13 18 MHz Bandwidth for 0.1 dB Flatness G = +2, V = 0.1 V p-p 6 MHz O Slew Rate G = +1, VO = 2 V Step 55 V/µs G = –1, V = 2 V Step 60 V/µs O Settling Time to 0.1% G = +2, V = 2 V Step 82 ns O NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p –73 dBc f = 5 MHz, V = 2 V p-p –55 dBc C O Input Voltage Noise f = 100 kHz 16.5 nV/√Hz Input Current Noise f = 100 kHz 1.1 pA/√Hz Crosstalk (AD8030/AD8040) f = 5 MHz, V = 2 V p-p -79 dB IN DC PERFORMANCE Input Offset Voltage PNP Active, VCM = 2.5 V 1.4 5 mV NPN Active, VCM = 4.5 V 1.8 6 mV Input Offset Voltage Drift T to T 25 µV/°C MIN MAX 1 Input Bias Current NPN Active, VCM = 4.5 V 0.8 1.2 µA T to T 1 µA MIN MAX PNP Active, V = 2.5 V –1.8 –2.8 µA CM TMIN to TMAX 2 µA Input Offset Current ±0.1 ±0.9 µA Open-Loop Gain Vo = 1 V to 4 V 65 74 dB INPUT CHARACTERISTICS Input Resistance 6 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range –0.2 to +5.2 V Common-Mode Rejection Ratio V = 0.25 V to 2 V, R = 10 kΩ 80 90 dB CM L DISABLE PIN (AD8029) DISABLE Low Voltage –V + 0.8 V S DISABLE Low Current –6.5 µA DISABLE –V + 1.2 V High Voltage S DISABLE High Current 0.2 µA Turn-Off Time 50% of DISABLE to <10% of Final VO, 155 ns V = –1 V, G = –1 IN Turn-On Time 50% of DISABLE to <10% of Final V , 90 ns O V = –1 V, G = –1 IN OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rising/Falling Edge) VIN = –1 V to +6 V, G = –1 45/50 ns Output Voltage Swing R = 1 kΩ –V + 0.17 +V – 0.17 V L S S R = 10 kΩ –V + 0.04 +V – 0.04 V L S S Short-Circuit Current Sinking and Sourcing 95/60 mA Off Isolation (AD8029) DISABLE –55 dB Vin = 0.1 V p-p, f = 1 MHz, = Low Capacitive Load Drive 30% Overshoot 15 pF POWER SUPPLY Operating Range 2.7 12 V Quiescent Current/Amplifier 1.3 1.5 mA Quiescent Current (Disabled) DISABLE = Low 140 200 µA Power Supply Rejection Ratio V ± 1 V 73 80 dB S 1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin. Rev. A | Page 4 of 20 AD8029/AD8030/AD8040 SPECIFICATIONS WITH +3 V SUPPLY Table 3. VS = +3 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, VO = 0.1 V p-p 80 112 MHz G = +1, VO = 2 V p-p 13 18 MHz Bandwidth for 0.1 dB Flatness G = +2, V = 0.1 V p-p 6 MHz O Slew Rate G = +1, VO = 2 V Step 55 V/µs G = –1, V = 2 V Step 57 V/µs O Settling Time to 0.1% G = +2, V = 2 V Step 110 ns O NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) fC = 1 MHz, VO = 2 V p-p –72 dBc f = 5 MHz, V = 2 V p-p –60 dBc C O Input Voltage Noise f = 100 kHz 16.5 nV/√Hz Input Current Noise f = 100 kHz 1.1 pA/√Hz Crosstalk (AD8030/AD8040) f = 5 MHz, V = 2 V p-p -80 dB IN DC PERFORMANCE Input Offset Voltage PNP Active, VCM = 1.5 V 1.1 5 mV NPN Active, VCM = 2.5 V 1.6 6 mV Input Offset Voltage Drift T to T 24 µV/°C MIN MAX 1 Input Bias Current NPN Active, VCM = 2.5 V 0.7 1.2 µA T to T 1 µA MIN MAX 1 Input Bias Current PNP Active, V = 1.5 V –1.5 –2.5 µA CM TMIN to TMAX 1.6 µA Input Offset Current ±0.1 ±0.9 µA Open-Loop Gain Vo = 0.5 V to 2.5 V 64 73 dB INPUT CHARACTERISTICS Input Resistance 6 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range –0.2 to +3.2 V Common-Mode Rejection Ratio V = 0.25 V to 1.25 V, R = 10 kΩ 78 88 dB CM L DISABLE PIN (AD8029) DISABLE Low Voltage –V + 0.8 V S DISABLE Low Current –6.5 µA DISABLE –V + 1.2 V High Voltage S DISABLE High Current 0.2 µA Turn-Off Time 50% of DISABLE to <10% of Final VO, 165 ns V = –1 V, G = –1 IN Turn-On Time 50% of DISABLE to <10% of Final V , 95 ns O V = –1 V, G = –1 IN OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) VIN = –1 V to +4 V, G = –1 75/100 ns Output Voltage Swing R = 1 kΩ –V + 0.09 +V – 0.09 V L S S R = 10 kΩ –V + 0.04 +V – 0.04 V L S S Short-Circuit Current Sinking and Sourcing 80/40 mA Off Isolation (AD8029) DISABLE –55 dB VIN = 0.1 V p-p, f = 1 MHz, = Low Capacitive Load Drive 30% Overshoot 10 pF POWER SUPPLY Operating Range 2.7 12 V Quiescent Current/Amplifier 1.3 1.4 mA Quiescent Current (Disabled) DISABLE = Low 145 200 µA Power Supply Rejection Ratio V ± 1 V 70 76 dB S 1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin. Rev. A | Page 5 of 20 AD8029/AD8030/AD8040 ABSOLUTE MAXIMUM RATINGS Table 4. AD8029/AD8030/AD8040 Stress Ratings PD = Quiescent Power + (Total Drive Power – Load Power) Parameter Rating Supply Voltage 12.6 V 2 ⎛ ⎞ V V V Power Dissipation See Figure 6 S OUT OUT ⎜ ⎟ P =() V × I + × – D S S ⎜ ⎟ Common-Mode Input Voltage ±V ± 0.5 V 2 R R S ⎝ L ⎠ L Differential Input Voltage ±1.8 V RMS output voltages should be considered. If RL is referenced to Storage Temperature –65°C to +125°C V –, as in single-supply operation, then the total drive power is S Operating Temperature Range –40°C to +125°C V × I . S OUT Lead Temperature Range 300°C (Soldering 10 sec) If the rms signal levels are indeterminate, consider the worst Junction Temperature 150°C case, when V = V /4 for R to midsupply: OUT S L Stresses above those listed under Absolute Maximum Ratings 2 may cause permanent damage to the device. This is a stress () V /4 S P =() V × I + D S S rating only; functional operation of the device at these or any R L other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute In single-supply operation with R referenced to V –, worst case L S maximum rating conditions for extended periods may affect is V = V /2. OUT S device reliability. Airflow will increase heat dissipation, effectively reducing θJA. MAXIMUM POWER DISSIPATION Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes will The maximum safe power dissipation in the AD8029/AD8030/ reduce the θJA. Care must be taken to minimize parasitic capaci- AD8040 package is limited by the associated rise in junction tances at the input leads of high speed op amps, as discussed in temperature (TJ) on the die. The plastic encapsulating the die the PCB Layout section. locally reaches the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic Figure 6 shows the maximum safe power dissipation in the changes its properties. Even temporarily exceeding this package versus the ambient temperature for the SOIC-8 temperature limit may change the stresses that the package (125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W), exerts on the die, permanently shifting the parametric TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a performance of the AD8029/AD8030/AD8040. Exceeding a JEDEC standard 4-layer board. θJA values are approximations. junction temperature of 175°C for an extended period can result in changes in silicon devices, potentially causing failure. 2.5 The still-air thermal properties of the package and PCB (θJA), ambient temperature (TA), and the total power dissipated in the 2.0 package (PD) determine the junction temperature of the die. The SOIC-14 junction temperature can be calculated as 1.5 TSSOP-14 T = T + (P × θ ) J A D JA SOIC-8 1.0 SOT-23-8 The power dissipated in the package (P ) is the sum of the D quiescent power dissipation and the power dissipated in the SC70-6 0.5 package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (I ). Assuming the load (R ) is referenced to S L 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110120 midsupply, the total drive power is V /2 × I , some of which is S OUT AMBIENT TEMPERATURE (°C) dissipated in the package and some in the load (V × I ). OUT OUT Figure 6. Maximum Power Dissipation The difference between the total drive power and the load power is the drive power dissipated in the package. Output Short Circuit Shorting the output to ground or drawing excessive current from the AD8029/AD8030/AD8040 could cause catastrophic failure. Rev. A | Page 6 of 20 MAXIMUM POWER DISSIPATION (W) 03679-A-018 AD8029/AD8030/AD8040 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: VS = 5 V (TA = 25°C, RL = 1 kΩ tied to midsupply, unless otherwise noted.) 1 0.2 R = 1kΩ F DASHED LINES: V = 2V p-p G = –1 OUT 0 SOLID LINES: V = 0.1V p-p R = R = 1kΩ OUT 0.1 F G –1 –2 0 G = +10 –3 R = 9kΩ, R = 1kΩ –0.1 F G –4 G = +1 –5 –0.2 G = +2 G = +1 –6 R = R = 1kΩ R = 0Ω F –0.3 F G –7 –8 –0.4 G = +2 –9 –0.5 –10 –11 –0.6 –12 –0.7 –13 V = 0.1V p-p O –14 –0.8 0.1 1 10 100 1000 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) 03679-0-004 03679-A-011 Figure 7. Small Signal Frequency Response for Various Gains Figure 10. 0.1 dB Flatness Frequency Response 1 1 G = +1 +3V G = +2 V = 0.1V p-p O V = 0.1V p-p O 0 0 R = 1kΩ F ±5V –1 –1 –2 –2 –3 –3 ±5V –4 –4 +5V –5 –5 –6 –6 +5V –7 –7 +3V –8 –8 1 10 100 1000 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) 03679-0-005 03679-A-012 Figure 8. Small Signal Frequency Response for Various Supplies Figure 11. Small Signal Frequency Response for Various Supplies 1 1 G = +2 G = +1 R = 1kΩ F V = 2V p-p V = 2V p-p O O 0 0 ±5V –1 –1 V =±5 S –2 –2 +3V V = +5 S –3 –3 –4 –4 V = +3 S –5 –5 –6 –6 +5V –7 –7 –8 –8 1 10 100 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) 03679-0-006 03679-A-013 Figure 9. Large Signal Frequency Response for Various Supplies Figure 12. Large Signal Frequency Response for Various Supplies Rev. A | Page 7 of 20 CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) AD8029/AD8030/AD8040 6 2 G = +1 G = +1 V = V – 0.2V ICM S+ 5 V = 0.1V p-p V = 0.1V p-p O O 1 20pF 4 V = 0V ICM 10pF 0 3 2 –1 5pF 1 V = V + 0.2V –2 ICM S– 0 –1 –3 0pF –2 –4 –3 –5 –4 –5 –6 –6 –7 –7 –8 –8 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) 03679-0-010 03679-0-013 Figure 13. Small Signal Frequency Response for Various CLOAD Figure 16. Small Signal Frequency Response for Various Input Common-Mode Voltages 1 2 G = +2 G = +1 +125°C R = 1kΩ F V = 0.1V p-p 0 O 1 +85°C +25°C –1 0 –2 –40°C –1 –3 –2 –4 –3 –5 2V p-p 1V p-p –4 –6 0.1V p-p –7 –5 –8 –6 1 10 100 1 10 100 FREQUENCY (MHz) 03679-A-014 FREQUENCY (MHz) 03679-0-014 Figure 14. Frequency Response for Various Output Amplitudes Figure 17. Small Signal Frequency Response vs. Temperature 80 225 1 G = +1 V = 2V p-p 70 O 0 +125°C 60 180 –1 +25°C 50 –2 40 135 +85°C –3 30 –4 20 90 –40°C –5 10 –6 0 45 –10 –7 –20 0 –8 10 100 1k 10k 100k 1M 10M 100M 1G 1 10 100 FREQUENCY (Hz) 03679-0-054 FREQUENCY (MHz) 03679-0-015 Figure 15. Open-Loop Gain and Phase vs. Frequency Figure 18. Large Signal Frequency Response vs. Temperature Rev. A | Page 8 of 20 OPEN-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) OPEN-LOOP PHASE (Degrees) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) AD8029/AD8030/AD8040 –40 –35 G = +1 G = +1 V = 2V p-p V = 2V p-p OUT OUT SECOND HARMONIC: SOLID LINE R = 1kΩ –45 –50 L THIRD HARMONIC: DASHED LINE SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE –60 –55 –65 –70 R = 1kΩ L V = +3V S –75 –80 –90 –85 V = +5V R = 5kΩ S L V =±5V S –95 –100 R = 2kΩ L –110 –105 0.01 0.1 1 10 0.01 0.1 1 10 FREQUENCY (MHz) FREQUENCY (MHz) 03679-0-016 03679-0-075 Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage Figure 22. Harmonic Distortion vs. Frequency and Load –40 –40 G = +2 G = +1 FREQ = 1MHz V = 2V p-p OUT –45 R = 1kΩ F FREQ = 1MHz –50 V = +5V V = +10V S S –50 V = +3V V = +5V S V = +3V S S –60 –55 –60 –70 –65 –80 –70 –90 –75 SECOND HARMONIC: SOLID LINE SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE THIRD HARMONIC: DASHED LINE –80 –100 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT AMPLITUDE (V p-p) 03679-A-015 INPUT COMMON-MODE VOLTAGE (V) 03679-0-020 Figure 23. Harmonic Distortion vs. Input Common Mode Voltage Figure 20. Harmonic Distortion vs. Output Amplitude 1000 100 –30 V = +5V S V = 2.0V p-p OUT –40 R = 1kΩ L R = 1kΩ F –50 G = +2 100 10 –60 G = –1 –70 VOLTAGE NOISE –80 10 1 CURRENT NOISE –90 G = +1 –100 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 1 0.1 –110 10 100 1k 10k 100k 1M 10M 0.01 0.1 1 10 FREQUENCY (Hz) FREQUENCY (MHz) 03679-0-069 03679-A-016 Figure 24. Voltage and Current Noise vs. Frequency Figure 21. Harmonic Distortion vs. Frequency and Gain Rev. A | Page 9 of 20 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) VOLTAGE NOISE (nV/ Hz) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) CURRENT NOISE (pA/ Hz) AD8029/AD8030/AD8040 100 100 G = +1 G = +1 C = 20pF L V = ±2.5V V = ±2.5V S S C = 10pF 75 75 L C = 5pF L 50 50 25 25 0 0 –25 –25 –50 –50 –75 –75 25mV/DIV 20ns/DIV 25mV/DIV 20ns/DIV –100 –100 TIME (ns) TIME (ns) 03679-0-025 03679-0-022 Figure 28. Small Signal Transient Response with Capacitive Load Figure 25. Small Signal Transient Response 2.5 5.0 G = +1 INPUT 4V p-p V = ±2.5V 4.5 2.0 S 4.0 1.5 1.0 3.5 2V p-p 3.0 0.5 2.5 0 –0.5 2.0 1.5 –1.0 1.0 –1.5 OUTPUT G = +1 V = +5V –2.0 0.5 S R = 1kΩ TIED TO MIDSUPPLY 1µs/DIV L 0.5V/DIV 25ns/DIV –2.5 0 TIME (Seconds) 03679-0-059 TIME (ns) Figure 29. Rail-to-Rail Response, G = +1 Figure 26. Large Signal Transient Response 4 4 G = +1 INPUT G = –1 (R = 1kΩ) INPUT F R = 1kΩ L R = 1kΩ L 3 3 V = ±2.5V S V = ±2.5V S 2 2 OUTPUT OUTPUT 1 1 0 0 –1 –1 –2 –2 –3 –3 1V/DIV 200ns/DIV 1V/DIV 200ns/DIV –4 –4 TIME (ns) 03679-0-027 03679-0-024 TIME (ns) Figure 30. Input Overdrive Recovery Figure 27. Output Overdrive Recovery Rev. A | Page 10 of 20 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 03679-A-023 OUTPUT VOLTAGE (mV) VOLTAGE (V) OUTPUT VOLTAGE (V) AD8029/AD8030/AD8040 V (250mV/DIV) G = +2 IN G = +2 V =±2.5V S V (500mV/DIV) OUT +1V +0.1% +0.1% V – 2V (0.1%/DIV) OUT IN V – 2V (0.1%/DIV) OUT IN –0.1% –0.1% V (500mV/DIV) OUT –1V 500ns/DIV 20ns/DIV 03679-0-062 03679-0-063 Figure 31. Long-Term Settling Time Figure 34.0.1% Short-Term Settling Time –20 0 –10 –30 –20 +PSRR –40 –30 –50 –40 –50 –60 –60 –70 –70 –PSRR –80 –80 –90 –90 –100 –100 1k 10k 100k 1M 10M 100M 1G 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) 03679-0-078 03679-0-033 Figure 32. Common-Mode Rejection Ratio vs. Frequency Figure 35. PSRR vs. Frequency –20 –30 G = +1 V IN DRIVE AMP R = 1kΩ L –40 50Ω DISABLE = LOW –30 1kΩ V = 0.1V p-p –50 IN –60 LISTEN AMP –40 V OUT –70 1kΩ –50 –80 V OUT CROSSTALK = 20log ( ) AD8030 V IN –90 (AMP 2 DRIVE –60 AMP 1 LISTEN) –100 –110 –70 AD8040 –120 (AMP 4 DRIVE AMP 1 LISTEN) –80 –130 0.1 1 10 100 1000 0.01 0.1 1.0 10 100 1000 FREQUENCY (MHz) 03679-0-055 FREQUENCY (MHz) Figure 36. AD8030/AD8040 Crosstalk vs. Frequency Figure 33. AD8029 Off-Isolation vs. Frequency Rev. A | Page 11 of 20 OUTPUT (dB) CMRR (dB) CROSSTALK (dB) PSRR (dB) 03679-A-005 AD8029/AD8030/AD8040 2.5 4 R = 1kΩ TO L MIDSUPPLY 2.0 3 G = +1 V = +5V V = +3V V = +10V S S S 1.5 V = +3V V = +5V V = +10V S S S 2 1.0 1 0.5 0 0 –0.5 –1 –1.0 –2 –1.5 –3 –2.0 –2.5 –4 –1 01234 56789 10 11 –1 0 1 2 345 67 89 10 11 INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) 03679-0-074 03679-A-017 Figure 37. Input Bias Current vs. Input Common-Mode Voltage Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage –1.0 1.0 4 3 –1.2 0.8 NPN ACTIVE 2 V = ±5V S 1 –1.4 0.6 V =±5 V = +5 V = +3 S S S 0 V = +5V S –1.6 0.4 –1 V = +3V S –2 PNP ACTIVE –1.8 0.2 –3 –2.0 0 –4 –40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) 03679-0-073 Figure 38. Input Bias Current vs. Temperature Figure 41. Input Offset Voltage vs. Temperature 1.8 120 COUNT = 1088 MEAN = 0.44mV 1.7 STDEV = 1.05mV 100 1.6 V = +5V S 1.5 V =±5V 80 S 1.4 1.3 60 V = +3V S 1.2 40 1.1 1.0 20 0.9 0.8 0 –40 –20 0 20 40 60 80 100 120 –5 –4 –3 –2 –1 0 1 2 3 4 5 TEMPERATURE (°C) INPUT OFFSET VOLTAGE (mV) 03679-0-067 03679-0-064 Figure 39 Quiescent Supply Current vs. Temperature Figure 42. Input Offset Voltage Distribution Rev. A | Page 12 of 20 INPUT BIAS CURRENT (PNP ACTIVE) (µA) INPUT BIAS CURRENT (µA) SUPPLY CURRENT (mA) INPUT BIAS CURRENT (NPN ACTIVE) (µA) INPUT OFFSET VOLTAGE (mV) FREQUENCY INPUT OFFSET VOLTAGE (mV) 03679-A-006 AD8029/AD8030/AD8040 1M 1000 DISABLE = LOW G = +1 100k 100 10k 1k 10 100 1 10 1 0.1 1k 10k 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G FREQUENCY (Hz) FREQUENCY (Hz) 03679-0-061 03679-0-060 Figure 45. Output Impedance vs. Frequency, Enabled Figure 43. AD8029 Output Impedance vs. Frequency, Disabled 2.0 0.5 LOAD RESISTANCE TIED V =±2.5V S TO MIDSUPPLY 0.4 1.5 0.3 1.0 0.2 V – V OL S 0.5 0.1 R = 10kΩ L V = +3V V = +5V V =±5V 0 0 S S S R = 1kΩ L –0.1 –0.5 V – V OH S –0.2 –1.0 –0.3 –1.5 –0.4 –2.0 –0.5 –2.5 –2.0 –1.5 –1.0 –0.5 –0 0.5 1.0 1.5 2.0 2.5 100 1000 10000 OUTPUT VOLTAGE (V) LOAD RESISTANCE (Ω) 03679-0-072 03679-0-041 Figure 46. Input Error Voltage vs. Output Voltage Figure 44. Output Saturation Voltage vs. Load Resistance 170 V =±5V 150 S 130 110 V = +5V 90 S 70 50 R = 1kΩ TIED TO MIDSUPPLY V = +3V L S SOLID LINE: V – VOH S+ DASHED LINE: VOL – V S– 30 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 03679-0-066 Figure 42. Output Saturation Voltage vs. Temperature Rev. A | Page 13 of 20 OUTPUT SATURATION VOLTAGE (V) OUTPUT SATURATION VOLTAGE (mV) OUTPUT IMPEDANCE (Ω) INPUT ERROR VOLTAGE (mV) OUTPUT IMPEDANCE (Ω) AD8029/AD8030/AD8040 1.5 1 DISABLE (–0.5V TO –2V) V = +3V, +5V, +10V S 0 1.0 –1 0.5 –2 R = 100Ω L OUTPUT DISABLED R = 1kΩ L 0 –3 R = 10kΩ L –4 –0.5 –5 –1.0 –6 V =±2.5V S G = –1 (R = 1kΩ) F –1.5 –7 0 50 100 150 200 250 300 350 01 0.8 1.2 2 3 TIME (ns) DISABLE PIN VOLTAGE (V) 03679-A-020 03679-A-022 Figure 47. AD8029 DISABLE Turn-Off Timing Figure 49. AD8029 DISABLE Pin Current vs. DISABLE Pin Voltage 1.5 DISABLE (–2V TO –0.5V) 1.0 OUTPUT ENABLED 0.5 0 R = 100Ω L –0.5 R = 1kΩ L R = 10kΩ L –1.0 V =±2.5V S G = –1 (R = 1kΩ) F –1.5 0 50 100 150 200 250 300 350 TIME (ns) 03679-A-021 DISABLE Figure 48. AD8029 Turn-On Timing Rev. A | Page 14 of 20 OUTPUT AMPLITUDE (V) OUTPUT AMPLITUDE (V) DISABLE PIN CURRENT (µA) AD8029/AD8030/AD8040 THEORY OF OPERATION +V S R TH I TAIL SPD +V –1.2V S DISABLE Q 9 OUTPUT R R R R 1 2 3 4 BUFFER I TO DISABLE TH CIRCUITRY –V S Q 10 AD8029 ONLY M TOP Q 1 C MT IN– Q 2 Q Q 5 6 V OUT C MB Q Q Q 7 8 3 IN+ Q 4 M BOT R R R R Q 5 6 7 8 11 OUT IN COM –V S 03679-0-051 Figure 50. Simplified Schematic The AD8029 (single), AD8030 (dual), and AD8040 (quad) are OUTPUT STAGE rail-to-rail input and output amplifiers fabricated using Analog The currents derived from the PNP and NPN input differential Devices’ XFCB process. The XFCB process enables the AD8029/ pairs are injected into the current mirrors M and M , thus BOT TOP AD8030/AD8040 to operate on 2.7 V to 12 V supplies with a establishing a common-mode signal voltage at the input of the 120 MHz bandwidth and a 60 V/µs slew rate. A simplified sche- output buffer. matic of the AD8029/AD8030/AD8040 is shown in Figure 50. The output buffer performs three functions: INPUT STAGE 1. It buffers and applies the desired signal voltage to the For input common-mode voltages less than a set threshold output devices, Q and Q . 10 11 (1.2 V below V ), the resistor degenerated PNP differential pair CC (comprising Q toQ ) carries the entire I current, allowing 1 4 TAIL 2. It senses the common-mode current level in the output the input voltage to go 200 mV below –VS. Conversely, input devices. common-mode voltages exceeding the same threshold cause 3. It regulates the output common-mode current by ITAIL to be routed away from the PNP differential pair and into the NPN differential pair through transistor Q9. Under this establishing a common-mode feedback loop. condition, the input common-mode voltage is allowed to rise The output devices Q10 and Q11 work in a common-emitter 200 mV above +V while still maintaining linear amplifier S configuration, and are Miller-compensated by internal behavior. The transition between these two modes of operation capacitors, CMT and CMB. leads to a sudden, temporary shift in input stage transconduc- tance, gm, and dc parameters (such as the input offset voltage The output voltage compliance is set by the output devices’ VOS), which in turn adversely affect the distortion performance. collector resistance R (about 25 Ω), and by the required load C The SPD block shortens the duration of this transition, thus current I . For instance, a light equivalent load (5 kΩ) allows the L improving the distortion performance. As shown in Figure 50, output voltage to swing to within 40 mV of either rail, while the input differential pair is protected by a pair of two series heavier loads cause this figure to deteriorate as RC × IL. diodes, connected in anti-parallel, which clamp the differential input voltage to approximately ±1.5 V. Rev. A | Page 15 of 20 AD8029/AD8030/AD8040 APPLICATIONS WIDEBAND OPERATION R F For example, if using the values shown in Table 5 for a gain of 2, with resistor values of 2.5 kΩ, the effective load at the output is C2 +V S 10µF 1.67 kΩ. For inverting configurations, only the feedback resistor RF is in parallel with the output load. If the load is greater than C1 0.1µF that specified in the data sheet, the amplifier can introduce R G nonlinearities in its open-loop response, which increases – distortion. Figure 53 and Figure 54 illustrate effective output V AD8029 OUT R1 loading and distortion performance. Increasing the resistance of V + IN DISABLE C4 the feedback network can reduce the current consumption, but 0.1µF has other implications. C3 R1 = R ||R 10µF F G –40 V V = 5V = 5V S S V V = 2.0V p-p = 0.1V p-p OUT OUT –V 03679-0-052 S –50 SECOND HARMONIC – SOLID LINES THIRD HARMONIC – DOTTED LINES Figure 51. Wideband Non-inverting Gain Configuration –60 R F –70 R = 1kΩ L C2 +V S –80 10µF –90 C1 R = 5kΩ L 0.1µF R –100 G R = 2.5kΩ V – L IN V –110 AD8029 OUT + DISABLE –120 R1 = R ||R C4 F G 0.01 0.1 1.0 10 0.1µF FREQUENCY (MHz) R1 C3 Figure 53. Gain of 1 Distortion 10µF –40 V = 5V –V V = 5V S 03679-0-053 S S V V = 2.0V p-p = 0.1V p-p OUT OUT –50 SECOND HARMONIC – SOLID LINES Figure 52. Wideband Inverting Gain Configuration THIRD HARMONIC – DOTTED LINES –60 R = R = 1kΩ F L OUTPUT LOADING SENSITIVITY –70 To achieve maximum performance and low power dissipation, –80 the designer needs to consider the loading at the output of R = R = 5kΩ F L AD8029/AD8030/AD8040. Table 5 shows the effects of output –90 loading and performance. –100 R = R = 2.5kΩ F L When operating at unity gain, the effective load at the amplifier –110 output is the resistance (R ) being driven by the amplifier. For L –120 gains other than 1, in noninverting configurations, the feedback 0.01 0.1 1.0 10 FREQUENCY (MHz) network represents an additional current load at the amplifier output. The feedback network (RF + RG) is in parallel with RL, Figure 54. Gain of 2 Distortion which lowers the effective resistance at the output of the amplifier. The lower effective resistance causes the amplifier to supply more current at the output. Lower values of feedback resistance increase the current draw, thus increasing the amplifier’s power dissipation. Rev. A | Page 16 of 20 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 03679-A-009 03679-A-008 AD8029/AD8030/AD8040 Table 5. Effect of Load on Performance Noninverting R R R –3 dB SS BW Peaking HD2 at 1 MHz, HD3 at 1 MHz, Output Noise F G LOAD Gain (kΩ) (kΩ) (kΩ) (MHz) (dB) 2 V p-p (dB) 2 V p-p (dB) (nV/√Hz) 1 0 N/A 1 120 0.02 –80 –72 16.5 1 0 N/A 2 130 0.6 –84 –83 16.5 1 0 N/A 5 139 1 –87.5 –92.5 16.5 2 1 1 1 36 0 –72 –60 33.5 2 2.5 2.5 2.5 44.5 0.2 –79 –72.5 34.4 2 5 5 5 43 2 –84 –86 36 –1 1 1 1 40 0.01 –68 –57 33.6 –1 2.5 2.5 2.5 40 0.05 –74 –68 34 –1 5 5 5 34 1 –78 –80 36 The feedback resistance (R || R ) combines with the input DISABLE PIN F G capacitance to form a pole in the amplifier’s loop response. This The AD8029 disable pin allows the amplifier to be shut down can cause peaking and ringing in the amplifier’s response if the for power conservation or multiplexing applications. When in RC time constant is too low. Figure 55 illustrates this effect. the disable mode, the amplifier draws only 150 µA of quiescent Peaking can be reduced by adding a small capacitor (1 pF–4 pF) current. The disable pin control voltage is referenced to the across the feedback resistor. The best way to find the optimal negative supply. The amplifier enters power-down mode any value of capacitor is to empirically try it in your circuit. Another time the disable pin is tied to the most negative supply or within factor of higher resistance values is the impact it has on noise 0.8 V of the negative supply. If left open, the amplifier will performance. Higher resistor values generate more noise. Each operate normally. For switching levels, refer to Table 6. application is unique and therefore a balance must be reached between distortion, peaking, and noise performance. Table 5 Table 6. Disable Pin Control Voltage outlines the trade-offs that different loads have on distortion, Supply Voltage Disable Pin peaking, and noise performance. In gains of 1, 2, and 10, Voltage +3 V +5 V ±5 V equivalent loads of 1 kΩ, 2 kΩ, and 5 kΩ are shown. Low (Disabled) 0 V to <0.8 V 0 V to <0.8 V –5 V to <–4 .2 V With increasing load resistance, the distortion and –3 dB High bandwidth improve, while the noise and peaking degrade (Enabled) 1.2 V to 3 V 1.2 V to 5 V –3.8 V to +5 V slightly. 2 V = 5V S R = R = 5kΩ F L V = 0.1V p-p OUT R = 1kΩ 1 L 0 R = 2.5kΩ L –1 R = R = 2.5kΩ F L R = 5kΩ L –2 R = R = 1kΩ F L –3 –4 G = +1 –5 –6 G = +2 –7 –8 1 10 100 1000 FREQUENCY (MHz) Figure 55. Frequency Response for Various Feedback/Load Resistances Rev. A | Page 17 of 20 NORMALIZED CLOSED-LOOP GAIN (dB) 03679-A-007 AD8029/AD8030/AD8040 CIRCUIT CONSIDERATIONS PCB Layout Power Supply Bypassing High speed op amps require careful attention to PCB layout to Power supply pins are actually inputs to the op amp. Care must achieve optimum performance. Particular care must be be taken to provide the op amp with a clean, low noise dc exercised to minimize lead lengths of the bypass capacitors. voltage source. Excess lead inductance can influence the frequency response Power supply bypassing is employed to provide a low imped- and even cause high frequency oscillations. Using a multilayer ance path to ground for noise and undesired signals at all board with an internal ground plane can help reduce ground frequencies. This cannot be achieved with a single capacitor noise and enable a more compact layout. type; but with a variety of capacitors in parallel the bandwidth To achieve the shortest possible trace length at the inverting of power supply bypassing can be greatly extended. The bypass input, the feedback resistor, R , should be located the shortest capacitors have two functions: F distance from the output pin to the input pin. The return node 1. Provide a low impedance path for noise and undesired of the resistor R should be situated as close as possible to the G signals from the supply pins to ground. return node of the negative supply bypass capacitor. 2. Provide local stored charge for fast switching conditions On multilayer boards, all layers beneath the op amp should be and minimize the voltage drop at the supply pins during cleared of metal to avoid creating parasitic capacitive elements. transients. This is typically achieved with large electrolytic This is especially true at the summing junction, i.e., the inver- capacitors. ting input, –IN. Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower Good quality ceramic chip capacitors should be used and phase margin. always kept as close as possible to the amplifier package. A parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic Grounding covers a wide range of rejection for unwanted noise. The 10 µF To minimize parasitic inductances and ground loops in high capacitor is less critical for high frequency bypassing and, in speed, densely populated boards, a ground plane layer is critical. most cases, one per supply line is sufficient. The values of Understanding where the current flows in a circuit is critical in capacitors are circuit-dependant and should be determined by the implementation of high speed circuit design. The length of the system’s requirements. the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of DESIGN TOOLS AND TECHNICAL SUPPORT the path. Fast current changes in an inductive ground return Analog Devices is committed to the design process by providing will create unwanted noise and ringing. technical support and online design tools. ADI offers technical The length of the high frequency bypass capacitor pads and support via free evaluation boards, sample ICs, Spice models, traces is critical. A parasitic inductance in the bypass grounding interactive evaluation tools, application notes, phone and email works against the low impedance created by the bypass support—all available at www.analog.com. capacitor. Because load currents flow from supplies as well as from ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. Rev. A | Page 18 of 20 AD8029/AD8030/AD8040 OUTLINE DIMENSIONS 5.00 (0.1968) 8.75 (0.3445) 4.80 (0.1890) 8.55 (0.3366) 85 14 8 4.00 (0.1574) 6.20 (0.2440) 4.00 (0.1575) 6.20 (0.2441) 1 5.80 (0.2284) 3.80 (0.1496) 7 5.80 (0.2283) 3.80 (0.1497) 1 4 1.27 (0.0500) 0.50 (0.0197) 1.27 (0.0500) 0.50 (0.0196) 1.75 (0.0689) × 45° 
BSC × 45° BSC 1.75 (0.0688) 0.25 (0.0098) 0.25 (0.0098) 0.25 (0.0099) 1.35 (0.0531) 1.35 (0.0532) 0.10 (0.0039) 0.25 (0.0098) 8° 0.10 (0.0040)
0.51 (0.0201)
8° SEATING 0° 1.27 (0.0500) 0.51 (0.0201) COPLANARITY 0.25 (0.0098) 0° 1.27 (0.0500) 0.31 (0.0122) PLANE COPLANARITY 0.10 0.40 (0.0157) 0.25 (0.0098) 0.31 (0.0122) 0.17 (0.0067) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-012AA (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 56. 8-Lead Standard Small Outline Package, Narrow Body [SOIC] (R-8) Figure 59. 14-Lead Standard Small Outline Package [SOIC] (R-14) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters and (inches) 2.00 BSC 5.10 5.00 4.90 6 5 4 2.10 BSC 1.25 BSC 14 8 1 2 3 4.50 PIN 1 6.40 4.40 BSC 0.65 BSC 4.30 1.30 BSC 1.00 1 7 1.10 MAX 0.90 0.70 PIN 1 0.22 0.08 0.65 1.05 0.46 BSC 1.00 8° 0.36 0.30 0.20 0.10 MAX 0.80 1.20 4° 0.26 SEATING 0.15 0.09 0.75 MAX PLANE 0° 8° 0.60 0.15 0.10 COPLANARITY 0.30 0° 0.45 0.05 SEATING 0.19 COPLANARITY PLANE COMPLIANT TO JEDEC STANDARDS MO-203AB 0.10 COMPLIANT TO JEDEC STANDARDS MO-153AB-1 Figure 57. 6-Lead Plastic Surface-Mount Package [SC70] (KS-6) Dimensions shown in millimeters Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 13 2 4 PIN 1 0.65 BSC 1.95 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.60 8° 0.45 0.38 0.15 MAX 4° 0.30 0.22 SEATING 0° PLANE COMPLIANT TO JEDEC STANDARDS MO-178BA Figure 58. 8-Lead Small Outline Transistor Package [SOT23] (RJ-8) Dimensions shown in millimeters Rev. A | Page 19 of 20 AD8029/AD8030/AD8040 ORDERING GUIDE Model Minimum Ordering Quantity Temperature Range Package Description Package Option Branding AD8029AR 1 –40°C to +125°C 8-Lead SOIC R-8 AD8029AR-REEL 2,500 –40°C to +125°C 8-Lead SOIC R-8 AD8029AR-REEL7 1,000 –40°C to +125°C 8-Lead SOIC R-8 AD8029AKS-R2 250 –40°C to +125°C 6-Lead SC70 KS-6 H6B AD8029AKS-REEL 10,000 –40°C to +125°C 6-Lead SC70 KS-6 H6B AD8029AKS-REEL7 3,000 –40°C to +125°C 6-Lead SC70 KS-6 H6B AD8030AR 1 –40°C to +125°C 8-Lead SOIC R-8 AD8030AR-REEL 2,500 –40°C to +125°C 8-Lead SOIC R-8 AD8030AR-REEL7 1,000 –40°C to +125°C 8-Lead SOIC R-8 AD8030ARJ-R2 250 –40°C to +125°C 8-Lead SOT23-8 RJ-8 H7B AD8030ARJ-REEL 10,000 –40°C to +125°C 8-Lead SOT23-8 RJ-8 H7B AD8030ARJ-REEL7 3,000 –40°C to +125°C 8-Lead SOT23-8 RJ-8 H7B AD8040AR 1 –40°C to +125°C 14-Lead SOIC R-14 AD8040AR-REEL 2500 –40°C to +125°C 14-Lead SOIC R-14 AD8040AR-REEL7 1000 –40°C to +125°C 14-Lead SOIC R-14 AD8040ARU 1 –40°C to +125°C 14-Lead TSSOP RU-14 AD8040ARU-REEL 2500 –40°C to +125°C 14-Lead TSSOP RU-14 AD8040ARU-REEL7 1000 –40°C to +125°C 14-Lead TSSOP RU-14 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03679–0–11/03(A) Rev. A | Page 20 of 20