ANALOG DEVICES AD8039

Low Power, 350 MHz Voltage Feedback Amplifiers AD8038/AD8039 FEATURES FUNCTIONAL BLOCK DIAGRAM Low power: 1 mA supply current/amp AD8038 NC 1 8 DISABLE –IN 2 7 +V High speed S +IN 3 6 V OUT 350 MHz, −3 dB bandwidth (G = +1) –V 4 5 NC S 425 V/μs slew rate Low cost NC = NO CONNECT Low noise Figure 1. 8-lead SOIC (R) 8 nV/√Hz @ 100 kHz AD8038 V 1 600 fA/√Hz @ 100 kHz 5 +V OUT S Low input bias current: 750 nA maximum –V 2 S Low distortion +IN 3 4 –IN −90 dB SFDR @ 1 MHz −65 dB SFDR @ 5 MHz Figure 2. 5-Lead SC70 (KS) Wide supply range: 3 V to 12 V AD8039 Small packaging: 8-lead SOT-23, 5-lead SC70, and 8-lead SOIC V 1 8 +V OUT1 S APPLICATIONS –IN1 2 7 V OUT2 Battery-powered instrumentation +IN1 3 6 –IN2 Filters –V 4 5 +IN2 S A/D drivers NC = NO CONNECT Level shifting Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ) Buffering Photo multipliers GENERAL DESCRIPTION The AD8038 (single) and AD8039 (dual) amplifiers are high speed The AD8039 amplifier is available in a 8-lead SOT-23 package, (350 MHz) voltage feedback amplifiers with an exceptionally low and the single AD8038 is available in both an 8-lead SOIC and a quiescent current of 1.0 mA/amplifier typical (1.5 mA maximum). 5-lead SC70 package. These amplifiers are rated to work over The AD8038 single amplifier in the 8-lead SOIC package has a the industrial temperature range of −40°C to +85°C. disable feature. Despite being low power and low cost, the amplifier 24 provides excellent overall performance. Additionally, it offers a G = +10 21 high slew rate of 425 V/μs and a low input offset voltage of 3 mV 18 maximum. 15 G = +5 The Analog Devices, Inc., proprietary XFCB process allows low 12 noise operation (8 nV/√Hz and 600 fA/√Hz) at extremely low 9 quiescent currents. Given a wide supply voltage range (3 V to 12 V), G = +2 6 wide bandwidth, and small packaging, the AD8038 and AD8039 3 amplifiers are designed to work in a variety of applications G = +1 where power and space are at a premium. 0 The AD8038 and AD8039 amplifiers have a wide input common- –3 mode range of 1 V from either rail and swing to within 1 V of each –6 0.1 1 10 100 1000 rail on the output. These amplifiers are optimized for driving FREQUENCY (MHz) capacitive loads up to 15 pF. If driving larger capacitive loads, a small Figure 4. Small Signal Frequency Response for Various Gains, series resistor is needed to avoid excessive peaking or overshoot. V = 500 mV p-p, V = ±5 V OUT S Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 02951-002 02951-003 02951-001 02951-004 AD8038/AD8039 TABLE OF CONTENTS Features .............................................................................................. 1  Disable ......................................................................................... 13  Applications ....................................................................................... 1  Power Supply Bypassing ............................................................ 13  Functional Block Diagram .............................................................. 1  Grounding ................................................................................... 13  General Description ......................................................................... 1  Input Capacitance ...................................................................... 13  Revision History ............................................................................... 2  Output Capacitance ................................................................... 13  Specif ica t ions ..................................................................................... 3  Input-to-Output Coupling ........................................................ 13  Absolute Maximum Ratings ............................................................ 5  Applications Information .............................................................. 14  Maximum Power Dissipation ..................................................... 5  Low Power ADC Driver ............................................................ 14  Output Short Circuit .................................................................... 5  Low Power Active Video Filter ................................................. 14  ESD Caution .................................................................................. 5  Outline Dimensions ....................................................................... 15  Typical Performance Characteristics ............................................. 6  Ordering Guide .......................................................................... 16  Layout, Grounding, and Bypassing Considerations .................. 13  REVISION HISTORY 8/09—Rev. F to Rev. G 5/02—Rev. A to Rev. B Changes to Applications Section and General Description Add Part Number AD8038 ............................................... Universal Section ................................................................................................ 1 Changes to Product Title .................................................................. 1 Changes to Disable Section and Grounding Section ................. 13 Changes to Features .......................................................................... 1 Changes to Low Power ADC Driver Section and Low Power Changes to Product Description ..................................................... 1 Changes to Connection Diagram .................................................... 1 Active Video Filter Section ............................................................ 14 Updated Outline Dimensions ....................................................... 15 Update to Specifications ................................................................... 2 Changes to Ordering Guide .......................................................... 16 Update to Maximum Power Dissipation ........................................ 4 Update to Output Short Circuit ....................................................... 4 8/04—Rev. E to Rev. F Update to Ordering Guide ............................................................... 4 Changes to Figure 4 ........................................................................ 10 Change to Figure 2 ............................................................................ 4 8/03—Rev. D to Rev. E Change to TPC 2 ............................................................................... 5 Change to TPC 18 ............................................................................. 6 Change to TPC 34............................................................................. 8 Change to TPC 27 ............................................................................. 7 7/03—Rev. C to Rev. D Change to TPC 29 ............................................................................. 8 Changes to Ordering Guide ............................................................ 4 Change to TPC 30 ............................................................................. 8 Updated TPC 35 Caption ................................................................ 8 Change to TPC 31 ............................................................................. 8 Added TPC 36 .................................................................................... 8 6/03—Rev. B to Rev. C Added TPC 37 .................................................................................... 9 Updated Connection Diagrams ...................................................... 1 Edits to Low Power Active Video Filter ....................................... 10 Updated Ordering Guide ................................................................. 4 Change to Figure 4 ......................................................................... 10 Updated Outline Dimensions ....................................................... 11 4/02—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Update Specifications ................................................................... 2, 3 Edits to TPC 19 .................................................................................. 7 Rev. G | Page 2 of 16 AD8038/AD8039 SPECIFICATIONS TA = 25°C, VS = ±5 V, RL = 2 kΩ, Gain = +1, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.5 V p-p 300 350 MHz O G = +2, VO = 0.5 V p-p 175 MHz G = +1, VO = 2 V p-p 100 MHz Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 45 MHz Slew Rate G = +1, V = 2 V step, R = 2 kΩ 400 425 V/μs O L Overdrive Recovery Time G = +2, 1 V overdrive 50 ns Settling Time to 0.1% G = +2, V = 2 V step 18 ns O NOISE/HARMONIC PERFORMANCE SFDR Second Harmonic fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ −90 dBc Third Harmonic fC = 1 MHz, VO = 2 V p-p, RL = 2 kΩ −92 dBc Second Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −65 dBc Third Harmonic f = 5 MHz, V = 2 V p-p, R = 2 kΩ −70 dBc C O L Crosstalk, Output-to-Output (AD8039) f = 5 MHz, G = +2 −70 dB Input Voltage Noise f = 100 kHz 8 nV/√Hz Input Current Noise f = 100 kHz 600 fA/√Hz DC PERFORMANCE Input Offset Voltage 0.5 3 mV Input Offset Voltage Drift 4.5 μV/°C Input Bias Current 400 750 nA Input Bias Current Drift 3 nA/°C Input Offset Current ±25 nA Open-Loop Gain V = ±2.5 V 70 dB O INPUT CHARACTERISTICS Input Resistance 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range RL = 1 kΩ ±4 V Common-Mode Rejection Ratio VCM = ±2.5 V 61 67 dB OUTPUT CHARACTERISTICS DC Output Voltage Swing RL = 2 kΩ, saturated output ±4 V Capacitive Load Drive 30% overshoot, G = +2 20 pF POWER SUPPLY Operating Range 3.0 12 V Quiescent Current per Amplifier 1.0 1.5 mA Power Supply Rejection Ratio −Supply −71 −77 dB +Supply −64 −70 dB 1 POWER-DOWN DISABLE Turn-On Time 180 ns Turn-Off Time 700 ns Disable Voltage—Part is Off +V − 4.5 V S Disable Voltage—Part is On +VS − 2.5 V Disabled Quiescent Current 0.2 mA Disabled In/Out Isolation f = 1 MHz −60 dB 1 Only available in AD8038 8-lead SOIC package. Rev. G | Page 3 of 16 AD8038/AD8039 T = 25°C, V = 5 V, R = 2 kΩ to V /2, Gain = +1, unless otherwise noted. A S L S Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p 275 300 MHz O G = +2, V = 0.2 V p-p 150 MHz O G = +1, V = 2 V p-p 30 MHz O Bandwidth for 0.1 dB Flatness G = +2, VO = 0.2 V p-p 45 MHz Slew Rate G = +1, VO = 2 V step, RL = 2 kΩ 340 365 V/μs Overdrive Recovery Time G = +2, 1 V overdrive 50 ns Settling Time to 0.1% G = +2, V = 2 V step 18 ns O NOISE/HARMONIC PERFORMANCE SFDR Second Harmonic f = 1 MHz, V = 2 V p-p, R = 2 kΩ −82 dBc C O L Third Harmonic f = 1 MHz, V = 2 V p-p, R = 2 kΩ −79 dBc C O L Second Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −60 dBc Third Harmonic fC = 5 MHz, VO = 2 V p-p, RL = 2 kΩ −67 dBc Crosstalk, Output-to-Output f = 5 MHz, G = +2 −70 dB Input Voltage Noise f = 100 kHz 8 nV/√Hz Input Current Noise f = 100 kHz 600 fA/√Hz DC PERFORMANCE Input Offset Voltage 0.8 3 mV Input Offset Voltage Drift 3 μV/°C Input Bias Current 400 750 nA Input Bias Current Drift 3 nA/°C Input Offset Current ±30 nA Open-Loop Gain VO = ±2.5 V 70 dB INPUT CHARACTERISTICS Input Resistance 10 MΩ Input Capacitance 2 pF Input Common-Mode Voltage Range R = 1 kΩ 1.0 − 4.0 V L Common-Mode Rejection Ratio V = ±1 V 59 65 dB CM OUTPUT CHARACTERISTICS DC Output Voltage Swing R = 2 kΩ, saturated output 0.9 − 4.1 V L Capacitive Load Drive 30% overshoot 20 pF POWER SUPPLY Operating Range 3 12 V Quiescent Current per Amplifier 0.9 1.5 mA Power Supply Rejection Ratio −65 −71 dB 1 POWER-DOWN DISABLE Turn-On Time 210 ns Turn-Off Time 700 ns Disable Voltage—Part is Off +VS − 4.5 V Disable Voltage—Part is On +VS − 2.5 V Disabled Quiescent Current 0.2 mA Disabled In/Out Isolation f = 1 MHz −60 dB 1 Only available in AD8038 8-lead SOIC package. Rev. G | Page 4 of 16 AD8038/AD8039 ABSOLUTE MAXIMUM RATINGS 2.0 Table 3. Parameter Rating 1.5 Supply Voltage 12.6 V SOIC-8 Power Dissipation See Figure 5 Common-Mode Input Voltage ±V S SOT-23-8 1.0 Differential Input Voltage ±4 V SC70-5 Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C 0.5 Lead Temperature (Soldering, 10 sec) 300°C Stresses above those listed under Absolute Maximum Ratings 0 may cause permanent damage to the device. This is a stress –55 –25 5 35 65 95 125 AMBIENT TEMPERATURE (°C) rating only; functional operation of the device at these or any Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute RMS output voltages should be considered. If RL is referenced to maximum rating conditions for extended periods may affect VS−, as in single-supply operation, then the total drive power is device reliability. VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS /4 for RL to midsupply MAXIMUM POWER DISSIPATION 2 P = (V × I ) + (V /4) /R D S S S L The maximum safe power dissipation in the AD8038/AD8039 package is limited by the associated rise in junction temperature In single-supply operation with R referenced to V , worst case L S− (T ) on the die. The plastic encapsulating the die locally reaches J is V = V /2. OUT S the junction temperature. At approximately 150°C, which is the Airflow increases heat dissipation, effectively reducing θ . In JA glass transition temperature, the plastic changes its properties. addition, more metal directly in contact with the package leads Even temporarily exceeding this temperature limit may change from metal traces, throughholes, ground, and power planes reduce the stresses that the package exerts on the die, permanently the θJA. Care must be taken to minimize parasitic capacitances at shifting the parametric performance of the AD8038/AD8039. the input leads of high speed op amps as discussed in the Exceeding a junction temperature of 175°C for an extended Layout, Grounding, and Bypassing Considerations section. time can result in changes in the silicon devices, potentially Figure 5 shows the maximum safe power dissipation in the causing failure. package vs. the ambient temperature for the 8-lead SOIC The still-air thermal properties of the package and PCB (θ ), JA (125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23 ambient temperature (T ), and total power dissipated in the A (160°C/W) packages on a JEDEC standard 4-layer board. ) determine the junction temperature of the die. package (PD θJA values are approximations. The junction temperature can be calculated as OUTPUT SHORT CIRCUIT TJ = TA + (PD × θJA) Shorting the output to ground or drawing excessive current The power dissipated in the package (PD) is the sum of the from the AD8038/AD8039 will likely cause a catastrophic failure. quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V ) multiplied by the S ESD CAUTION quiescent current (I ). Assuming the load (R ) is referenced to S L midsupply, then the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. P = quiescent power + (total drive power − load power) D 2 P = [V × I ] + [(V /2) × (V /R )] − [V /R ] D S S S OUT L OUT L Rev. G | Page 5 of 16 MAXIMUM POWER DISSIPATION (W) 02951-005 AD8038/AD8039 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: ±5 V, CL = 5 pF, G = +2, RG = RF = 1 kΩ, RL = 2 kΩ, VO = 2 V p-p, Frequency = 1 MHz, TA = 25°C. 24 7 G = +10 21 R = 2kΩ L 6 18 5 G = +5 15 R = 500Ω L 12 4 9 G = +2 3 6 = 1kΩ 3 R L 2 G = +1 0 1 –3 –6 0 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response for Various Gains, Figure 9. Small Signal Frequency Response for Various RL, VOUT = 500 mV p-p VS = 5 V, VOUT = 500 mV p-p 7 8 V = ±1.5V S R = 2kΩ 6 L V = ±2.5V 7 S 5 6 V = ±5V S R = 500Ω L 4 5 4 3 3 2 R = 1kΩ L 2 1 1 0 0.1 1 10 100 1000 0 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 7. Small Signal Frequency Response for Various Supplies, Figure 10. Large Signal Frequency Response for Various RL, VOUT = 500 mV p-p VOUT = 3 V p-p, VS = 5 V 7 8 R = 2kΩ L 6 7 R = 2kΩ L 6 5 5 R = 500Ω L 4 4 3 R = 500Ω 3 L R = 1kΩ L 2 R = 1kΩ L 2 1 1 0 0 0.1 1 10 100 1000 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Small Signal Frequency Response for Various RL, Figure 11. Large Signal Frequency Response for Various R , L VS = ±5 V, VOUT = 500 mV p-p V = 4 V p-p, V = ±5 V OUT S Rev. G | Page 6 of 16 GAIN (dB) GAIN (dB) GAIN (dB) 02951-008 02951-007 02951-006 GAIN (dB) GAIN (dB) GAIN (dB) 02951-011 02951-010 02951-009 AD8038/AD8039 5 80 180 C = 15pF L 4 70 3 60 135 C = 10pF L 50 2 PHASE 1 40 90 30 0 GAIN 20 45 –1 C = 5pF L 10 –2 0 0 –3 –10 –4 –20 –45 –5 0.01 0.1 1 10 100 1000 11 1000 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Small Signal Frequency Response for Various C , Figure 15. Open-Loop Gain and Phase, VS = ±5 V L V = 500 mV p-p, V = ±5 V, G = +1 OUT S 9 7 C = 15pF L 5 6 –40°C 3 C = 10pF L +25°C 3 1 +85°C –1 C = 5pF L 0 –3 –3 –5 0.1 1 10 100 1000 11 1000 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 16. Frequency Response vs. Temperature, Figure 13. Small Signal Frequency Response for Various CL, Gain = +2, VS = ±5 V, VOUT = 2 V p-p VOUT = 500 mV p-p, VS = 5 V, G = +1 –50 2 V = 200mV R = 500Ω HD2 L OUT –55 1 V = 1V OUT R = 500Ω HD3 L –60 0 –65 –1 –70 –2 V = 500mV OUT R = 2kΩ HD3 L –75 –3 R = 2kΩ HD2 L V = 2V OUT –80 –4 –85 –5 –90 –6 126 3 4 578 9 10 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 17. Harmonic Distortion vs. Frequency for Various Loads, Figure 14. Frequency Response for Various Output Voltage Levels VS = ±5 V, VOUT = 2 V p-p, G = +2 Rev. G | Page 7 of 16 GAIN (dB) GAIN (dB) GAIN (dB) 02951-014 02951-013 02951-012 OPEN-LOOP GAIN (dB) GAIN (dB) HARMONIC DISTORTION (dBc) PHASE (Degrees) 02951-017 02951-016 02951-015 AD8038/AD8039 –40 –45 10MHz HD2 –50 R = 500Ω HD2 L –50 –55 5MHz HD2 R = 500Ω HD3 10MHz HD3 L –60 –60 5MHz HD3 –65 –70 –70 R = 2kΩ HD3 1MHz HD3 L –75 –80 R = 2kΩ HD2 1MHz HD2 L –80 –90 –85 –90 –100 15 2 3 4 678 9 10 1 234 FREQUENCY (MHz) AMPLITUDE (V p-p) Figure 18. Harmonic Distortion vs. Frequency for Various Loads, Figure 21. Harmonic Distortion vs. VOUT Amplitude for Various Frequencies, VS = 5 V, VOUT = 2 V p-p, G = +2 VS = ±5 V, G = +2 –50 –45 10MHz HD2 G = +1 HD2 –55 –60 10MHz HD3 G = +2 HD2 5MHz HD2 –70 –65 5MHz HD3 G = +2 HD3 –80 –75 1MHz HD3 G = +1 HD3 1MHz HD2 –90 –85 –100 –95 15 2 3 4 6789 10 1.0 1.5 2.0 2.5 3.0 FREQUENCY (MHz) AMPLITUDE (V p-p) Figure 19. Harmonic Distortion vs. Frequency for Various Gains, Figure 22. Harmonic Distortion vs. Amplitude for Various Frequencies, VS = ±5 V, VOUT = 2 V p-p VS = 5 V, G = +2 1000 –50 G = +1 HD2 –60 G = +2 HD2 100 –70 G = +2 HD3 –80 10 G = +1 HD3 –90 1 10 100 1k 10k 100k 1M 10M 100M –100 15 2 3 4 678 9 10 FREQUENCY (Hz) Figure 23. Input Voltage Noise vs. Frequency Figure 20. Harmonic Distortion vs. Frequency for Various Gains, V = 5 V, V = 2 V p-p S OUT Rev. G | Page 8 of 16 FREQUENCY (MHz) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 02951-019 02951-018 02951-020 VOLTAGE NOISE (nV/ Hz) HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 02951-021 02951-022 02951-023 AD8038/AD8039 100k C = 25pF WITH L R = 19.6Ω SNUB 10k C = 5pF L 1k C = 10pF L 50mV/DIV 5ns/DIV 100 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 27. Small Signal Transient Response for Various CL, VS = 5 V Figure 24. Input Current Noise vs. Frequency = 500Ω R L R = 2kΩ C = 25pF WITH L L R = 19.6Ω SNUB C = 5pF L C = 10pF L 50mV/DIV 5ns/DIV 50mV/DIV 5ns/DIV Figure 25. Small Signal Transient Response for Various RL, VS = 5 V Figure 28. Small Signal Transient Response for Various CL, VS = ±5 V R = 2kΩ R = 500Ω L L R = 500Ω L R = 2kΩ L 2.5V 50mV/DIV 5ns/DIV 500mV/DIV 5ns/DIV Figure 26. Small Signal Transient Response for Various RL, VS = ±5 V Figure 29. Large Signal Transient Response for Various RL, VS = 5 V Rev. G | Page 9 of 16 NOISE (fA/√Hz) 02951-026 02951-025 02951-024 02951-029 02951-028 02951-027 AD8038/AD8039 IN R = 2kΩ L R = 500Ω L OUT 1V/DIV 5ns/DIV 2V/DIV 50ns/DIV Figure 30. Large Signal Transient Response for Various R , V = ±5 V Figure 33. Input Overdrive Recovery, Gain = +1 L S C = 25pF L IN OUT C = 5pF L 2.5V INPUT 1V/DIV 500mV/DIV 5ns/DIV OUTPUT 2V/DIV 50ns/DIV Figure 31. Large Signal Transient Response for Various CL, VS = 5 V Figure 34. Output Overdrive Recovery, Gain = +2 C = 10pF V = ±5V 2mV/DIV L S G = +2 V = 2V p-p OUT C = 5pF L ERROR VOLTAGE +0.1% 0 t = 0 –0.1% V IN 500mV/DIV 5ns/DIV 0.5V/DIV 5ns/DIV Figure 35. 0.1% Settling Time V = 2 V p-p Figure 32. Large Signal Transient Response for Various CL, VS = ±5 V OUT Rev. G | Page 10 of 16 02951-031 02951-032 02951-030 02951-033 02951-034 02951-035 AD8038/AD8039 –10 10 0 –20 –10 –30 –20 –40 –PSRR –30 –50 SIDE B –40 –60 +PSRR SIDE A –50 –70 –60 –80 –70 –90 –80 –100 –90 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 36. AD8039 Crosstalk, VIN = 1 V p-p, Gain = +1 Figure 39. PSRR vs. Frequency 9 –10 8 V = ±5V S –20 7 –30 6 5 –40 4 V = +5V V = ±5V S S –50 V = +5V S 3 –60 2 1 –70 0 0 100 200 300 400 500 –80 1 10 100 1000 R (Ω) LOAD FREQUENCY (MHz) Figure 40. Output Swing vs. Load Resistance Figure 37. CMRR vs. Frequency, VIN = 1 V p-p 1.25 1000 1.00 100 0.75 10 0.50 1 0.25 V = ±5V S V = +5V S 0 0.1 0.01 0.1 1 10 100 1000 01 2468 102 SUPPLY VOLTAGE (V) FREQUENCY (MHz) Figure 41. AD8038 Supply Current vs. Supply Voltage Figure 38. Output Impedance vs. Frequency Rev. G | Page 11 of 16 CMRR (dB) IMPEDANCEΩ) CROSSTALK (dB) 02951-038 02951-037 02951-036 PSRR (dB) V (p-p) SUPPLY CURRENT (mA) OUT 02951-041 02951-040 02951-039 AD8038/AD8039 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 42. AD8038 Input-Output Isolation (G = +2, RL = 2 kΩ, VS = ±5 V) Rev. G | Page 12 of 16 ISOLATION (dB) 02951-042 AD8038/AD8039 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS DISABLE INPUT CAPACITANCE The AD8038 in the 8-lead SOIC package provides a disable Along with bypassing and ground, high speed amplifiers can be feature. This feature disables the input from the output (see sensitive to parasitic capacitance between the inputs and ground. A Figure 42 for input-output isolation) and reduces the quiescent few picofarads of capacitance reduces the input impedance at current from typically 1 mA to 0.2 mA. When the DISABLE high frequencies, in turn increasing the gain of the amplifiers, causing peaking of the frequency response, or even oscillations node is pulled below 4.5 V from the positive supply rail, the part if severe enough. It is recommended that the external passive becomes disabled. To enable the part, the DISABLE node needs components that are connected to the input pins be placed as to be pulled to greater than (VS – 2.5). close as possible to the inputs to avoid parasitic capacitance. POWER SUPPLY BYPASSING The ground and power planes must be kept at a distance of at Power supply pins are actually inputs, and care must be taken least 0.05 mm from the input pins on all layers of the board. so that a noise-free stable dc voltage is applied. The purpose of OUTPUT CAPACITANCE bypass capacitors is to create low impedances from the supply To a lesser extent, parasitic capacitances on the output can cause to ground at all frequencies, thereby shunting or filtering a peaking of the frequency response. Two methods to minimize majority of the noise. this effect include the following: Decoupling schemes are designed to minimize the bypassing • Put a small value resistor in series with the output to isolate impedance at all frequencies with a parallel combination of the load capacitor from the output stage of the amplifier, see capacitors. The 0.01 μF or 0.001 μF (X7R or NPO) chip capacitors Figure 12, Figure 13, Figure 27, and Figure 28. are critical and should be placed as close as possible to the amplifier package. Larger chip capacitors, such as 0.1 μF • Increase the phase margin with higher noise gains or add capacitors, can be shared among a few closely spaced active a pole with a parallel resistor and capacitor from −IN to components in the same signal path. A 10 μF tantalum capacitor the output. is less critical for high frequency bypassing and, in most cases, INPUT-TO-OUTPUT COUPLING only one per board is needed at the supply inputs. The input and output signal traces should not be parallel to GROUNDING minimize capacitive coupling between the inputs and outputs, A ground plane layer is important in densely packed PC boards avoiding any positive feedback. to spread the current minimizing parasitic inductances. However, an understanding of where the current flows in a circuit is critical to implementing effective high speed circuit design. The length of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the high frequency impedance of the path. High speed currents in an inductive ground return create an unwanted voltage noise. The length of the high frequency bypass capacitor leads is most critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from the supplies as well, the ground for the load impedance should be at the same physical location as the bypass capacitor grounds. For the larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. Rev. G | Page 13 of 16 AD8038/AD8039 APPLICATIONS INFORMATION LOW POWER ADC DRIVER LOW POWER ACTIVE VIDEO FILTER 1kΩ 2.5V Some composite video signals derived from a digital source +5V 0.1µF 10µF contain clock feedthrough that can limit picture quality. Active 3V filters made from op amps can be used in this application, but 0.1µF 10µF they consume 25 mW to 30 mW for each channel. In power- 8 1kΩ 3 REF sensitive applications, this can be too much, requiring the use 50Ω 1 VINP V IN of passive filters that can create impedance matching problems 2 0V 1kΩ when driving any significant load. 1kΩ AD9203 AD8039 The AD8038 can be used to make an effective low-pass active 1kΩ 1kΩ 6 filter that consumes one-fifth of the power consumed by an 50Ω 7 VINN active filter made from an op amp. Figure 44 shows a circuit 5 4 that uses a AD8038 with ±2.5 V supplies to create a three-pole 1kΩ Sallen-Key filter. This circuit uses a single RC pole in front of a 0.1µF 10µF standard 2-pole active section. –5V 1kΩ R F 680pF Figure 43. Schematic to Drive AD9203 with the AD8039 1Ω +2.5V The AD9203 is a low power (125 mW on a 5 V supply), 40 MSPS 10µF 0.1µF 10-bit converter. As such, the low power, high performance AD8039 is an appropriate amplifier choice to drive it. R1 R2 R3 V AD8038 OUT 200Ω 499Ω 49.9Ω R5 V IN In low supply voltage applications, differential analog inputs 75Ω R4 C1 C3 49.9Ω 100pF 33pF are needed to increase the dynamic range of the ADC inputs. 0.1µF 10µF –2.5V Differential driving can also reduce second and other even-order Figure 44. Low-Pass Filter for Video distortion products. The AD8039 can be used to make a dc- coupled, single-ended-to-differential driver for driving these Figure 45 shows the frequency response of this filter. The ADCs. Figure 43 is a schematic of such a circuit for driving the response is down 3 dB at 6 MHz; therefore, it passes the video AD9203, 10-bit, 40 MSPS ADC. band with little attenuation. The rejection at 27 MHz is 45 dB, which provides more than a factor of 100 in suppression of the The AD9203 works best when the common-mode voltage at the clock components at this frequency. input is at the midsupply or 2.5 V. The output stage design of 10 the AD8039 makes it ideal for driving these types of ADCs. In this circuit, one of the op amps is configured in the inverting 0 mode, and the other is in the noninverting mode. However, to –10 provide better bandwidth matching, each op amp is configured for a noise gain of +2. The inverting op amp is configured for a –20 gain of −1, and the noninverting op amp is configured for a gain of +2. Each has a very similar ac response. The input signal to –30 the noninverting op amp is divided by 2 to normalize its voltage level and make it equal to the inverting output. –40 The outputs of the op amps are centered at 2.5 V, which is the –50 midsupply level of the ADC. This is accomplished by first taking the 2.5 V reference output of the ADC and dividing it by 2 with –60 0.1 110 100 a pair of 1 kΩ resistors. The resulting 1.25 V is applied to the FREQUENCY (MHz) positive input of each op amp. This voltage is then multiplied by Figure 45. Video Filter Response the gain of the op amps to provide a 2.5 V level at each output. Rev. G | Page 14 of 16 02951-043 GAIN (dB) 02951-045 02951-044 0 10 MA . X AD8038/AD8039 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 46. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 2.20 2.00 1.80 1.35 5 4 2.40 1.25 2.10 1.15 12 3 1.80 PIN 1 0.65 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.46 0.36 0.30 0.22 0.26 SEATING 0.15 0.08 PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 47. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters Rev. G | Page 15 of 16 012407-A AD8038/AD8039 3.00 2.90 2.80 8 76 5 3.00 1.70 2.80 1.60 2.60 1.50 12 34 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 0.22 MAX 1.45 MAX 0.08 MIN 0.95 MIN 0.60 0.15 MAX 8° 0.45 SEATING 0.60 0.05 MIN 4° 0.38 MAX 0.30 PLANE BSC 0° 0.22 MIN COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 48. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8038AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8038AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8038AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8038ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8038ARZ-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8038ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8038AKSZ-R2 −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-5 H1C 1 AD8038AKSZ-REEL −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-5 H1C 1 AD8038AKSZ-REEL7 −40°C to +85°C 5-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-5 H1C AD8039AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8039AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8039AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8039ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8039ARZ-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1 AD8039ARZ-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 AD8039ART-R2 −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA AD8039ART-REEL −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA AD8039ART-REEL7 −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA 1 AD8039ARTZ-R2 −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA# 1 AD8039ARTZ-REEL −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA# 1 AD8039ARTZ-REEL7 −40°C to +85°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 HYA# 1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.. ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02951-0-8/09(G) Rev. G | Page 16 of 16 121608-A