ANALOG DEVICES AD8034

Low Cost, 80 MHz FastFET Op Amps AD8033/AD8034 FEATURES CONNECTION DIAGRAMS FET input amplifier NC 1 8 NC AD8033 AD8033 1 pA typical input bias current V 1 5 +V OUT S –IN 2 7 +V S Very low cost +IN 3 6 V OUT –V 2 S High speed –V 4 5 NC S +IN 3 4 –IN 80 MHz, −3 dB bandwidth (G = +1) NC = NO CONNECT 80 V/μs slew rate (G = +2) Figure 1. 8-Lead SOIC (R) Figure 2. 5-Lead SC70 (KS) Low noise 11 nV/√Hz (f = 100 kHz) V 1 8 +V OUT1 S 0.7 fA/√Hz (f = 100 kHz) –IN1 2 7 V OUT2 +IN1 3 6 –IN2 Wide supply voltage range: 5 V to 24 V –V 4 5 +IN2 S Low offset voltage: 1 mV typical AD8034 Single-supply and rail-to-rail output Figure 3. 8-Lead SOIC (R) and 8-Lead SOT-23 (RJ) High common-mode rejection ratio: −100 dB Low power: 3.3 mA/amplifier typical supply current 24 No phase reversal V = 200mV p-p OUT G = +10 21 Small packaging: 8-lead SOIC, 8-lead SOT-23, and 5-lead SC70 18 G = +5 15 APPLICATIONS 12 Instrumentation 9 G = +2 Filters 6 Level shifting 3 Buffering G = +1 0 –3 G = –1 GENERAL DESCRIPTION –6 The AD8033/AD8034 FastFET™ amplifiers are voltage feedback –9 0.1 1 10 100 1000 amplifiers with FET inputs, offering ease of use and excellent FREQUENCY (MHz) performance. The AD8033 is a single amplifier and the AD8034 Figure 4. Small Signal Frequency Response is a dual amplifier. The AD8033/AD8034 FastFET op amps in Analog Devices, Inc., proprietary XFCB process offer significant The AD8033/AD8034 amplifiers only draw 3.3 mA/amplifier of performance improvements over other low cost FET amps, such quiescent current while having the capability of delivering up to as low noise (11 nV/√Hz and 0.7 fA/√Hz) and high speed (80 MHz 40 mA of load current. bandwidth and 80 V/μs slew rate). The AD8033 is available in a small package 8-lead SOIC and a With a wide supply voltage range from 5 V to 24 V and fully small package 5-lead SC70. The AD8034 is also available in a operational on a single supply, the AD8033/AD8034 amplifiers small package 8-lead SOIC and a small package 8-lead SOT-23. work in more applications than similarly priced FET input They are rated to work over the industrial temperature range of amplifiers. In addition, the AD8033/AD8034 have rail-to-rail −40°C to +85°C without a premium over commercial grade outputs for added versatility. products. Despite their low cost, the amplifiers provide excellent overall performance. They offer a high common-mode rejection of −100 dB, low input offset voltage of 2 mV maximum, and low noise of 11 nV/√Hz. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. GAIN (dB) 02924-001 02924-003 02924-004 02924-002 AD8033/AD8034 TABLE OF CONTENTS Features .............................................................................................. 1  Input Overdrive .......................................................................... 16  Applications ....................................................................................... 1  Input Impedance ........................................................................ 16  General Description ......................................................................... 1  Thermal Considerations ............................................................ 16  Connection Diagrams ...................................................................... 1  Layout, Grounding, and Bypassing Considerations .................. 18  Revision History ............................................................................... 2  Bypassing ..................................................................................... 18  Specif ica t ions ..................................................................................... 3  Grounding ................................................................................... 18  Absolute Maximum Ratings ............................................................ 6  Leakage Currents ........................................................................ 18  Maximum Power Dissipation ..................................................... 6  Input Capacitance ...................................................................... 18  Output Short Circuit .................................................................... 6  Applications Information .............................................................. 19  ESD Caution .................................................................................. 6  High Speed Peak Detector ........................................................ 19  Typical Performance Characteristics ............................................. 7  Active Filters ............................................................................... 20  Test Circuits ..................................................................................... 14  Wideband Photodiode Preamp ................................................ 21  Theory of Operation ...................................................................... 16  Outline Dimensions ....................................................................... 23  Output Stage Drive and Capacitive Load Drive ..................... 16  Ordering Guide .......................................................................... 24  8/02—Rev. 0 to Rev. A REVISION HISTORY Added AD8033 ................................................................... Universal 9/08—Rev. C to Rev. D VOUT = 2 V p-p Deleted from Default Conditions ......... Universal Deleted Usable Input Range Parameter, Table 1 ........................... 3 Added SOIC-8 (R) and SC70 (KS) .................................................. 1 Deleted Usable Input Range Parameter, Table 2 ........................... 4 Edits to General Description Section ............................................. 1 Deleted Usable Input Range Parameter, Table 3 ........................... 5 Changes to Specifications ................................................................. 2 New Figure 2 ...................................................................................... 5 Edits to Maximum Power Dissipation Section .............................. 5 4/08—Rev. B to Rev. C Changes to Format ............................................................. Universal Changes to Ordering Guide ............................................................. 5 Changes to Features and General Description ............................. 1 Change to TPC 3 ............................................................................... 6 Changes to Figure 13 Caption and Figure 14 Caption ................ 8 Change to TPC 6 ............................................................................... 6 Changes to Figure 22 and Figure 23 ............................................... 9 Change to TPC 9 ............................................................................... 7 Changes to Figure 25 and Figure 28 ............................................. 10 New TPC 16 ....................................................................................... 8 Changes to Input Capacitance Section ........................................ 18 New TPC 17 ....................................................................................... 8 New TPC 31 .................................................................................... 11 Changes to Active Filters Section ................................................. 21 New TPC 35 .................................................................................... 11 Changes to Outline Dimensions ................................................... 23 Changes to Ordering Guide .......................................................... 24 New Test Circuit 9 .......................................................................... 13 SC70 (KS) Package Added ............................................................ 19 2/03—Rev. A to Rev. B Changes to Features .......................................................................... 1 Changes to Connection Diagrams ................................................. 1 Changes to Specifications ................................................................ 2 Changes to Absolute Maximum Ratings ....................................... 4 Replaced TPC 31............................................................................. 11 Changes to TPC 35 ......................................................................... 11 Changes to Test Circuit 3 ............................................................... 12 Updated Outline Dimensions ....................................................... 19 Rev. D | Page 2 of 24 AD8033/AD8034 SPECIFICATIONS TA = 25°C, VS = ±5 V, RL = 1 kΩ, gain = +2, unless otherwise noted. Table 1. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p 65 80 MHz OUT G = +2, VOUT = 0.2 V p-p 30 MHz G = +2, VOUT = 2 V p-p 21 MHz Input Overdrive Recovery Time −6 V to +6 V input 135 ns Output Overdrive Recovery Time −3 V to +3 V input, G = +2 135 ns Slew Rate (25% to 75%) G = +2, V = 4 V step 55 80 V/μs OUT Settling Time to 0.1% G = +2, V = 2 V step 95 ns OUT G = +2, VOUT = 8 V step 225 ns NOISE/HARMONIC PERFORMANCE Distortion fC = 1 MHz, VOUT = 2 V p-p Second Harmonic RL = 500 Ω −82 dBc RL = 1 kΩ −85 dBc Third Harmonic R = 500 Ω −70 dBc L R = 1 kΩ −81 dBc L Crosstalk, Output-to-Output f = 1 MHz, G = +2 −86 dB Input Voltage Noise f = 100 kHz 11 nV/√Hz Input Current Noise f = 100 kHz 0.7 fA/√Hz DC PERFORMANCE Input Offset Voltage VCM = 0 V 1 2 mV TMIN − TMAX 3.5 mV Input Offset Voltage Match 2.5 mV Input Offset Voltage Drift 4 27 μV/°C Input Bias Current 1.5 11 pA TMIN − TMAX 50 pA Open-Loop Gain VOUT = ± 3 V 89 92 dB INPUT CHARACTERISTICS Common-Mode Input Impedance 1000||2.3 GΩ||pF Differential Input Impedance 1000||1.7 GΩ||pF Input Common-Mode Voltage Range FET Input Range −5.0 to +2.2 V Common-Mode Rejection Ratio V = −3 V to +1.5 V −89 −100 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing ±4.75 ±4.95 V Output Short-Circuit Current 40 mA Capacitive Load Drive 30% overshoot, G = +1, VOUT = 400 mV p-p 35 pF POWER SUPPLY Operating Range 5 24 V Quiescent Current per Amplifier 3.3 3.5 mA Power Supply Rejection Ratio VS = ±2 V −90 −100 dB Rev. D | Page 3 of 24 AD8033/AD8034 T = 25°C, V = 5 V, R = 1 kΩ, gain = +2, unless otherwise noted. A S L Table 2. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p 70 80 MHz OUT G = +2, V = 0.2 V p-p 32 MHz OUT G = +2, V = 2 V p-p 21 MHz OUT Input Overdrive Recovery Time −3 V to +3 V input 180 ns Output Overdrive Recovery Time −1.5 V to +1.5 V input, G = +2 200 ns Slew Rate (25% to 75%) G = +2, VOUT = 4 V step 55 70 V/μs Settling Time to 0.1% G = +2, V = 2 V step 100 ns OUT NOISE/HARMONIC PERFORMANCE Distortion fC = 1 MHz, VOUT = 2 V p-p Second Harmonic R = 500 Ω −80 dBc L R = 1 kΩ −84 dBc L Third Harmonic RL = 500 Ω −70 dBc RL = 1 kΩ −80 dBc Crosstalk, Output to Output f = 1 MHz, G = +2 −86 dB Input Voltage Noise f = 100 kHz 11 nV/√Hz Input Current Noise f = 100 kHz 0.7 fA/√Hz DC PERFORMANCE Input Offset Voltage V = 0 V 1 2 mV CM T − T 3.5 mV MIN MAX Input Offset Voltage Match 2.5 mV Input Offset Voltage Drift 4 30 μV/°C Input Bias Current 1 10 pA TMIN − TMAX 50 pA Open-Loop Gain V = 0 V to 3 V 87 92 dB OUT INPUT CHARACTERISTICS Common-Mode Input Impedance 1000||2.3 GΩ||pF Differential Input Impedance 1000||1.7 GΩ||pF Input Common-Mode Voltage Range FET Input Range 0 to 2.0 V Common-Mode Rejection Ratio VCM = 1.0 V to 2.5 V −80 −100 dB OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ 0.16 to 4.83 0.04 to 4.95 V Output Short-Circuit Current 30 mA Capacitive Load Drive 30% overshoot, G = +1, VOUT = 400 mV p-p 25 pF POWER SUPPLY Operating Range 5 24 V Quiescent Current per Amplifier 3.3 3.5 mA Power Supply Rejection Ratio V = ±1 V −80 −100 dB S Rev. D | Page 4 of 24 AD8033/AD8034 T = 25°C, V = ±12 V, R = 1 kΩ, gain = +2, unless otherwise noted. A S L Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, V = 0.2 V p-p 65 80 MHz OUT G = +2, V = 0.2 V p-p 30 MHz OUT G = +2, V = 2 V p-p 21 MHz OUT Input Overdrive Recovery Time −13 V to +13 V input 100 ns Output Overdrive Recovery Time −6.5 V to +6.5 V input, G = +2 100 ns Slew Rate (25% to 75%) G = +2, VOUT = 4 V step 55 80 V/μs Settling Time to 0.1% G = +2, V = 2 V step 90 ns OUT G = +2, V = 10 V step 225 ns OUT NOISE/HARMONIC PERFORMANCE Distortion f = 1 MHz, V = 2 V p-p C OUT Second Harmonic R = 500 Ω −80 dBc L RL = 1 kΩ −82 dBc Third Harmonic RL = 500 Ω −70 dBc RL = 1 kΩ −82 dBc Crosstalk, Output to Output f = 1 MHz, G = +2 −86 dB Input Voltage Noise f = 100 kHz 11 nV/√Hz Input Current Noise f = 100 kHz 0.7 fA/√Hz DC PERFORMANCE Input Offset Voltage V = 0 V 1 2 mV CM T − T 3.5 mV MIN MAX Input Offset Voltage Match 2.5 mV Input Offset Voltage Drift 4 24 μV/°C Input Bias Current 2 12 pA T − T 50 pA MIN MAX Open-Loop Gain V = ±8 V 88 96 dB OUT INPUT CHARACTERISTICS Common-Mode Input Impedance 1000||2.3 GΩ||pF Differential Input Impedance 1000||1.7 GΩ||pF Input Common-Mode Voltage Range FET Input Range −12.0 to +9.0 V Common-Mode Rejection Ratio VCM = ±5 V −92 −100 dB OUTPUT CHARACTERISTICS Output Voltage Swing ±11.52 ±11.84 V Output Short-Circuit Current 60 mA Capacitive Load Drive 30% overshoot, G = +1 35 pF POWER SUPPLY Operating Range 5 24 V Quiescent Current per Amplifier 3.3 3.5 mA Power Supply Rejection Ratio V = ±2 V −85 −100 dB S Rev. D | Page 5 of 24 AD8033/AD8034 ABSOLUTE MAXIMUM RATINGS If the rms signal levels are indeterminate, consider the worst case, Table 4. when VOUT = VS/4 for RL to midsupply Parameter Rating 2 PD = (VS × IS) + (VS/4) /RL Supply Voltage 26.4 V In single-supply operation with RL referenced to VS−, worst case Power Dissipation See Figure 5 is VOUT = VS/2. Common-Mode Input Voltage 26.4 V 2.0 Differential Input Voltage 1.4 V Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C 1.5 Lead Temperature (Soldering 10 sec) 300°C SOT-23-8 SOIC-8 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress 1.0 rating only; functional operation of the device at these or any other conditions above those indicated in the operational SC70-5 section of this specification is not implied. Exposure to absolute 0.5 maximum rating conditions for extended periods may affect device reliability. 0 MAXIMUM POWER DISSIPATION –60 –40 –20 020 40 60 80 100 AMBIENT TEMPERATURE (°C) The maximum safe power dissipation in the AD8033/AD8034 Figure 5. Maximum Power Dissipation vs. packages is limited by the associated rise in junction temperature Ambient Temperature for a 4-Layer Board (TJ) on the die. The plastic that encapsulates the die locally reaches the junction temperature. At approximately 150°C, Airflow increases heat dissipation, effectively reducing θ . In JA which is the glass transition temperature, the plastic changes its addition, more metal directly in contact with the package leads properties. Even temporarily exceeding this temperature limit from metal traces, through holes, ground, and power planes can change the stresses that the package exerts on the die, reduces the θJA. Care must be taken to minimize parasitic permanently shifting the parametric performance of the AD8033/ capacitances at the input leads of high speed op amps as discussed AD8034. Exceeding a junction temperature of 175°C for an in the Layout, Grounding, and Bypassing Considerations section. extended period can result in changes in silicon devices, potentially Figure 5 shows the maximum power dissipation in the package causing failure. vs. the ambient temperature for the 8-lead SOIC (125°C/W), The still-air thermal properties of the package and PCB (θJA), 5-lead SC70 (210°C/W), and 8-lead SOT-23 (160°C/W) packages ambient temperature (TA), and the total power dissipated in the on a JEDEC standard 4-layer board. θ values are approximations. JA package (PD) determine the junction temperature of the die. OUTPUT SHORT CIRCUIT The junction temperature can be calculated as Shorting the output to ground or drawing excessive current for T = T + (P × θ ) J A D JA the AD8033/AD8034 will likely cause catastrophic failure. P is the sum of the quiescent power dissipation and the power D dissipated in the package due to the load drive for all outputs. ESD CAUTION The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (V × I ). The difference between the total drive power and OUT OUT the load power is the drive power dissipated in the package P = Quiescent Power + (Total Drive Power − Load Power) D 2 PD = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT /RL] RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. Rev. D | Page 6 of 24 MAXIMUM POWER DISSIPATION (W) 02924-005 AD8033/AD8034 TYPICAL PERFORMANCE CHARACTERISTICS Default conditions: VS = ±5 V, CL = 5 pF, RL = 1 kΩ, TA = 25°C. 24 8 V = 200mV p-p G = +2 OUT G = +10 21 7 18 V = 0.2V p-p OUT 6 G = +5 15 12 5 V = 1V p-p OUT 9 G = +2 4 6 3 3 G = +1 0 V = 4V p-p 2 OUT –3 G = –1 1 –6 V = 2V p-p OUT –9 0 0.1 1 10 100 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 9. Frequency Response for Various Output Amplitudes (See Figure 45) Figure 6. Small Signal Frequency Response for Various Gains 8 1 V = +5V S 7 0 V = +5V S V =±5V 6 S –1 5 V = ±12V S –2 V =±5V S 4 –3 3 –4 2 V = ±12V S –5 1 G = +1 G = +2 V = 200mV p-p V = 200mV p-p OUT OUT –6 0 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Small Signal Frequency Response for Various Supplies Figure 7. Small Signal Frequency Response for Various Supplies (See Figure 45) (See Figure 44) 2 7 G = +1 V = ±12V V = 2V p-p S OUT 1 6 V = ±12V S 0 V =±5V 5 S V = +5V S V =±5V –1 S V = +5V S 4 –2 3 –3 2 –4 1 –5 G = +2 V = 2V p-p OUT –6 0 0.1 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Large Signal Frequency Response for Various Supplies Figure 11. Large Signal Frequency Response for Various Supplies (See Figure 44) (See Figure 45) Rev. D | Page 7 of 24 GAIN (dB) GAIN (dB) GAIN (dB) 02924-008 02924-006 02924-007 GAIN (dB) GAIN (dB) GAIN (dB) 02924-010 02924-009 02924-011 AD8033/AD8034 8 10 V = 200mV p-p V = 200mV p-p OUT C = 100pF OUT L C = 100pF G = +1 L G = +2 9 6 8 C = 51pF L C = 100pF L 4 7 R = 25Ω SNUB 6 2 5 C = 33pF L 0 4 C = 2pF C = 33pF L L 3 –2 C = 2pF L 2 –4 1 0 –6 0.1 1 10 100 0.1 110 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Small Signal Frequency Response for Various CL (See Figure 45) Figure 12. Small Signal Frequency Response for Various C (See Figure 44) L 9 8 V = 200mV p-p V = 200mV p-p OUT OUT C = 0pF F R = 3kΩ G = +2 F 8 G = +2 7 C = 1pF F R = 1kΩ L 7 6 6 5 C = 1.5pF F R = 500Ω L 5 4 C = 2pF F 4 3 3 2 2 1 1 0 0 0.1 110 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 13. Small Signal Frequency Response for Various C (See Figure 45) Figure 16. Small Signal Frequency Response for Various RL (See Figure 45) F 100 100 180 V = 200mV p-p V = ±12V OUT S 80 150 10 GAIN 60 120 G = +2 1 40 90 PHASE G = +1 20 60 0.1 0 30 0.01 –20 0 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Output Impedance vs. Frequency (See Figure 47) Figure 17. Open-Loop Response Rev. D | Page 8 of 24 IMPEDANCE (Ω) GAIN (dB) GAIN (dB) 02924-013 02924-012 02924-014 GAIN (dB) GAIN (dB) GAIN (dB) 02924-016 02924-015 PHASE (Degrees) 02924-017 AD8033/AD8034 –40 –40 G = +2 HD3 R = 500Ω L –50 –50 –60 –60 –70 –70 HD2 G = +1 –80 –80 HD3 R = 1kΩ L HD3 G = +2 –90 –90 HD2 G = +2 HD2 R = 500Ω –100 L –100 –110 –110 HD3 G = +1 HD2 R = 1kΩ L –120 –120 0.1 1 5 0.1 1 5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 18. Harmonic Distortion vs. Frequency for Various Loads Figure 21. Harmonic Distortion vs. Frequency for Various Gains (See Figure 45) –40 –20 G = +2 G = +2 HD3 V = 5V S –30 –50 HD3 V = 10V p-p HD2 V = 20V p-p OUT OUT –40 –60 –50 HD3 V = 20V p-p OUT –70 –60 –80 –70 HD2 V = 10V p-p OUT HD2 V = 5V S HD3 V = 24V S –80 –90 –90 HD3 V = 2V p-p OUT –100 –100 –110 = 24V HD2 V S –110 HD2 V = 2V p-p OUT –120 –120 1 0.1 5 0.1 1 5 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. Harmonic Distortion vs. Frequency for Various Supply Voltages Figure 22. Harmonic Distortion vs. Frequency for Various Amplitudes (See Figure 45) (See Figure 45), VS = 24 V 1000 80 G = +1 V = +5V S POSITIVE SIDE 70 60 V = +5V S NEGATIVE SIDE 50 100 40 30 V =±5V S NEGATIVE SIDE 20 V =±5V S POSITIVE SIDE 10 10 0 10 100 1k 10k 100k 1M 1 10M 0M 100M 10 30 50 70 90 110 FREQUENCY (Hz) CAPACITIVE LOAD (pF) Figure 20. Voltage Noise vs. Frequency Figure 23. Percent Overshoot vs. Capacitive Load (See Figure 44) Rev. D | Page 9 of 24 NOISE (nV/√Hz) DISTORTION (dBc) DISTORTION (dBc) 02924-019 02924-018 02924-020 DISTORTION (dBc) DISTORTION (dBc) PERCENT OVERSHOOT (%) 02924-023 02924-022 02924-021 AD8033/AD8034 G = +1 G = +1 38pF 15pF 80mV/DIV 25mV/DIV 20ns/DIV 80ns/DIV Figure 24. Small Signal Transient Response 5 V (See Figure 44) Figure 27. Small Signal Transient Response ±5 V (See Figure 44) G = +1 G = +2 V = 20V p-p V = 20V p-p OUT OUT V = 8V p-p V = 8V p-p OUT OUT V = 2V p-p V = 2V p-p OUT OUT 3V/DIV 320ns/DIV 320ns/DIV 3V/DIV Figure 25. Large Signal Transient Response (See Figure 44) Figure 28. Large Signal Transient Response (See Figure 45) G = –1 G = +1 V V V IN OUT IN V OUT 350ns/DIV 1.5V/DIV 1.5V/DIV 350ns/DIV Figure 26. Output Overdrive Recovery (See Figure 46) Figure 29. Input Overdrive Recovery (See Figure 44) Rev. D | Page 10 of 24 02924-026 02924-025 02924-024 02924-029 02924-028 02924-027 AD8033/AD8034 V = 1V IN V = 1V IN V – 2V OUT IN +0.1% +0.1% V – 2V –0.1% OUT IN –0.1% t = 0 t = 0 2mV/DIV 1.5µs/DIV 2mV/DIV 20ns/DIV Figure 33. 0.1% Short-Term Settling Time Figure 30. Long-Term Settling Time 0 7.0 6.9 –5 6.8 V = ±12V S –10 6.7 –I b 6.6 –15 6.5 –20 V = ±5V S +I 6.4 b –25 6.3 V = +5V S 6.2 –30 6.1 –35 6.0 –40 5.9 20 25 30 35 40 45 50 55 60 65 70 75 80 85 –40 –20 0 204060 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 31. I vs. Temperature Figure 34. Quiescent Supply Current vs. Temperature for Various Supply b Voltages BJT INPUT RANGE 4.0 42 3.5 36 V = ±12V S 30 –I 3.0 b 24 18 2.5 +I b 12 2.0 6 0 1.5 FET INPUT RANGE 10 +I 1.0 b 5 V = ±5V V = +5V S S 0 0.5 –5 –I b 0 –10 –15 –0.5 –20 –25 –1.0 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 –30 –12 –10 –8 –6 –4 –2 02 46 8 10 12 COMMON-MODE VOLTAGE (V) COMMON-MODE VOLTAGE (V) Figure 32. I vs. Common-Mode Voltage Range Figure 35. Input Offset Voltage vs. Common-Mode Voltage b Rev. D | Page 11 of 24 I (pA) I (µA) I (pA) b b b 02924-030 02924-031 02924-032 NORMALIZED OFFSET (mV) QUIESCENT SUPPLY CURRENT (mA) 02924-033 02924-035 02924-034 AD8033/AD8034 105 –20 100 –30 95 –40 90 R = 500Ω L 85 R = 1kΩ L –50 R = 2kΩ L 80 –60 75 70 –70 65 –80 60 –12–10 –8 –6 –4 –2 0 2468 10 12 0.1 1 10 100 OUTPUT VOLTAGE (V) FREQUENCY (MHz) Figure 36. CMRR vs. Frequency (See Figure 50) Figure 39. Open-Loop Gain vs. Output Voltage for Various RL 1.0 –40 –50 0.8 SOT-23 A/B V –V CC OH –60 0.6 SOIC A/B –70 SOT-23 B/A 0.4 SOIC B/A –80 V – V OL EE 0.2 –90 –100 0 05 10 15 20 25 30 0.1 1 10 50 FREQUENCY (MHz) I (mA) LOAD Figure 37. Output Saturation Voltage vs. Load Current Figure 40. Crosstalk (See Figure 52) 0 180 –10 150 –20 –30 120 –PSRR –40 –50 90 +PSRR –60 60 –70 –80 30 –90 0 –100 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 0.0001 0.001 0.01 0.1 1 10 100 V (mV) OS FREQUENCY (MHz) Figure 38. PSRR vs. Frequency (See Figure 49 and Figure 51) Figure 41. Initial Offset Rev. D | Page 12 of 24 PSRR (dB) CMRR (dB) OUTPUT SATURATION (V) 02924-037 02924-038 02924-036 FREQUENCY CROSSTALK (dB) OPEN-LOOP GAIN (dB) 02924-041 02924-039 02924-040 AD8033/AD8034 V OUT V OUT 1.2V/DIV V V 1µs/DIV 1.2V/DIV IN 1µs/DIV IN Figure 42. G = +1 Response, V = ±5 V Figure 43. G = +2 Response, VS = ±5 V S Rev. D | Page 13 of 24 02924-042 02924-043 AD8033/AD8034 TEST CIRCUITS +V +V S S 1µF 1µF + + 10nF 10nF R SNUB 976Ω V OUT V IN C 49.9Ω AD8033/AD8034 AD8033/AD8034 LOAD 49.9Ω 10nF 10nF + V SINE 0.2V p-p – + + 1µF 1µF –V –V S S Figure 44. G = +1 Figure 47. Output Impedance, G = +1 C F 1kΩ 1kΩ 1kΩ 1kΩ R F +V S +V S 1µF 1µF + + 10nF 10nF R SNUB 976Ω V OUT 499Ω V IN AD8033/AD8034 C AD8033/AD8034 LOAD 49.9Ω 49.9Ω 10nF 10nF + V SINE 0.2V p-p – + + 1µF 1µF –V S –V S Figure 45. G = +2 Figure 48. Output Impedance, G = +2 1kΩ 1kΩ V IN +V S 1µF + 10nF 976Ω V OUT 49.9Ω AD8033/AD8034 499Ω 10nF + 1µF –V S Figure 46. G = −1 Rev. D | Page 14 of 24 02924-046 02924-044 02924-045 02924-047 02924-048 AD8033/AD8034 1V p-p +V S +V S + – 1µF +V AC S + 49.9Ω 10nF V OUT V OUT AD8033/AD8034 AD8033/AD8034 10nF 1V p-p – + –V S + 49.9Ω –V AC S 1µF –V S Figure 49. Negative PSRR Figure 51. Positive PSRR 1kΩ 1kΩ 1kΩ 1kΩ –V S +V S – 1µF V TO PORT 1 499Ω IN B + + + 1kΩ 49.9Ω 50Ω V IN – +V 10nF S 976Ω –V S V OUT 1kΩ 499Ω + AD8033/AD8034 49.9Ω TO PORT 2 1kΩ 10nF A 1kΩ – +V + S 1µF 1kΩ 1kΩ –V S Figure 50. CMRR Figure 52. Crosstalk Rev. D | Page 15 of 24 02924-051 02924-050 02924-049 02924-052 AD8033/AD8034 THEORY OF OPERATION The incorporation of JFET devices into the Analog Devices As a result of entering the bipolar mode of operation, an offset high voltage XFCB process has enabled the ability to design the and input bias current shift occurs (see Figure 32 and Figure 35). AD8033/AD8034. The AD8033/AD8034 are voltage feedback After re-entering the JFET common-mode range, the amplifier rail-to-rail output amplifiers with FET inputs and a bipolar- recovers in approximately 100 ns (refer to Figure 29 for input enhanced common-mode input range. The use of JFET devices in overload behavior). Above and below the supply rails, ESD high speed amplifiers extends the application space into both the protection diodes activate, resulting in an exponentially low input bias current and low distortion, high bandwidth areas. increasing input bias current. If the inputs are driven well beyond the rails, series input resistance should be included Using N-channel JFETs and a folded cascade input topology, to limit the input bias current to <10 mA. the common-mode input level operates from 0.2 V below the negative rail to within 3.0 V of the positive rail. Cascading of INPUT IMPEDANCE the input stage ensures low input bias current over the entire The input capacitance of the AD8033/AD8034 forms a pole common-mode range as well as CMRR and PSRR specifications with the feedback network, resulting in peaking and ringing that are above 90 dB. Additionally, long-term settling issues that in the overall response. The equivalent impedance of the normally occur with high supply voltages are minimized as a feedback network should be kept small enough to ensure that result of the cascading. the parasitic pole falls well beyond the −3 dB bandwidth of the gain configuration being used. If larger impedance values are OUTPUT STAGE DRIVE AND CAPACITIVE LOAD desired, the amplifier can be compensated by placing a small DRIVE capacitor in parallel with the feedback resistor. Figure 13 shows The common emitter output stage adds rail-to-rail output the improvement in frequency response by including a small performance and is compensated to drive 35 pF (30% overshoot feedback capacitor with high feedback resistance values. at G = +1). Additional capacitance can be driven if a small snub resistor is put in series with the capacitive load, effectively THERMAL CONSIDERATIONS decoupling the load from the output stage, as shown in Figure 12. Because the AD8034 operates at up to ±12 V supplies in the The output stage can source and sink 20 mA of current within small 8-lead SOT-23 package (160°C/W), power dissipation can 500 mV of the supply rails and 1 mA within 100 mV of the easily exceed package limitations, resulting in permanent shifts supply rails. in device characteristics and even failure. Likewise, high supply voltages can cause an increase in junction temperature even INPUT OVERDRIVE with light loads, resulting in an input bias current and offset An additional feature of the AD8033/AD8034 is a bipolar input drift penalty. The input bias current doubles for every 10°C pair that adds rail-to-rail common-mode input performance shown in Figure 31. Refer to the Maximum Power Dissipation specifically for applications that cannot tolerate phase inversion section for an estimation of die temperature based on load and problems. supply voltage. Under normal common-mode operation, the bipolar input pair is kept reversed, maintaining I at less than 1 pA. When b the input common-mode operation comes within 3.0 V of the positive supply rail, I1 turns off and I4 turns on, supplying tail current to the bipolar pair Q25 and Q27. With this configuration, the inputs can be driven beyond the positive supply rail without any phase inversion (see Figure 53). Rev. D | Page 16 of 24 AD8033/AD8034 +V S R2 I2 R3 + + V2 V4 – – Q4 Q1 Q13 Q14 Q7 Q6 V TH R14 Q25 D4 Q27 J2 J1 +IN V –IN CC D5 V OUT Q11 Q9 Q29 Q28 I3 R7 R8 I1 I4 –V S Figure 53. Simplified AD8033/AD8034 Input Stage Rev. D | Page 17 of 24 02924-053 AD8033/AD8034 LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS BYPASSING LEAKAGE CURRENTS Power supply pins are actually inputs, and care must be taken Poor PCB layout, contaminants, and the board insulator material so that a noise-free stable dc voltage is applied. The purpose of can create leakage currents that are much larger than the input bypass capacitors is to create low impedances from the supply bias currents of the AD8033/AD8034. Any voltage differential to ground at all frequencies, thereby shunting or filtering a between the inputs and nearby runs set up leakage currents majority of the noise. Decoupling schemes are designed to through the PCB insulator, for example, 1 V/100 GΩ = 10 pA. minimize the bypassing impedance at all frequencies with a Similarly, any contaminants on the board can create significant parallel combination of capacitors. The chip capacitors, 0.01 μF leakage (skin oils are a common problem). To significantly reduce or 0.001 μF (X7R or NPO), are critical and should be placed as leakages, put a guard ring (shield) around the inputs and input close as possible to the amplifier package. Larger chip capacitors, leads that is driven to the same voltage potential as the inputs. such as the 0.1 μF capacitor, can be shared among a few closely This way there is no voltage potential between the inputs and spaced active components in the same signal path. The 10 μF surrounding area to set up any leakage currents. For the guard tantalum capacitor is less critical for high frequency bypassing, and ring to be completely effective, it must be driven by a relatively in most cases, only one per board is needed at the supply inputs. low impedance source and should completely surround the input leads on all sides, above, and below using a multilayer board. GROUNDING Another effect that can cause leakage currents is the charge A ground plane layer is important in densely packed PCBs to absorption of the insulator material itself. Minimizing the amount spread the current, thereby minimizing parasitic inductances. of material between the input leads and the guard ring helps to However, an understanding of where the current flows in a reduce the absorption. In addition, low absorption materials circuit is critical to implementing effective high speed circuit such as Teflon® or ceramic may be necessary in some instances. design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and, thus, the INPUT CAPACITANCE high frequency impedance of the path. High speed currents Along with bypassing and ground, high speed amplifiers can be in an inductive ground return create unwanted voltage noise. sensitive to parasitic capacitance between the inputs and The length of the high frequency bypass capacitor leads is most ground. A few pF of capacitance reduces the input impedance at critical. A parasitic inductance in the bypass grounding works high frequencies, in turn it increases the gain of the amplifier against the low impedance created by the bypass capacitor. and can cause peaking of the overall frequency response or even Place the ground leads of the bypass capacitors at the same oscillations if severe enough. It is recommended that the external physical location. passive components that are connected to the input pins be placed Because load currents flow from the supplies as well, the ground as close as possible to the inputs to avoid parasitic capacitance. for the load impedance should be at the same physical location The ground and power planes must be kept at a distance of at as the bypass capacitor grounds. For the larger value capacitors least 0.05 mm from the input pins on all layers of the board. that are intended to be effective at lower frequencies, the current return path distance is less critical. Rev. D | Page 18 of 24 AD8033/AD8034 APPLICATIONS INFORMATION Using two amplifiers, the difference between the peak and the HIGH SPEED PEAK DETECTOR current input level is forced across R2 instead of either amplifier’s The low input bias current and high bandwidth of the AD8033/ input pins. In the event of a rising pulse, the first amplifier AD8034 make the parts ideal for a fast settling, low leakage peak compensates for the drop across D2 and D3, forcing the voltage detector. The classic fast-low leakage topology with a diode in at Node 3 equal to Node 1. D1 is off and the voltage drop across the output is limited to ~1.4 V p-p maximum in the case of the R2 is zero. Capacitor C3 speeds up the loop by providing the AD8033/AD8034 because of the protection diodes across the charge required by the input capacitance of the first amplifier, inputs, as shown in Figure 54. helping to maintain a minimal voltage drop across R2 in the sampling mode. A negative going edge results in D2 and D3 turning off and D1 turning on, closing the loop around the first amplifier and forcing VOUT − VIN across R2. R4 makes AD8033/ V OUT the voltage across D2 zero, minimizing leakage current and AD8034 kickback from D3 from affecting the voltage across C2. V IN ~1.4V p-p MAX The rate of the incoming edge must be limited so that the output of the first amplifier does not overshoot the peak value of V IN Figure 54. High Speed Peak Detector with Limited Input Range before the output of the second amplifier can provide negative feedback at the summing junction of the first amplifier. This Using the AD8033/AD8034, a unity gain peak detector can is accomplished with the combination of R1 and C1, which be constructed that captures a 300 ns pulse while still taking allows the voltage at Node 1 to settle to 0.1% of VIN in 270 ns. advantage of the low input bias current and wide common- The selection of C2 and R3 is made by considering droop mode input range of the AD8033/AD8034, as shown in Figure 55. rate, settling time, and kickback. R3 prevents overshoot from occurring at Node 3. The time constants of R1, C1 and R3, C2 are roughly equal to achieve the best performance. Slower time constants can be selected by increasing C2 to minimize droop rate and kickback at the cost of increased settling time. R1 and C1 should also be increased to match, reducing the incoming pulse’s effect on kickback. C3 10pF R2 1kΩ D1 LS4148 C4 R4 4.7pF 6kΩ +V S +V S 1/2 V AD8034 OUT D3 D2 1/2 R1 AD8034 1kΩ –V LS4148 LS4148 S V IN –V S R5 180pF/ 39pF/ C2 C1 49.9Ω 560pF 120pF R3 200Ω Figure 55. High Speed, Unity Gain Peak Detector Using AD8034 Rev. D | Page 19 of 24 02924-054 02924-056 AD8033/AD8034 The Sallen-Key topology is the least dependent on the active device, requiring that the bandwidth be flat to beyond the stop- INPUT band frequency because it is used simply as a gain block. In the case of high Q filter stages, the peaking must not exceed the open- OUTPUT loop bandwidth and the linear input range of the amplifier. Using an AD8033/AD8034, a 4-pole cascaded Sallen-Key filter can be constructed with fC = 1 MHz and over 80 dB of stop-band attenuation, as shown in Figure 58. 2 C3 33pF +V S 1/2 R1 R2 AD8034 4.22kΩ 6.49kΩ 1V/DIV 100ns/DIV V IN Figure 56. Peak Detector Response 4 V, 300 ns Pulse –V S R5 C1 49.9Ω 27pF Figure 56 shows the peak detector in Figure 55 capturing a 300 ns, 4 V pulse with 10 mV of kickback and a droop rate of 5 V/s. For larger peak-to-peak pulses, increase the time constants of R1, C1 and R3, C3 to reduce overshoot. The best droop rate occurs by isolating parasitic resistances from Node 3, which can C4 82pF +V be accomplished using a guard band connected to the output of the S 1/2 second amplifier that surrounds its summing junction (Node 3). R4 R3 V AD8034 OUT 4.99kΩ 4.99kΩ Increasing both time constants by a factor of 3 permits a larger –V peak pulse to be captured and increases the output accuracy. S C2 10pF INPUT Figure 58. 4-Pole Cascade Sallen-Key Filter Component values are selected using a normalized cascaded, OUTPUT 2-stage Butterworth filter table and Sallen-Key 2-pole active filter equations. The overall frequency response is shown in Figure 59. 0 –10 2 –20 –30 1V/DIV 200ns/DIV –40 Figure 57. Peak Detector Response 5 V, 1 μs Pulse –50 Figure 57 shows a 5 V peak pulse being captured in 1 μs with –60 less than 1 mV of kickback. With this selection of time constants, –70 up to a 20 V peak pulse can be captured with no overshoot. –80 ACTIVE FILTERS –90 The response of an active filter varies greatly depending on the –100 performance of the active device. Open-loop bandwidth and 10k 100k 1M 10M gain, along with the order of the filter, determines the stop-band FREQUENCY (Hz) attenuation as well as the maximum cutoff frequency, while Figure 59. 4-Pole Cascade Sallen-Key Filter Response input capacitance can set a limit on which passive components are used. Topologies for active filters are varied, and some are more dependent on the performance of the active device than others are. Rev. D | Page 20 of 24 02924-057 02924-055 REF LEVEL (dB) 02924-059 02924-058 AD8033/AD8034 When selecting components, the common-mode input capacitance WIDEBAND PHOTODIODE PREAMP must be taken into consideration. Figure 62 shows an I/V converter with an electrical model of a Filter cutoff frequencies can be increased beyond 1 MHz using the photodiode. AD8033/AD8034 but limited open-loop gain and input impedance The basic transfer function is begin to interfere with the higher Q stages. This can cause early I × R F PHOTO roll-off of the overall response. V = OUT 1+ sC R F F Additionally, the stop-band attenuation decreases with decreasing open-loop gain. where I is the output current of the photodiode, and the PHOTO parallel combination of R and C sets the signal bandwidth. F F Keeping these limitations in mind, a 2-pole Sallen-Key Butterworth C F filter with f = 4 MHz can be constructed that has a relatively C low Q of 0.707 while still maintaining 15 dB of attenuation an octave above fC and 35 dB of stop-band attenuation. The filter R F and response are shown in Figure 60 and Figure 61, respectively. 11 R = 10 Ω C SH M C C3 D +V S 22pF I PHOTO C S R1 R2 V AD8033 OUT C V OUT M 2.49kΩ 2.49kΩ V IN –V S R5 C1 C + C R 49.9Ω 10pF F S F V B Figure 60. 2-Pole Butterworth Active Filter Figure 62. Wideband Photodiode Preamp 5 The stable bandwidth attainable with this preamp is a function 0 of RF, the gain bandwidth product of the amplifier, and the total –5 capacitance at the summing junction of the amplifier, including CS and the amplifier input capacitance. RF and the total capacitance –10 produce a pole in the loop transmission of the amplifier that –15 can result in peaking and instability. Adding C creates a zero F –20 in the loop transmission that compensates for the effect of the pole and reduces the signal bandwidth. It can be shown that the –25 signal bandwidth resulting in a 45°phase margin (f ) is defined (45) –30 by the expression –35 f CR –40 f = (45) 2π× R × C F S –45 100k 1M 10M 100M where: FREQUENCY (Hz) fCR is the amplifier crossover frequency. Figure 61. 2-Pole Butterworth Active Filter Response RF is the feedback resistor. C is the total capacitance at the amplifier summing junction S (amplifier + photodiode + board parasitics). The value of C that produces f is F (45) C S C = F 2π× R × f F CR The frequency response in this case shows about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half results in a flat frequency response, with about 5% transient overshoot. Rev. D | Page 21 of 24 GAIN (dB) 02924-060 02924-061 02924-062 AD8033/AD8034 The output noise over frequency of the preamp is shown in 1 Figure 63. f = 1 2πR (C + C + C + 2C ) F F S M D The pole in the loop transmission translates to a zero in the 1 f = 2 noise gain of the amplifier, leading to an amplification of the 2πR C F F input voltage noise over frequency. The loop transmission zero f CR f = 3 (C + C + 2C + C )/C S M D F F introduced by CF limits the amplification. The bandwidth of the noise gain extends past the preamp signal bandwidth and is eventually rolled off by the decreasing loop gain of the amplifier. RF NOISE Keeping the input terminal impedances matched is recommended f 3 f VEN (C + C + C + 2C )/C 2 F S M D F to eliminate common-mode noise peaking effects that add to f 1 the output noise. VEN Integrating the square of the output voltage noise spectral density NOISE DUE TO AMPLIFIER over frequency and then taking the square root results in the FREQUENCY (Hz) total rms output noise of the preamp. Figure 63. Photodiode Voltage Noise Contributions Rev. D | Page 22 of 24 VOLTAGE NOISE (nV/√Hz) 02924-063 0.10 MAX AD8033/AD8034 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 0.50 (0.0196) 1.27 (0.0500) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 64. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 2.20 2.00 1.80 1.35 2.40 5 4 1.25 2.10 12 3 1.15 1.80 PIN 1 0.65 BSC 1.00 0.40 1.10 0.90 0.10 0.80 0.70 0.46 0.36 0.30 0.22 0.26 0.15 SEATING 0.08 PLANE 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 65. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 13 2 4 PIN 1 INDICATOR 0.65 BSC 1.95 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.60 8° 0.45 0.38 0.15 MAX 4° SEATING 0.30 0.22 PLANE 0° COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 66. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters Rev. D | Page 23 of 24 012407-A AD8033/AD8034 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8033AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8033AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8 AD8033AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8033ARZ –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8033ARZ-REEL –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8033ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 AD8033AKS-R2 –40°C to +85°C 5-Lead SC70 KS-5 H3B AD8033AKS-REEL –40°C to +85°C 5-Lead SC70 KS-5 H3B AD8033AKS-REEL7 –40°C to +85°C 5-Lead SC70 KS-5 H3B 1 AD8033AKSZ-R2 –40°C to +85°C 5-Lead SC70 KS-5 H3C 1 AD8033AKSZ-REEL –40°C to +85°C 5-Lead SC70 KS-5 H3C 1 AD8033AKSZ-REEL7 –40°C to +85°C 5-Lead SC70 KS-5 H3C AD8034AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8034AR-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 AD8034AR-REEL –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8034ARZ –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8034ARZ-REEL –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8034ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N R-8 AD8034ART-R2 –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA AD8034ART-REEL –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA AD8034ART-REEL7 –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA 1 AD8034ARTZ-R2 –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA# 1 AD8034ARTZ-REEL –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA# 1 AD8034ARTZ-REEL7 –40°C to +85°C 8-Lead SOT-23 RJ-8 HZA# AD8034CHIPS DIE 1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. ©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02924-0-9/08(D) Rev. D | Page 24 of 24