ANALOG DEVICES AD8031

2.7 V, 800 μA, 80 MHz Rail-to-Rail I/O Amplifiers AD8031/AD8032 FEATURES CONNECTION DIAGRAMS Low power NC 1 8 NC OUT1 1 AD8032 8 +V S –IN 2 – Supply current 800 μA/amplifier 7 +V –IN1 2 7 OUT2 S + +IN 3 6 OUT +IN1 3 6 –IN2 Fully specified at +2.7 V, +5 V, and ±5 V supplies +– –V 4 5 NC AD8031 S –V 4 5 +IN2 S High speed and fast settling on 5 V NC = NO CONNECT 80 MHz, −3 dB bandwidth (G = +1) Figure 1. 8-Lead PDIP (N) and Figure 2. 8-Lead PDIP (N), 30 V/μs slew rate SOIC_N (R) SOIC_N (R), and MSOP (RM) 125 ns settling time to 0.1% AD8031 Rail-to-rail input and output V 1 5 +V OUT S No phase reversal with input 0.5 V beyond supplies –V 2 S Input CMVR extends beyond rails by 200 mV + – +IN 3 4 –IN Output swing to within 20 mV of either rail Low distortion Figure 3. 5-Lead SOT-23 (RJ-5) −62 dB @ 1 MHz, VO = 2 V p-p −86 dB @ 100 kHz, VO = 4.6 V p-p Output current: 15 mA Operating on supplies from +2.7 V to +12 V and dual supplies up to ±6 V, the AD8031/AD8032 are ideal for a wide range of High grade option: VOS (maximum) = 1.5 mV applications, from battery-operated systems with large bandwidth requirements to high speed systems where component density APPLICATIONS requires lower power dissipation. The AD8031/AD8032 are High speed, battery-operated systems available in 8-lead PDIP and 8-lead SOIC_N packages and High component density systems operate over the industrial temperature range of −40°C to Portable test instruments +85°C. The AD8031A is also available in the space-saving A/D buffers 5-lead SOT-23 package, and the AD8032A is available in an Active filters 8-lead MSOP package. High speed, set-and-demand amplifiers V =4.85Vp-p V =4.65Vp-p IN OUT G=+1 GENERAL DESCRIPTION The AD8031 (single) and AD8032 (dual) single-supply, voltage feedback amplifiers feature high speed performance with 80 MHz of small signal bandwidth, 30 V/μs slew rate, and 125 ns settling time. This performance is possible while consuming less than 4.0 mW of power from a single 5 V supply. These features 2µs/DIV 2µs/DIV increase the operation time of high speed, battery-powered Figure 4. Input V Figure 5. Output V IN OUT systems without compromising dynamic performance. +5V The products have true single-supply capability with rail-to-rail – V input and output characteristics and are specified for +2.7 V, +5 V, OUT V IN + 1kΩ 1.7pF and ±5 V supplies. The input voltage range can extend to 500 mV +2.5V beyond each rail. The output voltage swings to within 20 mV of each rail providing the maximum output dynamic range. Figure 6. Rail-to-Rail Performance at 100 kHz The AD8031/AD8032 also offer excellent signal quality for only 800 μA of supply current per amplifier; THD is −62 dBc with a 2 V p-p, 1 MHz output signal, and –86 dBc for a 100 kHz, 4.6 V p-p signal on +5 V supply. The low distortion and fast settling time make them ideal as buffers to single-supply ADCs. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 1V/DIV 01056-001 01056-004 1V/DIV 01056-003 01056-006 01056-002 01056-005 +– AD8031/AD8032 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Input Stage Operation ................................................................ 13 General Description ......................................................................... 1 Overdriving the Input Stage ...................................................... 13 Connection Diagrams ...................................................................... 1 Output Stage, Open-Loop Gain and Distortion vs. Clearance from Power Supply ..................................................................... 14 Revision History ............................................................................... 2 Output Overdrive Recovery ...................................................... 14 Specif ica t ions ..................................................................................... 3 Driving Capacitive Loads .......................................................... 15 +2.7 V Supply ................................................................................ 3 A pplica t ions ..................................................................................... 16 +5 V Supply ................................................................................... 4 A 2 MHz Single-Supply, Biquad Band-Pass Filter ................. 16 ±5 V Supply ................................................................................... 5 High Performance, Single-Supply Line Driver........................... 16 Absolute Maximum Ratings ............................................................ 6 Outline Dimensions ....................................................................... 18 Maximum Power Dissipation ..................................................... 6 Ordering Guide .......................................................................... 20 ESD Caution .................................................................................. 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 11/08—Rev. C to Rev. D Change to Table 3 Column Heading .............................................. 5 Change to Ordering Guide ............................................................ 20 7/06—Rev. B to Rev. C Updated Format .................................................................. Universal Updated Outline Dimensions ....................................................... 18 Change to Ordering Guide ............................................................ 20 9/99—Rev. A to Rev. B Rev. D | Page 2 of 20 AD8031/AD8032 SPECIFICATIONS +2.7 V SUPPLY @ T = 25°C, V = 2.7 V, R = 1 kΩ to 1.35 V, R = 2.5 kΩ, unless otherwise noted. A S L F Table 1. AD8031A/AD8032A AD8031B/AD8032B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth G = +1, V < 0.4 V p-p 54 80 54 80 MHz O Slew Rate G = −1, VO = 2 V step 25 30 25 30 V/μs Settling Time to 0.1% G = −1, VO = 2 V step, CL = 10 pF 125 125 ns DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion fC = 1 MHz, VO = 2 V p-p, G = +2 −62 −62 dBc fC = 100 kHz, VO = 2 V p-p, G = +2 −86 −86 dBc Input Voltage Noise f = 1 kHz 15 15 nV/√Hz Input Current Noise f = 100 kHz 2.4 2.4 pA/√Hz f = 1 kHz 5 5 pA/√Hz Crosstalk (AD8032 Only) f = 5 MHz −60 −60 dB DC PERFORMANCE Input Offset Voltage V = V /2; V = 135 V ±1 ±6 ±0.5 ±1.5 mV CM CC OUT TMIN to TMAX ±6 ±10 ±1.6 ±2.5 mV Offset Drift VCM = VCC/2; VOUT = 135 V 10 10 μV/°C Input Bias Current VCM = VCC/2; VOUT = 135 V 0.45 2 0.45 2 μA T to T 2.2 2.2 μA MIN MAX Input Offset Current 50 500 50 500 nA Open-Loop Gain V = V /2; V = 0.35 V to 2.35 V 76 80 76 80 dB CM CC OUT TMIN to TMAX 74 74 dB INPUT CHARACTERISTICS Common-Mode Input Resistance 40 40 MΩ Differential Input Resistance 280 280 kΩ Input Capacitance 1.6 1.6 pF Input Voltage Range −0.5 to −0.5 to V +3.2 +3.2 Input Common-Mode Voltage Range −0.2 to −0.2 to V +2.9 +2.9 Common-Mode Rejection Ratio VCM = 0 V to 2.7 V 46 64 46 64 dB VCM = 0 V to 1.55 V 58 74 58 74 dB Differential Input Voltage 3.4 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low RL = 10 kΩ 0.05 0.02 0.05 0.02 V Output Voltage Swing High 2.6 2.68 2.6 2.68 V Output Voltage Swing Low R = 1 kΩ 0.15 0.08 0.15 0.08 V L Output Voltage Swing High 2.55 2.6 2.55 2.6 V Output Current 15 15 mA Short Circuit Current Sourcing 21 21 mA Sinking −34 −34 mA Capacitive Load Drive G = +2 (See Figure 46) 15 15 pF POWER SUPPLY Operating Range 2.7 12 2.7 12 V Quiescent Current per Amplifier 750 1250 750 1250 μA Power Supply Rejection Ratio V − = 0 V to −1 V or 75 86 75 86 dB S VS+ = +2.7 V to +3.7 V Rev. D | Page 3 of 20 AD8031/AD8032 +5 V SUPPLY @ TA = 25°C, VS = 5 V, RL = 1 kΩ to 2.5 V, RF = 2.5 kΩ, unless otherwise noted. Table 2. AD8031A/AD8032A AD8031B/AD8032B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, VO < 0.4 V p-p 54 80 54 80 MHz Slew Rate G = −1, V = 2 V step 27 32 27 32 V/μs O Settling Time to 0.1% G = −1, V = 2 V step, C = 10 pF 125 125 ns O L DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f = 1 MHz, V = 2 V p-p, G = +2 −62 −62 dBc C O f = 100 kHz, V = 2 V p-p, G = +2 −86 −86 dBc C O Input Voltage Noise f = 1 kHz 15 15 nV/√Hz Input Current Noise f = 100 kHz 2.4 2.4 pA/√Hz f = 1 kHz 5 5 pA/√Hz Differential Gain R = 1 kΩ 0.17 0.17 % L Differential Phase R = 1 kΩ 0.11 0.11 Degrees L Crosstalk (AD8032 Only) f = 5 MHz −60 −60 dB DC PERFORMANCE Input Offset Voltage V = V /2; V = 2.5 V ±1 ±6 ±0.5 ±1.5 mV CM CC OUT T to T ±6 ±10 ±1.6 ±2.5 mV MIN MAX Offset Drift VCM = VCC/2; VOUT = 2.5 V 5 5 μV/°C Input Bias Current VCM = VCC/2; VOUT = 2.5 V 0.45 1.2 0.45 1.2 μA TMIN to TMAX 2.0 2.0 μA Input Offset Current 50 350 50 250 nA Open-Loop Gain V = V /2; V = 1.5 V to 3.5 V 76 82 76 82 dB CM CC OUT TMIN to TMAX 74 74 dB INPUT CHARACTERISTICS Common-Mode Input Resistance 40 40 MΩ Differential Input Resistance 280 280 kΩ Input Capacitance 1.6 1.6 pF Input Voltage Range −0.5 to −0.5 to V +5.5 +5.5 Input Common-Mode Voltage Range −0.2 to −0.2 to V +5.2 +5.2 Common-Mode Rejection Ratio VCM = 0 V to 5 V 56 70 56 70 dB VCM = 0 V to 3.8 V 66 80 66 80 dB Differential Input Voltage 3.4 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low RL = 10 kΩ 0.05 0.02 0.05 0.02 V Output Voltage Swing High 4.95 4.98 4.95 4.98 V Output Voltage Swing Low R = 1 kΩ 0.2 0.1 0.2 0.1 V L Output Voltage Swing High 4.8 4.9 4.8 4.9 V Output Current 15 15 mA Short Circuit Current Sourcing 28 28 mA Sinking −46 −46 mA Capacitive Load Drive G = +2 (See Figure 46) 15 15 pF POWER SUPPLY Operating Range 2.7 12 2.7 12 V Quiescent Current per Amplifier 800 1400 800 1400 μA Power Supply Rejection Ratio V − = 0 V to −1 V or 75 86 75 86 dB S VS+ = +5 V to +6 V Rev. D | Page 4 of 20 AD8031/AD8032 ±5 V SUPPLY @ TA = 25°C, VS = ±5 V, RL = 1 kΩ to 0 V, RF = 2.5 kΩ, unless otherwise noted. Table 3. AD8031A/AD8032A AD8031B/AD8032B Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth G = +1, VO < 0.4 V p-p 54 80 54 80 MHz Slew Rate G = −1, V = 2 V step 30 35 30 35 V/μs O Settling Time to 0.1% G = −1, V = 2 V step, C = 10 pF 125 125 ns O L DISTORTION/NOISE PERFORMANCE Total Harmonic Distortion f = 1 MHz, V = 2 V p-p, G = +2 −62 −62 dBc C O f = 100 kHz, V = 2 V p-p, G = +2 −86 −86 dBc C O Input Voltage Noise f = 1 kHz 15 15 nV/√Hz Input Current Noise f = 100 kHz 2.4 2.4 pA/√Hz f = 1 kHz 5 5 pA/√Hz Differential Gain R = 1 kΩ 0.15 0.15 % L Differential Phase R = 1 kΩ 0.15 0.15 Degrees L Crosstalk (AD8032 Only) f = 5 MHz −60 −60 dB DC PERFORMANCE Input Offset Voltage V = 0 V; V = 0 V ±1 ±6 ±0.5 ±1.5 mV CM OUT T to T ±6 ±10 ±1.6 ±2.5 mV MIN MAX Offset Drift VCM = 0 V; VOUT = 0 V 5 5 μV/°C Input Bias Current VCM = 0 V; VOUT = 0 V 0.45 1.2 0.45 1.2 μA TMIN to TMAX 2.0 2.0 μA Input Offset Current 50 350 50 250 nA Open-Loop Gain V = 0 V; V = ±2 V 76 80 76 80 dB CM OUT TMIN to TMAX 74 74 dB INPUT CHARACTERISTICS Common-Mode Input Resistance 40 40 MΩ Differential Input Resistance 280 280 kΩ Input Capacitance 1.6 1.6 pF Input Voltage Range −5.5 to −5.5 to V +5.5 +5.5 Input Common-Mode Voltage Range −5.2 to −5.2 to V +5.2 +5.2 Common-Mode Rejection Ratio VCM = −5 V to +5 V 60 80 60 80 dB VCM = −5 V to +3.5 V 66 90 66 90 dB Differential/Input Voltage 3.4 3.4 V OUTPUT CHARACTERISTICS Output Voltage Swing Low RL = 10 kΩ −4.94 −4.98 −4.94 −4.98 V Output Voltage Swing High +4.94 +4.98 +4.94 +4.98 V Output Voltage Swing Low R = 1 kΩ −4.7 −4.85 −4.7 −4.85 V L Output Voltage Swing High +4.7 +4.75 +4.7 +4.75 V Output Current 15 15 mA Short Circuit Current Sourcing 35 35 mA Sinking −50 −50 mA Capacitive Load Drive G = +2 (See Figure 46) 15 15 pF POWER SUPPLY Operating Range ±1.35 ±6 ±1.35 ±6 V Quiescent Current per Amplifier 900 1600 900 1600 μA Power Supply Rejection Ratio V − = −5 V to −6 V or 76 86 76 86 dB S VS+ = +5 V to +6 V Rev. D | Page 5 of 20 AD8031/AD8032 ABSOLUTE MAXIMUM RATINGS Table 4. MAXIMUM POWER DISSIPATION Parameter Rating The maximum power that can be safely dissipated by the Supply Voltage 12.6 V AD8031/AD8032 is limited by the associated rise in junction 1 Internal Power Dissipation temperature. The maximum safe junction temperature for 8-Lead PDIP (N) 1.3 W plastic encapsulated devices is determined by the glass 8-Lead SOIC_N (R) 0.8 W transition temperature of the plastic, approximately 150°C. 8-Lead MSOP (RM) 0.6 W Exceeding this limit temporarily can cause a shift in parametric 5-Lead SOT-23 (RJ) 0.5 W performance due to a change in the stresses exerted on the die Input Voltage (Common Mode) ±V ± 0.5 V S by the package. Exceeding a junction temperature of 175°C for Differential Input Voltage ±3.4 V an extended period can result in device failure. Output Short-Circuit Duration Observe Power Derating Curves While the AD8031/AD8032 are internally short-circuit Storage Temperature Range (N, R, RM, RJ) −65°C to +125°C protected, this may not be sufficient to guarantee that the Lead Temperature (Soldering 10 sec) 300°C maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to Stresses above those listed under Absolute Maximum Ratings observe the maximum power derating curves shown in Figure 7. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any 2.0 T = +150°C J other conditions above those indicated in the operational 8-LEAD PDIP section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect 1.5 8-LEAD SOIC device reliability. 8-LEAD MSOP 1 1.0 Specification is for the device in free air: 8-Lead PDIP: θ = 90°C/W. JA 8-Lead SOIC_N: θJA = 155°C/W. 8-Lead MSOP: θ = 200°C/W. JA 0.5 5-LEAD SOT-23 5-Lead SOT-23: θJA = 240°C/W. 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 7. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 6 of 20 MAXIMUM POWER DISSIPATION (W) 01056-007 AD8031/AD8032 TYPICAL PERFORMANCE CHARACTERISTICS 90 800 80 600 N = 250 70 400 60 200 V =10V S 50 V =2.7V V =5V S S 0 40 –200 30 –400 20 –600 10 0 –800 –5 –4 –3 –2 –1 0123 45 01 2 34 567 89 10 COMMON-MODE VOLTAGE (V) V (mV) OS Figure 8. Typical VOS Distribution @ VS = 5 V Figure 11. Input Bias Current vs. Common-Mode Voltage 2.5 0 V =5V S –0.1 2.3 –0.2 2.1 V =+5V S –0.3 1.9 –0.4 V =±5V S 1.7 –0.5 1.5 –0.6 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) COMMON-MODE VOLTAGE (V) Figure 9. Input Offset Voltage vs. Temperature Figure 12. V vs. Common-Mode Voltage OS 1.00 1000 0.95 ±I ,V =±5V S S 950 V =5V S 0.90 900 0.85 850 0.80 +I ,V =+5V S S 0.75 800 0.70 750 0.65 +I ,V = +2.7V S S 700 0.60 650 0.55 0.50 600 –40 –30–20–10 0 10203040 5060 7080 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) TEMPERATURE (°C) Figure 10. Input Bias Current vs. Temperature Figure 13. Supply Current vs. Temperature Rev. D | Page 7 of 20 INPUT BIAS (µA) OFFSET VOLTAGE (mV) NUMBER OF PARTS IN BIN 01056-008 01056-009 01056-010 OFFSET VOLTAGE (mV) INPUT BIAS CURRENT (nA) SUPPLY CURRENT/AMPLIFIER (µA) 01056-013 01056-012 01056-011 AD8031/AD8032 0 1.2 V =2.7V CC V CC 1.0 –0.5 V =10V V CC OUT V IN R LOAD 0.8 V =5V V CC EE –1.0 V CC 2 0.6 V CC –1.5 V =5V CC 0.4 V = 10V V OUT CC V IN R LOAD –2.0 0.2 V EE V CC V =2.7V CC 2 –2.5 0 100 1k 10k 100 1k 10k R (Ω) LOAD R (Ω) LOAD Figure 14. +Output Saturation Voltage vs. RLOAD @ +85°C Figure 17. −Output Saturation Voltage vs. R @ +85°C LOAD 0 1.2 V =2.7V CC V CC 1.0 –0.5 V V = 10V OUT CC V IN R LOAD 0.8 V V =5V CC EE –1.0 V CC 2 0.6 V CC V =5V –1.5 CC 0.4 V V =10V CC OUT V IN R LOAD –2.0 V 0.2 EE V CC V =2.7V CC 2 –2.5 0 100 1k 10k 100 1k 10k R (Ω) LOAD R (Ω) LOAD Figure 18. −Output Saturation Voltage vs. R @ +25°C Figure 15. +Output Saturation Voltage vs. RLOAD @ +25°C LOAD 0 1.2 V =2.7V CC V CC 1.0 –0.5 V V = 10V OUT CC V IN R LOAD 0.8 V EE –1.0 V =5V CC V CC 2 0.6 V CC V =5V CC –1.5 0.4 V V = 10V OUT CC V IN R LOAD –2.0 0.2 V EE V CC V =2.7V CC 2 –2.5 0 100 1k 10k 100 1k 10k R (Ω) LOAD R (Ω) LOAD Figure 16. +Output Saturation Voltage vs. RLOAD @ −40°C Figure 19. −Output Saturation Voltage vs. RLOAD @ −40°C Rev. D | Page 8 of 20 DIFFERENCE FROM V (V) DIFFERENCE FROM V (V) DIFFERENCE FROM V (V) CC CC CC 01056-016 01056-015 01056-014 DIFFERENCE FROM V (V) DIFFERENCE FROM V (V) DIFFERENCE FROM V (V) EE EE EE 01056-019 01056-018 01056-017 AD8031/AD8032 110 V =5V S 500mV 1V 105 100 100 –A OL 10 90 95 90 +A OL 0 85 80 V =5V S 75 10 –10 0% 70 65 500mV 60 0 2k4k6k8k 10k –1.5 0.5 2.5 4.5 6.5 (Ω) R LOAD INPUT VOLTAGE (V) Figure 20. Open-Loop Gain (A ) vs. R Figure 23. Differential Input Overvoltage I-V Characteristics OL LOAD 86 0.05 V =5V S 0 R =1kΩ L 84 –0.05 –A OL –0.10 82 –0.15 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH +A 0.10 OL 80 0.05 0 78 –0.05 –0.10 76 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 21. Open Loop Gain vs. (A ) Temperature Figure 24. Differential Gain and Phase @ V = ±5 V; R = 1 kΩ OL S L 110 100 V =5V S V =5V R = 10kΩ S LOAD 100 30 100 VOLTAGE NOISE 90 10 10 R =1kΩ LOAD 80 3 1 70 CURRENT NOISE 1 0.1 60 0.3 50 10 100 1k 10k 100k 1M 10M 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (Hz) V (V) OUT Figure 22. Open-Loop Gain (A ) vs. V Figure 25. Input Voltage Noise vs. Frequency OL OUT Rev. D | Page 9 of 20 A (dB) GAIN (dB) OL GAIN (dB) 01056-021 01056-022 01056-020 INPUT VOLTAGE NOISE (nV/ Hz) INPUT BIAS CURRENT (mA) DIFF PHASE (Degrees) DIFF GAIN (%) INPUT CURRENT NOISE (pA/ Hz) 01056-024 01056-023 01056-025 AD8031/AD8032 5 40 V =5V 4 S G= +1 30 R =1kΩ 3 L GAIN 20 2 10 1 0 0 –10 –90 –1 PHASE –20 –135 –2 –180 –3 –225 –4 –5 0.3 1 10 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Open-Loop Frequency Response Figure 26. Unity Gain, −3 dB Bandwidth –20 3 V = 5V S 2 V = –16dBm IN –30 +85°C V CC 1 G= +1,R =2kΩ TO L 2 –40 0 –40°C +25°C 1.3V p-p –50 –1 V =2.7V 2.5V p-p S V =2.7V S –2 V S –60 2V p-p 2kΩ –3 V =2.7V S V OUT V IN –70 50Ω –4 4.8V p-p V =5V S –80 –5 0.1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (MHz) FUNDAMENTAL FREQUENCY (Hz) Figure 27. Closed-Loop Gain vs. Temperature Figure 30. Total Harmonic Distortion vs. Frequency; G = +1 2 –20 V = +2.7V S V =+5V S 1 R +C TO 1.35V L L –30 R +C L L G= +2 TO 2.5V 0 V =5V S V CC –40 R =1kΩ TO V =±5V L S –1 2 –50 –2 4.8V p-p –3 –60 1V p-p G= +1 C =5pF –4 L –70 R =1kΩ L –5 4.6V p-p –80 –6 4V p-p –90 –7 –8 –100 100k 1M 10M 100M 1k 10k 100k 1M 10M FREQUENCY (Hz) FUNDAMENTAL FREQUENCY (Hz) Figure 28. Closed-Loop Gain vs. Supply Voltage Figure 31. Total Harmonic Distortion vs. Frequency; G +2 Rev. D | Page 10 of 20 NORMALIZED GAIN (dB) CLOSED-LOOP GAIN (dB) NORMALIZED GAIN (dB) 01056-028 01056-027 01056-026 PHASE (Degrees) TOTAL HARMONIC DISTORTION (dBc) TOTAL HARMONIC DISTORTION (dBc) OPEN-LOOPGAIN (dB) 01056-031 01056-030 01056-029 AD8031/AD8032 10 0 V =±5V S –20 8 V =5V S –40 6 V =+5V –60 S 4 –80 V =+2.7V S –100 2 –120 0 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 32. Large Signal Response Figure 35. PSRR vs. Frequency V =5V S R = 10kΩ TO 2.5V L 100 RB =50Ω =6Vp-p T V IN 5.5 G= +1 50 4.5 10 3.5 2.5 1 1.5 0.5 RB T 0.1 V OUT –0.5 RB =0Ω T 0.1 1 10 100 200 FREQUENCY (MHz) 10µs/DIV Figure 33. R vs. Frequency OUT Figure 36. Output Voltage 0 V =5V V =5V S S INPUT G= +1 INPUT = 650mV –20 5.5 BEYOND RAILS 4.5 –40 3.5 2.5 –60 1.5 0.5 –0.5 –80 –100 100 1k 10k 100k 1M 10M 10µs/DIV FREQUENCY (Hz) Figure 34. CMRR vs. Frequency Figure 37. Output Voltage Phase Reversal Behavior Rev. D | Page 11 of 20 COMMON-MODE REJECTION RATIO (dB) R (Ω) OUTPUT (V p-p) OUT 01056-034 01056-033 01056-032 POWER SUPPLY REJECTION RATIO (dB) 1V/DIV 1V/DIV 01056-037 01056-035 01056-036 AD8031/AD8032 G= +1 R TO L R =0Ω F +2.5V R =2kΩ TO 2.5V L 2.56 C = 5pF TO 2.5V L V =5V S 2.54 2.52 2.50 2.48 2.46 V =+5V S 2.44 R =1kΩ L G=–1 R TO GND L 0 50ns/DIV 10µs/DIV Figure 41. 100 mV Step Response Figure 38. Output Swing –50 G= +2 R =R =2.5kΩ F G –60 R =2kΩ L 3.1 C =5pF L –70 V =5V 2.9 S V =±2.5V S –80 V =+10dBm IN 2.7 –90 2.5 –100 2.3 2.5kΩ 2.5kΩ 2.5kΩ 2.5kΩ 2.1 V OUT V IN 1.9 1kΩ 50Ω 50Ω TRANSMITTER RECEIVER 0 0..1 1 11 1 100 1 100 00 20 200 0 50ns/DIV FREQUENCY (MHz) Figure 39. 1 V Step Response Figure 42. Crosstalk vs. Frequency V = 2.7V S R = 1kΩ L G = –1 2.85 2.35 1.85 1.35 R TO L 0.85 1.35V 0.35 R TO GND L 10µs/DIV Figure 40. Output Swing Rev. D | Page 12 of 20 500mV/DIV 200mV/DIV 500mV/DIV 01056-038 01056-039 01056-040 20mV/DIV CROSSTALK(dB) 01056-042 01056-041 AD8031/AD8032 THEORY OF OPERATION Switching to the NPN pair as the common-mode voltage is The AD8031/AD8032 are single and dual versions of high speed, low power, voltage feedback amplifiers featuring an driven beyond 1 V within the positive supply allows the amplifier innovative architecture that maximizes the dynamic range to provide useful operation for signals at either end of the capability on the inputs and outputs. The linear input common- supply voltage range and eliminates the possibility of phase mode range exceeds either supply voltage by 200 mV, and the reversal for input signals up to 500 mV beyond either power amplifiers show no phase reversal up to 500 mV beyond supply. supply. Offset voltage also changes to reflect the offset of the The output swings to within 20 mV of either supply when input pair in control. The transition region is small, approximately driving a light load; 300 mV when driving up to 5 mA. 180 mV. These sudden changes in the dc parameters of the input stage can produce glitches that adversely affect distortion. Fabricated on Analog Devices, Inc. eXtra Fast Complementary Bipolar (XFCB) process, the amplifier provides an impressive OVERDRIVING THE INPUT STAGE 80 Hz bandwidth when used as a follower and a 30 V/μs slew Sustained input differential voltages greater than 3.4 V should rate at only 800 μA supply current. Careful design allows the be avoided as the input transistors can be damaged. Input clamp amplifier to operate with a supply voltage as low as 2.7 V. diodes are recommended if the possibility of this condition exists. INPUT STAGE OPERATION A simplified schematic of the input stage appears in Figure 43. The voltages at the collectors of the input pairs are set to For common-mode voltages up to 1.1 V within the positive 200 mV from the power supply rails. This allows the amplifier supply (0 V to 3.9 V on a single 5 V supply), tail current I2 to remain in linear operation for input voltages up to 500 mV flows through the PNP differential pair, Q13 and Q17. Q5 is cut beyond the supply voltages. Driving the input common-mode off; no bias current is routed to the parallel NPN differential voltage beyond that point will forward bias the collector junction of pair, Q2 and Q3. As the common-mode voltage is driven within the input transistor, resulting in phase reversal. Sustaining this 1.1 V of the positive supply, Q5 turns on and routes the tail condition for any length of time should be avoided because it is current away from the PNP pair and to the NPN pair. During easy to exceed the maximum allowed input differential voltage this transition region, the input current of the amplifier changes when the amplifier is in phase reversal. magnitude and direction. Reusing the same tail current ensures that the input stage has the same transconductance, which determines the gain and bandwidth of the amplifier, in both regions of operation. V CC R1 I3 R2 I2 2kΩ 25µA 2kΩ Q9 90µA 1.1V R5 V Q3 Q2 Q6 Q10 IN 50kΩ 1 1 R6 R7 Q8 850Ω 850Ω Q7 Q5 R8 R9 4 4 850Ω 850Ω V Q13 Q17 IP I4 OUTPUT STAGE, 25µA COMMON-MODE FEEDBACK Q14 Q11 4 4 1 1 Q15 Q16 R4 R3 I1 2kΩ 2kΩ 5µA Q18 Q4 V EE Figure 43. Simplified Schematic of AD8031 Input Stage Rev. D | Page 13 of 20 01056-043 AD8031/AD8032 OUTPUT STAGE, OPEN-LOOP GAIN AND The open-loop gain of the AD8031 decreases approximately linearly with load resistance and depends on the output voltage. DISTORTION vs. CLEARANCE FROM POWER Open-loop gain stays constant to within 250 mV of the positive SUPPLY power supply, 150 mV of the negative power supply, and then The AD8031 features a rail-to-rail output stage. The output decreases as the output transistors are driven further into transistors operate as common-emitter amplifiers, providing the saturation. output drive current as well as a large portion of the amplifier’s open-loop gain. The distortion performance of the AD8031/AD8032 amplifiers differs from conventional amplifiers. Typically, the distortion I2 I1 Q42 Q51 performance of the amplifier degrades as the output voltage 25µA 25µA Q47 amplitude increases. DIFFERENTIAL Q37 Q38 DRIVE Used as a unity gain follower, the output of the AD8031/ FROM C9 Q68 INPUT STAGE 5pF AD8032 exhibits more distortion in the peak output voltage R29 Q20 300Ω region around VCC − 0.7 V. This unusual distortion characteristic is Q27 Q21 V OUT caused by the input stage architecture and is discussed in detail C5 Q43 Q48 1.5pF in the Input Stage Operation section, Q49 I4 OUTPUT OVERDRIVE RECOVERY I5 25µA 25µA Output overdrive of an amplifier occurs when the amplifier Q50 Q44 attempts to drive the output voltage to a level outside its normal range. After the overdrive condition is removed, the amplifier Figure 44. Output Stage Simplified Schematic must recover to normal operation in a reasonable amount of The output voltage limit depends on how much current the time. As shown in Figure 45, the AD8031/AD8032 recover output transistors are required to source or sink. For applications within 100 ns from negative overdrive and within 80 ns from with low drive requirements (for instance, a unity gain follower positive overdrive. driving another amplifier input), the AD8031 typically swings R R G F within 20 mV of either voltage supply. As the required current R =R =2kΩ F G load increases, the saturation output voltage increases linearly as V OUT V IN R L ILOAD × RC 50Ω where: I is the required load current. LOAD R is the output transistor collector resistance. C For the AD8031, the collector resistances for both output V =±2.5V transistors are typically 25 Ω. As the current load exceeds the S V =±2.5V IN rated output current of 15 mA, the amount of base drive current R =1kΩ TO GND 1V L 100ns required to drive the output transistor into saturation reaches its Figure 45. Overdrive Recovery limit, and the amplifier’s output swing rapidly decreases. Rev. D | Page 14 of 20 + + 01056-044 01056-045 AD8031/AD8032 1000 R =5Ω S DRIVING CAPACITIVE LOADS V =5V S 200mV STEP Capacitive loads interact with an op amp’s output impedance to WITH 30% OVERSHOOT R =0Ω S create an extra delay in the feedback path. This reduces circuit 100 stability and can cause unwanted ringing and oscillation. A given value of capacitance causes much less ringing when the R =20Ω S amplifier is used with a higher noise gain. R =20Ω S The capacitive load drive of the AD8031/AD8032 can be 10 R R G F increased by adding a low valued resistor in series with the R V S OUT R =0Ω,5Ω S capacitive load. Introducing a series resistor tends to isolate the C L capacitive load from the feedback loop, thereby diminishing its 1 influence. Figure 46 shows the effects of a series resistor on the 01 23 45 capacitive drive for varying voltage gains. As the closed-loop CLOSED-LOOP GAIN (V/V) gain is increased, the larger phase margin allows for larger Figure 46. Capacitive Load Drive vs. Closed-Loop Gain capacitive loads with less overshoot. Adding a series resistor at lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier is dominated by the roll-off of the series resistor and capacitive load. Rev. D | Page 15 of 20 CAPACITIVE LOAD (pF) 01056-046 AD8031/AD8032 APPLICATIONS A 2 MHz SINGLE-SUPPLY, BIQUAD BAND-PASS FILTER 0 Figure 47 shows a circuit for a single-supply, biquad band-pass filter with a center frequency of 2 MHz. A 2.5 V bias level is –10 easily created by connecting the noninverting inputs of all three op amps to a resistor divider consisting of two 1 kΩ resistors –20 connected between 5 V and ground. This bias point is also decoupled to ground with a 0.1 μF capacitor. The frequency –30 response of the filter is shown in Figure 48. To maintain an accurate center frequency, it is essential that the –40 op amp have sufficient loop gain at 2 MHz. This requires the choice of an op amp with a significantly higher unity gain, –50 crossover frequency. The unity gain, crossover frequency of the 10k 100k 1M 10M 100M FREQUENCY (Hz) AD8031/AD8032 is 40 MHz. Multiplying the open-loop gain by Figure 48. Frequency Response of 2 MHz Band-Pass Filter the feedback factors of the individual op amp circuits yields the loop gain for each gain stage. From the feedback networks of HIGH PERFORMANCE, SINGLE-SUPPLY LINE DRIVER the individual op amp circuits, it can be seen that each op amp Even though the AD8031/AD8032 swing close to both rails, the has a loop gain of at least 21 dB. This level is high enough to AD8031 has optimum distortion performance when the signal ensure that the center frequency of the filter is not affected by has a common-mode level half way between the supplies and the op amp’s bandwidth. If, for example, an op amp with a gain when there is about 500 mV of headroom to each rail. If low bandwidth product of 10 MHz was chosen in this application, distortion is required in single-supply applications for signals the resulting center frequency would shift by 20% to 1.6 MHz. that swing close to ground, an emitter-follower circuit can be R6 1kΩ used at the op amp output. C1 5V 50pF 10µF R2 R4 2kΩ 2kΩ 5V 0.1µF 5V 0.1µF C2 R1 0.1µF 7 50pF 3 3kΩ V R3 IN V 6 IN 2kΩ R5 2N3904 49.9Ω 1kΩ 2 2kΩ AD8031 4 AD8031 1/2 49.9Ω 1/2 2.49kΩ 2.49kΩ AD8032 V OUT AD8032 200Ω 49.9Ω 0.1µF 1kΩ V OUT Figure 49. Low Distortion Line Driver for Single-Supply, Ground Referenced Signals Figure 47. A 2 MHz, Biquad Band-Pass Filter Using AD8031/AD8032 Figure 49 shows the AD8031 configured as a single-supply, gain- of-2 line driver. With the output driving a back-terminated 50 Ω line, the overall gain from V to V is unity. In addition IN OUT to minimizing reflections, the 50 Ω back termination resistor protects the transistor from damage if the cable is short circuited. The emitter follower, which is inside the feedback loop, ensures that the output voltage from the AD8031 stays about 700 mV above ground. Using this circuit, low distortion is attainable even when the output signal swings to within 50 mV of ground. The circuit was tested at 500 kHz and 2 MHz. Rev. D | Page 16 of 20 01056-047 GAIN (dB) 01056-048 01056-049 AD8031/AD8032 Figure 50 and Figure 51 show the output signal swing and This circuit could also be used to drive the analog input of a frequency spectrum at 500 kHz. At this frequency, the output single-supply, high speed ADC whose input voltage range is signal (at V ), which has a peak-to-peak swing of 1.95 V OUT referenced to ground (for example, 0 V to 2 V or 0 V to 4 V). In (50 mV to 2 V), has a THD of −68 dB (SFDR = −77 dB). this case, a back termination resistor is not necessary (assuming a short physical distance from transistor to ADC); therefore, the emitter of the external transistor would be connected directly to the ADC input. The available output voltage swing of the circuit 100 90 would therefore be doubled. 2V 1.5V 100 90 10 0% 50mV 1µs 0.5V Figure 50. Output Signal Swing of Low Distortion Line Driver at 500 kHz 10 0% +9dBm 0.2V 200ns 50mV Figure 52. Output Signal Swing of Low Distortion Line Driver at 2 MHz +7dBm START 0Hz STOP 5MHz Figure 51. THD of Low Distortion Line Driver at 500 kHz Figure 52 and Figure 53 show the output signal swing and frequency spectrum at 2 MHz. As expected, there is some START 0Hz STOP 20MHz degradation in signal quality at the higher frequency. When the Figure 53. THD of Low Distortion Line Driver at 2 MHz output signal has a peak-to-peak swing of 1.45 V (swinging from 50 mV to 1.5 V), the THD is −55 dB (SFDR = −60 dB). Rev. D | Page 17 of 20 VERTICAL SCALE (10dB/DIV) 01056-051 01056-050 VERTICAL SCALE (10dB/DIV) 01056-053 01056-052 AD8031/AD8032 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 4 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) 0.195 (4.95) MAX 0.210 (5.33) 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) MIN 0.130 (3.30) GAUGE 0.014 (0.36) PLANE 0.115 (2.92) SEATING 0.010 (0.25) PLANE 0.008 (0.20) 0.022 (0.56) 0.430 (10.92) 0.005 (0.13) 0.018 (0.46) MAX MIN 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 54. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2441) 4.00 (0.1574) 1 5.80 (0.2284) 3.80 (0.1497) 4 1.27 (0.0500) 0.50 (0.0196) 45° BSC 1.75 (0.0688) 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 8° 0.10 (0.0040) 0° 0.51 (0.0201) COPLANARITY 1.27 (0.0500) 0.10 0.31 (0.0122) 0.25 (0.0098) SEATING 0.40 (0.0157) PLANE 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. D | Page 18 of 20 012407-A 070606-A AD8031/AD8032 2.90 BSC 5 4 1.60 BSC 2.80 BSC 12 3 PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 10° 0.15 MAX 5° 0.50 0.60 SEATING 0° 0.30 PLANE 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AA Figure 56. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 1 2.80 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 8° 0.15 0.60 0.38 0.23 0° 0.00 0.22 0.40 0.08 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 57. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. D | Page 19 of 20 AD8031/AD8032 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8031AN –40°C to +85°C 8-Lead PDIP N-8 1 AD8031ANZ –40°C to +85°C 8-Lead PDIP N-8 AD8031AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8031AR-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8031AR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8031ARZ –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8031ARZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8031ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8031ART-R2 –40°C to +85°C 5-Lead SOT-23 RJ-5 H0A AD8031ART-REEL –40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H0A AD8031ART-REEL7 –40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H0A 1 AD8031ARTZ-R2 –40°C to +85°C 5-Lead SOT-23 RJ-5 H04 1 AD8031ARTZ-REEL –40°C to +85°C 5-Lead SOT-23, 13" Tape and Reel RJ-5 H04 1 AD8031ARTZ-REEL7 –40°C to +85°C 5-Lead SOT-23, 7" Tape and Reel RJ-5 H04 AD8031BN –40°C to +85°C 8-Lead PDIP N-8 1 AD8031BNZ –40°C to +85°C 8-Lead PDIP N-8 AD8031BR –40°C to +85°C 8-Lead SOIC_N R-8 AD8031BR-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8031BR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8031BRZ –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8031BRZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8031BRZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8032AN –40°C to +85°C 8-Lead PDIP N-8 1 AD8032ANZ –40°C to +85°C 8-Lead PDIP N-8 AD8032AR –40°C to +85°C 8-Lead SOIC_N R-8 AD8032AR-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8032AR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8032ARZ –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8032ARZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8032ARZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD8032ARM –40°C to +85°C 8-Lead MSOP RM-8 H9A AD8032ARM-REEL –40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H9A AD8032ARM-REEL7 –40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H9A 1 AD8032ARMZ –40°C to +85°C 8-Lead MSOP RM-8 H9A# 1 AD8032ARMZ-REEL –40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 H9A# 1 AD8032ARMZ-REEL7 –40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 H9A# AD8032BN –40°C to +85°C 8-Lead PDIP N-8 1 AD8032BNZ –40°C to +85°C 8-Lead PDIP N-8 AD8032BR –40°C to +85°C 8-Lead SOIC_N R-8 AD8032BR-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD8032BR-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 AD8032BRZ –40°C to +85°C 8-Lead SOIC_N R-8 1 AD8032BRZ-REEL –40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 1 AD8032BRZ-REEL7 –40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 1 Z = RoHS Compliant Part, # denotes lead-free product may be top or bottom marked. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01056-0-11/08(D) Rev. D | Page 20 of 20