ANALOG DEVICES AD8016

Low Power, High Output Current xDSL Line Driver Data Sheet AD8016 FEATURES PIN CONFIGURATIONS xDSL line driver that features full ADSL central office (CO) +V1 1 24 +V2 Performance on ±12 V supplies V 1 2 23 V 2 OUT OUT V 1 3 22 V 2 Low power operation INN INN +– V 1 4 21 V 2 INP INP ±5 V to ±12 V voltage supply AGND 5 20 AGND 12.5 mA/amp (typical) total supply current AD8016 AGND 6 19 AGND TOP VIEW Power reduced keep alive current of 4.5 mA/amp AGND 7 18 AGND (Not to Scale) High output voltage and current drive 8 17 AGND AGND I = 600 mA PWDN0 9 16 PWDN1 OUT DGND 10 15 BIAS 40 V p-p differential output voltage R = 50 Ω, V = ±12 V L S –V1 11 14 –V2 Low single-tone distortion NC 12 13 NC –75 dBc @ 1 MHz SFDR, R = 100 Ω, V = 2 V p-p L OUT MTPR = –75 dBc, 26 kHz to 1.1 MHz, Z = 100 Ω, NC = NO CONNECT LINE P = 20.4 dBm LINE Figure 1. 24-Lead SOIC_W_BAT (RB-24) High Speed NC 1 28 NC 78 MHz bandwidth (–3 dB), G = +5 NC 2 27 NC 40 MHz gain flatness 3 26 NC NC 1000 V/μs slew rate 4 25 +V 2 NC IN –V 2 5 24 PWDN1 IN V 2 6 23 BIAS OUT +V2 7 AD8016ARE 22 –V2 TOP VIEW 8 21 +V1 –V1 (Not to Scale) 9 20 V 1 DGND OUT –V 1 10 19 NC IN +V 1 11 18 PWDN0 IN 12 17 NC NC 13 16 NC NC 14 15 NC NC NOTES 1. THE EXPOSED PADDLE IS FLOATING, NOT ELECTRICALLY CONNECTED INTERNALLY. 2. NC = NO CONNECT. Figure 2. 28-Lead TSSOP_EP (RE-28-1) GENERAL DESCRIPTION The AD8016 high output current dual amplifier is designed for the xDSL hybrid in Figure 35 and Figure 36. Two digital bits the line drive interface in Digital Subscriber Line systems such (PWDN0, PWDN1) allow the driver to be capable of full as ADSL, HDSL2, and proprietary xDSL systems. The drivers performance, an output keep-alive state, or two intermediate are capable, in full-bias operation, of providing 24.4 dBm bias states. The keep-alive state biases the output transistors output power into low resistance loads, enough to power a enough to provide a low impedance at the amplifier outputs 20.4 dBm line, including hybrid insertion loss. for back termination. The AD8016 is available in a low cost 24-lead SOIC_W_BAT The low power dissipation, high output current, high output and a 28-lead TSSOP_EP with an exposed lead frame (ePAD). voltage swing, flexible power-down, and robust thermal Operating from ±12 V supplies, the AD8016 requires only 1.5 W packaging enable the AD8016 to be used as the central office of total power dissipation (refer to the Power Dissipation section (CO) terminal driver in ADSL, HDSL2, VDSL, and proprietary for details) while driving 20.4 dBm of power downstream using xDSL systems. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 01019-002 01019-003 +– AD8016 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Feedback Resistor Selection ...................................................... 14 Pin Configurations ........................................................................... 1 Bias Pin and PWDN Features ................................................... 14 General Description ......................................................................... 1 Thermal Shutdown .................................................................... 15 Revision History ............................................................................... 2 Applications Information .............................................................. 16 Specifications ..................................................................................... 3 Multitone Power Ratio (MTPR) ............................................... 16 Logic Inputs (CMOS Compatible Logic) .................................. 4 Generating DMT ........................................................................ 17 Absolute Maximum Ratings ............................................................ 5 Power Dissipation....................................................................... 17 Maximum Power Dissipation ..................................................... 5 Thermal Enhancements and PCB Layout ............................... 18 ESD Caution .................................................................................. 5 Thermal Testing .......................................................................... 18 Pin Configurations and Function Descriptions ........................... 6 Air Flow Test Conditions .......................................................... 18 Typical Performance Characteristics ............................................. 7 Experimental Results ................................................................. 19 Test Circuts ...................................................................................... 13 Outline Dimensions ....................................................................... 20 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 20 Power Supply and Decoupling .................................................. 14 REVISION HISTORY 3/12—Rev. B to Rev. C Updated Format .................................................................. Universal Deleted PSOP Package and Evaluation Boards (Throughout) ... 1 Added Pin Configurations and Function Descriptions Sections .. 7 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 19 11/03—Rev. A to Rev. B Changes to Ordering Guide ............................................................ 4 Changes to TPC 21 ........................................................................... 8 Updated Outline Dimensions ..................................................19-20 Rev. C | Page 2 of 20 Data Sheet AD8016 SPECIFICATIONS @ 25°C, VS = ±12 V, RL = 100 Ω, PWDN0, PWDN1 = (1, 1), TMIN = −40°C, TMAX = +85°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth G = +1, R = 1.5 kΩ, V = 0.2 V p-p 380 MHz F OUT G = +5, R = 499 Ω, V < 0.5 V p-p 69 78 MHz F OUT Bandwidth for 0.1 dB Flatness G = +5, R = 499 Ω, V = 0.2 V p-p 16 38 MHz F OUT Large Signal Bandwidth VOUT = 4 V p-p 90 MHz Peaking VOUT = 0.2 V p-p < 50 MHz 0.1 dB Slew Rate VOUT = 4 V p-p, G = +2 1000 V/μs Rise and Fall Time VOUT = 2 V p-p 2 ns Settling Time 0.1%, VOUT = 2 V p-p 23 ns Input Overdrive Recovery Time VOUT = 12.5 V p-p 350 ns NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended V = 2 V p-p, G = +5, R = 499 Ω OUT F Second Harmonic f = 1 MHz, R = 100 Ω/25 Ω −75/−62 −77/−64 dBc C L Third Harmonic f = 1 MHz, R = 100 Ω/25 Ω −88/−74 −93/−76 dBc C L 1 Multitone Power Ratio 26 kHz to 1.1 MHz, ZLINE = 100 Ω, PLINE = 20.4 dBm –75 dBc IMD 500 kHz, Δf = 10 kHz, RL = 100 Ω/25 Ω −84/−80 −88/−85 dBc IP3 500 kHz, RL = 100 Ω/25 Ω 42/40 43/41 dBm Voltage Noise (RTI) f = 10 kHz 2.6 4.5 nV/√Hz Input Current Noise f = 10 kHz 18 21 pA√Hz INPUT CHARACTERISTICS RTI Offset Voltage −3.0 1.0 +3.0 mV +Input Bias Current −45 +45 μA –Input Bias Current −75 4 +75 μA Input Resistance 400 kΩ Input Capacitance 2 pF Input Common-Mode Voltage Range −10 +10 V Common-Mode Rejection Ratio 58 64 dB OUTPUT CHARACTERISTICS Output Voltage Swing Single-ended, R = 100 Ω −11 +11 V L Linear Output Current G = 5, R = 10 Ω, f = 100 kHz, −60 dBc SFDR 400 600 mA L 1 Short-Circuit Current 2000 mA Capacitive Load Drive 80 pF POWER SUPPLY Operating Range ±3 ±13 V Quiescent Current PWDN1, PWDN0 = (1, 1) 12.5 13.2 mA/Amp PWDN1, PWDN0 = (1, 0) 8 10 mA/Amp PWDN1, PWDN0 = (0, 1) 5 8 mA/Amp PWDN1, PWDN0 = (0, 0) 4 6 mA/Amp Recovery Time To 95% of I 25 μs Q Shutdown Current 250 μA out of bias pin 1.5 4.0 mA/Amp Power Supply Rejection Ratio ΔV = ±1 V 63 75 dB S OPERATING TEMPERATURE RANGE −40 +85 °C 1 See Figure 48, R20, R21 = 0 Ω, R1 = open. Rev. C | Page 3 of 20 AD8016 Data Sheet @ 25°C, V = ±6 V, R = 100 Ω, PWDN0, PWDN1 = (1, 1), T = –40°C, T = +85°C, unless otherwise noted. S L MIN MAX Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Bandwidth G = +1, RF = 1.5 kΩ, VOUT = 0.2 V p-p 320 MHz G = +5, RF = 499 Ω, VOUT < 0.5 V p-p 70 71 MHz Bandwidth for 0.1 dB Flatness G = +5, RF = 499 Ω, VOUT = 0.2 V p-p 10 15 MHz Large Signal Bandwidth V = 1 V rms 80 MHz OUT Peaking V = 0.2 V p-p < 50 MHz 0.7 1.0 dB OUT Slew Rate V = 4 V p-p, G = +2 300 V/μs OUT Rise and Fall Time V = 2 V p-p 2 ns OUT Settling Time 0.1%, V = 2 V p-p 39 ns OUT Input Overdrive Recovery Time V = 6.5 V p-p 350 ns OUT NOISE/DISTORTION PERFORMANCE Distortion, Single-Ended G = +5, VOUT = 2 V p-p, RF = 499 Ω Second Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω −73/61 −75/−63 dBc Third Harmonic fC = 1 MHz, RL = 100 Ω/25 Ω −80/−68 −82/−70 dBc 1 Multitone Power Ratio 26 kHz to 138 kHz, Z = 100 Ω, P = 13 dBm −68 dBc LINE LINE IMD 500 kHz, Δf = 110 kHz, R = 100 Ω/25 Ω −87/−82 −88/−83 dBc L IP3 500 kHz 42/39 42/39 dBm Voltage Noise (RTI) f = 10 kHz 4 5 nV/√Hz Input Current Noise f = 10 kHz 17 20 pA√Hz INPUT CHARACTERISTICS RTI Offset Voltage −3.0 0.2 +3.0 mV +Input Bias Current −25 10 +25 μA −Input Bias Current −30 10 +30 μA Input Resistance 400 kΩ Input Capacitance 2 pF Input Common-Mode Voltage Range −4 +4 V Common-Mode Rejection Ratio 60 66 dB OUTPUT CHARACTERISTICS Output Voltage Swing Single-Ended, RL = 100 Ω −5 +5 V Linear Output Current G = +5, RL = 5 Ω, f = 100 kHz, −60 dBc SFDR 300 420 mA Short-Circuit Current 830 mA Capacitive Load Drive RS = 10 Ω 50 pF POWER SUPPLY Quiescent Current PWDN1, PWDN0 = (1, 1) 8 9.7 mA/Amp PWDN1, PWDN0 = (1, 0) 6 6.9 mA/Amp PWDN1, PWDN0 = (0, 1) 4 5.0 mA/Amp PWDN1, PWDN0 = (0, 0) 3 4.1 mA/Amp Recovery Time To 95% of IQ 23 μs Shutdown Current 250 μA out of bias pin 1.0 2.0 mA/Amp Power Supply Rejection Ratio ΔVS = ±1 V 63 80 dB OPERATING TEMPERATURE RANGE −40 +85 °C 1 See Figure 48, R20, R21 = 0 Ω, R1 = open. LOGIC INPUTS (CMOS COMPATIBLE LOGIC) PWDN0, PWDN1, V = ±12 V or ±6 V; full temperature range. CC Table 3. Parameter Min Typ Max Unit Logic 1 Voltage 2.2 V V CC Logic 0 Voltage 0 0.8 V Rev. C | Page 4 of 20 Data Sheet AD8016 ABSOLUTE MAXIMUM RATINGS The output stage of the AD8016 is designed for maximum load Table 4. current capability. As a result, shorting the output to common Parameter Rating can cause the AD8016 to source or sink 2000 mA. To ensure Supply Voltage 26.4 V proper operation, it is necessary to observe the maximum Internal Power Dissipation power derating curves. Direct connection of the output to 1 SOIC_W_BAT Package 1.4 W either power supply rail can destroy the device. 2 TSSOP_EP Package 1.4 W 8 Input Voltage (Common-Mode) ±V S Differential Input Voltage ±V S 7 Output Short-Circuit Duration Observe power derating curves 6 Storage Temperature Range −65°C to +125°C 5 Operating Temperature Range −40°C to +85°C Lead Temperature Range (Soldering 10 sec) 300°C 4 SOIC_W_BAT 1 2 Specification is for device on a 4-layer board with 10 inches of 1 oz copper 3 at 85°C 24-lead SOIC_W_BAT package: θJA = 28°C/W. TSSOP-EP 2 2 Specification is for device on a 4-layer board with 9 inches of 1 oz copper at 2 85°C 28-lead (TSSOP_EP) package: θJA = 29°C/W. Stresses above those listed under Absolute Maximum Ratings 1 may cause permanent damage to the device. This is a stress 0 rating only; functional operation of the device at these or any 010 20 30 40 50 60 70 80 90 other conditions above those indicated in the operational AMBIENT TEMPERATURE (°C) section of this specification is not implied. Exposure to absolute Figure 3. Maximum Power Dissipation vs. Temperature for AD8016 for T = 125 °C J maximum rating conditions for extended periods may affect device reliability. ESD CAUTION MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8016 is limited by the associated rise in junction temper- ature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric perfor- mance due to a change in the stresses exerted on the die by the package. Rev. C | Page 5 of 20 MAXIMUM POWER DISSIPATION (W) 01019-005 AD8016 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC 1 28 NC NC 2 27 NC 3 26 NC NC +V 2 4 25 NC IN –V 2 5 24 PWDN1 IN +V1 1 24 +V2 V 2 6 23 BIAS OUT V 1 2 23 V 2 OUT OUT 7 AD8016ARE 22 +V2 –V2 V 1 3 22 V 2 INN INN +– TOP VIEW +V1 8 21 –V1 (Not to Scale) V 1 4 21 V 2 INP INP V 1 9 20 DGND OUT AGND 5 20 AGND –V 1 10 19 NC AD8016 IN AGND 6 19 AGND 11 18 TOP VIEW +V 1 PWDN0 IN AGND 7 18 AGND (Not to Scale) 12 17 NC NC AGND 8 17 AGND NC 13 16 NC PWDN0 9 16 PWDN1 NC 14 15 NC DGND 10 15 BIAS –V1 11 14 –V2 NOTES 1. THE EXPOSED PADDLE IS FLOATING, NC 12 13 NC NOT ELECTRICALLY CONNECTED INTERNALLY. NC = NO CONNECT 2. NC = NO CONNECT. Figure 4. 24-Lead SOIC_W_BAT (RB-24) Figure 5. 28-Lead TSSOP_EP (RE-28-1) Table 5. Pin Function Descriptions Pin No. SOIC_W_BAT TSSOP_EP Mnemonic Description 1 8 +V1 Positive Power Supply, Amp 1. 2 9 VOUT1 Output Signal, Amp 1. 3 VINN1 Negative Input Signal, Amp 1. 4 VINP1 Positive Input Signal, Amp1. 5 to 8, 17 to 20 AGND Analog Ground. 9 18 PWDN0 Power-Down Input 0. 10 20 DGND Digital Ground. 11 21 −V1 Negative Power Supply, Amp1. 12, 13 1 to 3, 12 to 17, 19, NC This pin is not connected internally (see Figure 4 and Figure 5). 25 to 28 14 22 −V2 −V Power Supply, Amp 2. 15 23 BIAS Quiescent Current Adjust. 16 24 PWDN1 Power-Down Input 1. 21 VINP2 Positive Input Signal, Amp 2. 22 VINN2 Negative Input Signal, Amp 2. 23 6 V 2 Output Signal, Amp 2. OUT 24 7 +V2 Positive Power Supply, Amp 2. 4 +V 2 Positive Input Signal, Amp 2. IN 5 −VIN2 Negative Input Signal, Amp 2. 10 −VIN1 Negative Input Signal, Amp 1. 11 +VIN1 Positive Input Signal, Amp 1. EP EPAD Exposed Pad. The exposed paddle is floating, not electrically connected internally. Rev. C | Page 6 of 20 01019-002 01019-003 +– Data Sheet AD8016 TYPICAL PERFORMANCE CHARACTERISTICS V = 100mV OUT –75dBc V = 20mV IN TIME (100ns/DIV) 549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY (kHz) Figure 9. 100 mV Step Response; G = +5, V = ±12 V, R = 25 Ω, Single-Ended Figure 6. Multitone Power Ratio; VS = ±12 V, 20.4 dBm Output Power into S L 100 Ω, Downstream V = 100mV V = 4V OUT OUT V = 20mV IN V = 800mV IN TIME (100ns/DIV) TIME (100ns/DIV) Figure 7. 100 mV Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended Figure 10. 4 V Step Response; G = +5, VS = ±12 V, RL = 25 Ω, Single-Ended –30 R = 499Ω F V = 5V (0,0) OUT G = +10 V = 4V p-p –40 OUT –50 (0,1) (1,0) –60 –70 V = 800mV IN –80 PWDN1, PWDN0 = (1,1) –90 –100 –110 TIME (100ns/DIV) 0.01 0.1 1 10 20 FREQUENCY (MHz) Figure 8. 4 V Step Response; G = +5, VS = ±6 V, RL = 25 Ω, Single-Ended Figure 11. Distortion vs. Frequency; Second Harmonic, VS = ±12 V, RL = 50 Ω, Differential Rev. C | Page 7 of 20 10dB/DIV VOLTS VOLTS 01019-009 01019-008 01019-004 DISTORTION (dBc) VOLTS VOLTS 01019-011 01019-010 01019-012 AD8016 Data Sheet –30 –30 R = 499Ω (0,0) R = 499Ω F F G = +10 G = +10 V = 4V p-p V = 4V p-p –40 OUT –40 OUT (0,1) (0,0) –50 –50 (1,0) (0,1) (1,0) –60 –60 –70 –70 PWDN1, PWDN0 = (1,1) –80 –80 PWDN1, PWDN0 = (1,1) –90 –90 –100 –100 –110 –110 0.01 0.1 1 10 20 0.01 0.1 1 10 20 FREQUENCY (MHz) FREQUENCY (MHz) Figure 12. Distortion vs. Frequency; Second Harmonic, V = ±6 V, R = 50 Ω Figure 15. Distortion vs. Frequency; Third Harmonic, V = ±6 V, R = 50 Ω, S L S L Differential –30 –30 R = 499Ω R = 499Ω F F G = +5 G = +5 –35 –40 –40 (1,0) (0,0) –45 –50 –50 (0,1) –55 –60 (1,0) (0,0) (0,1) –60 –70 –65 –70 –80 PWDN1, PWDN0 = (1,1) –75 PWDN1, PWDN0 = (1,1) –80 –90 0 100 200 300400500600700800 0 100 200 300 400 500 600 700 PEAK OUTPUT CURRENT (mA) PEAK OUTPUT CURRENT (mA) Figure 13. Distortion vs. Peak Output Current; Second Harmonic, VS = ±12 V, Figure 16. Distortion vs. Peak Output Current, Third Harmonic; VS = ±12 V, RL = 10 Ω, f = 100 kHz, Single-Ended RL = 10 Ω, G = +5, f = 100 kHz, Single-Ended –30 –30 (0,0) R = 499Ω R = 499Ω F F G = +10 G = +5 –35 V = 4V p-p –40 OUT (0,1) –40 –50 –45 (0,0) –60 (1,0) –50 (0,1) –70 –55 (1,0) PWDN1, PWDN0 = (1,1) –60 –80 –65 –90 –70 –100 –75 PWDN1, PWDN0 = (1,1) –110 –80 0100 200 300 400 500 600 0.01 0.1 1 10 20 FREQUENCY (MHz) PEAK OUTPUT CURRENT (mA) Figure 14. Distortion vs. Frequency; Third Harmonic, VS = ±12 V, RL = 50 Ω, Figure 17. Distortion vs. Peak Output Current; Second Harmonic, VS = ±6 V, Differential RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 8 of 20 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01019-015 01019-013 01019-014 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01019-016 01019-018 01019-017 Data Sheet AD8016 –30 –30 –40 –40 (0,0) –50 –50 (0,0) (0,1) –60 –60 (1,0) (0,1) –70 –70 (1,0) –80 –80 PWDN1, PWDN0 = (1,1) PWDN1, PWDN0 = (1,1) –90 –90 –100 –100 05 10 15 20 25 30 35 40 05 10 15 20 25 30 35 40 DIFFERENTIAL OUTPUT (V p-p) DIFFERENTIAL OUTPUT (V p-p) Figure 18. Distortion vs. Output Voltage; Second Harmonic, V = ±12 V, Figure 21. Distortion vs. Output Voltage; Third Harmonic, V = ±12 V, S S G = +10, f = 1 MHz, R = 50 Ω, Differential G = +10, f = 1 MHz, R = 50 Ω, Differential L L –30 –30 –40 –40 (0,0) –50 –50 (0,1) –60 –60 (0,0) (1,0) (0,1) –70 –70 (1,0) PWDN1, PWDN0 = (1,1) –80 –80 PWDN1, PWDN0 = (1,1) –90 –90 05 10 15 20 05 10 15 20 DIFFERENTIAL OUTPUT (V p-p) DIFFERENTIAL OUTPUT (V p-p) Figure 19. Distortion vs. Output Voltage; Second Harmonic, VS = ±6 V, Figure 22. Distortion vs. Output Voltage, Third Harmonic, VS = ±6 V, G = +10, G = +10, f = 1 MHz, RL = 50 Ω, Differential f = 1 MHz, RL = 50 Ω, Differential –30 3 –35 0 –40 –3 (1,1) –45 –6 (1,0) –9 –50 (0,0) –55 –12 (0,1) (0,1) –15 –60 (1,0) –65 –18 (0,0) –21 –70 V = 40mV p-p IN –75 –24 G = +5 PWDN1, PWDN0 = (1,1) R = 100Ω L –80 –27 0100 200 300 400 500 600 15 10 10000 PEAK OUTPUT CURRENT (mA) FREQUENCY (MHz) Figure 20. Distortion vs. Peak Output Current; Third Harmonic, VS = ±6 V, Figure 23. Frequency Response; VS = ±12 V, @ PWDN1, PWDN0 Codes G = +5, RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 9 of 20 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) 01019-020 01019-021 01019-022 NORMALIZED FREQUENCY RESPONSE (dB) DISTORTION (dBc) DISTORTION (dBc) 01019-023 01019-024 01019-025 AD8016 Data Sheet 11 11 G = +5 G = +5 R = 100Ω R = 100Ω L L 8 8 R = 499Ω R = 499Ω F F 5 5 2 2 –1 –1 –4 –4 –7 –7 –10 –10 –13 –13 –16 –16 –19 –19 1 10 100 500 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. Output Voltage vs. Frequency; V = ±12 V Figure 27. Output Voltage vs. Frequency; V = ±6 V S S 20 –10 V = 2V rms R = 499Ω IN F R = 602Ω F 10 –20 (1,1) 0 (1,0) –30 –10 +PSRR –40 –20 –30 –50 (0,1) –PSRR –40 –60 (0,0) –50 –70 –60 –80 –70 –80 –90 0.01 0.1 1 10 100 500 0.03 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 25. CMRR vs. Frequency; VS = ±12 V @ PWDN1, PWDN0 Codes Figure 28. PSRR vs. Frequency; VS = ±12 V 6 180 90 3 160 80 0 140 70 (1,1) –3 120 60 –6 100 50 (1,0) –9 80 40 –12 (0,1) 60 30 +I –15 NOISE 40 20 –18 (0,0) V IN NOISE V = 40mV p-p 20 10 IN –21 G = +5 R = 100Ω L –24 0 0 1 10 100 500 10 100 1k 10k 100k 1M 10M FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Noise vs. Frequency Figure 26. Frequency Response; VS = ±6 V, @ PWDN1, PWDN0 Codes Rev. C | Page 10 of 20 CMRR (dB) OUTPUT VOLTAGE (dBV) NORMALIZED FREQUENCY RESPONSE (dB) 01019-028 01019-027 01019-026 + INPUT CURRENT NOISE (pA/ Hz) PSRR (dB) OUTPUT VOLTAGE (dBV) INPUT VOLTAGE NOISE (nV/ Hz) 01019-030 01019-029 01019-031 Data Sheet AD8016 G = +2 G = +2 R = 1kΩ R = 1kΩ F F V = 2V V = 2V OUT STEP OUT STEP R = 100Ω R = 100Ω L L +2mV (–0.1%) +2mV (–0.1%) 0 0 –2mV V IN (–0.1%) –2mV V V – V (–0.1%) V OUT IN OUT IN V OUT V – V OUT IN –5 0 5 10 15 20 25 30 35 40 45 –5 0 5 10 15 20 25 30 35 40 45 TIME (ns) TIME (ns) Figure 30. Settling Time 0.1%; V = ±12 V Figure 33. Settling Time 0.1%; V = ±6 V S S 1000 –20 V = 2V p-p OUT R = 499Ω F G = +5 –30 R = 100Ω L 100 –40 (0,0) (0,1) 10 –50 (1,0) –60 1 (1,1) –70 0.1 –80 0.01 –90 0.03 0.1 1 10 100 500 0.03 0.1 1 10 100 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 31. Output Crosstalk vs. Frequency Figure 34. Output Impedance vs. Frequency @ PWDN1, PWDN0 Codes 1M 360 V = 2V/DIV IN V = 5V/DIV OUT 100k 320 V OUT 10k 280 PHASE 1k 240 100 200 0V TRANSIMPEDANCE V IN 10 160 1 120 0.1 80 0V 0.01 40 0.001 0 –100 0 100 200 300 400 500 600 700 800 900 0.0001 0.001 0.01 0.1 1 10 100 1k 10k TIME (ns) FREQUENCY (MHz) Figure 32. Open-Loop Transimpedance and Phase vs. Frequency Figure 35. Positive Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω Rev. C | Page 11 of 20 TRANSIMPEDANCE (kΩ) OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV)) CROSSTALK (dB) PHASE (Degrees) 01019-033 01019-032 01019-034 OUTPUT VOLTAGE ERROR (2mV/DIV (0.1%/DIV)) OUTPUT IMPEDANCE (Ω) 01019-037 01019-036 01019-035 AD8016 Data Sheet 18 V = 2V/DIV IN V = 5V/DIV OUT 16 PWDN1, PWDN0 = (1,1) 14 0V V OUT 12 (1,0) 10 (0,1) 8 0V (0,0) V IN 6 4 2 –100 0 100 200 300 400 500 600 700 800 900 0 0 50 100 150 200 TIME (ns) I (µA) BIAS Figure 36. Negative Overdrive Recovery; VS = ±12 V, G = +5, RL = 100 Ω Figure 38. IQ vs. IBIAS Current; VS = ±6 V 25 12 +V , V = ±12V OUT S PWDN1, PWDN0 = (1,1) 8 20 +V , V = ±6V OUT S 4 15 (1,0) 0 (0,1) 10 –4 (0,0) –V , V = ±6V OUT S 5 –8 –V , V = ±12V OUT S 0 –12 0 50 100 150 200 10 100 1k 10k I (µA) BIAS R (Ω) LOAD Figure 37. IQ vs. IBIAS Current; VS = ±12 V Figure 39. Output Voltage vs. RLOAD Rev. C | Page 12 of 20 I (mA) Q 01019-038 01019-039 OUTPUT SWING (V) I (mA) Q 01019-041 01019-040 Data Sheet AD8016 TEST CIRCUTS 10µF +V S + 0.1µF 124Ω 499Ω +V IN V OUT +V O 49.9Ω R L 499Ω V 111Ω R IN 499Ω L 49.9Ω +V S + –V O 0.1µF 10µF 0.1µF –V IN 49.9Ω 10µF + 0.1µF 10µF + –V S –V S Figure 40. Single-Ended Test Circuit; G = +5 Figure 41. Differential Test Circuit; G = +10 Rev. C | Page 13 of 20 01019-006 01019-007 AD8016 Data Sheet THEORY OF OPERATION The AD8016 is a current feedback amplifier with high POWER SUPPLY AND DECOUPLING (500 mA) output current capability. With a current feedback The AD8016 should be powered with a good quality (that is, amplifier, the current into the inverting input is the feedback low noise) dual supply of ±12 V for the best distortion and signal and the open-loop behavior is that of a transimpedance, multitone power ratio (MTPR) performance. Careful attention dV /dI or T . The open-loop transimpedance is analogous OUT IN Z must be paid to decoupling the power supply pins. A 10 μF to the open-loop voltage gain of a voltage feedback amplifier. capacitor located in near proximity to the AD8016 is required Figure 42 shows a simplified model of a current feedback ampli- to provide good decoupling for lower frequency signals. In fier. Because RIN is proportional to 1/gm, the equivalent voltage addition, 0.1 μF decoupling capacitors should be located as gain is just TZ × gm, where gm is the transconductance of the close to each of the four power supply pins as is physically input stage. Basic analysis of the follower with gain circuit yields possible. All ground pins should be connected to a common T (S) low impedance ground plane. V Z OUT =G× V T (S)+G×R +R IN Z IN F FEEDBACK RESISTOR SELECTION where: In current feedback amplifiers, selection of feedback and gain resistors has an impact on the MTPR performance, bandwidth, R F G= 1+ and gain flatness. Take care in selecting these resistors so that R G optimum performance is achieved. Table 6 below shows the 1 recommended resistor values for use in a variety of gain R = ≈ 25Ω IN g settings. These values are suggested as a good starting point m when designing for any application. Recognizing that G × RIN << RF for low gains, the familiar result of constant bandwidth with gain for current feedback amplifiers Table 6. Resistor Selection Guide is evident, the 3 dB point being set when |TZ| = RF. Of course, Gain RF (Ω) RG (Ω) for a real amplifier there are additional poles that contribute +1 1000 ∞ excess phase and there is a value for R below which the ampli- F −1 500 500 fier is unstable. Tolerance for peaking and desired flatness +2 650 650 determines the optimum R in each application. F +5 750 187 +10 1000 111 R F R G – BIAS PIN AND PWDN FEATURES R IN + I IN T V The AD8016 is designed to cover both central office (CO) Z OUT R and customer premise equipment (CPE) ends of an xDSL N + application. It offers full versatility in setting quiescent bias V IN levels for the particular application from full on to reduced bias (in three steps) to full off (via BIAS pin). This versatility Figure 42. Simplified Block Diagram gives the modem designer the flexibility to maximize efficiency The AD8016 is the first current feedback amplifier capable of while maintaining reasonable levels of MTPR performance. delivering 400 mA of output current while swinging to within Optimizing driver efficiency while delivering the required DMT 2 V of either power supply rail. This enables full CO ADSL power is accomplished with the AD8016 through the use of on- performance on only 12 V rails, an immediate 20% power chip power management features. Two digitally programmable saving. The AD8016 is also unique in that it has a power logic pins, PWDN1 and PWDN0, may be used to select four management system included on-chip. It features four user different bias levels: 100%, 60%, 40%, and 25% of full quiescent programmable power levels (all of which provide a low output power (see Table 7). impedance of the driver), as well as the provision for complete Table 7. PWDN Code Selection Guide shutdown (high impedance state). Also featured is a thermal PWDN1 PWDN0 shutdown with alarm signal. Code Code Quiescent Bias Level 1 1 100% (full on) 1 0 60% 0 1 40% 0 0 25% (low ZOUT but not off) X X Full off (high ZOUT via 250 μA pulled out of BIAS pin) Rev. C | Page 14 of 20 01019-042 Data Sheet AD8016 The bias level can be controlled with TTL logic levels (high = 1) THERMAL SHUTDOWN applied to the PWDN1 and PWDN0 pins alone or in combina- The AD8016 ARB is designed to incorporate shutdown tion with the BIAS control pin. The DGND or digital ground protection against accidental thermal overload. In the event pin is the logic ground reference for the PWDN1 and PWDN0 of thermal overload, the AD8016 was designed to shut down pins. In typical ADSL applications where ±12 V or ±6 V at a junction temperature of 165°C and return to normal supplies (also single supplies) are used, the DGND pin is operation at a junction temperature 140°C. The AD8016 connected to analog ground. continues to operate, cycling on and off, as long as the thermal The BIAS control pin by itself is a means to continuously adjust overload condition remains. The frequency of the protection the AD8016 internal biasing and, thus, quiescent current I . By Q cycle depends on the ambient environment, severity of the pulling out a current of 0 μA (or open) to approximately200 μA, thermal overload condition, the power being dissipated, and the quiescent current can be adjusted from 100% (full on) to a the thermal mass of the PCB beneath the AD8016. When the full off condition. The full off condition yields a high output AD8016 begins to cycle due to thermal stress, the internal impedance. Because of an on-chip resistor variation of up to shutdown circuitry draws current out of the node connected ±20%, the actual amount of current required to fully shut down in common with the BIAS pin, while the voltage at the BIAS the AD8016 can vary. To institute a full chip shutdown, a pull- pin goes to the negative rail. When the junction temperature down current of 250 μA is recommended. See Figure 43 for the returns to 140°C, current is no longer drawn from this node, logic drive circuit for complete amplifier shutdown. Figure 37 and the BIAS pin voltage returns to the positive rail. Under and Figure 38 show the relationship between current pulled out these circumstances, the BIAS pin can be used to trip an alarm of the BIAS pin (I BIAS) and the supply current (IQ). A typical indicating the presence of a thermal overload condition. shutdown IQ is less than 1 mA total. Alternatively, an external Figure 44 also shows three circuits for converting this signal to pull-down resistor to ground or a current sink attached to the a standard logic level. BIAS pin can be used to set IQ to lower levels (see Figure 44). V CC AD8016 The BIAS pin may be used in combination with the PWDN1 200µA V = V –0.2V and PWDN0 pins; however, diminished MTPR performance CC 10kΩ may result when I is lowered too much. Current pulled away Q BIAS SHUT- OR 0µA – 200µA DOWN from the BIAS pin shunts away a portion of the internal bias BIAS current. Setting PWDN1 or PWDN0 to Logic 0 also shunts V EE PWDN0 PWDN1 away a portion of the internal bias current. The reduction of 5V quiescent bias levels due to the use of PWDN1 and PWDN0 is V CC 10kΩ consistent with the percentages established in Table 7. When 5V ALARM 10kΩ 1MΩ PWDN0 alone is set to Logic 0, and no other means of reducing BIAS ALARM OR BIAS MINβ 350 100kΩ the internal bias currents is used, full-rate ADSL signals may be 1/4 HCF 40109B driven while maintaining reasonable levels of MTPR. SGS–THOMSON 3.3V LOGIC R1* Figure 44. Shutdown and Alarm Circuit R2 BIAS 50kΩ 2N3904 *R1 = 47kΩ FOR ±12V OR +12V , S S R1 = 22kΩ FOR ±6V . S Figure 43. Logic Drive of BIAS Pin for Complete Amplifier Shutdown Rev. C | Page 15 of 20 01019-043 01019-044 AD8016 Data Sheet APPLICATIONS INFORMATION See Figure 6 for a sample of the ADSL downstream spectrum The AD8016 dual amplifier forms an integrated single-channel ADSL line driver. The AD8016 may be applied in driving mod- showing MTPR results while driving 20.4 dBm of power onto ulated signals including discrete multitone (DMT) in either a 100 Ω line. Measurements of MTPR are typically made at direction; upstream from CPE to the CO and downstream the output (line side) of ADSL hybrid circuits. MTPR can be from CO to CPE. The most significant thermal management affected by the components contained in the hybrid circuit, challenge lies in driving downstream information from CO sites including the quality of the capacitor dielectrics, voltage ratings, to the CPE. Driving xDSL information downstream suggests and the turns ratio of the selected transformers. Other compo- nents aside, an ADSL driver hybrid containing the AD8016 can the need to locate many xDSL modems in a single CO site. The implication is that several modems will be placed onto a single be optimized for the best MTPR performance by selecting the printed circuit board residing in a card cage located in a variety turns ratio of the transformers. The voltage and current demands of ambient conditions. Environmental conditioners such as fans from the differential driver changes, depending on the trans- or air conditioning may or may not be available, depending on former turns ratio. The point on the curve indicating maximum the density of modems and the facilities contained at the CO dynamic headroom is achieved when the differential driver site. To achieve long-term reliability and consistent modem delivers both the maximum voltage and current while maintaining performance, designers of CO solutions must consider the wide the lowest possible distortion. Below this point, the driver has array of ambient conditions that exist within various CO sites. reserve current-driving capability and experiences voltage clipping. Above this point, the amplifier runs out of current MULTITONE POWER RATIO (MTPR) drive capability before the maximum voltage drive capability ADSL systems rely on discrete multitone modulation to carry is reached. Because a transformer reflects the secondary load digital data over phone lines. DMT modulation appears in the impedance back to the primary side by the square of the turns frequency domain as power contained in several individual ratio, varying the turns ratio changes the load across the frequency subbands, sometimes referred to as tones or bins, differential driver. The following equation may be used to each of which is uniformly separated in frequency. (See Figure 6 calculate the load impedance across the output of the differen- for an example of downstream DMT signals used in evaluating tial driver, reflected by the transformers, from the line side of MTPR performance.) A uniquely encoded, quadrature ampli- the xDSL driver hybrid. tude modulation (QAM) signal occurs at the center frequency Z 2 of each subband or tone. Difficulties arise when decoding these Z′≡ 2 (2×N) subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands, regardless of whether the where: corruption comes from an adjacent subband or harmonics of Z' is the primary side impedance as seen by the differential other subbands. Conventional methods of expressing the output driver. signal integrity of line drivers, such as spurious-free dynamic Z is the line impedance. 2 range (SFDR), single-tone harmonic distortion or THD, two- N is the transformer turns ratio. tone intermodulation distortion (IMD), and third-order inter- Figure 45 shows the dynamic headroom in each subband of a cept (IP3) become significantly less meaningful when amplifiers downstream DMT waveform vs. turns ratio running at 100% are required to drive DMT and other heavily modulated and 60% of the quiescent power while maintaining −65 dBc waveforms. A typical xDSL downstream DMT signal may of MTPR at VS = ±12 V. contain as many as 256 carriers (subbands or tones) of QAM 4 signals. MTPR is the relative difference between the measured V = ±12V S PWDN1, PWDN0 = (1,1) power in a typical subband (at one tone or carrier) vs. the power 3 at another subband specifically selected to contain no QAM V = ±11.4V S data. In other words, a selected subband (or tone) remains PWDN1, PWDN0 = (1,1) 2 open or void of intentional power (without a QAM signal), V = ±12V S yielding an empty frequency bin. MTPR, sometimes referred PWDN1, PWDN0 = (1,0) 1 to as the empty bin test, is typically expressed in dBc, similar to expressing the relative difference between single-tone 0 fundamentals and second or third harmonic distortion V = ±11.4V S PWDN1, PWDN0 = (1,0) components. –1 –2 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 DOWNSTREAM TURNS RATIO Figure 45. Dynamic Headroom vs. XFMR Turns Ratio, V = ±12 V S Rev. C | Page 16 of 20 DYNAMIC HEADROOM (dB) 01019-045 Data Sheet AD8016 Once an optimum turns ratio is determined, the amplifier has The situation is more complicated with a complex modulated an MTPR performance for each setting of the power-down signal. In the case of a DMT signal, taking the equivalent sine pins. Table 8 demonstrates the effects of reducing the total wave power overestimates the power dissipation by ~23%. For power dissipated by using the PWDN pins on MTPR perfor- example: mance when driving 20.4 dBm downstream onto the line with POUT = 23.4 dBm = 220 mW a transformer turns ratio of 1:1.4. VOUT @ 50 Ω = 3.31 V rms Table 8. Dynamic Power Dissipation of Downstream V = 2.354 V OUT Transmission at each amplifier output, which yields a P of 1.81 W. D PWDN1 PWDN0 PD (W) MTPR Through measurement, a DMT signal of 23.4 dBm requires 1 1 1.454 −78 dBc 1.47 W of power to be dissipated by the AD8016. Figure 46 1 0 1.262 −75.3 dBc shows the results of calculation and actual measurements 0 1 1.142 −57.2 dBc 1 detailing the relationship between the power dissipated by 0 0 0.120 N/A the AD8016 vs. the total output power delivered to the back 1 This mode is quiescent power dissipation. termination resistors and the load combined. A 1:2 transformer GENERATING DMT turns ratio was used in the calculations and measurements. 2.5 At this time, DMT modulated waveforms are not typically menu selectable items contained within arbitrary waveform generators. Even using AWG software to generate DMT signals, 2.0 CALCULATED AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limita- 1.5 tions in the DAC and output drivers used by AWG manufacturers. MEASURED SINE Similar to evaluating single-tone distortion performance of an MEASURED amplifier, MTPR evaluation requires a DMT signal generator 1.0 DMT capable of delivering MTPR performance better than that of the driver under evaluation. 0.5 POWER DISSIPATION To properly size the heat sinking area for the user’s application, 0 0 100 200 300 it is important to consider the total power dissipation of the OUTPUT POWER (mW) AD8016. The dc power dissipation for VIN = 0 V is IQ (VCC − Figure 46. Power Dissipation vs. Output Power (Including Back Terminations), See Figure 9 for Test Circuit VEE), or 2 × IQ × VS. For the AD8016 powered on +12 V and −12 V supplies (±VS), the number is 0.6 W. In a differential driver circuit (Figure 41), one can use symmetry to simplify the computation for a dc input signal. V OUT P = 2×I ×V + 4× (V −V ) D Q S S OUT R L where: VOUT is the peak output voltage of an amplifier. This formula is slightly pessimistic due to the fact that some of the quiescent supply current is commutated during sourcing or sinking current into the load. For a sine wave source, integra- tion over a half cycle yields 2   4V V V OUT S OUT   P = 2×I ×V + 2 − D Q S   π R R L L   Rev. C | Page 17 of 20 POWER DISSIPATION 01019-046 AD8016 Data Sheet THERMAL ENHANCEMENTS AND PCB LAYOUT AIR FLOW TEST CONDITIONS DUT Power There are several ways to enhance the thermal capacity of the CO solution. Additional thermal capacity can be created using A typical DSL DMT signal produces about 1.5 W of power enhanced PCB layout techniques such as interlacing (some- dissipation in the AD8016 package. The fully biased (PWDN0 times referred to as stitching or interconnection) of the layers and PWDN1 = Logic 1) quiescent current of the AD8016 is immediately beneath the line driver. This technique serves to ~25 mA. A 1 MHz differential sine wave at an amplitude of increase the thermal mass or capacity of the PCB immediately 8 V p-p/amplifier into an RLOAD of 100 Ω differential (50 Ω beneath the driver. The AD8016 in a TSSOP_EP (ARE model) per side) produces the 1.5 W of power typical in the AD8016 package can be designed to operate in the CO solution using device. (See the Power Dissipation section for details.) prudent measures to manage the power dissipation through Thermal Resistance careful PCB design. The ARE package is available for use in The junction-to-case thermal resistance (θ ) of the AD8016 JC designing the highest density CO solutions. Maximum heat ARB or SOIC_W_BAT package is 8.6°C/W and for the AD8016 transfer to the PCB can be accomplished using the ARE ARE or TSSOP_EP it is 5.6°C/W. These package specifications package when the thermal slug is soldered to an exposed were used in this study to determine junction temperature copper pad directly beneath the AD8016. Optimum thermal based on the measured case temperature. performance can be achieved in the ARE package only when the back of the package is soldered to a PCB designed for PCB Dimensions of a Differential Driver Circuit maximum thermal capacity (see Figure 48). Thermal experi- Several components are required to support the AD8016 in a ments with the ARE package were conducted without soldering differential driver circuit. The PCB area necessary for these the heat slug to the PCB. Heat transfer was through physical components (that is, feedback and gain resistors, ac-coupling contact only. The following offers some insight into the AD8016 and decoupling capacitors, termination and load resistors) power dissipation and relative junction temperature, as well as dictated the area of the smallest PCB in this study, 4.7 square the effects of PCB size and composition on the junction-to-air inches. Further reduction in PCB area, although possible, has thermal resistance or θJA. consequences in terms of the maximum operating junction temperature method of thermal enhancement.) A cooling fan THERMAL TESTING that draws moving air over the PCB and xDSL drivers, while A wind tunnel study was conducted to determine the relation- not always required, may be useful in reducing the operating ship between thermal capacity (that is, printed circuit board temperature. copper area), air flow, and junction temperature. Junction-to- ambient thermal resistance, θJA, was also calculated for the AD8016 ARE and AD8016 ARB packages. The AD8016 was operated in a noninverting differential driver configuration, typical of an xDSL application yet isolated from any other modem components. Testing was conducted using a 1 oz. copper board in an ambient temperature of ~24°C over air flows of 200, 150, 100, and 50 linear feet per minute (LFM) (0.200 and 400 for AD8016 ARE) and for the ARB packages as well as in still air. The 4-layer PCB was designed to maximize the area of copper on the outer two layers of the board, while the inner layers were used to configure the AD8016 in a differential driver circuit. The PCB measured 3 inches × 4 inches in the beginning of the study and was progressively reduced in size to approximately 2 inches × 2 inches. The testing was performed in a wind tunnel to control airflow in units of LFM. The tunnel is approximately 11 inches in diameter. Rev. C | Page 18 of 20 Data Sheet AD8016 35 EXPERIMENTAL RESULTS ARB 0 LFM The experimental data suggests that for both packages, and ARB 50 LFM 30 a PCB as small as 4.7 square inches, reasonable junction ARB 100 LFM temperatures can be maintained even in the absence of air flow. The graph in Figure 47 shows junction temperature vs. 25 airflow for various dimensions of 1 oz. copper PCBs at an ARB 150 LFM ARB 200 LFM ambient temperature of 24°C in the ARB package. For the 20 worst-case package, the AD8016 ARB and the worst-case PCB at 4.7 square inches, the extrapolated junction temperature 15 for an ambient environment of 85°C would be approximately 132°C with 0 LFM of airflow. If the target maximum junction temperature of the AD8016 ARB is 125°C, a 4-layer PCB with 10 4 7 10 1 oz. copper covering the outer layers and measuring 9 square PCB AREA (SQ-IN) inches is required with 0 LFM of air flow. Figure 48. Junction-to-Ambient Thermal Resistance vs. PCB Area Note that the AD8016 ARE is targeted at xDSL applications 50 other than full-rate CO ADSL. The AD8016 ARE is targeted 45 at g.lite and other xDSL applications where reduced power dissipation can be achieved through a reduction in output 40 power. Extreme temperatures associated with full-rate ADSL 35 ARE 0 LFM using the AD8016 ARE should be avoided whenever possible. 30 75 ARE 200 LFM +24°C AMBIENT ARB 4.7 SQ-IN 25 ARB 6 SQ-IN 70 ARE 400 LFM 20 65 15 ARB 7.125 SQ-IN 60 ARB 9 SQ-IN 10 0 1 23 45 67 89 10 55 PCB AREA (SQ-IN) Figure 49. Junction-to-Ambient Thermal Resistance vs. PCB Area 50 45 40 0 50 100 150 200 AIR FLOW (LFM) Figure 47. Junction Temperature vs. Air Flow Rev. C | Page 19 of 20 JUNCTION TEMPERATURE (°C) 01019-047 θ (°C/W) JA θ (°C/W) JA 01019-048 01019-049 AD8016 Data Sheet OUTLINE DIMENSIONS 15.60 15.20 24 13 7.60 7.40 10.65 1 10.00 12 PIN 1 0.75  45° 2.65 0.25 2.35 8° 0.30 0.32 1.27 0.51 0° 1.27 0.10 SEATING 0.23 BSC 0.33 0.40 PLANE COMPLIANT WITH JEDEC STANDARDS MS-013-AD Figure 50. 24-Lead Batwing SOIC, Thermally Enhanced w/Fused Leads [SOIC_W_BAT] (RB-24) Dimensions shown in millimeters 9.80 3.55 9.70 3.50 9.60 3.45 28 15 3.05 4.50 EXPOSED 6.40 PAD 3.00 4.40 BSC (Pins Up) 2.95 4.30 1 14 TOP VIEW BOTTOM VIEW 1.05 1.20 MAX 1.00 8° FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0° THE PIN CONFIGURATION AND 0.20 0.15 FUNCTION DESCRIPTIONS 0.65 BSC 0.30 0.75 SEATING 0.09 0.05 SECTION OF THIS DATA SHEET. 0.19 PLANE 0.60 COPLANARITY 0.45 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AET Figure 51. 28-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP] (RE-28-1) Dimensions shown in millimeters ORDERING GUIDE 1 Model Temperature Range Package Description Package Option AD8016ARBZ −40°C to +85°C 24-Lead SOIC_W_BAT RB-24 AD8016ARBZ-REEL −40°C to +85°C 24-Lead SOIC_W_BAT RB-24 AD8016AREZ −40°C to +85°C 28-Lead TSSOP_EP RE-28-1 AD8016AREZ-REEL −40°C to +85°C 28-Lead TSSOP_EP RE-28-1 AD8016AREZ-REEL7 −40°C to +85°C 28-Lead TSSOP_EP RE-28-1 1 Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01019-0-3/12(C) Rev. C | Page 20 of 20 02-23-2012-A