ANALOG DEVICES AD8011

300 MHz Current Feedback Amplifier AD8011 FEATURES FUNCTIONAL BLOCK DIAGRAM Easy to Use 8-Lead PDIP and SOIC Low Power 1 mA Power Supply Current (5 mW on 5 V ) S High Speed and Fast Settling on 5 V NC 1 8 NC 300 MHz, –3 dB Bandwidth (G = +1) V+ –IN 2 7 180 MHz, –3 dB Bandwidth (G = +2) +IN 3 6 OUT 2000 V/�s Slew Rate 29 ns Settling Time to 0.1% 4 5 NC V– AD8011 Good Video Specifications (R = 1 k�, G = +2) L Gain Flatness 0.1 dB to 25 MHz NC = NO CONNECT 0.02% Differential Gain Error 0.06� Differential Phase Error PRODUCT DESCRIPTION Low Distortion The AD8011 is a very low power, high speed amplifier designed –70 dBc Worst Harmonic @ 5 MHz to operate on +5 V or ±5 V supplies. With wide bandwidth, –62 dBc Worst Harmonic @ 20 MHz low distortion, and low power, this device is ideal as a general- Single Supply Operation purpose amplifier. It also can be used to replace high speed Fully Specified for 5 V Supply amplifiers consuming more power. The AD8011 is a current feed- back amplifier and features gain flatness of 0.1 dB to 25 MHz APPLICATIONS while offering differential gain and phase error of 0.02% and 0.06° Power Sensitive, High Speed Systems on a single 5 V supply. This makes the AD8011 ideal for profes- Video Switchers sional video electronics such as cameras, video switchers, or any Distribution Amplifiers high speed portable equipment. Additionally, the AD8011’s low A-to-D Driver distortion and fast settling make it ideal for buffering high speed Professional Cameras 8-, 10-, and 12-bit A-to-D converters. CCD Imaging Systems Ultrasound Equipment (Multichannel) The AD8011 offers very low power of 1 mA maximum and can run on single 5 V to 12 V supplies. All this is offered in a small 8-lead PDIP or 8-lead SOIC package. These features fit well with 5 portable and battery-powered applications where size and power G = +2 are critical. 4 R = 1k� F V = +5V OR �5V S The AD8011 is available in the industrial temperature range of 3 V = 200mV p-p OUT –40°C to +85°C. 2 1 –40 0 G = +2 THIRD –1 R = 150� L –2 –3 –60 SECOND R = 150� L –4 –5 1 10 100 500 FREQUENCY (MHz) THIRD –80 R =1k� L Figure 1. Frequency Response; G = +2, V = +5 V, or ±5 V S SECOND R = 1k� L –100 10 20 FREQUENCY (MHz) REV. C Figure 2. Distortion vs. Frequency; V = ±5 V S Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. NORMALIZED GAIN (dB) DISTORTION (dBc) AD8011–SPECIFICATIONS DUAL SUPPLY (@ T = 25�C, V = �5 V, G = +2, R = 1 k�, R = 1 k�, unless otherwise noted.) A S F L AD8011A Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, V < 1 V p-p G = +1 340 400 MHz O –3 dB Small Signal Bandwidth, V < 1 V p-p G = +2 180 210 MHz O –3 dB Large Signal Bandwidth, V = 5 V p-p G = +10, R = 500 Ω 57 MHz O F Bandwidth for 0.1 dB Flatness G = +2 20 25 MHz Slew Rate G = +2, V = 4 V Step 3500 V/µs O G = –1, V = 4 V Step 1100 V/µs O Settling Time to 0.1% G = +2, V = 2 V Step 25 ns O Rise and Fall Time G = +2, V = 2 V Step 0.4 ns O G = –1, V = 2 V Step 3.7 ns O NOISE/HARMONIC PERFORMANCE Second Harmonic f = 5 MHz, V = 2 V p-p, G = +2 C O R = 1 kΩ –75 dB L R = 150 Ω –67 dB L Third Harmonic R = 1 kΩ –70 dB L R = 150 Ω –54 dB L Input Voltage Noise f = 10 kHz 2 nV/√Hz Input Current Noise f = 10 kHz, +In 5 pA/√Hz –In 5 pA/√Hz Differential Gain Error NTSC, G = +2, R = 1 kΩ 0.02 % L R = 150 Ω 0.02 % L Differential Phase Error NTSC, G = +2, R = 1 kΩ 0.06 Degrees L R = 150 Ω 0.3 Degrees L DC PERFORMANCE Input Offset Voltage 25 ±mV T –T 26 ±mV MIN MAX Offset Drift 10 µV/°C –Input Bias Current 515 ±µA T –T 20 ±µA MIN MAX +Input Bias Current 515 ±µA T –T 20 ±µA MIN MAX Open-Loop Transresistance 800 1300 kΩ T –T 550 kΩ MIN MAX INPUT CHARACTERISTICS Input Resistance +Input 450 kΩ Input Capacitance +Input 2.3 pF Input Common-Mode Voltage Range 3.8 4.1 ±V Common-Mode Rejection Ratio Offset Voltage V = ±2.5 V –52 –57 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing 3.9 4.1 ±V Output Resistance 0.1 0.3 Ω Output Current T –T 15 30 mA MIN MAX Short-Circuit Current 60 mA POWER SUPPLY Operating Range ±1.5 ±6.0 V Quiescent Current T –T 1.0 1.3 mA MIN MAX Power Supply Rejection Ratio V = ±5 V ± 1 V 55 58 dB S Specifications subject to change without notice. –2– REV. C AD8011 (@ T = 25�C, V = 5 V, G = +2, R = 1 k�, V = 2.5 V, R = 1 k�, unless otherwise noted.) SINGLE SUPPLY A S F CM L AD8011A Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +1 270 328 MHz O –3 dB Small Signal Bandwidth, V < 0.5 V p-p G = +2 150 180 MHz O –3 dB Large Signal Bandwidth, V = 2.5 V p-p G = +10, R = 500 Ω 57 MHz O F Bandwidth for 0.1 dB Flatness G = +2 15 20 MHz Slew Rate G = +2, V = 2 V Step 2000 V/µs O G = –1, V = 2 V Step 500 V/µs O Settling Time to 0.1% G = +2, V = 2 V Step 29 ns O Rise and Fall Time G = +2, V = 2 V Step 0.6 ns O G = –1, V = 2 V Step 4 ns O NOISE/HARMONIC PERFORMANCE Second Harmonic f = 5 MHz, V = 2 V p-p, G = +2 C O R = 1 kΩ –84 dB L R = 150 Ω –67 dB L Third Harmonic R = 1 kΩ –76 dB L R = 150 Ω –54 dB L Input Voltage Noise f = 10 kHz 2 nV/√Hz Input Current Noise f = 10 kHz, +In 5 pA/√Hz –In 5 pA/√Hz Differential Gain Error NTSC, G = +2, R = 1 kΩ 0.02 % L R = 150 Ω 0.6 % L Differential Phase Error NTSC, G = +2, R = 1 kΩ 0.06 Degrees L R = 150 Ω 0.8 Degrees L DC PERFORMANCE Input Offset Voltage 25 mV T –T 26 mV MIN MAX Offset Drift 10 µV/°C –Input Bias Current 515 ±µA T –T 20 ±µA MIN MAX +Input Bias Current 515 ±µA T –T 20 ±µA MIN MAX Open-Loop Transresistance 800 1300 kΩ T –T 550 kΩ MIN MAX INPUT CHARACTERISTICS Input Resistance +Input 450 kΩ Input Capacitance +Input 2.3 pF Input Common-Mode Voltage Range 1.5 to 3.5 1.2 to 3.8 V Common-Mode Rejection Ratio Offset Voltage V = 1.5 V to 3.5 V –52 –57 dB CM OUTPUT CHARACTERISTICS Output Voltage Swing 1.2 to 3.8 0.9 to 4.1 +V Output Resistance 0.1 0.3 Ω Output Current T –T 15 30 mA MIN MAX Short-Circuit Current 50 mA POWER SUPPLY Operating Range +3 +12 V Quiescent Current T –T 0.8 1.15 mA MIN MAX Power Supply Rejection Ratio ∆V = ±1 V 55 58 dB S Specifications subject to change without notice. REV. C –3– AD8011 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V The maximum power that can be safely dissipated by the AD8011 2 Internal Power Dissipation is limited by the associated rise in junction temperature. The Plastic DIP Package (N) . . . . . . . Observe Derating Curves maximum safe junction temperature for plastic encapsulated Small Outline Package (R) . . . . . . Observe Derating Curves devices is determined by the glass transition temperature of the Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V S plastic, approximately 150°C. Exceeding this limit temporarily Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±2.5 V may cause a shift in parametric performance due to a change in Output Short-Circuit Duration the stresses exerted on the die by the package. Exceeding a . . . . . . . . . . . . . . . . . .Observe Power Derating Curves junction temperature of 175°C for an extended period can result Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C in device failure. Operating Temperature Range (A Grade) . . . –40°C to +85°C While the AD8011 is internally short-circuit protected, this may Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C not be sufficient to guarantee that the maximum junction tem- NOTES perature is not exceeded under all conditions. To ensure proper 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- operation, it is necessary to observe the maximum power derating nent damage to the device. This is a stress rating only; functional operation of the curves (shown in Figure 3). device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating 1k� 1k� conditions for extended periods may affect device reliability. V 2 OUT Specification is for device in free air: R L 8-Lead PDIP Package: � = 90°C/W 1k� JA 8-Lead SOIC Package: � = 155°C/W JA V IN +V S 50� 0.01�F 10�F 2.0 T = 150�C 0.01�F 10�F J –V S 8-LEAD PLASTIC DIP PACKAGE Figure 4. Test Circuit; Gain = +2 1.5 1k� 1k� V IN V OUT 1.0 R L 52.3� 1k� 8-LEAD SOIC PACKAGE +V S 0.5 0.01�F 10�F 0.01�F 10�F –V S 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Figure 5. Test Circuit; Gain = –1 AMBIENT TEMPERATURE (�C) Figure 3. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Temperature Package Package Model Range Description Option AD8011AN –40°C to +85°C8-Lead PDIP N-8 AD8011AR –40°C to +85°C 8-Lead SOIC R-8 AD8011AR-REEL –40°C to +85°C 13" Tape and Reel R-8 AD8011AR-REEL7 –40°C to +85°C 7" Tape and Reel R-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8011 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. C MAXIMUM POWER DISSIPATION (W) Typical Performance Characteristics–AD8011 5ns 5ns 20mV 20mV *TPC 1. 100 mV Step Response; G = +2, *TPC 4. 100 mV Step Response; G = –1, V = ±2.5 V or ±5 V V = ±2.5 V or ±5 V S S 4V STEP 4V STEP 2V STEP 2V STEP 800mV 10ns 800mV 10ns *TPC 2. Step Response; G = +2, V = ±2.5 V *TPC 5. Step Response; G = –1, V = ±2.5 V S S (2 V Step) and ±5 V (4 V Step) (2 V Step) and ±5 V (4 V Step) 9 6.5 G = +2 6.4 8 V = 100mV p-p IN R = 1k� L �5V 6.3 R = 1k� F V = +5V S 7 6.2 6 6.1 5 V = �5V S 6.0 4 +5V 5.9 3 5.8 2 5.7 1 5.6 5.5 0 10 100 1000 10000 1 10 100 500 LOAD RESISTANCE (�) FREQUENCY (MHz) TPC 3. Gain Flatness; G = +2 TPC 6. Output Voltage Swing vs. Load *NOTE: V = ±5 V operation is identical to V = +5 V single-supply operation. S S REV. C –5– GAIN (dB) SWING (V p-p) AD8011 –40 –40 THIRD G = +2 G = +2 R = 150� L THIRD R = 150� L –60 –60 SECOND SECOND R = 150� L R = 150� L THIRD –80 –80 THIRD R =1k� L R =1k� L SECOND SECOND R = 1k� L R =1k� L –100 –100 1 1 10 20 10 20 FREQUENCY (MHz) FREQUENCY (MHz) TPC 10. Distortion vs. Frequency; V = +5 V TPC 7. Distortion vs. Frequency; V = ±5 V S S 0.04 0.8 0.08 V = �5V 0.03 S V = +5V 0.6 0.06 S G = +2 0.02 G = +2 0.04 0.4 R = 150� 0.01 0.2 L 0.02 R =1k� L 0.00 0.0 0.00 –0.01 –0.2 –0.02 –0.02 –0.04 –0.4 R = 1k� –0.03 L R =150� –0.6 –0.06 L –0.04 –0.8 –0.08 0 IRE 100 0IRE 100 0.04 0.4 0.08 0.8 0.03 V = �5V 0.3 0.06 V = +5V 0.6 S S R = 150� 0.02 G = +2 L 0.2 G = +2 0.4 0.04 0.01 0.1 0.02 0.2 0.00 R = 1k� 0.00 L 0.00 0.0 R =150� L –0.01 –0.1 –0.2 –0.02 R =1k� L –0.02 –0.2 –0.4 –0.04 –0.03 –0.3 –0.06 –0.6 –0.04 –0.4 –0.8 –0.08 0 IRE 100 0 100 IRE TPC 8. Diff Phase and Diff Gain; V = ±5 V S TPC 11. Diff Phase and Diff Gain; V = +5 V S 3 9 1V rms 0 6 –3 3 1V rms –6 0 –9 –3 –12 –6 –15 –9 –18 –12 –21 –15 –24 –18 –27 –21 1 10 40 100 500 1 10 40 100 500 FREQUENCY (MHz) FREQUENCY (MHz) TPC 9. Large Signal Frequency Response; TPC 12. Large Signal Frequency Response; V = ±5 V, G = +2 V = +5 V, G = +2 S S –6– REV. C 1k� DIFF PHASE (Degrees) DIFF GAIN (%) OUTPUT VOLTAGE (dBV) DISTORTION (dBc) 150� DIFF PHASE (Degrees) 1k� DIFF PHASE (Degrees) 1k� DIFF GAIN (%) OUTPUT VOLTAGE (dBV) DISTORTION (dBc) 150� DIFF PHASE (Degrees) 150� DIFF GAIN (%) AD8011 5 4 G = +2 G = +1 V = +5V OR �5V S R = 1K� F R = 1k� 3 V = 200mV p-p F OUT 2V STEP 2 G = +2 1 R = 1k� F 0 –1 G = +10 R = 500� F –2 –3 –4 5ns 0.1% –5 1 10 100 500 t = 0 FREQUENCY (MHz) TPC 13. Frequency Response; G = +1, +2, +10; TPC 16. Short-Term Settling Time; V = +5 V or ±5 V S V = +5 V or ±5 V S 2 G = –10 V = +5V OR �5V S 1 R = 500� V = 200mV p-p F OUT G = +2 R = 1k� L R = 1k� F 0 2V STEP –1 G = –1 R = 1k� F –2 R = 1k� L –3 –4 –5 –6 –7 0.1% 100ns –8 1 10 100 500 FREQUENCY (MHz) t = 0 TPC 14. Frequency Response; G = –1, –10; TPC 17. Long-Term Settling Time; V = +5 V or ±5 V S V = +5 V or ±5 V S –10 10 –15 0 –PSRR V = +5V OR �5V S V = +5V OR �5V S G = +2 G = +2 –20 –10 R = 1k� F –25 –20 +PSRR –30 –30 –35 –40 –40 –50 –45 –60 –50 –70 –55 –80 –60 –90 0.1 1 10 100 100k 1M 10M 100M 500M FREQUENCY (MHz) FREQUENCY (Hz) TPC 15. CMRR vs. Frequency; V = +5 V or ±5 V TPC 18. PSRR vs. Frequency; V = +5 V or ±5 V S S REV. C –7– NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) CMRR (dB) PSRR (dB) OUTPUT VOLTAGE (0.1%/DIV) OUTPUT VOLTAGE (0.1%/DIV) AD8011 12.5 50 V = +5V OR �5V S 100 G = +2 R = 1k� F 40 10.0 10 7.5 30 1 5.0 20 0.1 10 2.5 0.01 0 0 10k 0.1M 1M 10M 100M 500M 500 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) TPC 19. Output Resistance vs. Frequency; TPC 21. Noise vs. Frequency; V = +5 V or ±5 V S V = +5 V or ±5 V S 140 0 9 R = 1k� L 8 120 –40 f = 5MHz G = +2 PHASE 7 R = 1k� F 100 –80 6 R = 150� L 80 –120 5 GAIN 4 60 –160 3 40 –200 2 20 –240 1 0 –280 0 3 4 5 6 7 8 9 10 11 1k 10k 100k 1M 10M 100M 1G TOTAL SUPPLY VOLTAGE (V) FREQUENCY (Hz) TPC 20. Transimpedance Gain and Phase vs. Frequency TPC 22. Output Swing vs. Supply –8– REV. C GAIN (dB �) OUTPUT RESISTANCE (�) PHASE (Degrees) INPUT VOLTAGE NOISE (nV/ Hz) PEAK-TO-PEAK OUTPUT AT 5MHz [ 0.5% THD] (V) INPUT CURRENT NOISE (pA/ Hz) AD8011 THEORY OF OPERATION Overall, when high external load drive and low ac distortion is a The AD8011 is a revolutionary generic high speed CF amplifier requirement, a twin gain stage integrating amplifier like the AD8011 that attains new levels of BW, power, distortion, and signal swing will provide superior results for lower power over the traditional capability. If these key parameters were combined as a figure of single-stage complementary devices. In addition, being a CF ac merit performance or [(frequency � V )/(distortion � power)], amplifier, closed-loop BW variations versus external gain variations SIG no IC amplifier today would come close to the merit value of the (varying RN) will be much lower compared to a VF op amp, where AD8011 for frequencies above a few MHz. Its wide dynamic the BW varies inversely with gain. Another key attribute of this performance (including noise) is the result of both a new com- amplifier is its ability to run on a single 5 V supply due in part to plementary high speed bipolar process and a new and unique its wide common-mode input and output voltage range capability. architectural design. The AD8011 uses basically a two gain stage For 5 V supply operation, the device obviously consumes half complementary design approach versus the traditional “single the quiescent power (versus 10 V supply) with little degradation stage” complementary mirror structure sometimes referred to as in its ac and dc performance characteristics. See Specifications. the Nelson amplifier. Though twin stages have been tried before, they typically consumed high power since they were of a folded DC GAIN CHARACTERISTICS cascade design much like the AD9617. This design allows for Gain stages A1/A1B and A2/A2B combined provide negative the standing or quiescent current to add to the high signal or slew feedforward transresistance gain (see Figure 6). Stage A3 is a unity current induced stages much like the Nelson or single-stage design. gain buffer that provides external load isolation to A2. Each stage Thus, in the time domain, the large signal output rise/fall time uses a symmetrical complementary design. (A3 is also complemen- and slew rate is controlled typically by the small signal BW of the tary though not explicitly shown.) This is done to reduce second amplifier and the input signal step amplitude respectively, not the order signal distortion and overall quiescent power as discussed dc quiescent current of the gain stages (with the exception of previously. In the quasi dc to low frequency region, the closed- input level shift diodes Q1/Q2). Using two stages versus one also loop gain relationship can be approximated as allows for a higher overall gain bandwidth product (GBWP) for G = 1 + R /R noninverting operation F N the same power, thus lower signal distortion and the ability to G = –R /R inverting operation F N drive heavier external loads. In addition, the second gain stage These basic relationships are common to all traditional opera- also isolates (divides down) A3’s input reflected load drive and tional amplifiers. Due to the inverting input error current (I ) E the nonlinearities created resulting in relatively lower distortion required to servo the output and the inverting I � R drop E I and higher open-loop gain. C A1 D Z1 = R1 || C1 Z1 IPN IPP –V I A2 C 1 IQ1 P Q3 C 2 IR + IFC P ICQ + IO Q1 V V P N V O Z I A3 Z2 V O R L C Q2 L R F IE R L IR – IFC Q4 ICQ – IO Z1 IQ1 A2 –V I C 1 INP P IPN AD8011 A1 C D Figure 6. Simplified Block Diagram REV. C –9– AD8011 (error current times the open-loop inverting input resistance) that This analysis assumes perfect current sources and infinite transistor results (see Figure 7), a more exact low frequency closed-loop V s. (Q3, Q4 output conductances are assumed zero.) These A transfer function can be described as assumptions result in actual versus model open-loop voltage gain and associated input referred error terms being less accurate for G G low gain (G) noninverting operation at the frequencies below the A = = V GR × R G R I F F open-loop pole of the AD8011. This is primarily a result of the 11 + + ++ T T A T O OO O input signal (V ) modulating the output conductances of Q3/Q4, P resulting in R less negative than derived here. For inverting I for noninverting (G is positive). operation, the actual versus model dc error terms are relatively much less. G A = V 1– G R F 1++ –90 80 A T O O 70 –100 for inverting (G is negative). 60 –110 PHASE 50 –120 where G is the ideal gain as previously described. With R = T /A I O O (open-loop inverting input resistance), the second expression 40 –130 GAIN (positive G) clearly relates to the classical voltage feedback op amp 30 –140 equation with T omitted due to its relatively much higher value O 20 –150 and thus insignificant effect. A and T are the open-loop dc O O 10 –160 voltage and transresistance gains of the amplifier, respectively. A (s) O 0 –170 These key transfer variables can be described as –10 –180 | Rg××|A 12 mf –20 –190 A = O (1– g × ) –30 –200 R1 mc 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 FREQUENCY (Hz) | RA ×| 12 Figure 8. Open-Loop Voltage Gain and Phase and T = O 2 AC TRANSFER CHARACTERISTICS – g × R1 1 The ac small signal transfer derivations below are based on a mc R = I simplified single-pole model. Though inaccurate at frequencies 2 × g Therefore mf approaching the closed-loop BW (CLBW) of the AD8011 at low where g is the positive feedback transconductance (not shown) mc noninverting external gains, they still provide a fair approxima- and 1/g is the thermal emitter resistance of devices D1/D2 and mf tion and an intuitive understanding of its primary ac small signal Q3/Q4. The g × R1 product has a design value that results in a mc characteristics. negative dc open-loop gain of typically –2500 V/V (see Figure 8). For inverting operation and high noninverting gains, these transfer equations provide a good approximation to the actual +V S ac performance of the device. To accurately quantify the V versus V relationship, A (s) O P O L S L R N S and T (s) need to be derived. This can be seen by the following O nonexpanded noninverting gain relationship T (s) O V IE O V A (s) P O R C L L G Vs ()/V ()s = OP Z L I L I G R S F ++ 1 As [] Ts [] O O R C F R P N –V S Z = OPEN LOOP INPUT IMPEDANCE = C || R I I L with Rg12 ××|| A mf Figure 7. Z = Open-Loop Input Impedance I As () = O 11 – g × R mc Though atypical of conventional CF or VF amps, this negative Sτ1 open-loop voltage gain results in an input referred error term (V –V /G = G/A + R /T ) that will typically be negative for G, P O O F O – g R 11 × mc greater than +3/–4. As an example, for G = 10, A = –2500, O and T = 1.2 MΩ, results in an error of –3 mV using the A where R1 is the input resistance to A2/A2B, and τ1 (equal to O V derivation above. CD � R1 � A2) is the open-loop dominate time constant, ||AR 21 × T () s = and O 2 sτ11 + –10– REV. C GAIN (dB �) PHASE (Degrees) AD8011 140 0 400 20 SERIES 1 0 370 IMPEDANCE 120 –40 PHASE –20 340 PHASE –80 100 –40 310 280 –60 80 –120 –80 250 GAIN Z (s) I 60 –160 220 –100 T (s) O 190 40 –120 –200 –140 160 20 –240 SERIES 2 –160 130 0 –280 –180 100 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09 FREQUENCY (Hz) FREQUENCY (Hz) Figure 9. Open-Loop Transimpedance Gain Figure 10. Open-Loop Inverting Input Impedance Note that the ac open-loop plots in Figures 8, 9, and 10 are based Z (s) goes positive real and approaches 1/2 g as � approaches I mf on the full SPICE AD8011 simulations and do not include (g � R1 – 1)/τ1. This results in the input resistance for the A (s) mc V external parasitics (see equations below). Nevertheless, these ac complex term being 1/2 g , the parallel thermal emitter mf loop equations still provide a good approximation to simulated resistances of Q3/Q4. Using the computed CLBW from A (s) V and actual performance up to the CLBW of the amplifier. Typi- and the nominal design values for the other parameters, results in cally, g � R1 is –4, resulting in A (s) having a right half plane mc O a closed-loop 3 dB BW equal to the open-loop corner frequency pole. In the time domain (inverse Laplace of A ), it appears as O (1/2 πτ1) × 1/[G/(2 g � T ) + R /T ]. For a fixed R , the mf O F O F unstable, causing V to exponentially rail out of its linear region. O 3 dB BW is controlled by the R /T term for low gains and F O When the loop is closed however, the BW is greatly extended and G/(2 g � T ) for high gains. For example, using nominal design mf O the transimpedance gain, T (s), overrides and directly controls O parameters and R = 1 kΩ (which results in a nominal T of 1 O the amplifiers stability behavior due to Z approaching 1/2 g I mf 1.2 MΩ), the computed BW is 80 MHz for G = 0 (inverting for s>>1/τ1 (see Figure 10). This can be seen by the Z (s) and I I-V mode with R removed) and 40 MHz for G = +10/–9. N A (s) noninverting transfer equations below. V DRIVING CAPACITIVE LOADS The AD8011 was designed primarily to drive nonreactive loads.   Sτ1 If driving loads with a capacitive component is desired, the best (11 – g × R ) +1   mc 11 – g × R settling response is obtained by the addition of a small series    mc  Zs () = resistance as shown in Figure 11. The accompanying graph shows I 21 ×+ g() Sτ1 mf the optimum value for R versus capacitive load. It is worth SERIES noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off G of R and C . SERIES L As () = V      G R  G R F F   1k� 11 ++ Sτ + +1     A T  2 g T T    OOO O    mf    R SERIES 1k� AD8011 R L C L 1k� Figure 11. Driving Capacitive Load REV. C –11– GAIN (dB �) PHASE (Degrees) RESISTANCE (�) PHASE (Degrees) AD8011 40 11 10 V = �5V S G = +2 9 V = 200mV IN 8 30 R = 750� F 7 6 R = 1k� F 5 20 4 3 2 10 1 01 50152025 1 10 100 500 C (pF) L FREQUENCY (MHz) Figure 12. Recommended R vs. Capacitive Figure 13. Flatness vs. Feedback SERIES Load for ≤ 30 ns Settling to 0.1% OPTIMIZING FLATNESS As mentioned, the previous ac transfer equations are based on a Output pin and external component capacitance (designated C ) L simplified single-pole model. Due to the device’s internal para- will further extend the devices BW and can also cause peaking sitics (primarily C 1/C 1B and C 2 in Figure 6) and external below and above the CLBW if too high. In the time domain, P P P package/board parasites (partially represented in Figure 12) the poor step settling characteristics (ringing up to about 2 GHz computed BW, using the previous V (s) equation, typically will and excessive overshoot) can result. For high C values greater O L be lower than the AD8011’s measured small signal BW. See than about 5 pF, an external series damping resistor is recom- data sheet Bode plots. mended. For light loads, any output capacitance will reflect on A2’s output (Z2 of buffer A3) as both added capacitance near With only internal parasitics included, the BW is extended due the CLBW (CLBW > f /B) and eventually negative resistance at T to the complex pole pairs created primarily by C 1/C 2B and P P much higher frequencies. These added effects are proportional C 2 versus the single-pole assumption shown above. This P to the load C. This reflected capacitance and negative resistance results in a design controlled, closed-loop damping factor (�) of has the effect of both reducing A2’s phase margin and causing nominally 0.6 resulting in the CLBW increasing by approxi- high frequency, L � C, peaking respectively. Using an external mately 1.3� higher than the computed single-pole value above series resistor (as previously specified) reduces these unwanted for optimized external gains of +2/–1. As external noninverting effects by creating a reflected zero to A2’s output, which will gain (G) is increased, the actual closed-loop bandwidth versus reduce the peaking and eliminate ringing. For heavy resistive the computed single-pole ac response is in closer agreement. loads, relatively more load C would be required to cause these Inverting pin and external component capacitance (designated C ) P same effects. will further extend the CLBW due to the closed-loop zero created High inductive parasitics, especially on the supplies and inverting/ by C and R �R when operating in the noninverting mode. Using P N F noninverting inputs, can cause modulated low level R ringing on F proper R component and layout techniques (see the Layout F the output in the transient domain. Proper R component and F Considerations section), this capacitance should be about 1.5 pF. board layout practices need to be observed. Relatively high para- This results in a further incremental BW increase of almost 2� sitic lead inductance (roughly L >15 nh) can result in L� C (versus the computed value) for G = +1 decreasing and approach- underdamped ringing. Here L/C means all associated input pins, ing its complex pole pair BW for gains approaching +6 or higher. external components, and lead frame strays, including collector As previously discussed, the single-pole response begins to corre- to substrate device capacitance. In the ac domain, this L� C late well. Note that a pole is also created by 1/2 g and C , which mf P resonance effect would typically not appear in the pass band of prevents the AD8011 from becoming unstable. This parasitic the amplifier but would appear in the open-loop response at has the greatest effect on BW and peaking for low positive gains frequencies well above the CLBW of the amplifier. as the data sheet Bode plots clearly show. For inverting operation, C has relatively much less effect on CLBW variation. P –12– REV. C R (�) SERIES GAIN (dB) AD8011 INCREASING BW AT HIGH GAINS The analog input of the AD876 spans 2 V centered at about As presented previously, for a fixed R (feedback gain setting 2.6 V. The resistor network and bias voltages provide the level F resistor), the AD8011 CLBW will decrease as R is reduced shifting and gain required to convert the 0 V to 1 V input signal N (increased G). This effect can be minimized by simply reducing to a 3.6 V to 1.6 V range that the AD876 wants to see. R and partially restoring the devices optimized BW for gains F Biasing the noninverting input of the AD8011 at 1.6 V dc forces greater than +2/–1. Note that the AD8011 is ac optimized (high the inverting input to be at 1.6 V dc for linear operation of the BW and low peaking) for A = +2/–1 and R = 1 kΩ. Using this V F amplifier. When the input is at 0 V, there is 3.2 mA flowing out of optimized G as a reference and the previous V (s) equations, O the summing junction via R1 (1.6 V/499 Ω). R3 has a current of the following relationships result: R = 1kΩ + 2 – G/2 gm for F 1.2 mA flowing into the summing junction (3.6 V – 1.6 V)/1.65 kΩ. G = 1+ R /R (noninverting) or R = 1kΩ + G + 1/2 gm for F N F The difference of these two currents (2 mA) must flow through G = –R /R (inverting). F N R2. This current flows toward the summing junction and Using 1/2 gm equal to 120 Ω results in a R of 500 Ω for G = requires that the output be 2 V higher than the summing junction F +5/–4 and a corresponding R of 125 Ω. This will extend the or at 3.6 V. N AD8011’s BW to near its optimum design value of typically When the input is at 1 V, there is 1.2 mA flowing into the sum- 180 MHz at R = 1 kΩ. In general, for gains greater than +7/–6, L ming junction through R3 and 1.2 mA flowing out through R1. R should not be reduced to values much below 400 Ω or else ac F These currents balance and leave no current to flow through R2. peaking can result. Using this R value as the lower limit will F Thus, the output is at the same potential as the inverting input result in BW restoration near its optimized value to the upper G or 1.6 V. values specified. Gains greater than about +7/–6 will result in The input of the AD876 has a series MOSFET switch that turns CLBW reduction. The derivations above are just approximations. on and off at the sampling rate. This MOSFET is connected to a hold capacitor, internal to the device. The on impedance of the DRIVING A SINGLE-SUPPLY A/D CONVERTER MOSFET is about 50 Ω, while the hold capacitor is about 5 pF. New CMOS A/D converters are placing greater demands on the amplifiers that drive them. Higher re solutions, faster conversion In a worst-case condition, the input voltage to the AD876 will rates, and input switching irregularities require superior settling change by a full-scale value (2 V) in one sampling cycle. When characteristics. In addition, these devices run off a single 5 V supply the input MOSFET turns on, the output of the op amp will be and consume little power, so good single-supply operation with connected to the charged hold capacitor through the series resis- low power consumption are very important. The AD8011 is tance of the MOSFET. Without any other series resistance, the well positioned for driving this new class of A/D converters. instantaneous current that flows would be 40 mA. This would cause settling problems for the op amp. Figure 14 shows a circuit that uses an AD8011 to drive an AD876, a single-supply, 10-bit, 20 MSPS A/D converter that requires The series 100 Ω resistor limits the current that flows instantane- only 140 mW. Using the AD8011 for level shifting and driving, ously to about 13 mA after the MOSFET turns on. This resistor the A/D exhibits no degradation in performance compared to cannot be made too large or the high frequency performance when it is driven from a signal generator. will be affected. The sampling MOSFET of the AD876 is closed for only half of +5V each cycle or for 25 ns. Approximately seven time constants are required for settling to 10 bits. The series 100 Ω resistor, the 0.1�F 10�F R2 R3 50 Ω on resistance, and the hold capacitor create a 750 ps time 1.65k� 1k� 3.6V constant. These values leave a comfortable margin for settling. 0.1�F Obtaining the same results with the op amp A/D combination +3.6V R1 as compared to driving with a signal generator indicates that the V 499k� IN REFT 1V op amp is settling fast enough. 0V 100� 50� AD8011 AD876 0.1�F Overall, the AD8011 provides adequate buffering for the AD876 3.6V A/D converter without introducing distortion greater than that REFB 1.6V of the A/D converter by itself. +1.6V 1.6V Figure 14. AD8011 Driving the AD876 REV. C –13– AD8011 LAYOUT CONSIDERATIONS The feedback resistor should be located close to the inverting The specified high speed performance of the AD8011 requires input pin in order to keep the stray capacitance at this node to a careful attention to board layout and component selection. Table I minimum. Capacitance greater than 1.5 pF at the inverting input shows the recommended component values for the AD8011. will significantly affect high speed performance when operating Proper R design techniques and low parasitic component selec- at low noninverting gains. F tion are mandatory. Stripline design techniques should be used for long signal traces (greater than about 1 in.). These should be designed with the Table I. Typical Bandwidth vs. Gain Setting Resistors proper system characteristic impedance and be properly terminated at each end. Small Signal –3 dB BW (MHz), R R R G F O Gain R (�)R (�)R (�)V = �5 V V V F G T S IN OUT R T –1 1000 1000 52.3 150 –2 1000 499 54.9 130 +V S –10 499 49.9 140 C1 C3 0.01�F 10�F +1 1000 49.9 400 C2 C4 +2 1000 1000 49.9 250 0.01�F 10�F –V +10 422 47.5 49.9 100 S INVERTING CONFIGURATION +6 1000 200 49.9 70 +6 500 100 49.9 170 R R R G F O V OUT R chosen for 50 Ω characteristic input impedance. R chosen for characteristic T O output impedance. V IN The PCB should have a ground plane covering all unused +V S R T C1 C3 portions of the component side of the board to provide a low 0.01�F 10�F impedance ground path. The ground plane should be removed C4 C2 10�F 0.01�F from the area near the input pins to reduce stray capacitance. –V S NONINVERTING CONFIGURATION Chip capacitors should be used for supply bypassing (see Figure 15). One end should be connected to the ground plane Figure 15. Inverting and Noninverting Configurations and the other within 1/8 in. of each power pin. An additional tan- talum electrolytic capacitor (4.7 µF – 10 µF) should be connected in parallel. –14– REV. C AD8011 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 0.295 (7.49) 0.285 (7.24) 4 0.275 (6.98) 1 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.150 (3.81) 0.300 (7.62) BSC 0.135 (3.43) 0.015 0.120 (3.05) 0.180 (0.38) (4.57) MIN MAX 0.015 (0.38) 0.150 (3.81) 0.010 (0.25) SEATING 0.130 (3.30) PLANE 0.008 (0.20) 0.110 (2.79) 0.060 (1.52) 0.022 (0.56) 0.050 (1.27) 0.018 (0.46) 0.045 (1.14) 0.014 (0.36) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 85 6.20 (0.2440) 4.00 (0.1574) 3.80 (0.1497) 5.80 (0.2284) 1 4 0.50 (0.0196) 1.27 (0.0500) � 45� 1.75 (0.0688) BSC 0.25 (0.0099) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 8� 0.51 (0.0201) 0� 1.27 (0.0500) COPLANARITY 0.31 (0.0122) 0.25 (0.0098) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. C –15– AD8011 Revision History Location Page 7/03—Data Sheet changed from REV. B to REV. C. Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Format updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Renumbered figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to TPC 9 and 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to TPC 13 and 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Changes to TPC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 –16– REV. C C01048–0–7/03(C)