ANALOG DEVICES AD8001

800 MHz, 50 mW a Current Feedback Amplifier AD8001 FUNCTIONAL BLOCK DIAGRAMS FEATURES Excellent Video Specifications (R = 150 �, G = +2) L 5-Lead SOT-23-5 8-Lead PDIP (N-8), Gain Flatness 0.1 dB to 100 MHz (RT-5) CERDIP (Q-8) and SOIC (R-8) 0.01% Differential Gain Error 0.025� Differential Phase Error Low Power AD8001 NC 8 NC 1 +V V 1 5 S 5.5 mA Max Power Supply Current (55 mW) OUT –IN 2 7 V+ High Speed and Fast Settling –V 2 S 880 MHz, –3 dB Bandwidth (G = +1) +IN 3 6 OUT 34 440 MHz, –3 dB Bandwidth (G = +2) +IN –IN V– 4 5 NC AD8001 1200 V/�s Slew Rate 10 ns Settling Time to 0.1% NC = NO CONNECT Low Distortion transimpedance linearization circuitry. This allows it to drive –65 dBc THD, f = 5 MHz C video loads with excellent differential gain and phase perfor- 33 dBm Third Order Intercept, F = 10 MHz 1 mance on only 50 mW of power. The AD8001 is a current –66 dB SFDR, f = 5 MHz feedback amplifier and features gain flatness of 0.1 dB to 100 MHz High Output Drive while offering differential gain and phase error of 0.01% and 70 mA Output Current 0.025°. This makes the AD8001 ideal for professional video Drives Up to 4 Back-Terminated Loads (75 � Each) electronics such as cameras and video switchers. Additionally, While Maintaining Good Differential Gain/Phase the AD8001’s low distortion and fast settling make it ideal for Performance (0.05%/0.25�) buffer high speed A-to-D converters. APPLICATIONS The AD8001 offers low power of 5.5 mA max (V = ±5 V) and S A-to-D Drivers can run on a single +12 V power supply, while being capable of Video Line Drivers delivering over 70 mA of load current. These features make this Professional Cameras amplifier ideal for portable and battery-powered applications Video Switchers where size and power are critical. Special Effects RF Receivers The outstanding bandwidth of 800 MHz along with 1200 V/µs of slew rate make the AD8001 useful in many general-purpose GENERAL DESCRIPTION high speed applications where dual power supplies of up to ±6 V The AD8001 is a low power, high speed amplifier designed and single supplies from 6 V to 12 V are needed. The AD8001 is to operate on ±5V supplies. The AD8001 features unique available in the industrial temperature range of –40°C to +85°C. 9 V = �5V S 6 R = 820� FB G = +2 3 R = 100� L 0 V = �5V S –3 R = 1k� FB –6 –9 –12 10M 100M 1G FREQUENCY – Hz Figure 1. Frequency Response of AD8001 Figure 2. Transient Response of AD8001; 2 V Step, G = +2 REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. GAIN – dB (@ T = + 25�C, V = �5 V, R = 100 �, unless otherwise noted.) AD8001–SPECIFICATIONS A S L AD8001A Model Conditions Min Typ Max Unit DYNAMIC PERFORMANCE –3 dB Small Signal Bandwidth, N Package G = +2, < 0.1 dB Peaking, R = 750 Ω 350 440 MHz F G= +1, < 1 dB Peaking, R = 1 kΩ 650 880 MHz F R Package G = +2, < 0.1 dB Peaking, R = 681 Ω 350 440 MHz F G= +1, < 0.1 dB Peaking, R = 845 Ω 575 715 MHz F RT Package G = +2, < 0.1 dB Peaking, R = 768 Ω 300 380 MHz F G= +1, < 0.1 dB Peaking, R = 1 kΩ 575 795 MHz F Bandwidth for 0.1 dB Flatness N Package G = +2, R = 750 Ω 85 110 MHz F R Package G = +2, R = 681 Ω 100 125 MHz F RT Package G = +2, R = 768 Ω 120 145 MHz F Slew Rate G = +2, V = 2 V Step 800 1000 V/µs O G = –1, V = 2 V Step 960 1200 V/µs O Settling Time to 0.1% G = –1, V = 2 V Step 10 ns O Rise and Fall Time G = +2, V = 2 V Step, R = 649 Ω 1.4 ns O F NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion f = 5 MHz, V = 2 V p-p –65 dBc C O = 100 Ω G = +2, R L Input Voltage Noise f = 10 kHz 2.0 nV/√Hz Input Current Noise f = 10 kHz, +In 2.0 pA/√Hz –In 18 pA/√Hz Differential Gain Error NTSC, G = +2, R = 150 Ω 0.01 0.025 % L Differential Phase Error NTSC, G = +2, R = 150 Ω 0.025 0.04 Degree L Third Order Intercept f = 10 MHz 33 dBm 1 dB Gain Compression f = 10 MHz 14 dBm SFDR f = 5 MHz –66 dB DC PERFORMANCE Input Offset Voltage 2.0 5.5 mV T –T 2.0 9.0 mV MIN MAX Offset Drift 10 µV/°C –Input Bias Current 5.0 25 ±µA T –T 35 ±µA MIN MAX +Input Bias Current 3.0 6.0 ±µA T –T 10 ±µA MIN MAX Open-Loop Transresistance V = ±2.5 V 250 900 kΩ O T –T 175 kΩ MIN MAX INPUT CHARACTERISTICS Input Resistance +Input 10 MΩ –Input 50 Ω Input Capacitance +Input 1.5 pF Input Common-Mode Voltage Range 3.2 ±V Common-Mode Rejection Ratio Offset Voltage V = ±2.5 V 50 54 dB CM –Input Current V = ±2.5 V, T –T 0.3 1.0 µA/V CM MIN MAX +Input Current V = ±2.5 V, T –T 0.2 0.7 µA/V CM MIN MAX OUTPUT CHARACTERISTICS Output Voltage Swing R = 150 Ω 2.7 3.1 ±V L Output Current R = 37.5 Ω 50 70 mA L Short Circuit Current 85 110 mA POWER SUPPLY Operating Range ±3.0 ±6.0 V Quiescent Current T –T 5.0 5.5 mA MIN MAX Power Supply Rejection Ratio +V = +4 V to +6 V, –V = –5 V 60 75 dB S S –V = – 4 V to –6 V, +V = +5 V 50 56 dB S S –Input Current T –T 0.5 2.5 µA/V MIN MAX +Input Current T –T 0.1 0.5 µA/V MIN MAX Specifications subject to change without notice. –2– REV. D AD8001 1 ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V The maximum power that can be safely dissipated by the 2 Internal Power Dissipation @ 25°C AD8001 is limited by the associated rise in junction tempera- PDIP Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W ture. The maximum safe junction temperature for plastic SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W encapsulated devices is determined by the glass transition tem- 8-Lead CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W perature of the plastic, approximately 150°C. Exceeding this SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W limit temporarily may cause a shift in parametric performance Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V due to a change in the stresses exerted on the die by the package. S Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V Exceeding a junction temperature of 175°C for an extended Output Short Circuit Duration period can result in device failure. .. . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves While the AD8001 is internally short circuit protected, this Storage Temperature Range N, R . . . . . . . . . –65°C to +125°C may not be sufficient to guarantee that the maximum junction Operating Temperature Range (A Grade) . . . –40°C to +85°C temperature (150°C) is not exceeded under all conditions. To Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C ensure proper operation, it is necessary to observe the maximum NOTES power derating curves. 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the 2.0 device at these or any other conditions above those indicated in the operational T = +150�C section of this specification is not implied. Exposure to absolute maximum rating 8-LEAD J PDIP PACKAGE conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-LEAD 1.5 8-Lead PDIP Package: θ = 90°C/W CERDIP PACKAGE JA 8-LEAD 8-Lead SOIC Package: θ = 155°C/W SOIC PACKAGE JA 8-Lead CERDIP Package: θ = 110°C/W JA 5-Lead SOT-23-5 Package: θ = 260°C/W JA 1.0 0.5 5-LEAD SOT-23-5 PACKAGE 0 –50 –40 –30 –20 –10 010 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE – �C Figure 3. Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Temperature Package Package Model Range Description Option Branding AD8001AN –40°C to +85°C 8-Lead PDIP N-8 AD8001AQ –55°C to +125°C 8-Lead CERDIP Q-8 AD8001AR –40°C to +85°C 8-Lead SOIC R-8 AD8001AR-REEL –40°C to +85°C 13" Tape and REEL R-8 AD8001AR-REEL7 –40°C to +85°C 7" Tape and REEL R-8 AD8001ART-REEL –40°C to +85°C 13" Tape and REEL RT-5 HEA AD8001ART-REEL7 –40°C to +85°C 7" Tape and REEL RT-5 HEA AD8001ACHIPS –40°C to +85°CDie Form * 5962-9459301MPA –55°C to +125°C 8-Lead CERDIP Q-8 * Standard Military Drawing Device. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD8001 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. D –3– MAXIMUM POWER DISSIPATION – W AD8001–Typical Performance Characteristics 806� 0.001�F +V S V TO OUT 0.1�F TEKTRONIX CSA 404 COMM. 806� SIGNAL ANALYZER AD8001 0.1�F V R = 100� IN L HP8133A 50� PULSE 0.001�F GENERATOR T /T = 50ps R F –V S 400mV 5ns TPC 4. 2 V Step Response, G = +2 TPC 1. Test Circuit , Gain = +2 909� 0.001�F +V S V TO OUT 0.1�F TEKTRONIX CSA 404 COMM. SIGNAL ANALYZER AD8001 0.1�F V R = 100� IN L LeCROY 9210 50� PULSE 0.001�F GENERATOR T /T = 350ps R F –V S TPC 2. 1 V Step Response, G = +2 TPC 5. Test Circuit, Gain = +1 0.5V 5ns TPC 3. 2 V Step Response, G = +1 TPC 6. 100 mV Step Response, G = +1 REV. D –4– AD8001 1000 9 V = �5V S V = �5V 6 R = 820� S FB 800 R = 100� L G = +2 G = +2 3 R = 100� L 600 N 0 PACKAGE V = �5V S –3 R = 1k� 400 FB R –6 PACKAGE 200 –9 –12 0 10M 100M 1G 500 600 700 800 900 1000 FREQUENCY – Hz VALUE OF FEEDBACK RESISTOR (R ) – � F TPC 7. Frequency Response, G = +2 TPC 10. –3 dB Bandwidth vs. R F 0.1 –50 R = F �5V SUPPLIES 649� 0 R = 698� F –0.1 –60 V = 2V p-p OUT R = 100� L –0.2 R = 750� F G = +2 –0.3 –70 G = +2 –0.4 R = 100� L SECOND HARMONIC V = 50mV IN –0.5 –80 THIRD HARMONIC –0.6 –0.7 –90 –0.8 –0.9 –100 1M 10M 100M 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz TPC 8. 0.1 dB Flatness, R Package (for N Package Add TPC 11. Distortion vs. Frequency, R = 100 Ω L 50 Ω to R ) F 0.08 –50 G = +2 �5V SUPPLIES 0.06 R = 806� V = 2V p-p F OUT 2 BACK TERMINATED –60 R = 1k� L 0.04 LOADS (75�) G = +2 0.02 –70 SECOND HARMONIC 0.00 1 BACK TERMINATED LOAD (150�) –80 0.02 1 AND 2 BACK TERMINATED –90 THIRD HARMONIC 0.01 LOADS (150� AND 75�) 0.00 –100 –0.01 –0.02 –110 0 100 10k 100k 1M 10M 100M IRE FREQUENCY – Hz TPC 12. Differential Gain and Differential Phase TPC 9. Distortion vs. Frequency, R = 1 kΩ L REV. D –5– HARMONIC DISTORTION – dBc OUTPUT – dB GAIN – dB DIFF GAIN – % DIFF PHASE – Degrees HARMONIC DISTORTION – dBc –3dB BANDWIDTH – MHz AD8001 5 1000 0 N PACKAGE 900 –5 V = –26dBm IN –10 800 R = 909� F –15 R PACKAGE 700 –20 V = 50mV IN –25 R = 100� L 600 G = +1 –30 –35 500 100M 1G 3G 700 800 900 1100 600 1000 FREQUENCY – Hz VALUE OF FEEDBACK RESISTOR (R ) – � F TPC 13. Frequency Response, G = +1 TPC 16. –3 dB Bandwidth vs. R , G = +1 F 1 –40 0 R = 649� F R = 100� L –50 –1 G = +1 V = 2V p-p R = 953� OUT F –2 –60 –3 SECOND HARMONIC –4 –70 G = +1 R = 100� –5 L V = 50mV IN –80 THIRD HARMONIC –6 –7 –90 –8 –9 –100 2M 10M 100M 1G 10k 100k 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz TPC 14. Flatness, R Package, G = +1 (for N Package Add TPC 17. Distortion vs. Frequency, R = 100 Ω L 100 Ω to R ) F 3 –40 0 G = +1 –50 R = 1k� L –3 V = 2V p-p OUT –60 –6 –9 –70 SECOND HARMONIC –12 –80 –15 THIRD HARMONIC –18 –90 R = 100� L –21 G = +1 –100 –24 –27 –110 10k 100k 1M 10M 100M 1M 10M 100M FREQUENCY – Hz FREQUENCY – Hz TPC 15. Distortion vs. Frequency, R = 1 kΩ TPC 18. Large Signal Frequency Response, G = +1 L REV. D –6– DISTORTION – dBc GAIN – dB OUTPUT – dB DISTORTION – dBc –3dB BANDWIDTH – MHz OUTPUT – dBV AD8001 45 2.2 40 2.0 DEVICE NO. 1 G = +100 35 30 1.8 R = 1000� F 25 1.6 20 DEVICE NO. 2 G = +10 15 1.4 10 R = 470� F 1.2 5 0 1.0 –5 R = 100� L DEVICE NO. 3 0.8 –10 –15 0.6 –20 –25 0.4 1M 10M 100M 1G –60 –40 –20 0 20 40 60 80 100 FREQUENCY – Hz JUNCTION TEMPERATURE – �C TPC 19. Frequency Response, G = +10, G = +100 TPC 22. Input Offset vs. Temperature 5.8 3.35 3.25 5.6 3.15 +V OUT 5.4 R = 150� L V = �5V S 3.05 5.2 | –V | OUT 2.95 V = �5V S 5.0 2.85 +V OUT 4.8 R = 50� 2.75 L V = �5V S 4.6 | –V | 2.65 OUT 4.4 2.55 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – �C JUNCTION TEMPERATURE – �C TPC 23. Supply Current vs. Temperature TPC 20. Output Swing vs. Temperature 5 125 4 120 3 SOURCE I SC 115 –IN 2 110 | SINK I | 1 SC 105 0 100 –1 +IN 95 –2 90 –3 –4 85 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – �C JUNCTION TEMPERATURE – �C TPC 21. Input Bias Current vs. Temperature TPC 24. Short Circuit Current vs. Temperature REV. D –7– OUTPUT SWING – Volts GAIN – dB INPUT BIAS CURRENT – �A SUPPLY CURRENT – mA SHORT CIRCUIT CURRENT – mA INPUT OFFSET VOLTAGE – mV AD8001 6 1k 5 100 V = �5V S R = 150� L 4 V = �2.5V OUT 10 3 1 –T Z 2 G = +2 0.1 1 +T Z R = 909� F 0 0.01 –60 –40 –20 0 20 40 60 80 100 120 140 10k 100k 1M 10M 100M JUNCTION TEMPERATURE – �C FREQUENCY – Hz TPC 25. Transresistance vs. Temperature TPC 28. Output Resistance vs. Frequency 100 100 1 R = 576� F 0 –1 INVERTING CURRENT V = �5V S R = 649� F –2 –3 G = –1 R = 750� F R = 100� 10 10 –4 L V = 50mV IN NONINVERTING CURRENT V = �5V S –5 –6 –7 –8 VOLTAGE NOISE V = �5V S 1 1 –9 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 26. Noise vs. Frequency TPC 29. –3 dB Bandwidth vs. Frequency, G = –1 –48 –52.5 –55.0 –49 –PSRR –CMRR –57.5 –50 –60.0 3V SPAN –51 –62.5 +CMRR CURVES ARE FOR WORST- –52 –65.0 CASE CONDITION WHERE ONE SUPPLY IS VARIED –67.5 WHILE THE OTHER IS –53 HELD CONSTANT. 2.5V SPAN –70.0 –54 –72.5 +PSRR –55 –75.0 –56 –77.5 –60 –40 –20 0 20 40 60 80 100 120 140 –60 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE – �C JUNCTION TEMPERATURE – �C TPC 27. CMRR vs. Temperature TPC 30. PSRR vs. Temperature REV. D –8– CMRR – dB NOISE VOLTAGE – nV/√Hz TRANSRESISTANCE – k� NOISE CURRENT – pA/√Hz PSRR – dB R – � OUTPUT – dB OUT AD8001 30 –10 20 CURVES ARE FOR WORST- 910� CASE CONDITION WHERE +PSRR 910� V IN 10 ONE SUPPLY IS VARIED 51� 150� WHILE THE OTHER IS –20 V OUT HELD CONSTANT. 0 62� 150� –10 –30 –PSRR –20 –30 –PSRR –40 +PSRR –40 R = 909� F G = +2 –50 –50 –60 300k 1M 10M 100M 1G 1M 10M 100M 1G FREQUENCY – Hz FREQUENCY – Hz TPC 31. CMRR vs. Frequency TPC 34. PSRR vs. Frequency 1 R = 549� F 0 –1 R = 649� F –2 –3 G = –2 R = 100� –4 L V = 50mV R = 750� IN rms F –5 –6 –7 –8 –9 1M 10M 100M 1G FREQUENCY – Hz TPC 35. 2 V Step Response, G = –1 TPC 32. –3 dB Bandwidth vs. Frequency, G = –2 100 100 3 WAFER LOTS 90 90 COUNT = 895 MEAN = 1.37 80 80 STD DEV = 1.13 CUMULATIVE MIN = –2.45 70 70 MAX = +4.69 60 60 50 50 FREQ DIST 40 40 30 30 20 20 10 10 0 0 –5 –4 –3 –2 –1 0 1 2 3 4 5 INPUT OFFSET VOLTAGE – mV TPC 36. Input Offset Voltage Distribution TPC 33. 100 mV Step Response, G = –1 REV. D –9– CMRR – dB OUTPUT – dB COUNT PSRR – dB PERCENT AD8001 Considering that additional poles contribute excess phase at THEORY OF OPERATION high frequencies, there is a minimum feedback resistance below A very simple analysis can put the operation of the AD8001, a which peaking or oscillation may result. This fact is used to current feedback amplifier, in familiar terms. Being a current determine the optimum feedback resistance, R . In practice, feedback amplifier, the AD8001’s open-loop behavior is expressed F parasitic capacitance at Pin 2 will also add phase in the feedback as transimpedance, ∆V /∆I , or T . The open-loop transimped- O –IN Z loop, so picking an optimum value for R can be difficult. ance behaves just as the open-loop voltage gain of a voltage F Figure 6 illustrates this problem. Here the fine scale (0.1 dB/ feedback amplifier, that is, it has a large dc value and decreases div) flatness is plotted versus feedback resistance. These plots at roughly 6 dB/octave in frequency. were taken using an evaluation card which is available to cus- Since the R is proportional to 1/g , the equivalent voltage IN M tomers so that these results may readily be duplicated. gain is just T × g , where the g in question is the trans- Z M M Achieving and maintaining gain flatness of better than 0.1 dB at conductance of the input stage. This results in a low open-loop frequencies above 10 MHz requires careful consideration of input impedance at the inverting input, a now familiar result. several issues. Using this amplifier as a follower with gain, Figure 4, basic analysis yields the following result. 0.1 V TS () O Z R = F =× G 649� 0 V TS ()+× G R +R1 IN ZIN R = 698� F –0.1 R1 G=+ 1 Rg =15 / ≈0 Ω IN M –0.2 R2 G = +2 R = 750� F –0.3 –0.4 R1 –0.5 R2 –0.6 R IN –0.7 V OUT –0.8 V –0.9 IN 1M 10M 100M FREQUENCY – Hz Figure 6. 0.1 dB Flatness vs. Frequency Figure 4. Follower with Gain Choice of Feedback and Gain Resistors Recognizing that G × R << R1 for low gains, it can be seen to IN Because of the above-mentioned relationship between the band- the first order that bandwidth for this amplifier is independent width and feedback resistor, the fine scale gain flatness will, to of gain (G). This simple analysis in conjunction with Figure 5 some extent, vary with feedback resistance. It, therefore, is can, in fact, predict the behavior of the AD8001 over a wide recommended that once optimum resistor values have been range of conditions. determined, 1% tolerance values should be used if it is desired to 1M maintain flatness over a wide range of production lots. In addition, resistors of different construction have different associated parasitic capacitance and inductance. Surface-mount resistors were used 100k for the bulk of the characterization for this data sheet. It is not recommended that leaded components be used with the AD8001. 10k 1k 100 10 100k 1M 10M 100M 1G FREQUENCY – Hz Figure 5. Transimpedance vs. Frequency REV. D –10– T – � Z OUTPUT – dB AD8001 Printed Circuit Board Layout Considerations Driving Capacitive Loads As to be expected for a wideband amplifier, PC board parasitics The AD8001 was designed primarily to drive nonreactive loads. can affect the overall closed-loop performance. Of concern are If driving loads with a capacitive component is desired, best stray capacitances at the output and the inverting input nodes. If frequency response is obtained by the addition of a small series a ground plane is to be used on the same side of the board as resistance, as shown in Figure 8. The accompanying graph the signal traces, a space (5 mm min) should be left around the shows the optimum value for R versus capacitive load. It is SERIES signal lines to minimize coupling. Additionally, signal lines worth noting that the frequency response of the circuit when connecting the feedback and gain resistors should be short driving large capacitive loads will be dominated by the passive enough so that their associated inductance does not cause high roll-off of R and C . SERIES L frequency gain errors. Line lengths on the order of less than 909� 5 mm are recommended. If long runs of coaxial cable are being driven, dispersion and loss must be considered. Power Supply Bypassing R SERIES Adequate power supply bypassing can be critical when optimiz- I N ing the performance of a high frequency circuit. Inductance in R L C L 500� the power supply leads can form resonant circuits that produce peaking in the amplifier’s response. In addition, if large current transients must be delivered to the load, then bypass capacitors Figure 8. Driving Capacitive Loads (typically greater than 1 µF) will be required to provide the best settling time and lowest distortion. A parallel combination of 4.7 µF and 0.1 µF is recommended. Some brands of electrolytic 40 capacitors will require a small series damping resistor ≈4.7 Ω for optimum results. G = +1 DC Errors and Noise 30 There are three major noise and offset terms to consider in a current feedback amplifier. For offset errors, refer to the equation below. For noise error the terms are root-sum-squared to give a net output error. In the circuit in Figure 7 they are input offset 20 (V ), which appears at the output multiplied by the noise gain IO of the circuit (1 + R /R ), noninverting input current (I × R ) F I BN N also multiplied by the noise gain, and the inverting input current, 10 which when divided between R and R and subsequently F I multiplied by the noise gain always appears at the output as I × R . The input voltage noise of the AD8001 is a low 2 nV/ BN F 0 √Hz. At low gains though the inverting input current noise times 0 5 10 15 20 25 C – pF L R is the dominant noise source. Careful layout and device F matching contribute to better offset and drift specifications for Figure 9. Recommended R vs. Capacitive Load SERIES the AD8001 compared to many other current feedback ampli- fiers. The typical performance curves in conjunction with the following equations can be used to predict the performance of the AD8001 in any application.     R R F F VV=×11 + ±×IR× + ±×IR OUT IO BN N BI F      R   R  I I R F I BI R I V OUT I BN R N Figure 7. Output Offset Voltage REV. D –11– R – � SERIES AD8001 Communications Operation as a Video Line Driver Distortion is a key specification in communications applications. The AD8001 has been designed to offer outstanding perfor- Intermodulation distortion (IMD) is a measure of the ability of mance as a video line driver. The important specifications of an amplifier to pass complex signals without the generation of differential gain (0.01%) and differential phase (0.025°) meet spurious harmonics. The third order products are usually the the most exacting HDTV demands for driving one video load. most problematic since several of them fall near the fundamentals The AD8001 also drives up to two back terminated loads as and do not lend themselves to filtering. Theory predicts that the shown in Figure 11, with equally impressive performance (0.01%, third order harmonic distortion components increase in power at 0.07°). Another important consideration is isolation between three times the rate of the fundamental tones. The specification loads in a multiple load application. The AD8001 has more of third order intercept as the virtual point where fundamental and than 40 dB of isolation at 5 MHz when driving two 75 Ω back harmonic power are equal is one standard measure of distortion terminated loads. performance. Op amps used in closed-loop applications do not 75� always obey this simple theory. At a gain of +2, the AD8001 CABLE 909� 909� 75� has performance summarized in Figure 10. Here the worst third V NO. 1 OUT order products are plotted versus input power. The third order 75� +V S 0.001�F intercept of the AD8001 is +33 dBm at 10 MHz. + 0.1�F –45 75� G = +2 CABLE 75� F = 10MHz –50 1 75� V NO. 2 OUT AD8001 CABLE F = 12MHz 2 75� V 0.1�F 2F – F IN 2 1 –55 75� –60 0.001�F 2F – F 1 2 –V –65 S Figure 11. Video Line Driver –70 –75 –80 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 INPUT POWER – dBm Figure 10. Third Order IMD; F = 10 MHz, F = 12 MHz 1 2 REV. D –12– THIRD ORDER IMD – dBc AD8001 Driving A-to-D Converters ADC. Using the AD9058’s internal +2 V reference connected The AD8001 is well suited for driving high speed analog-to- to both ADCs as shown in Figure 12 reduces the number of digital converters such as the AD9058. The AD9058 is a dual external components required to create a complete data 8-bit 50 MSPS ADC. In the circuit below, the AD8001 is acquisition system. The 20 Ω resistors in series with ADC inputs shown driving the inputs of the AD9058, which are configured are used to help the AD8001s drive the 10 pF ADC input for 0 V to 2 V ranges. Bipolar input signals are buffered, amplified capacitance. The AD8001 only adds 100 mW to the power (–2×), and offset (by +1.0 V) into the proper input range of the consumption while not limiting the performance of the circuit. 1k� ENCODE 74ACT04 10pF 50� 10 36 ENCODE A ENCODE B 8 649� –V 5, 9, 22, REF A +5V +V S 38 24, 37, 41 –V REF B 0.1�F ANALOG 324� AD9058 IN A RZ1 20� (J-LEAD) 6 �0.5V A 18 AD8001 IN A D (LSB) 0A 1.3k� 17 16 2 –2V 15 +V INT 8 AD707 14 20k� 3 0.1�F +V REF A 13 43 12 20k� 0.1�F +V REF B 11 D (MSB) 7A 1.3k� RZ2 649� 28 D (LSB) 0B 29 ANALOG 324� 30 IN B 20� �0.5V 40 31 8 A AD8001 IN B 32 33 1 34 COMP 35 0.1�F D (MSB) 7B 7, 20, CLOCK –V –5V S 26, 39 RZ1, RZ2 = 2,000� SIP (8-PKG) 1N4001 0.1�F 4,19, 21 25, 27, 42 Figure 12. AD8001 Driving a Dual A-to-D Converter REV. D –13– 74ACT 273 74ACT 273 AD8001 Layout Considerations (4.7 µF–10 µF) tantalum electrolytic capacitor should be con- The specified high speed performance of the AD8001 requires nected in parallel, but not necessarily so close, to supply current careful attention to board layout and component selection. Proper for fast, large-signal changes at the output. R design techniques and low parasitic component selection F The feedback resistor should be located close to the inverting are mandatory. input pin in order to keep the stray capacitance at this node to a The PCB should have a ground plane covering all unused portions minimum. Capacitance variations of less than 1 pF at the invert- of the component side of the board to provide a low impedance ing input will significantly affect high speed performance. ground path. The ground plane should be removed from the area Stripline design techniques should be used for long signal traces near the input pins to reduce stray capacitance. (greater than about 1 inch). These should be designed with a Chip capacitors should be used for supply bypassing (see Figure 13). characteristic impedance of 50 Ω or 75 Ω and be properly termi- One end should be connected to the ground plane and the other nated at each end. within 1/8 inch of each power pin. An additional large R R F F +V +V +V S S S R C1 C3 R G G 0.1�F 10�F IN R R O O OUT OUT R T IN C2 C4 R 0.1�F 10�F S R T –V –V S S –V S Inverting Configuration Supply Bypassing Noninverting Configuration Figure 13. Inverting and Noninverting Configurations for Evaluation Boards Table I. Recommended Component Values AD8001AN (PDIP) AD8001AR (SOIC) AD8001ART (SOT-23-5) Gain Gain Gain Component –1 +1 +2 +10 +100 –1 +1 +2 +10 +100 –1 +1 +2 +10 +100 R (Ω) 649 1050 750 470 1000 604 953 681 470 1000 845 1000 768 470 1000 F R (Ω) 649 750 51 10 604 681 51 10 845 768 51 10 G R (Nominal) (Ω) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 O R (Ω)0 0 0 S R (Nominal) (Ω) 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 54.9 49.9 49.9 49.9 49.9 T Small Signal 340 880 460 260 20 370 710 440 260 20 240 795 380 260 20 BW (MHz) 0.1 dB Flatness 105 70 105 130 100 120 110 300 145 (MHz) REV. D –14– AD8001 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Ceramic Dual In-Line Package [CERDIP] (N-8) (Q-8) Dimensions shown in inches and (millimeters) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.005 (0.13) 0.055 (1.40) MIN MAX 0.365 (9.27) 0.355 (9.02) 85 8 5 0.295 (7.49) 0.310 (7.87) 0.285 (7.24) 0.220 (5.59) PIN 1 1 1 4 0.275 (6.98) 4 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) BSC 0.100 (2.54) 0.320 (8.13) 0.150 (3.81) 0.300 (7.62) 0.405 (10.29) MAX BSC 0.290 (7.37) 0.135 (3.43) 0.060 (1.52) 0.015 0.120 (3.05) 0.180 0.015 (0.38) 0.200 (5.08) (0.38) (4.57) MAX MIN MAX 0.150 (3.81) 0.015 (0.38) 0.200 (5.08) MIN 0.150 (3.81) 0.010 (0.25) 0.125 (3.18) SEATING 0.130 (3.30) PLANE 0.008 (0.20) 0.015 (0.38) 0.023 (0.58) SEATING 15 0.070 (1.78) 0.110 (2.79) 0.060 (1.52) PLANE 0.008 (0.20) 0.014 (0.36) 0 0.030 (0.76) 0.022 (0.56) 0.050 (1.27) 0.018 (0.46) 0.045 (1.14) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS 0.014 (0.36) (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 8-Lead Standard Small Outline Package [SOIC] 5-Lead Small Outline Transistor Package [SOT-23] (R-8) (RT-5) Dimensions shown in millimeters and (inches) Dimensions shown in millimeters 5.00 (0.1968) 2.90 BSC 4.80 (0.1890) 85 5 4 4.00 (0.1574) 6.20 (0.2440) 3.80 (0.1497) 5.80 (0.2284) 1 4 2.80 BSC 1.60 BSC 1 2 3 0.50 (0.0196) 1.27 (0.0500) PIN 1 � 45� 1.75 (0.0688) BSC 0.25 (0.0099) 0.95 BSC 1.35 (0.0532) 0.25 (0.0098) 1.90 1.30 0.10 (0.0040) BSC 1.15 8� 0.51 (0.0201) 0.90 0� 1.27 (0.0500) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) SEATING 0.10 0.40 (0.0157) 0.17 (0.0067) PLANE 1.45 MAX 0.22 0.08 COMPLIANT TO JEDEC STANDARDS MS-012AA 10� CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS 0.15 MAX 5� 0.60 (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0.50 SEATING 0� REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 0.45 0.30 PLANE 0.30 COMPLIANT TO JEDEC STANDARDS MO-178AA –15– REV. D AD8001 Revision History Location Page 7/03—Data Sheet changed from REV. C to REV. D Renumbered figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 –16– REV. D C01043–0–7/03(D)