ANALOG DEVICES AD7998

2 8-Channel, 10- and 12-Bit ADCs with I C- Compatible Interface in 20-Lead TSSOP AD7997/AD7998 FEATURES FUNCTIONAL BLOCK DIAGRAM V AGND REF CONVST DD IN 10- and 12-bit ADC with fast conversion time: 2 µs typ 8 single-ended analog input channels AD7997/AD7998 Specified for V of 2.7 V to 5.5 V DD 10-/12-BIT V 1 IN SUCCESSIVE CONTROL Low power consumption T/H 8:1 APPROXIMATION LOGIC I/P ADC Fast throughput rate: up to 188 kSPS MUX Sequencer operation V 8 OSCILLATOR IN Automatic cycle mode 2 I C®-compatible serial interface supports standard, fast, CONVERSION DATA LIMIT LOW RESULT and high speed modes REGISTER REGISTER CH1–CH4 Out-of-range indicator/alert function CONFIGURATION ALERT/BUSY Pin-selectable addressing via AS REGISTER DATA LIMIT HIGH REGISTER CH1–CH4 Shutdown mode: 1 µA max ALERT STATUS REGISTER Temperature range: −40°C to +85°C HYSTERESIS 20-lead TSSOP package CYCLE TIMER REGISTER CH1–CH4 REGISTER See the AD7992 and AD7994 for 2-channel and 4-channel AS SCL equivalent devices, respectively 2 I C INTERFACE SDA AGND GENERAL DESCRIPTION Figure 1. The AD7997/AD7998 are 8-channel, 10- and 12-bit, low power, 2 On-chip limit registers can be programmed with high and successive approximation ADCs with an I C-compatible low limits for the conversion result, and an open-drain, out-of- interface. The parts operate from a single 2.7 V to 5.5 V power range indicator output (ALERT) becomes active when the supply and feature a 2 µs conversion time. The parts contain an programmed high or low limits are violated by the conversion 8-channel multiplexer and track-and-hold amplifier that can result. This output can be used as an interrupt. handle input frequencies up to 11 MHz. PRODUCT HIGHLIGHTS The AD7997/AD7998 provide a 2-wire serial interface that is 2 1. 2 µs conversion time with low power consumption. compatible with I C interfaces. Each part comes in two versions, AD7997-0/AD7998-0 and AD7997-1/AD7998-1, and each 2 2. I C-compatible serial interface with pin-selectable 2 2 version allows at least two different I C addresses. The I C addresses. Two AD7997/AD7998 versions allow five interface on the AD7997-0/AD7998-0 supports standard and AD7997/AD7998 devices to be connected to the same 2 2 fast I C interface modes. The I C interface on the AD7997-1/ serial bus. 2 AD7998-1 supports standard, fast, and high speed I C interface 3. The parts feature automatic shutdown while not converting modes. to maximize power efficiency. Current consumption is 1 µA The AD7997/AD7998 normally remain in a shutdown state max when in shutdown mode at 3V. while not converting, and power up only for conversions. The 4. Reference can be driven up to the power supply. conversion process can be controlled using the pin, CONVST 2 by a command mode where conversions occur across I C write 5. Out-of-range indicator that can be software disabled or operations or an automatic conversion interval mode selected enabled. through software control. 6. One-shot and automatic conversion rates. The AD7997/AD7998 require an external reference that should 7. Registers store minimum and maximum conversion be applied to the REFIN pin and can be in the range of 1.2 V to results. VDD. This allows the widest dynamic input range to the ADC. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. 03473-0-001 AD7997/AD7998 TABLE OF CONTENTS AD7997 Specifications..................................................................... 3 Serial Bus Address ...................................................................... 23 AD7998 Specifications..................................................................... 5 Writing to the AD7997/AD7998 .................................................. 24 2 I C Timing Specifications................................................................ 7 Writing to the Address Pointer Register for a Subsequent Read.............................................................................................. 24 Absolute Maximum Ratings............................................................ 9 Writing a Single Byte of Data to the Alert Status Register or ESD Caution.................................................................................. 9 Cycle Register.............................................................................. 24 Pin Configuration and Pin Function Descriptions.................... 10 Writing Two Bytes of Data to a Limit, Hysteresis, or Configuration Register .............................................................. 24 Terminology .................................................................................... 11 Reading Data from the AD7997/AD7998................................... 26 Typical Performance Characteristics ........................................... 12 ALERT/BUSY Pin .......................................................................... 27 Circuit Information........................................................................ 15 SMBus ALERT ............................................................................ 27 Converter Operation.................................................................. 15 BUSY............................................................................................ 27 Typical Connection Diagram ................................................... 16 Placing the AD7997-1/AD7998-1 into High Speed Mode ... 27 Analog Input ............................................................................... 16 The Address Select (AS) Pin ..................................................... 27 Internal Register Structure ............................................................ 18 Modes of Operation ....................................................................... 28 Address Pointer Register ........................................................... 18 Mode 1—Using the CONVST Pin ........................................... 28 Configuration Register .............................................................. 19 Mode 2 – COMMAND MODE ............................................... 29 Conversion Result Register ....................................................... 20 Mode 3—Automatic Cycle Interval Mode.............................. 30 Limit Registers ............................................................................ 20 Outline Dimensions ....................................................................... 31 Alert Status Register (CH1 to CH4) ........................................ 21 Ordering Guide .......................................................................... 31 Cycle Timer Register.................................................................. 22 2 Related Parts in I C-Compatible ADC Product Family........ 31 Sample Delay and Bit Trial Delay............................................. 22 Serial Interface ................................................................................ 23 REVISION HISTORY 9/04—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD7997/AD7998 AD7997 SPECIFICATIONS Temperature range for B version is −40°C to +85°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7997-0, all specifications apply for fSCL up to 400 kHz; for the AD7997-1, all specifications apply for fSCL up to 3.4 MHz, unless otherwise noted; TA = TMIN to TMAX. Table 1. Parameter B Version Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE FIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz FIN = 1 kHz sine wave for fSCL up to 400 kHz 2 Signal to Noise + Distortion (SINAD) 61 dB min 2 Total Harmonic Distortion (THD) –75 dB max 2 Peak Harmonic or Spurious Noise (SFDR) –76 dB max 2 Intermodulation Distortion (IMD) fa = 10.1 kHz, fb = 9.9 kHz for fSCL from 1.7 MHz to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for fSCL up to 400 kHz Second-Order Terms –86 dB typ Third-Order Terms –86 dB typ 2 Aperture Delay 10 ns max 2 Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation –90 dB typ FIN = 108 Hz, see the Terminology section 2 Full-Power Bandwidth 11 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 10 Bits 1, 2 Integral Nonlinearity ±0.5 LSB max 1, 2 Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 2 Offset Error ±1.5 LSB max Mode 1 (CONVST Mode) ±2.5 LSB max Mode 2 (Command Mode) 2 Offset Error Match ±0.5 LSB max 2 Gain Error ±1.5 LSB max 2 Gain Error Match ±0.5 LSB max ANALOG INPUT Input Voltage Range 0 to REF V IN DC Leakage Current ±1 µA max Input Capacitance 30 pF typ REFERENCE INPUT REF Input Voltage Range 1.2 to V V min/V max IN DD DC Leakage Current ±1 µA max Input Impedance 69 kΩ typ During a conversion LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) V min Input Low Voltage, VINL 0.3 (VDD) V max Input Leakage Current, IIN ±1 µA max VIN = 0 V or VDD 3 Input Capacitance, C 10 pF max IN Input Hysteresis, V 0.1 (V ) V min HYST DD Rev. 0 | Page 3 of 32 AD7997/AD7998 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, V 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD Input Leakage Current, I ±1 µA max V = 0 V or V IN IN DD 3 Input Capacitance, CIN 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ± 1 µA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See the Modes of Operation section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ f = 100 kHz SCL 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ f = 400 kHz SCL 147 kSPS typ f = 3.4 MHz, 188 kSPS typ @ 5 V SCL POWER REQUIREMENTS V 2.7/5.5 V min/max DD I Digital inputs = 0 V or V DD DD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.3/0.6 mA max V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Operating, Interface Active 0.15/0.4 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 2 Mode 3 (I C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V Power Dissipation Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Power Down, Interface Inactive 3.3/11 µW max V = 3.3 V/5.5 V DD 1 2 Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I C Hs-Mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the Terminology section. 3 Guaranteed by initial characterization. Rev. 0 | Page 4 of 32 AD7997/AD7998 AD7998 SPECIFICATIONS Temperature range for B version is −40°C to +85°C. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; For the AD7998-0, all specifications apply for fSCL up to 400 kHz; for the AD7998-1, all specifications apply for fSCL up to 3.4 MHz, unless otherwise noted; TA = TMIN to TMAX. Table 2. Parameter B Version Unit Test Conditions/Comments 1 DYNAMIC PERFORMANCE FIN = 10 kHz sine wave for fSCL from 1.7 MHz to 3.4 MHz FIN = 1 kHz sine wave for fSCL up to 400 kHz 2 Signal-to-Noise + Distortion (SINAD) 70.5 dB min 2 Signal to Noise Ratio (SNR) 71 dB min 2 Total Harmonic Distortion (THD) –78 dB max 2 Peak Harmonic or Spurious Noise (SFDR) –79 dB max 2 Intermodulation Distortion (IMD) fa = 10.1 kHz, fb = 9.9 kHz fSCL from 1.7 MHz to 3.4 MHz fa = 1.1 kHz, fb = 0.9 kHz for f up to 400 kHz SCL Second-Order Terms –90 dB typ Third-Order Terms –90 dB typ 2 Aperture Delay 10 ns max 2 Aperture Jitter 50 ps typ 2 Channel-to-Channel Isolation –90 dB typ FIN = 108 Hz, see the Terminology section 2 Full-Power Bandwidth 11 MHz typ @ 3 dB 2 MHz typ @ 0.1 dB DC ACCURACY Resolution 12 Bits 1,2 Integral Nonlinearity ±1 LSB max ±0.2 LSB typ 1,2 Differential Nonlinearity +1/–0.9 LSB max Guaranteed no missed codes to 12 bits ±0.2 LSB typ 2 Offset Error ±4 LSB max Mode 1 (CONVST Mode) ±6 LSB max Mode 2 (Command Mode) 2 Offset Error Match ±1 LSB max 2 Gain Error ±2 LSB max 2 Gain Error Match ±1 LSB max ANALOG INPUT Input Voltage Range 0 to REFINV DC Leakage Current ± 1 µA max Input Capacitance 30 pF typ REFERENCE INPUT REFIN Input Voltage Range 1.2 to VDD V min/V max DC Leakage Current ± 1 µA max Input Impedance 69 kΩ typ LOGIC INPUTS (SDA, SCL) Input High Voltage, V 0.7 (V ) V min INH DD Input Low Voltage, V 0.3 (V ) V max INL DD Input Leakage Current, IIN ± 1 µA max VIN = 0 V or VDD 3 Input Capacitance, CIN 10 pF max Input Hysteresis, VHYST 0.1 (VDD) V min Rev. 0 | Page 5 of 32 AD7997/AD7998 Parameter B Version Unit Test Conditions/Comments LOGIC INPUTS (CONVST) Input High Voltage, VINH 2.4 V min VDD = 5 V 2.0 V min VDD = 3 V Input Low Voltage, V 0.8 V max V = 5 V INL DD 0.4 V max V = 3 V DD Input Leakage Current, I ±1 µA max V = 0 V or V IN IN DD 3 Input Capacitance, CIN 10 pF max LOGIC OUTPUTS (OPEN-DRAIN) Output Low Voltage, VOL 0.4 V max ISINK = 3 mA 0.6 V max ISINK = 6 mA Floating-State Leakage Current ±1 µA max 3 Floating-State Output Capacitance 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE See the Modes of Operation section Conversion Time 2 µs typ Throughput Rate Mode 1 (Reading after the Conversion) 5 kSPS typ f = 100 kHz SCL 21 kSPS typ fSCL = 400 kHz 121 kSPS typ fSCL = 3.4 MHz Mode 2 5.5 kSPS typ fSCL = 100 kHz 22 kSPS typ f = 400 kHz SCL 147 kSPS typ f = 3.4 MHz , 188 kSPS typ @ 5 V SCL POWER REQUIREMENTS V 2.7/5.5 V min/max DD I Digital inputs = 0 V or V DD DD Power-Down Mode, Interface Inactive 1/2 µA max VDD = 3.3 V/5.5 V Power-Down Mode, Interface Active 0.07/0.3 mA max VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.3/0.6 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Operating, Interface Inactive 0.06/0.1 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.3/0.6 mA max V = 3.3 V/5.5 V, 3.4 MHz f DD SCL Operating, Interface Active 0.15/0.4 mA max V = 3.3 V/5.5 V, 400 kHz f DD SCL 0.6/1.1 mA max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 0.7/1.4 mA typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 2 Mode 3 (I C Inactive, TCONVERT x 32) 0.7/1.5 mA max VDD = 3.3 V/5.5 V Power Dissipation Fully Operational Operating, Interface Active 0.495/2.2 mW max VDD = 3.3 V/5.5 V, 400 kHz fSCL 1.98/6.05 mW max VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1 2.31/7.7 mW typ VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2 Power Down, Interface Inactive 3.3/11 µW max V = 3.3 V/5.5 V DD 1 2 Max/min ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I C Hs-Mode SCL frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled. 2 See the Terminology section. 3 Guaranteed by initial characterization. Rev. 0 | Page 6 of 32 AD7997/AD7998 2 I C TIMING SPECIFICATIONS Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line. tr and tf measured between 0.3 VDD and 0.7 VDD. High speed mode timing specifications apply to the AD7997-1/AD7998-1 only. Standard and fast mode timing specifications apply to both the AD7997-0/AD7998-0 and the AD7997-1/AD7998-1. See Figure 2. Unless otherwise noted, VDD = 2.7 V to 5.5 V; REFIN = 2.5 V; T =T to T . A MIN MAX Table 3. AD7997/AD7998 Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description f Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz High speed mode CB = 100 pF max 3.4 MHz CB = 400 pF max 1.7 MHz t1 Standard mode 4 µs tHIGH, SCL high time Fast mode 0.6 µs High speed mode C = 100 pF max 60 ns B C = 400 pF max 120 ns B t Standard mode 4.7 µs t , SCL low time 2 LOW Fast mode 1.3 µs High speed mode C = 100 pF max 160 ns B CB = 400 pF max 320 ns t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns High speed mode 10 ns 1 t Standard mode 0 3.45 µs t , data hold time 4 HD;DAT Fast mode 0 0.9 µs High speed mode 2 CB = 100 pF max 0 70 ns CB = 400 pF max 0 150 ns t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs High speed mode 160 ns t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition Fast mode 0.6 µs High speed mode 160 ns t Standard mode 4.7 µs t , bus free time between a stop and a start condition 7 BUF Fast mode 1.3 µs t Standard mode 4 µs t , setup time for stop condition 8 SU;STO Fast mode 0.6 µs High speed mode 160 ns t Standard mode 1000 ns t , rise time of SDA signal 9 RDA Fast mode 20 + 0.1 C 300 ns B High speed mode C = 100 pF max 10 80 ns B CB = 400 pF max 20 160 ns Rev. 0 | Page 7 of 32 AD7997/AD7998 AD7997/AD7998 Limit at TMIN, TMAX Parameter Conditions Min Max Unit Description t10 Standard mode 300 ns tFDA, fall time of SDA signal Fast mode 20 + 0.1 CB 300 ns High speed mode CB = 100 pF max 10 80 ns C = 400 pF max 20 160 ns B t Standard mode 1000 ns t , rise time of SCL signal 11 RCL Fast mode 20 + 0.1 C 300 ns B High speed mode C = 100 pF max 10 40 ns B CB = 400 pF max 20 80 ns t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after an Acknowledge bit Fast mode 20 + 0.1 C 300 ns B High speed mode CB = 100 pF max 10 80 ns C = 400 pF max 20 160 ns B t Standard mode 300 ns t , fall time of SCL signal 12 FCL Fast mode 20 + 0.1 CB 300 ns High speed mode C = 100 pF max 10 40 ns B CB = 400 pF max 20 80 ns tSP Fast mode 0 50 ns Pulse width of suppressed spike High speed mode 0 10 ns t 1 typ µs Power-up time POWER-UP 1 A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. 2 For 3 V supplies, the maximum hold time with C = 100 pF max is 100 ns max. B t 11 t 12 t t 2 6 SCL t t 6 t t t 5 4 3 8 t 1 t 9 t 10 SDA t 7 S P P S S = START CONDITION P = STOP CONDITION Figure 2. Timing Diagram for 2-Wire Serial Interface Rev. 0 | Page 8 of 32 03473-0-002 AD7997/AD7998 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to 7 V DD rating only; functional operation of the device at these or any Analog Input Voltage to GND −0.3 V to V + 0.3 V DD other conditions above those listed in the operational sections Reference Input Voltage to GND −0.3 V to VDD + 0.3 V of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to +7 V maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to VDD + 0.3 V device reliability. 1 Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150° Junction Temperature 150°C 20-Lead TSSOP θ Thermal Impedance 143°C/W JA θ Thermal Impedance 45°C/W JC Pb/SN Temperature, Soldering Reflow (10 s to 30 s) 240 (+0/-5)°C Pb-free Temperature, Soldering Reflow 260 (+0)°C ESD 1.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 32 AD7997/AD7998 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS AGND 1 20 AGND V 2 19 SCL DD AD7997/ AGND 3 18 SDA AD7998 AGND ALERT/BUSY 4 17 TOP VIEW V (Not to Scale) 5 16 CONVST DD REF 6 AS IN 15 V 1 V 2 7 14 IN IN V 3 V 4 8 13 IN IN V 5 V 6 9 12 IN IN V 7 10 11 V 8 IN IN Figure 3. AD7998/AD7997 Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Function 1, 3, AGND Analog Ground. Ground reference point for all circuitry on the AD7997/AD7998. All analog input signals should be 4, 20 referred to this AGND voltage. 2, 5 VDD Power Supply Input. The VDD range for the AD7997/AD7998 is from 2.7 V to 5.5 V. 6 REFIN Voltage Reference Input. The external reference for the AD7997/AD7998 should be applied to this input pin. The voltage range for the external reference is 1.2 V to V . A 0.1 µF and 1 µF capacitors should be placed between REF DD IN and AGND. See Typical Connection Diagram. 7 V 1 Analog Input 1. Single-ended analog input channel. The input range is 0 V to REF . IN IN 8 VIN3 Analog Input 3. Single-ended analog input channel. The input range is 0 V to REFIN. 9 VIN5 Analog Input 5. Single-ended analog input channel. The input range is 0 V to REFIN. 10 V 7 Analog Input 7. Single-ended analog input channel. The input range is 0 V to REF . IN IN 11 VIN8 Analog Input 8. Single-ended analog input channel. The input range is 0 V to REFIN. 12 V 6 Analog Input 6. Single-ended analog input channel. The input range is 0 V to REF . IN IN 13 V 4 Analog Input 4. Single-ended analog input channel. The input range is 0 V to REF . IN IN 14 VIN2 Analog Input 2. Single-ended analog input channel. The input range is 0 V to REFIN. 2 15 AS Logic Input. Address select input that selects one of three I C addresses for the AD7997/AD7998, as shown in Table 6. The device address depends on the voltage applied to this pin. 16 CONVST Logic Input Signal. Convert start signal. This is an edge-triggered logic input. The rising edge of this signal powers up the part. The power-up time for the part is 1 µs. The falling edge of CONVST places the track/hold into hold mode and CONVST high pulse; otherwise, the initiates a conversion. A power-up time of at least 1 µs must be allowed for the conversion result is invalid (see the Modes of Operation section). 17 ALERT/BUSY Digital Output. Selectable as an ALERT or BUSY output function. When configured as an ALERT, this pin acts as an out- of-range indicator and, if enabled, becomes active when the conversion result violates the DATAHIGH or DATALOW register values. See the Limit Registers section. When configured as a BUSY output, this pin becomes active when a conversion is in progress. Open-drain output. 18 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. External pull-up resistor required. 19 SCL Digital Input. Serial bus clock. Open-drain input. External pull-up resistor required. 2 Table 6. I C Address Selection 2 Part Number AS Pin I C Address AD7997-0 AGND 010 0001 AD7997-0 VDD 010 0010 AD7997-1 AGND 010 0011 AD7997-1 VDD 010 0100 1 AD7997-x Float 010 0000 AD7998-0 AGND 010 0001 AD7998-0 VDD 010 0010 AD7998-1 AGND 010 0011 AD7998-1 V 010 0100 DD 1 AD7998-x Float 010 0000 1 If the AS pin is left floating on any of the AD7997/AD7998 parts, the device address is 010 0000. Rev. 0 | Page 10 of 32 03473-0-003 AD7997/AD7998 TERMINOLOGY Signal-to-Noise and Distortion Ratio (SINAD) Channel-to-Channel Isolation The measured ratio of signal-to-noise and distortion at the out- A measure of the level of crosstalk between channels, taken put of the A/D converter. The signal is the rms amplitude of the by applying a full-scale sine wave signal to the unselected input fundamental. Noise is the sum of all nonfundamental signals up channels, and determining how much the 108 Hz signal is to half the sampling frequency (f /2), excluding dc. The ratio is attenuated in the selected channel. The sine wave signal applied S dependent on the number of quantization levels in the digiti- to the unselected channels is then varied from 1 kHz up to zation process; the more levels, the smaller the quantization 2 MHz, each time determining how much the 108 Hz signal in noise. The theoretical signal-to-noise and distortion ratio for the selected channel is attenuated. This figure represents the an ideal N-bit converter with a sine wave input is given by worst-case level across all channels. Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Aperture Delay The measured interval between the sampling clock’s leading Thus, the SINAD is 61.96 dB for a 10-bit converter and 74 dB edge and the point at which the ADC takes the sample. for a 12-bit converter. Aperture Jitter Total Harmonic Distortion (THD) This is the sample-to-sample variation in the effective point in The ratio of the rms sum of harmonics to the fundamental. For time at which the sample is taken. the AD7997/AD7998, it is defined as Full-Power Bandwidth 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 The input frequency at which the amplitude of the reconstructed THD (dB)= 20 log V1 fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. where V1 is the rms amplitude of the fundamental and V2, V3, Power Supply Rejection Ratio (PSRR) V4, V5, and V6 are the rms amplitudes of the second through The ratio of the power in the ADC output at the full-scale sixth harmonics. frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC V supply of frequency f : DD S Peak Harmonic or Spurious Noise PSRR (dB) = 10 log (Pf/Pf ) The ratio of the rms value of the next largest component in the S ADC output spectrum (up to f /2 and excluding dc) to the rms S where Pf is the power at frequency f in the ADC output; PfS is value of the fundamental. Typically, the value of this specification the power at frequency fS coupled onto the ADC VDD supply. is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a Integral Nonlinearity noise peak. The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints are Intermodulation Distortion zero scale, a point 1 LSB below the first code transition, and full With inputs consisting of sine waves at two frequencies, fa scale, a point 1 LSB above the last code transition. and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where Differential Nonlinearity m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms The difference between the measured and the ideal 1 LSB are those for which neither m nor n equal zero. For example, change between any two adjacent codes in the ADC. second-order terms include (fa + fb) and (fa − fb), while Offset Error third-order terms include (2fa + fb), (2fa − fb),(fa + 2fb) and The deviation of the first code transition (00…000) to (fa − 2fb). (00…001) from the ideal—that is, AGND + 1 LSB. The AD7997/AD7998 is tested using the CCIF standard where Offset Error Match two input frequencies near the top end of the input bandwidth The difference in offset error between any two channels. are used. In this case, the second-order terms are usually dis- tanced in frequency from the original sine waves while the Gain Error third-order terms are usually at a frequency close to the input The deviation of the last code transition (111…110) to frequencies. As a result, the second and third-order terms are (111…111) from the ideal (that is, REF − 1 LSB) after the IN specified separately. The calculation of intermodulation distor- offset error has been adjusted out. tion is, like the THD specification, the ratio of the rms sum of the individual distortion products to the rms amplitude of the Gain Error Match sum of the fundamentals, expressed in dB. The difference in gain error between any two channels. Rev. 0 | Page 11 of 32 AD7997/AD7998 TYPICAL PERFORMANCE CHARACTERISTICS 0 75 V = 5.5V DD FS = 121kSPS V = 5V DD FSCL = 3.4MHz FIN = 10kHz 70 –20 SNR = 71.84dB SINAD = 71.68dB V = 4.5V DD THD = 86.18dB 65 –40 SFDR = –88.70dB V = 3V DD 60 V = 3.3V DD –60 55 V = 2.7V DD –80 50 –100 45 40 –120 1 10 100 1000 06 20 400 FREQUENCY (kHz) FREQUENCY (kHz) Figure 4. AD7998 Dynamic Performance with 5 V Supply and Figure 7. AD7998 SINAD vs. Analog Input Frequency for 2.5 V Reference, 121 kSPS, Mode 1 Various Supply Voltages, 3.4 MHz fSCL, 136 kSPS 1.0 FS = 121kSPS FSCL = 3.4MHz –10 0.8 FIN = 10kHz SINAD = 61.63dB 0.6 THD = 91.82dB –30 SFDR = –94.95dB 0.4 0.2 –50 0 –0.2 –70 –0.4 –90 –0.6 –0.8 –110 –1.0 06 10 20 30 40 500 0 500 1000 1500 2000 2500 3000 3500 4000 INPUT FREQUENCY (kHz) CODE Figure 5. AD7997 Dynamic Performance with 5 V Supply and Figure 8. Typical INL, VDD = 5.5 V, Mode 1, 3.4 MHz fSCL, 121 kSPS 2.5 V Reference, 121 kSPS, Mode 1 100 1.0 V = 5V DD 0.8 90 V = 3V DD 0.6 80 0.4 70 0.2 60 0 –0.2 50 –0.4 40 –0.6 V = 3V/5V DD  200mV p-p SINE WAVE 30 –0.8 ON V DD 2nF CAPACITOR ON V DD 20 –1.0 10 100 1000 0 500 1000 1500 2000 2500 3000 3500 4000 SUPPLY RIPPLE FREQUENCY(kHz) CODE Figure 6. PSRR vs. Supply Ripple Frequency Figure 9. Typical DNL, VDD = 5.5 V, Mode 1, 3.4 MHz fSCL, 121 kSPS Rev. 0 | Page 12 of 32 PSRR (dB) SINAD (dB) SINAD (dB) 03473-0-006 03473-0-005 03473-0-004 DNL ERROR (LSB) INL ERROR (LSB) SINAD (dB) 03473-0-009 03473-0-008 03473-0-007 AD7997/AD7998 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 POSITIVE DNL 0.2 0.2 0 0 –0.2 –0.2 NEGATIVE DNL –0.4 –0.4 –0.6 -0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 2000 2500 3000 3500 4000 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 REFERENCE VOLTAGE (V) CODE Figure 13. AD7998 Change in DNL vs. Reference Voltage V = 5 V, Figure 10. Typical INL, VDD = 2.7 V, Mode 1, 3.4 MHz fSCL, 121 kSPS DD Mode 1, 121 kSPS 0.0007 1.0 0.8 0.0006 0.6 0.0005 0.4 –40°C 0.2 0.0004 +25°C 0 0.0003 –0.2 +85°C –0.4 0.0002 –0.6 0.0001 –0.8 –1.0 0 2.7 3.2 3.7 4.2 4.7 5.2 0 500 1000 1500 2000 2500 3000 3500 4000 SUPPLY VOLTAGE (V) CODE Figure 11. Typical DNL, VDD = 2.7 V, Mode 1, 3.4 MHz fSCL, 121 kSPS Figure 14. AD7998 Shutdown Current vs. Supply Voltage, –40°C, +25°C, and +85°C 2.0 1.0 0.8 1.8 0.6 1.6 1.4 0.4 POSITIVE INL MODE 2 0.2 1.2 VDD = 5V 0 1.0 MODE 2 –0.2 0.8 VDD = 3V NEGATIVE INL MODE 1 –0.4 0.6 VDD = 5V -0.6 0.4 MODE 1 –0.8 0.2 VDD = 3V –1.0 0 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 100 600 1100 1600 2100 2600 3100 REFERENCE VOLTAGE (V) SCL FREQUENCY (kHz) 2 Figure 12. AD7998 Change in INL vs. Reference Voltage VDD = 5 V, Figure 15. AD7998 Average Supply Current vs. I C Bus Rate for Mode 1, 121 kSPS VDD = 3 V and 5 V Rev. 0 | Page 13 of 32 INL ERROR (LSB) DNL ERROR (LSB) INL ERROR (LSB) 03473-0-011 03473-0-010 03473-0-012 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) DNL ERROR (LSB) 03473-0-015 03473-0-013 03473-0-014 AD7997/AD7998 2.0 12.0 74 TEMPERATURE = +85°C ENOB V = 5V DD 1.8 TEMPERATURE = +25°C 11.8 TEMPERATURE = –40°C ENOB V = 3V DD 73 1.6 TEMPERATURE = +85°C TEMPERATURE = +25°C 11.6 SINAD V = 5V DD MODE 2 - 147kSPS 1.4 TEMPERATURE = –40°C 72 11.4 1.2 1.0 11.2 71 MODE 1 - 121kSPS SINAD V = 3V DD 0.8 11.0 70 0.6 10.8 0.4 69 10.6 0.2 0 10.4 68 2.7 3.2 3.7 4.2 4.7 5.2 1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000 REFERENCE VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 16. AD7998 Average Supply Current vs. Supply Voltage Figure 17. SINAD/ENOB vs. Reference Voltage, Mode 1, 121 kSPS for Various Temperatures Rev. 0 | Page 14 of 32 SUPPLY CURRENT (mA) 03473-0-016 ENOB (BITS) SINAD (dB) 03473-0-017 AD7997/AD7998 CIRCUIT INFORMATION The AD7997/AD7998 are low power, 10- and 12-bit, single- At the beginning of a conversion, SW2 opens and SW1 moves supply, 8-channel A/D converters. The parts can be operated to position B, causing the comparator to become unbalanced, as from a 2.7 V to 5.5 V supply. shown in Figure 19. The input is disconnected once the con- version begins. The control logic and the capacitive DAC are The AD7997/AD7998 have an 8-channel multiplexer, an on- used to add and subtract fixed amounts of charge from the chip track-and-hold, an A/D converter, an on-chip oscillator, sampling capacitor to bring the comparator back into a 2 internal data registers, and an I C-compatible serial interface, all balanced condition. When the comparator is rebalanced, the housed in a 20-lead TSSOP. This package offers considerable conversion is complete. The control logic generates the ADC space-saving advantages over alternative solutions. The output code. Figure 20 shows the ADC transfer characteristic. AD7997/AD7998 require an external reference in the range of CAPACITIVE 1.2 V to VDD. DAC The AD7997/AD7998 typically remain in a power-down state A while not converting. When supplies are first applied, the parts V IN CONTROL SW1 come up in a power-down state. Power-up is initiated prior to LOGIC B SW2 a conversion, and the device returns to shutdown when the COMPARATOR conversion is complete. Conversions can be initiated on the AGND AD7997/AD7998 by pulsing the signal, using an CONVST Figure 19. ADC Conversion Phase automatic cycle interval mode, or a command mode where ADC Transfer Function wake-up and a conversion occur during a write address function (see the Modes of Operation section). When the The output coding of the AD7997/AD7998 is straight binary. conversion is complete, the AD7997/AD7998 again enter The designed code transitions occur at successive integer LSB shutdown mode. This automatic shutdown feature allows power values (1 LSB, 2 LSB, and so on). The LSB size is REF /1024 for IN saving between conversions. This means any read or write the AD7997 and REF /4096 for the AD7998. Figure 20 shows IN 2 operation across the I C interface can occur while the device is the ideal transfer characteristic for the AD7997/AD7998. in shutdown. 111...111 CONVERTER OPERATION 111...110 The AD7997/AD7998 are successive approximation analog-to- 111...000 digital converters based around a capacitive DAC. Figure 18 and Figure 19 show simplified schematics of the ADC during 011...111 AD7997 1LSB = REF /1024 IN AD7998 1LSB = REF /4096 the acquisition and conversion phase, respectively. Figure 18 IN 000...010 shows the acquisition phase. SW2 is closed and SW1 is in 000...001 position A, the comparator is held in a balanced condition, 000...000 AGND + 1LSB +REF – 1LSB IN and the sampling capacitor acquires the signal on V . IN ANALOG INPUT 0V TO REF IN CAPACITIVE DAC Figure 20. AD7997/AD7998 Transfer Characteristic A V IN CONTROL SW1 LOGIC B SW2 COMPARATOR AGND Figure 18. ADC Acquisition Phase Rev. 0 | Page 15 of 32 03473-0-018 ADC CODE 03473-0-020 03473-0-019 AD7997/AD7998 TYPICAL CONNECTION DIAGRAM ANALOG INPUT The typical connection diagram for the AD7997/AD7998 is Figure 21 shows an equivalent circuit of the AD7997/AD7998 shown in Figure 22. In this figure, the address select pin (AS) analog input structure. The two diodes, D1 and D2, provide is tied to VDD; however, AS can also be tied to AGND or left ESD protection for the analog inputs. Care must be taken to floating, allowing the user to select up to five AD7997/AD7998 ensure that the analog input signal does not exceed the supply devices on the same serial bus. An external reference must be rails by more than 300 mV. This causes the diodes to become applied to the AD7997/AD7998. This reference can be in the forward biased and start conducting current into the substrate. range of 1.2 V to VDD. A precision reference like the REF 19x These diodes can conduct a maximum current of 10 mA family, AD780, ADR03, or ADR381 can be used to supply the without causing irreversible damage to the part. reference voltage to the ADC. V DD 2 SDA and SCL form the 2-wire I C-/SMBus-compatible interface. External pull-up resisters are required for both SDA D1 C2 and SCL lines. 30pF R1 V IN 2 The AD7998-0/AD7997-0 support standard and fast I C C1 D2 interface modes. The AD7998-1/AD7997-1 support standard, 4pF 2 fast, and high speed I C interface modes. Therefore if operating CONVERSION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED in either standard or fast mode, up to five AD7997/AD7998 devices can be connected to the bus, as noted: Figure 21. Equivalent Analog Input Circuit Capacitor C1 in Figure 21 is typically about 4 pF and can 3 × AD7997-0/AD7998-0 and 2 × AD7997-1/ AD7998-1 or primarily be attributed to pin capacitance. Resistor R1 is a 3 × AD7997-1/AD7998-1 and 2 × AD7997-0/AD7998-0 lumped component made up of the on resistance (RON) of a track-and-hold switch, and also includes the RON of the In high speed mode, up to three AD7997-1/AD7998-1 devices input multiplexer. The total resistance is typically about 400 Ω. can be connected to the bus. C2, the ADC sampling capacitor, has a typical capacitance of 30 pF. Wake-up from shutdown and acquisition prior to a conversion is approximately 1 µs, and conversion time is approximately 2 µs. The AD7997/AD7998 enters shutdown mode again after each conversion, which is useful in applications where power consumption is a concern. 5V SUPPLY 10µF 0.1µF 2-WIRE SERIAL INTERFACE R R R P P P V V 1 DD IN SDA 0V to REF IN INPUT AD7997/ SCL µC/µP V 8 AD7998 IN ALERT CONVST AGND V REF 19x REF AS DD IN 0.1µF 1µF Figure 22. AD7997/AD7998 Typical Connection Diagram Rev. 0 | Page 16 of 32 03473-0-021 03473-0-022 AD7997/AD7998 –40 For ac applications, removing high frequency components from the analog input signal is recommended, by using an RC band- –50 pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the V = 3V –60 DD analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance –70 V = 3.3V DD of the ADC. This may necessitate the use of an input buffer V = 2.7V DD amplifier. The choice of the op amp is a function of the particular –80 V = 4.5V DD application. V = 5.5V DD V = 5V –90 DD When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source –100 impedance depends on the amount of total harmonic distortion 10 100 1000 (THD) that can be tolerated. THD increases as the source imped- INPUT FREQUENCY(kHz) ance increases, and performance degrades. Figure 23 shows the Figure 23. THD vs. Analog Input Frequency for Various THD vs. the analog input signal frequency when using supply Supply Voltages, F = 136 kSPS, Mode 1 S voltages of 3 V ± 10% and 5 V ± 10%. Figure 24 shows the THD –40 vs. the analog input signal frequency for different source V = 5V DD impedances. –50 R = 1000Ω IN –60 –70 R = 100Ω IN –80 R = 50Ω IN R = 10Ω –90 IN –100 10 100 1000 INPUT FREQUENCY(kHz) Figure 24. THD vs. Analog Input Frequency for Various Source Impedances for V = 5 V, 136 kSPS, Mode 1 DD Rev. 0 | Page 17 of 32 THD (dB) THD (dB) 03473-0-023 03473-0-024 AD7997/AD7998 INTERNAL REGISTER STRUCTURE The AD7997/AD7998 contain 17 internal registers that are used CONVERSION RESULT REGISTER to store conversion results, high and low conversion limits, and information to configure and control the device (see Figure 25). ALERT STATUS REGISTER Sixteen are data registers and one is an address pointer register. CONFIGURATION Each data register has an address that the address pointer register REGISTER points to when communicating with it. The conversion result CYCLE TIMER register is the only data register that is read only. REGISTER DATA LOW ADDRESS POINTER REGISTER REGISTER CH1 Because it is the register to which the first data byte of every DATA HIGH write operation is written automatically, the address pointer REGISTER CH1 D register does not have and does not require an address. The HYSTERESIS A REGISTER CH1 address pointer register is an 8-bit register in which the 4 LSBs T DATA are used as pointer bits to store an address that points to one of ADDRESS LOW A POINTER REGISTER CH2 the AD7997/AD7998’s data registers. The 4 MSBs are used as REGISTER DATA HIGH command bits when operating in Mode 2 (see the Modes of REGISTER CH2 Operation section). The first byte following each write address HYSTERESIS is to the address pointer register, containing the address of one REGISTER CH2 of the data registers. The 4 LSBs select the data register to which DATA LOW subsequent data bytes are written. Only the 4 LSBs of this register REGISTER CH3 are used to select a data register. On power-up, the address DATA HIGH REGISTER CH3 pointer register contains all 0s, pointing to the conversion result HYSTERESIS register. REGISTER CH3 Table 7. Address Pointer Register DATA LOW C4 C3 C2 C1 P3 P2 P1 P0 REGISTER CH4 0 0 0 0 Register Select DATA HIGH REGISTER CH4 HYSTERESIS REGISTER CH4 Table 8. AD7997/AD7998 Register Addresses P3 P2 P1 P0 Registers SDA 0 0 0 0 Conversion Result Register (Read) SERIAL BUS INTERFACE SCL 0 0 0 1 Alert Status Register (Read/Write) Figure 25. AD7997/AD7998 Register Structure 0 0 1 0 Configuration Register (Read/Write) 0 0 1 1 Cycle Timer Register (Read/Write) 0 1 0 0 DATA Reg CH1 (Read/Write) LOW 0 1 0 1 DATAHIGH Reg CH1 (Read/Write) 0 1 1 0 Hysteresis Reg CH1 (Read/Write) 0 1 1 1 DATALOW Reg CH2 (Read/Write) 1 0 0 0 DATA Reg CH2 (Read/Write) HIGH 1 0 0 1 Hysteresis Reg CH2 (Read/Write) 1 0 1 0 DATALOW Reg CH3 (Read/Write) 1 0 1 1 DATAHIGH Reg CH3 (Read/Write) 1 1 0 0 Hysteresis Reg CH3 (Read/Write) 1 1 0 1 DATA Reg CH4 (Read/Write) LOW 1 1 1 0 DATA Reg CH4 (Read/Write) HIGH 1 1 1 1 Hysteresis Reg CH4 (Read/Write) Rev. 0 | Page 18 of 32 03473-0-025 AD7997/AD7998 CONFIGURATION REGISTER The configuration register is a 16-bit read/write register that is used to set the operating mode of the AD7997/AD7998. The 4 MSBs of the register are unused. The bit functions of all 12 LSBs of the configuration register are outlined in Table 9. A 2-byte write is necessary when writing to the configuration register. Table 9. Configuration Register Bits and Default Settings at Power-Up D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALERT BUSY/ ALERT/BUSY DONTC DONTC DONTC DONTC CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 FLTR EN ALERT POLARITY 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Table 10. Bit Function Descriptions Bit Mnemonic Comment D11 to D4 CH8 to CH1 These 8-channel address bits select the analog input channel(s) to be converted. A 1 in any of Bits D11 to D4 selects a channel for conversion. If more than one channel bit is set to 1, the AD7997/AD7998 sequence through the selected channels, starting with the lowest channel. All unused channels should be set to 0. Prior to initiating a conversion, a channel or channels for conversion must be selected in the configuration register. D3 FLTR The value written to this bit of the control register determines whether the filtering on SDA and SCL is enabled or is to be bypassed. If this bit is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed. D2 ALERT EN The hardware ALERT function is enabled if this bit is set to 1, and disabled if this bit is set to 0. This bit is used in conjunction with the BUSY/ALERT bit to determine if the ALERT/BUSY pin acts as an ALERT or a BUSY output (see Table 12). D1 BUSY/ALERT This bit is used in conjunction with the ALERT EN bit to determine if the ALERT/ BUSY output, Pin 17, acts as an ALERT or BUSY output (see Table 12), and if Pin 17 is configured as an ALERT output pin, if it is to be reset. D0 BUSY/ALERT This bit determines the active polarity of the ALERT/BUSY pin regardless of whether it is configured as an POLARITY ALERT or BUSY output. It is active low if this bit is set to 0, and active high if set to 1. Table 11. Channel Selection D11 D10 D9 D8 D7 D6 D5 D4 Selected Analog Input Channel Comments 0 0 0 0 0 0 0 1 Convert on Channel 1 (V 1) If more than one channel is IN selected, the AD7997/AD7998 0 0 0 0 0 0 1 0 Convert on Channel 2 (V 2) IN start converting on the selected 0 0 0 0 0 1 0 0 Convert on Channel 3 (VIN3) sequence of channels starting with 0 0 0 0 1 0 0 0 Convert on Channel 4 (VIN4) the lowest channel in the 0 0 0 1 0 0 0 0 Convert on Channel 5 (VIN5) sequence. 0 0 1 0 0 0 0 0 Convert on Channel 6 (V 6) IN 0 1 0 0 0 0 0 0 Convert on Channel 7 (V 7) IN 1 0 0 0 0 0 0 0 Convert on Channel 8 (V 8) IN Table 12. ALERT/BUSY Function D2 D1 ALERT/BUSY Pin Configuration 0 0 Pin does not provide any interrupt signal. 0 1 Pin configured as a BUSY output. 1 0 Pin configured as an ALERT output. Resets the ALERT output pin, the Alert_Flag bit in the conversion result register, and the entire alert status register 1 1 (if any is active). If 1/1 is written to Bits D2/D1 in the configuration register to reset the ALERT pin, the Alert_Flag bit, and the alert status register, the contents of the configuration register read 1/0 for D2/D1, respectively, if read back. Rev. 0 | Page 19 of 32 AD7997/AD7998 DATA Register CH1/CH2/CH3/CH4 CONVERSION RESULT REGISTER HIGH The DATAHIGH registers for CH1 to CH 4 are 16-bit read/write The conversion result register is a 16-bit, read-only register that registers; only the 12 LSBs of each register are used. This stores the conversion result from the ADC in straight binary register stores the upper limit that activates the ALERT output format. A 2-byte read is necessary to read data from this register. and/or the Alert_Flag bit in the conversion result register. If the Table 13 shows the contents of the first byte to be read from the value in the conversion result register is greater than the value AD7997/AD7998, and Table 14 shows the contents of the second in the DATA register, an ALERT occurs for that channel. byte to be read. HIGH When the conversion result returns to a value at least N LSBs Table 13. Conversion Value Register (First Read) below the DATA register value, the ALERT output pin and HIGH D15 D14 D13 D12 D11 D10 D9 D8 Alert_Flag bit are reset. The value of N is taken from the Alert_Flag CH CH CH M S B B10 B9 B8 ID2 ID1 ID0 hysteresis register associated with that channel. The ALERT pin can also be reset by writing to Bits D2 and D1 in the Table 14. Conversion Value Register (Second Read) configuration register. For the AD7997, D1 and D0 of the D7 D6 D5 D4 D3 D2 D1 D0 DATA register should contain 0s. HIGH B7 B6 B5 B4 B3 B2 B1 B0 Table 15. DATA Register (First Read/Write) HIGH D15 D14 D13 D12 D11 D10 D9 D8 The AD7997/AD7998 conversion result consists of an Alert_Flag 0 0 0 0 B11 B10 B9 B8 bit, three channel identifier bits, and the 10- and 12-bit data result (MSB first). For the AD7997, the 2 LSBs (D1 and D0) of Table 16. DATAHIGH Register (Second Read/Write) the second read contain two 0s. The three channel identification D7 D6 D5 D4 D3 D2 D1 D0 bits can be used to identify to which of the eight analog input B7 B6 B5 B4 B3 B2 B1 B0 channels the conversion result corresponds. DATA Register CH1/CH2/CH3/CH4 LOW The Alert_Flag bit indicates whether the conversion result being read or any other channel result has violated the limit registers The DATALOW register for each channel is a 16-bit read/write associated with it. If an ALERT occurs, the master can read the register; only the 12 LSBs of each register are used. The register ALERT status register to obtain more information on where the stores the lower limit that activates the ALERT output and/or ALERT occurred. the Alert_Flag bit in the conversion result register. If the value in the conversion result register is less than the value in the LIMIT REGISTERS DATALOW register, an ALERT occurs for that channel. When the The AD7997/AD7998 have four pairs of limit registers. Each conversion result returns to a value at least N LSBs above the pair stores high and low conversion limits for the first four DATALOW register value, the ALERT output pin and Alert_Flag analog input channels, CH1 to CH4. Each pair of limit registers bit are reset. The value of N is taken from the hysteresis register has one associated hysteresis register. All 12 registers are 16 bits associated with that channel. The ALERT output pin can also be wide; only the 12 LSBs of the registers are used for the AD7997 reset by writing to Bits D2 and D1 in the configuration register. and AD7998. For the AD7997, the 2 LSBs, D1 and D0 in these For the AD7997, D1 to D0 of the DATA register should LOW registers, should contain 0s. On power-up, the contents of the contain 0s. DATA register for each channel is full scale, while the HIGH Table 17. DATALOW Register (First Read/Write) contents of the DATA registers is zero scale by default. The LOW D15 D14 D13 D12 D11 D10 D9 D8 AD7997/AD7998 signal an alert (in either hardware, software, 0 0 0 0 B11 B10 B9 B8 or both depending on configuration) if the conversion result moves outside the upper or lower limit set by the limit registers. Table 18. DATALOW Register (Second Read/Write) There are no limit registers or hysteresis registers associated D7 D6 D5 D4 D3 D2 D1 D0 with CH5 to CH8. B7 B6 B5 B4 B3 B2 B1 B0 Rev. 0 | Page 20 of 32 AD7997/AD7998 Hysteresis Register (CH1/CH2/CH3/CH4) ALERT STATUS REGISTER (CH1 TO CH4) Each hysteresis register is a 16-bit read/write register, of which The alert status register is an 8-bit, read/write register that only the 12 LSBs are used. The hysteresis register stores the provides information on an alert event. If a conversion result hysteresis value, N, when using the limit registers. Each pair of activates the ALERT pin or the Alert_Flag bit in the conversion limit registers has a dedicated hysteresis register. The hysteresis result register, as described in the Limit Registers section, the value determines the reset point for the ALERT pin/Alert_Flag alert status register may be read to gain further information. if a violation of the limits has occurred. For example, if a The Alert Status Register contains two status bits per channel, hysteresis value of 8 LSBs is required on the upper and lower one corresponding to the DATAHIGH limit and the other to the limits of Channel 1, the 12-bit word, 0000 0000 0000 1000, DATALOW limit. The bit with a status of 1 shows where the should be written to the hysteresis register of CH1, the address violation occurred—that is, on which channel—and whether of which is shown in Table 8. On power-up, the hysteresis the violation occurred on the upper or lower limit. If a second registers contain a value of 2 for the AD7997 and a value of 8 alert event occurs on the other channel between receiving the for the AD7998. If a different hysteresis value is required, that first alert and interrogating the alert status register, the value must be written to the hysteresis register for the channel corresponding bit for that alert event is also set. in question. For the AD7997, D1 and D0 of the hysteresis register should contain 0s. The alert status register only contains information for CH1 to CH4 because these are the only channels with associated limit Table 19. Hysteresis Register (First Read/Write) registers. D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 B11 B10 B9 B8 The entire contents of the alert status register can be cleared by writing 1,1, to Bits D2 and D1 in the configuration register, as Table 20. Hysteresis Register (Second Read/Write) shown in Table 12. This may also be done by writing all 1s to D7 D6 D5 D4 D3 D2 D1 D0 the alert status register itself. Thus, if the alert status register is B7 B6 B5 B4 B3 B2 B1 B0 addressed for a write operation, which is all 1s, the contents of the alert status register are cleared or reset to all 0s. Using the Limit Registers to Store Min/Max Conversion Table 21. Alert Status Register Results for CH1 to CH4 D7 D6 D5 D4 D3 D2 D1 D0 If full scale, that is, all 1s, is written to the hysteresis register for CH4 CH4 CH3 CH3 CH2 CH2 CH1 CH1 HI LO HI LO HI LO HI LO a particular channel, the DATA and DATA registers for HIGH LOW that channel no longer act as limit registers as previously Table 22. Alert Status Register Bit Function Description described, but instead act as storage registers for the maximum Bit Mnemonic If bit is set to 1, violation of… and minimum conversion results returned from conversions on D0 CH1LO DATALOW limit on Channel 1. a channel over any given period of time. This function is useful No violation if bit is set to 0. in applications where the widest span of actual conversion D1 CH1HI DATAHIGH limit on Channel 1. results is required rather than using the ALERT to signal that an No violation if bit is set to 0. intervention is necessary. This function could be useful for D2 CH2 DATA limit on Channel 2. LO LOW monitoring temperature extremes during refrigerated goods No violation if bit is set to 0. transportation. It must be noted that on power-up, the contents D3 CH2HI DATAHIGH limit on Channel 2. of the DATAHIGH register for each channel are full scale, while the No violation if bit is set to 0. contents of the DATALOW registers are zero scale by default. D4 CH3LO DATA limit on Channel 3. LOW No violation if bit is set to 0. Therefore, minimum and maximum conversion values being D5 CH3 DATA limit on Channel 3. stored in this way are lost if power is removed or cycled. HI HIGH No violation if bit is set to 0. D6 CH4LO DATALOW limit on Channel 4. No violation if bit is set to 0. D7 CH4HI DATA limit on Channel 4. HIGH No violation if bit is set to 0. Rev. 0 | Page 21 of 32 AD7997/AD7998 SAMPLE DELAY AND BIT TRIAL DELAY CYCLE TIMER REGISTER 2 It is recommended that no I C bus activity occurs when a The cycle timer register is an 8-bit, read/write register that conversion is taking place. However, if this is not possible, for stores the conversion interval value for the automatic cycle example when operating in Mode 2 or Mode 3, then in order to interval mode of the AD7997/AD7998 (see the Modes of maintain the performance of the ADC, Bits D7 and D6 in the Operation section). D5 to D3 of the cycle timer register are cycle timer register are used to delay critical sample intervals unused and should contain 0s at all times. On power-up, the 2 and bit trials from occurring while there is activity on the I C cycle timer register contains all 0s, thus disabling automatic bus. This results in a quiet period for each bit decision. In cycle operation of the AD7997/AD7998. To enable automatic certain cases where there is excessive activity on the interface cycle mode, the user must write to the cycle timer register, lines, this may have the effect of increasing the overall selecting the required conversion interval by programming Bits conversion time. However, if bit trial delays extend longer than D2 to D0. Table 23 shows the structure of the cycle timer 1 µs, the conversion terminates. register, while Table 24 shows how the bits in this register are decoded to provide various automatic sampling intervals. When Bits D7 and D6 are both 0, the bit trial and sample Table 23. Cycle Timer Register and Defaults at Power-Up interval delaying mechanism is implemented. The default D7 D6 D5 D4 D3 D2 D1 D0 setting of D7 and D6 is 0. To turn off both delay mechanisms, Sample Bit Trial Cyc Cyc Cyc set D7 and D6 to 1. 0 0 0 Delay Delay Bit2 Bit1 Bit0 Table 25. Cycle Timer Register and Defaults at Power-up 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Sample Bit Trial Cyc Cyc Cyc 0 0 0 Table 24. Cycle Timer Intervals Delay Delay Bit 2 Bit 1 Bit 0 Typical Conversion Interval 0 0 0 0 0 0 0 0 D2 D1 D0 (TCONVERT = Conversion Time) 0 0 0 Mode Not Selected 0 0 1 TCONVERT × 32 0 1 0 TCONVERT × 64 0 1 1 TCONVERT × 128 1 0 0 T × 256 CONVERT 1 0 1 T × 512 CONVERT 1 1 0 T × 1024 CONVERT 1 1 1 TCONVERT × 2048 Rev. 0 | Page 22 of 32 AD7997/AD7998 SERIAL INTERFACE 2 Control of the AD7997/AD7998 is carried out via the I C- Data is sent over the serial bus in sequences of nine clock compatible serial bus. The devices are connected to this bus as pulses, eight bits of data followed by an acknowledge bit from slave devices under the control of a master device, such as the the receiver of data. Transitions on the data line must occur processor. during the low period of the clock signal and remain stable during the high period because a low-to-high transition when SERIAL BUS ADDRESS the clock is high may be interpreted as a stop signal. 2 Like all I C-compatible devices, the AD7997/AD7998 have a When all data bytes have been read or written, stop conditions 7-bit serial address. The 3 MSBs of this address for the AD7997/ are established. In write mode, the master pulls the data line AD7998 are set to 010. The AD7997/AD7998 come in two high during the 10th clock pulse to assert a stop condition. In versions, the AD7997-0/AD7997-0 and AD7997-1AD7998-1. 2 read mode, the master device pulls the data line high during the The two versions have three different I C addresses available, low period before the ninth clock pulse. This is known as No which are selected by either tying the address select pin, AS, to Acknowledge. The master then takes the data line low during AGND or V , or by letting the pin float (see Table 6). By giving DD the low period before the 10th clock pulse, then high during the different addresses for the two versions, up to five AD7997/ 10th clock pulse to assert a stop condition. AD7998 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the Any number of bytes of data may be transferred over the serial bus. (See Table 6.) bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at The serial bus protocol operates as follows. the beginning and cannot subsequently be changed without The master initiates data transfer by establishing a start starting a new operation. condition, defined as a high-to-low transition on the serial data line SDA, while the serial clock line, SCL, remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus responds to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/ W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Rev. 0 | Page 23 of 32 AD7997/AD7998 WRITING TO THE AD7997/AD7998 Depending on the register being written to, there are three WRITING TWO BYTES OF DATA TO A LIMIT, different writes for the AD7997/AD7998. HYSTERESIS, OR CONFIGURATION REGISTER Each of the four limit registers are 16-bit registers, so two bytes WRITING TO THE ADDRESS POINTER REGISTER of data are required to write a value to any one of them. Writing FOR A SUBSEQUENT READ two bytes of data to one of these registers consists of the serial In order to read from a particular register, the address pointer bus write address, the chosen limit register address written to register must first contain the address of that register. If it does the address pointer register, followed by two data bytes written not, the correct address must be written to the address pointer to the selected data register. See Figure 28. register by performing a single-byte write operation, as shown in Figure 26. The write operation consists of the serial bus If the master is write addressing the AD7997/AD7998, it can address followed by the address pointer byte. No data is written write to more than one register without readdressing the ADC. to any of the data registers. A read operation may be subsequently After the first write operation has completed for the first data performed to read the register of interest. register, during the next byte the master simply writes to the address pointer byte to select the next data register for a write WRITING A SINGLE BYTE OF DATA TO THE ALERT operation. This eliminates the need to readdress the device in STATUS REGISTER OR CYCLE REGISTER order to write to another data register. The alert status register and cycle register are both 8-bit registers, so only one byte of data can be written to each. Writing a single byte of data to one of these registers consists of the serial bus write address, the chosen data register address written to the address pointer register, followed by the data byte written to the selected data register. See Figure 27. 191 9 SCL P3 0 1 0 A3 A2 A1 A0 R/W C4 C3 C2 C1 P2 P1 P0 SDA START BY ACK. BY ACK. BY STOP BY MASTER AD7997/AD7998 AD7997/AD7998 MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER BYTE Figure 26. Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation 11 9 9 SCL P3 0 1 0 A3 A2 A1 A0 R/W C4 C3 C2 C1 P2 P1 P0 SDA START BY ACK. BY ACK. BY MASTER AD7997/AD7998 AD7997/AD7998 FRAME 2 FRAME 1 ADDRESS POINTER REGISTER BYTE SERIAL BUS ADDRESS BYTE 91 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY AD7997/AD7998 MASTER FRAME 3 DATA BYTE Figure 27. Single-Byte Write Sequence Rev. 0 | Page 24 of 32 03473-0-027 03473-0-026 AD7997/AD7998 11 9 9 SCL 0 1 0 A3 A2 A1 A0 R/W C4 C3 C2 C1 P3 P2 P1 P0 SDA START BY ACK. BY ACK. BY AD7997/AD7998 AD7997/AD7998 MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE ADDRESS POINTER REGISTER 91 99 1 SCL (CONTINUED) SDA (CONTINUED) 00 D11 D3 0 0 D10 D9 D8 D7 D6 D5 D4 D2 D1/0 D0/0 ACK. BY ACK. BY STOP BY AD7997/AD7998 AD7997/AD7998 MASTER MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE Figure 28. 2-Byte Write Sequence Rev. 0 | Page 25 of 32 03473-0-028 AD7997/AD7998 READING DATA FROM THE AD7997/AD7998 Reading data from the AD7997/AD7998 is a 1- or 2-byte Reading data from the configuration register, conversion result operation. Reading back the contents of the alert status register register, DATAHIGH registers, DATALOW registers, or hysteresis or the cycle timer register is a single-byte read operation, as registers is a 2-byte operation, as shown in Figure 30. The same shown in Figure 29. This assumes the particular register address rules apply for a 2-byte read as a single-byte read. has previously been set up by a single-byte write operation to When reading data back from a register, for example the the address pointer register, as shown in Figure 26. Once the conversion result register, if more than two read bytes are register address has been set up, any number of reads can be supplied, the same or new data is read from the AD7997/ performed from that particular register without having to write AD7998 without the need to readdress the device. This allows to the address pointer register again. the master to continuously read from a data register without If a read from a different register is required, the relevant having to readdress the AD7997/AD7998. register address has to be written to the address pointer register, and again any number of reads from this register may then be performed. 1199 SCL 0 1 0 A3 A2 A1 A0 D7 D6 D5 D3 D2 D1 D0 R/W D4 SDA START BY ACK. BY NO ACK. BY STOP BY MASTER AD7997/AD7998 MASTER MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE SINGLE DATA BYTE FROM AD7997/AD7998 Figure 29. Reading a Single Byte of Data from a Selected Register 11 9 9 SCL 0 1 0 A3 A2 A1 A0 R/W D11 D10 D9 D8 SDA ACK. BY ACK. BY START BY ALERT CHID2 CH CH ID1 ID0 AD7997/AD7998 MASTER MASTER FLAG FRAME 2 FRAME 1 MOST SIGNIFICANT DATA BYTE FROM SERIAL BUS ADDRESS BYTE AD7997/AD7998 1 9 SCL (CONTINUED) SDA (CONTINUED) D1/0 D0/0 D7 D6 D5 D4 D3 D2 NO ACK. BY STOP BY MASTER MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD7997/AD7998 Figure 30. Reading Two Bytes of Data from the Conversion Result Register Rev. 0 | Page 26 of 32 03473-0-030 03473-0-029 AD7997/AD7998 ALERT/BUSY PIN The ALERT/BUSY pin may be configured as an alert output or BUSY as a busy output, as shown in Table 12. When the ALERT/BUSY pin is configured as a BUSY output the pin is used to indicate when a conversion is taking place. The SMBus ALERT polarity of the BUSY pin is programmed through bit D0 in the The AD7997/AD7998 ALERT output is an SMBus interrupt line Configuration register. for devices that want to trade their ability to master for an extra pin. The AD7997/AD7998 is a slave-only device that uses the PLACING THE AD7997-1/AD7998-1 INTO SMBus ALERT to signal the host device that it wants to talk. HIGH SPEED MODE The SMBus ALERT on the AD7997/AD7998 is used as an out- High speed mode communication commences after the master of-range indicator (a limit violation indicator). addresses all devices connected to the bus with the master code, 00001XXX, to indicate that a high speed mode transfer is to The ALERT pin has an open-drain configuration that allows begin. No device connected to the bus is allowed to acknowledge the ALERT outputs of several AD7997/AD7998s to be wired- the high speed master code; therefore, the code is followed by a AND’ed together when the ALERT pin is active low. D0 of the not-acknowledge (see Figure 31). The master must then issue a configuration register is used to set the active polarity of the repeated start followed by the device address with an R/W bit. ALERT output. The power-up default is active low. The ALERT The selected device then acknowledges its address. function can be enabled or disabled by setting D2 of the con- figuration register to 1 or 0, respectively. All devices continue to operate in high speed mode until such a time as the master issues a stop condition. When the stop condi- The host device can process the alert interrupt and simultane- tion is issued, the devices all return to fast mode. ously access all SMBus alert devices through the alert response address. Only the device that pulled the alert low acknowledges THE ADDRESS SELECT (AS) PIN the alert response address (ARA). If more than one device pulls The address select pin on the AD7997/AD7998 is used to set the ALERT pin low, the highest priority (lowest address) device 2 2 the I C address for the AD7997/AD7998 device. The AS pin can wins communication rights via standard I C arbitration during be tied to VDD, to AGND, or left floating. The selection should the slave address transfer. be made as close as possible to the AS pin; avoid having long The ALERT output becomes active when the value in the tracks introducing extra capacitance on to the pin. This is conversion result register exceeds the value in the DATA HIGH important for the float selection, as the AS pin has to charge to a register or falls below the value in the DATA register for a LOW midpoint after the start bit during the first address byte. Extra selected channel. It is reset when a write operation to the capacitance on the AS pin increases the time taken to charge to configuration register sets D1 to a 1, or when the conversion the midpoint and may cause an incorrect decision on the device result returns N LSB below or above the value stored in the address. When the AS pin is left floating, the AD7997/AD7998 DATAHIGH register or the DATALOW register, respectively. N is the can work with a capacitive load up to 40 pF. value in the hysteresis register (see the Limit Registers section). The ALERT output requires an external pull-up resistor that can be connected to a voltage different from V provided the maxi- DD mum voltage rating of the ALERT output pin is not exceeded. The value of the pull-up resistor depends on the application, but should be as large as possible to avoid excessive sink currents at the ALERT output. FAST MODE HIGH SPEED MODE 19 1 9 SCL 0 0 0 0 1 X X X 0 1 0 A3 A2 A1 A0 SDA NACK Sr ACK. BY START BY AD7997/AD7998 MASTER HS MODE MASTER CODE SERIAL BUS ADDRESS BYTE Figure 31. Placing the Part into High Speed Mode Rev. 0 | Page 27 of 32 03473-0-031 AD7997/AD7998 MODES OF OPERATION When supplies are first applied to the AD7997/AD7998, the If the CONVST pulse does not remain high for more than 1 µs, ADC powers up in sleep mode and normally remains in this the falling edge of CONVST still initiates a conversion but the shutdown state while not converting. There are three methods result is invalid because the AD7997/AD7998 are not fully of initiating a conversion on the AD7997/AD7998. powered-up when the conversion takes place. To maintain the performance of the AD7997/AD7998 in this mode it is MODE 1—USING THE CONVST PIN 2 recommended that the I C bus is quiet when a conversion is A conversion can be initiated on the AD7997/AD7998 by taking place. pulsing the CONVST signal. The conversion clock for the part The cycle timer register and Bits C4 to C1 in the address pointer is internally generated so no external clock is required, except register should contain all 0s when operating the AD7997/ when reading from or writing to the serial port. On the rising AD7998 in this mode. The pin should be tied low for CONVST edge of CONVST, the AD7997/AD7998 begins to power up (see all other modes of operation. point A in Figure 32). The power-up time from shutdown mode for the AD7997/AD7998 is approximately 1 µs; the CONVST To select an analog input channel for conversion in this mode, signal must remain high for 1 µs for the part to power up fully. the user must write to the configuration register and select the CONVST can be brought low after this time. This power-up corresponding channel for conversion. To set up a sequence of time also includes the acquisition time of the ADC. The falling channels to be converted with each pulse, set the CONVST edge of the signal places the track-and-hold into hold CONVST corresponding channel bits in the configuration register (see mode; a conversion is also initiated at this point (point B in Table 11). Figure 32). When the conversion is complete, approximately Once a conversion is complete, the master can address the 2 µs later, the part returns to shutdown (point C in Figure 32) AD7997/AD7998 to read the conversion result. If further and remains there until the next rising edge of . The CONVST conversions are required, the SCL line can be taken high while master can then read the ADC to obtain the conversion result. the CONVST signal is pulsed again; then an additional 18 SCL The address pointer register must be pointing to the conversion pulses are required to read the conversion result. result register in order to read back the conversion result. When operating the AD7997-1/AD7998-1 in Mode 1 and reading after conversion with a 3.4 MHz f , the ADCs can SCL achieve a typical throughput rate of up to 121 kSPS. A B C t POWER-UP CONVST t CONVERT 11 9 9 9 SCA SDA S 7-BIT ADDRESS RA A A P FIRST DATA BYTE (MSBs) SECOND DATA BYTE (LSBs) Figure 32. Mode 1 Operation Rev. 0 | Page 28 of 32 03473-0-032 AD7997/AD7998 MODE 2 – COMMAND MODE This mode allows a conversion to be automatically initiated any Table 26 shows the channel selection in this mode via time a write operation occurs. In order to use this mode, the Command Bits C4 to C1 in the address pointer register. The Command Bits C4 to C1 in the address pointer byte shown in wake-up, acquisition, and conversion times combined should Table 7 must be programmed. take approximately 3 µs. Following the write operation, the AD7997/AD7998 must be addressed again to indicate that a To select a single analog input for conversion in this mode, the read operation is required. The read then takes place from the user must set Bits C4 to C1 of the address pointer byte to conversion result register. This read accesses the conversion indicate which channel to convert on (see Table 26). When all result from the channel selected via the command bits. If four command bits are 0, this mode is not in use. Command Bits C4 to C1 were set to 0111, and Bits D4 and D5 were set in the configuration register, a 4-byte read would be To select a sequence of channels for conversion in this mode, necessary. The first read accesses the data from the conversion first select the channels to be included in the sequence by on V 1. While this read takes place, a conversion occurs on IN setting the channel bits in the configuration register. Next, set V 2. The second read accesses this data from V 2. Figure 34 IN IN the command bits in the address pointer byte to 0111. With the illustrates how this mode operates; the user would first have command bits of the address pointer byte set to 0111, the ADC written to the configuration register to select the sequence of knows to look in the configuration register for the sequence of channels to be converted before write addressing the part with channels to be converted. The ADC starts converting on the the command bits set to 0111. lowest channel in the sequence and then the next lowest until all the channels in the sequence are converted. The ADC stops When operating the AD7997-1/AD7998-1 in Mode 2 with a converting the sequence when it receives a STOP bit. high speed mode, 3.4 MHz SCL, the conversion may not be complete before the master tries to read the conversion result. Figure 29 illustrates a 2-byte read operation from the If this is the case, the AD7997-1/AD7998-1 holds the SCL line conversion result register. This operation is preceded typically low during the ACK clock after the read address, until the con- by a write to the address pointer register so that the following version is complete. When the conversion is complete, the read accesses the desired register, in this case the conversion AD7997-1/AD7998-1 releases the SCL line and the master can result register (see Figure 26). If Command Bits C4 to C1 are set then read the conversion result. when the contents of the address pointer register are being loaded, the AD7997/AD7998 begins to power up and convert After the conversion is initiated by setting the command bits upon the selected channel(s). Power-up begins on the fifth SCL in the address pointer byte, if the AD7997/AD7998 receives a falling edge of the address point byte, (see point A in Figure 33). STOP or NACK from the master, the AD7997/AD7998 stops converting. Table 26. Address Pointer Byte C4 C3 C2 C1 P3 P2 P1 P0 Mode 2, Convert On Comments 0 0 0 0 0 0 0 0 Not selected 1 0 0 0 0 0 0 0 V 1 IN 1 0 0 1 0 0 0 0 VIN2 1 0 1 0 0 0 0 0 VIN3 1 0 1 1 0 0 0 0 VIN4 With the pointer Bits P3–P0 set to all 0s, the next read accesses the results of the 1 1 0 0 0 0 0 0 V 5 IN conversion result register. 1 1 0 1 0 0 0 0 V 6 IN 1 1 1 0 0 0 0 0 VIN7 1 1 1 1 0 0 0 0 VIN8 0 1 1 1 0 0 0 0 Sequence of channels selected in the configuration register, Bits D11 to D4. Rev. 0 | Page 29 of 32 AD7997/AD7998 11 8 9 A 9 SCL SDA COMMAND/ADDRESS 7-BIT ADDRESS WA A S POINT BYTE ACK BY ACK BY AD7997/AD7998 AD7997/AD7998 11 9 9 9 SCL SDA FIRST DATA BYTE SECOND DATA BYTE Sr 7-BIT ADDRESS RA A A Sr/P (MSBs) (LSBs) ACK BY ACK BY NACK BY AD7997/AD7998 MASTER MASTER Figure 33. Mode 2 Operation 11 8 9 9 SCL SDA COMMAND/ADDRESS 7-BIT ADDRESS A S WA POINT BYTE ACK BY ACK BY AD7997/AD7998 AD7997/AD7998 9 9 9 1 9 1 9 SCL SDA FIRST DATA BYTE SECOND DATA BYTE FIRST DATA BYTE SECOND DATA BYTE A A A Sr 7-BIT ADDRESS RA A/A (MSBs) (LSBs) (MSBs) (LSBs) ACK BY ACK BY ACK BY ACK BY AD7997/AD7998 MASTER MASTER MASTER RESULT FROM CH1 RESULT FROM CH2 Figure 34. Mode 2 Sequence Operation MODE 3—AUTOMATIC CYCLE INTERVAL MODE An automatic conversion cycle can be selected and enabled by To select a channel(s) for operation in the cycle mode, set the writing a value to the cycle timer register. A conversion cycle corresponding channel bit(s), D11 to D4, of the configuration interval can be set up on the AD7997/AD7998 by programming register. If more than one channel bit is set in the configuration the relevant bits in the 8-bit cycle timer register, as decoded in register, the ADC automatically cycles through the channel Table 24. Only the 3 LSBs are used to select the cycle interval; sequence starting with the lowest channel and working its way the 5 MSBs should contain 0s. When the 3 LSBs of the register up through the sequence. Once the sequence is complete, the are programmed with any configuration other than all 0s, a ADC starts converting on the lowest channel again, continuing conversion takes place every X ms; the cycle interval, X, to loop through the sequence until the cycle timer register depends on the configuration of these three bits in the cycle contents are set to all 0s. This mode is useful for monitoring timer register. There are seven different cycle time intervals to signals, such as battery voltage and temperature, alerting only choose from, as shown in Table 24. Once the conversion has when the limits are violated. taken place, the part powers down again until the next conver- sion occurs. To exit this mode of operation, the user must program the 3 LSBs of the cycle timer register to contain all 0s. Rev. 0 | Page 30 of 32 03473-0-033 03473-0-034 AD7997/AD7998 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.75 8° 0.60 0.30 0° 0.45 COPLANARITY 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153AC Figure 35. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE 1 2 Model Temperature Range Linearity Error (Max) Package Option Package Description AD7997BRU-0 –40°C to +85°C ±0.5 LSB RU-20 TSSOP AD7997BRU-0REEL –40°C to +85°C ±0.5 LSB RU-20 TSSOP 3 AD7997BRUZ-0 –40°C to +85°C ±0.5 LSB RU-20 TSSOP 3 AD7997BRUZ-0REEL –40°C to +85°C ±0.5 LSB RU-20 TSSOP AD7997BRU-1 –40°C to +85°C ±0.5 LSB RU-20 TSSOP AD7997BRU-1REEL –40°C to +85°C ±0.5 LSB RU-20 TSSOP 3 AD7997BRUZ-1 –40°C to +85°C ±0.5 LSB RU-20 TSSOP 3 AD7997BRUZ-1REEL –40°C to +85°C ±0.5 LSB RU-20 TSSOP AD7998BRU-0 –40°C to +85°C ±1 LSB RU-20 TSSOP AD7998BRU-0REEL –40°C to +85°C ±1 LSB RU-20 TSSOP 3 AD7998BRUZ-0 –40°C to +85°C ±1 LSB RU-20 TSSOP 3 AD7998BRUZ-0REEL –40°C to +85°C ±1 LSB RU-20 TSSOP AD7998BRU-1 –40°C to +85°C ±1 LSB RU-20 TSSOP AD7998BRU-1REEL –40°C to +85°C ±1 LSB RU-20 TSSOP 3 AD7998BRUZ-1 –40°C to +85°C ±1 LSB RU-20 TSSOP 3 AD7998BRUZ-1REEL –40°C to +85°C ±1 LSB RU-20 TSSOP EVAL-AD7997CB Standalone Evaluation Board EVAL-AD7998CB Standalone Evaluation Board 1 2 2 The AD7997-0/AD7998-0 support standard and fast I C interface modes. The AD7997-1/AD7998-1 support standard, fast, and high speed I C interface modes. 2 Linearity error here refers to integral nonlinearity. 3 Z = Pb-free part. 2 RELATED PARTS IN I C-COMPATIBLE ADC PRODUCT FAMILY Part Number Resolution Number of Input Channels Package AD7994 12 4 16 TSSOP AD7993 10 4 16 TSSOP AD7992 12 2 10 MSOP Rev. 0 | Page 31 of 32 AD7997/AD7998 NOTES 2 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent 2 2 Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03473–0–9/04(0) Rev. 0 | Page 32 of 32